A method of fabricating a MOSFET device

Abstract

The application provides a preparation method of a MOSFET device, comprising the following steps: providing a semiconductor substrate; forming a gate material layer of doped conductive ions on the semiconductor substrate; performing annealing treatment on the gate material layer, so that the annealing treatment forms an oxide layer on at least part of the surface of the gate material layer away from the semiconductor substrate; after the annealing treatment, performing etching cleaning treatment on the gate material layer to remove the oxide layer; and after the oxide layer is removed, performing etching on the gate material layer to form a gate electrode layer. The preparation method of the MOSFET device effectively reduces the risk of failure of the MOSFET device.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor devices, in particular to a preparation method of a MOSFET device. BACKGROUND

[0002] Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET) is a kind of field effect transistor that can be widely applied in analog circuits and digital circuits. The current output capability of the traditional Si-based MOSFET device is limited by the contradictory relationship between reducing on-resistance and improving breakdown voltage. The critical breakdown field of silicon carbide (SiC) material is one order of magnitude higher than that of silicon-based material. For a given breakdown voltage, by selecting a thin and lightly doped drift region, the on-resistance of the SiC-based MOSFET device is at least two orders of magnitude smaller than that of the Si-based MOSFET device, and the breakdown voltage of the SiC-based MOSFET device is also higher than that of the Si-based MOSFET device, which makes the SiC-based MOSFET device widely used in the field of low-power and high-frequency switching.

[0003] Polysilicon is widely used for the gate electrode of the SiC-based MOSFET device. Polysilicon has very high requirements for critical linewidth (CD), and the industry tends to use lower radio frequency energy and can produce low voltage and high density plasma to realize dry etching of polysilicon, among which inductively coupled plasma etching process (ICP) is widely used. In order to achieve better electrical conduction characteristics, phosphorus elements need to be implanted in polysilicon to achieve heavy doping. At present, the industry mostly uses ion implantation and annealing to dope polysilicon with phosphorus.

[0004] However, after the gate electrode is prepared, there are several particle residues with different heights and diameters between adjacent gate electrodes, and the existence of the particle residues increases the risk of failure of the MOSFET device. SUMMARY

[0005] Therefore, the technical problem to be solved by the present application is to overcome the defect that the existence of the particle residues between adjacent gate electrodes increases the risk of failure of the MOSFET device, and to provide a preparation method of a MOSFET device.

[0006] The application provides a preparation method of a MOSFET device, comprising: providing a semiconductor substrate; forming a gate material layer of doped conductive ions on the semiconductor substrate; performing annealing treatment on the gate material layer, the annealing treatment forms an oxide layer on at least part of the surface of the gate material layer away from the semiconductor substrate; after the annealing treatment, performing etching cleaning treatment on the gate material layer to remove the oxide layer; and after the oxide layer is removed, etching part of the gate material layer to form a gate electrode layer.

[0007] Optionally, the process parameters of the etching cleaning treatment on the gate material layer comprise: the cleaning solution used is hydrofluoric acid solution, the volume ratio of hydrofluoric acid to water in the hydrofluoric acid solution is 1:(50-100), the cleaning time is 2-15 min, and the cleaning temperature is 25-35℃.

[0008] Optionally, the preparation method of the MOSFET device further comprises: before etching the gate material layer to form the gate electrode layer, coating a first initial photoresist layer on the gate material layer; sequentially performing exposure and development on the first initial photoresist layer to form a patterned first photoresist layer; and the step of etching part of the gate material layer to form the gate electrode layer comprises: etching the gate material layer with the first photoresist layer as a mask; and after etching the gate material layer, removing the first photoresist layer.

[0009] Optionally, the preparation method of the MOSFET device further comprises: before performing exposure on the first initial photoresist layer, baking the first initial photoresist layer; after performing development on the first initial photoresist layer, hardening the first initial photoresist layer; and during the baking and hardening processes, the oxygen content in the chamber is less than or equal to 50 ppm, and the temperature is 110-130℃.

[0010] Optionally, the preparation method of the MOSFET device further comprises: after the etching cleaning treatment is performed and before the first initial photoresist layer is coated on the gate material layer, performing water washing treatment on the gate material layer; and after the water washing treatment is performed, removing water stains on the surface of the MOSFET device.

[0011] Optionally, the time interval from the end time of removing the water stains on the surface of the MOSFET device to the start time of coating the first initial photoresist layer on the gate material layer is less than or equal to 2 hours; or, after the water stains on the surface of the MOSFET device are removed and before the first initial photoresist layer is coated on the gate material layer, the MOSFET device is placed in an inert environment or a nitrogen environment.

[0012] Optionally, the preparation method of the MOSFET device further comprises: forming a gate dielectric material layer on the semiconductor substrate before forming the gate material layer doped with conductive ions on the semiconductor substrate; etching part of the gate material layer until the surface of the gate dielectric material layer is exposed; and detecting the concentration of the reaction product by emission spectroscopy during etching part of the gate material layer to detect the etching endpoint.

[0013] Optionally, the step of etching part of the gate material layer comprises main etching and over-etching after the main etching, the etching endpoint detected by the emission spectroscopy is the etching endpoint of the main etching, and the time of the over-etching is 30s-50s.

[0014] Optionally, in the annealing process, the annealing temperature is 900-1000℃, the annealing gas comprises argon, and the annealing time is 30-40min.

[0015] Optionally, the semiconductor substrate is a semiconductor substrate; or the semiconductor substrate comprises a semiconductor substrate and an epitaxial layer on the semiconductor substrate; the semiconductor substrate is a silicon carbide-based substrate; and the epitaxial layer is a silicon carbide-based epitaxial layer.

[0016] The technical scheme of the present application has the following advantages:

[0017] 1. The preparation method of the MOSFET device provided by the present application removes the oxide layer to expose the gate material layer by etching and cleaning the gate material layer after the annealing process, thereby avoiding the formation of particle residues between adjacent gate electrodes after etching part of the gate material layer, and further avoiding the short circuit of adjacent gate electrode layers caused by the communication between the adjacent gate electrode layers and the particle residues between the adjacent gate electrode layers, thereby effectively reducing the risk of failure of the MOSFET device.

[0018] 2. The preparation method of the MOSFET device provided by the present application limits the oxygen content in the chamber to be less than or equal to 50ppm during baking and hardening, thereby avoiding the oxidation of the surface of the gate material layer during baking and hardening, and further avoiding the formation of particle residues between adjacent gate electrodes after the formation of gate electrodes, and avoiding the failure of etching and cleaning.

[0019] 3. The MOSFET device preparation method provided in the present application, by washing the gate material layer after the etching cleaning treatment and before coating the first initial photoresist layer on the gate material layer, the cleaning liquid left on the surface of the MOSFET device is removed, and the water stain on the surface of the MOSFET device is removed by the washing treatment, so that the surface of the gate material layer is ensured to have a high degree of cleanliness, and the coating effect of the first initial photoresist layer is ensured.

[0020] 4. The MOSFET device preparation method provided in the present application, by limiting the time interval from the end time of removing the water stain on the surface of the MOSFET device to the start time of coating the first initial photoresist layer on the gate material layer, the surface oxidation of the gate material layer caused by long time in the area with high oxygen content is avoided, and the formation of particle residues between adjacent gate electrodes after the formation of the gate electrode is avoided, and the failure of the etching cleaning treatment is avoided; by placing the MOSFET device in an inert environment or a nitrogen environment after removing the water stain on the surface of the MOSFET device and before coating the first initial photoresist layer on the gate material layer, the surface oxidation of the gate material layer is avoided, and the formation of particle residues between adjacent gate electrodes after the formation of the gate electrode is avoided, and the failure of the etching cleaning treatment is avoided.

[0021] 5. The MOSFET device preparation method provided in the present application, in the process of etching part of the gate material layer, the concentration of the reaction product is detected by emission spectroscopy to detect the etching end point. Specifically, before the surface of the gate dielectric material layer is exposed, the concentration of the reaction product is stable, and after the surface of the gate dielectric material layer is exposed, the concentration of the reaction product drops sharply, which is the etching end point. The etching end point detection is conducive to the control of the etching process and the accurate control of the etching depth.

[0022] 6. The MOSFET device preparation method provided in the present application, by over-etching after the etching end point, the complete removal of the to-be-removed area in the gate material layer is ensured, and the etching effect is improved. By limiting the time of over-etching, the complete removal effect of the to-be-etched area of the gate material layer is ensured, and the surface damage degree of the exposed gate dielectric material layer caused by plasma bombardment is reduced. BRIEF DESCRIPTION OF DRAWINGS

[0023] In order to more clearly illustrate the specific embodiments of the present application or the technical solutions in the prior art, the drawings needed in the specific embodiments or prior art description will be briefly introduced below. Obviously, the drawings in the following description are some embodiments of the present application, and other drawings can also be obtained by those skilled in the art without creative labor.

[0024] Figure 1 Process flow chart for the preparation method of the MOSFET device provided in the embodiments of the present application;

[0025] Figures 2-12 Structural schematic diagram in the preparation process of the MOSFET device in the present embodiment;

[0026] Explanation of reference signs:

[0027] 1-semiconductor substrate; 2-epitaxial layer; 3-gate dielectric material layer; 4-gate material layer; 41-gate electrode layer; 5-metal layer; 51-contact metal layer; 6-first photoresist layer; 7-second photoresist layer. DETAILED DESCRIPTION

[0028] As described in the background, the presence of the particle residues increases the risk of failure of the MOSFET device.

[0029] The conventional annealing and pushing process is usually carried out in an atmospheric furnace tube, and the furnace is mainly filled with nitrogen atmosphere with a small amount of residual oxygen, which causes the local oxidation of the polysilicon surface to form an oxide layer during the annealing and pushing process. The thickness of the oxide layer is several nanometers, and the oxide layers at different positions have different thicknesses.

[0030] Dry etching of polysilicon usually uses a chlorine-based atmosphere. The chlorine-based atmosphere is ionized to generate plasma, which is accelerated by an electric field to bombard the surface of the polysilicon and react with the polysilicon. The etching selectivity ratio of polysilicon to silicon oxide is greater than 100:1, i.e., it is difficult for the chlorine-based atmosphere to etch silicon oxide. During the dry etching of polysilicon, the areas not covered by the oxide layer are etched away, while the physical bombardment of the plasma can break the thin oxide layer and etch the underlying polysilicon, but it cannot break the thick oxide layer, resulting in several particle residues with different heights and diameters in the etched area of the polysilicon after etching is completed. The height of the particle residues is 300-500 nm.

[0031] In the MOSFET device, an insulating medium is usually filled between adjacent gates to isolate the adjacent gates and prevent short circuit of the gates, which can cause device failure. However, since the particle residues include an upper oxide layer and an underlying polysilicon layer, the particle residues have electrical conductivity. When several particle residues are connected and the particle residues are connected to the gates on both sides, the adjacent gates are short-circuited, which can cause failure of the MOSFET device. That is, the presence of the particle residues increases the risk of failure of the SiC-based MOSFET device.

[0032] Photoetching and etching processes are widely used in the preparation of various functional layers of MOSFET devices. The photoetching process includes the steps of pre-baking, coating, exposure, development and hardening to form a photoresist layer with an etching pattern; the etching process is performed with the photoresist layer as a mask to obtain a functional layer with a corresponding etching pattern. Whether the exposure step in the photoetching process is aligned directly affects the accuracy of the final functional layer.

[0033] In order to obtain an accurate functional layer, before preparing multiple functional layers, it is necessary to first form a plurality of spaced alignment marks arranged periodically on one side surface of the silicon carbide epitaxial layer using photoetching and etching processes, and the projection of the alignment marks on the silicon carbide epitaxial layer is located within the etching area of the polysilicon on the silicon carbide epitaxial layer. The alignment mark is a micron-level recess or protrusion with a height or depth of 0.5 μm-1 μm. Therefore, the etching area of the polysilicon not only includes the protrusions or recesses corresponding to the alignment marks, but also includes a plurality of particle residues, and the surface topography is complex.

[0034] The coating step in the photoetching process forms a photoresist film with an area equal to the size of the upper surface of the semiconductor substrate, and the upper surface of the photoresist film also has the shape of the alignment marks at positions corresponding to the alignment marks; the exposure step in the photoetching process needs to identify the position information of the alignment marks by comparing the reflection gain difference of ultraviolet light at the position of the alignment marks and the positions near the alignment marks through an optical detector, and the photoetching machine needs to identify the position information of most or all of the alignment marks and judge the alignment between the alignment marks and the photoetching plate before exposure, so as to obtain a photoresist layer with no position error of the etching pattern.

[0035] After forming the gate electrode of the MOSFET device, a metal layer with a partial thickness needs to be formed above the gate electrode and between adjacent gate electrodes, and the metal layer is etched by photoetching and etching processes to form a contact metal layer; then the preparation of subsequent functional layers is carried out by photoetching and etching processes. However, the metal layer not only has the topography of the alignment marks, but also has the topography of the particle residues, and the surface of the metal layer itself has a certain roughness, so the surface topography of the metal layer is relatively complex, which has a bad influence on the exposure of the subsequent photoresist layer. Specifically, the particle residues and the roughness of the surface of the metal layer cause no significant difference in the reflection gain of the light path at different positions on the upper surface of the metal layer, which makes it impossible to identify the position of the alignment mark, so that the exposure of the subsequent photoresist layer cannot be carried out normally.

[0036] On this basis, the application provides a preparation method of a MOSFET device, comprising: providing a semiconductor substrate; forming a gate material layer doped with conductive ions on the semiconductor substrate; performing annealing treatment on the gate material layer, the annealing treatment forms an oxide layer on at least part of the surface of the gate material layer away from the semiconductor substrate; after the annealing treatment, performing etching cleaning treatment on the gate material layer to remove the oxide layer; and after removing the oxide layer, etching part of the gate material layer to form a gate electrode layer. The preparation method of the MOSFET device effectively reduces the risk of failure of the MOSFET device.

[0037] The technical solutions of the application will be clearly and completely described below with reference to the drawings. Obviously, the described embodiments are part of the embodiments of the application, rather than all the embodiments. Based on the embodiments in the application, all other embodiments obtained by those skilled in the art without creative work fall within the protection scope of the application.

[0038] Referring to Figure 1 The embodiment provides a preparation method of a MOSFET device, comprising:

[0039] S1, providing a semiconductor substrate;

[0040] S2, forming a gate material layer doped with conductive ions on the semiconductor substrate;

[0041] S3, performing annealing treatment on the gate material layer, the annealing treatment forms an oxide layer on at least part of the surface of the gate material layer away from the semiconductor substrate;

[0042] S4, after the annealing treatment, performing etching cleaning treatment on the gate material layer to remove the oxide layer;

[0043] S5, after removing the oxide layer, etching part of the gate material layer to form a gate electrode layer.

[0044] The preparation method of the MOSFET device removes the oxide layer to expose the gate material layer by performing etching cleaning treatment on the gate material layer after the annealing treatment, thereby avoiding the formation of particle residues between adjacent gate electrodes after etching part of the gate material layer, and further avoiding the short circuit of adjacent gate electrode layers caused by the communication of the adjacent gate electrode layers and the particle residues between the adjacent gate electrode layers, and effectively reducing the risk of failure of the MOSFET device.

[0045] The technical solutions of the application will be clearly and completely described below with reference to the drawings. Obviously, the described embodiments are part of the embodiments of the application, rather than all the embodiments. Based on the embodiments in the application, all other embodiments obtained by those skilled in the art without creative work fall within the protection scope of the application. Figures 2-12 The technical solutions of the application will be clearly and completely described below with reference to the drawings. Obviously, the described embodiments are part of the embodiments of the application, rather than all the embodiments. Based on the embodiments in the application, all other embodiments obtained by those skilled in the art without creative work fall within the protection scope of the application.

[0046] Referring to Figure 2, and a semiconductor substrate is provided.

[0047] Specifically, in one embodiment, referring to Figure 2 , the semiconductor substrate includes a semiconductor substrate 1 and an epitaxial layer 2 located on the semiconductor substrate 1, the semiconductor substrate 1 is a silicon carbide-based substrate, and the epitaxial layer 2 is a silicon carbide-based epitaxial layer. In other embodiments, the semiconductor substrate is the semiconductor substrate 1, which can be a silicon carbide-based substrate.

[0048] Further, before depositing other functional layers on the semiconductor substrate, the semiconductor substrate is cleaned by using the RCA standard cleaning method to remove metal particles, impurity particles, macromolecular particles, natural oxide layers and other impurities on the surface of the semiconductor substrate, improve the interface quality between the semiconductor substrate and other functional layers, reduce the interface state density, improve the channel mobility, and improve the on-state characteristics of the MOSFET device.

[0049] Specifically, the steps of the RCA standard cleaning method include:

[0050] Clean the sample holder and blow dry the cleaned sample for standby;

[0051] Prepare cleaning solution A: first add hydrogen peroxide with a concentration of 30% to container A, then add concentrated sulfuric acid with a concentration of 98.3% to container A, and then heat to 250°C, the volume ratio of concentrated sulfuric acid to hydrogen peroxide is 3:1;

[0052] Prepare cleaning solution B: first mix ammonia water with a concentration of 25% and hydrogen peroxide with a concentration of 30% in container B2, then pour the mixed solution in container B2 into container B1 containing deionized water, and then heat to 75-85°C, the volume ratio of ammonia water, hydrogen peroxide and water is 1:1:(5-7); for example, the heating temperature can be 75°C, 80°C or 85°C, and the volume ratio of ammonia water, hydrogen peroxide and water can be 1:1:5, 1:1:6 or 1:1:7;

[0053] Prepare cleaning solution C: first mix hydrochloric acid with a concentration of 36%-38% and hydrogen peroxide with a concentration of 30% in container C2, then pour the mixed solution in container C2 into container C1 containing deionized water, the volume ratio of concentrated hydrochloric acid, hydrogen peroxide and water is 1:1:5;

[0054] Prepare hydrofluoric acid solution: mix hydrofluoric acid with a concentration of 50% and deionized water in container D, the volume ratio of hydrofluoric acid to deionized water is 1:(20-50);

[0055] Prepare hot water: add deionized water to container E and heat to 40°C;

[0056] Place the semiconductor substrate on the sample holder and immerse in cleaning solution A for 10-20 minutes; illustratively, the soaking time can be 10 minutes, 15 minutes or 20 minutes;

[0057] Subsequently, the semiconductor substrate is taken out and, after slightly cooling, is placed in container E for water flushing;

[0058] Subsequently, the semiconductor substrate is placed in cleaning solution B for 10-20 minutes, and after taking out, is flushed with normal temperature water for 15-20 times; illustratively, the soaking time can be 10 minutes, 15 minutes or 20 minutes, and the water flushing time can be 15 times, 18 times or 20 times;

[0059] Subsequently, the semiconductor substrate is placed in cleaning solution C for 10-20 minutes, and after taking out, is flushed with normal temperature water for 15-20 times; illustratively, the soaking time can be 10 minutes, 15 minutes or 20 minutes, and the water flushing time can be 15 times, 18 times or 20 times;

[0060] Subsequently, the semiconductor substrate is placed in a hydrofluoric acid solution for 5-10 seconds, and after taking out, is flushed with normal temperature water for 15-20 minutes; illustratively, the soaking time can be 5 seconds, 8 seconds or 10 seconds, and the water flushing time can be 15 minutes, 18 minutes or 20 minutes.

[0061] Referring to Figure 3 A gate dielectric material layer 3 is formed on the semiconductor substrate.

[0062] Specifically, the material of the gate dielectric material layer 3 is silicon dioxide, and the thickness of the gate dielectric material layer 3 is 40-60 nm; illustratively, the thickness of the gate dielectric material layer 3 can be 40 nm, 45 nm, 50 nm, 55 nm or 60 nm. The gate dielectric material layer 3 is formed by a dry oxygen oxidation process, and the equipment used includes a vertical furnace tube or a horizontal furnace tube, the oxidation temperature is 1250-1350°C, and after oxidation is completed, nitric oxide annealing is performed, and the annealing environment is NO or N2O environment; illustratively, the oxidation temperature can be 1250°C, 1300°C or 1350°C.

[0063] Referring to Figure 4 A gate material layer 4 doped with conductive ions is formed on the side surface of the gate dielectric material layer 3 away from the semiconductor substrate.

[0064] Specifically, first, a gate material layer without doped conductive ions is formed on the surface of the gate dielectric material layer 3; then, ion implantation is performed on the gate material layer without doped conductive ions to form a gate material layer 4 with doped conductive ions. The material of the gate material layer 4 without doped conductive ions is polysilicon, the thickness of the polysilicon is 300 nm-800 nm, and the polysilicon layer is formed by using a low pressure chemical vapor deposition (LPCVD) process; for example, the thickness of the polysilicon can be 300 nm, 400 nm, 500 nm, 600 nm, 700 nm, or 800 nm. The energy of the ion implantation is 60 keV, the doping elements include but are not limited to phosphorus, and the doping concentration is 1e16 cm-9e16 cm. -2 -9e16cm -2 ; for example, the doping concentration can be 1e16 cm -2 , 3e16 cm -2 , 5e16 cm -2 , 7e16 cm -2 , or 9e16 cm -2 .

[0065] Then, the gate material layer 4 is subjected to an annealing treatment to diffuse the doping elements in the gate material layer 4.

[0066] Specifically, the annealing temperature is 900℃-1000℃, the annealing time is 30 min-40 min, the annealing atmosphere includes argon, and the sheet resistance of the gate material layer 4 after the annealing is 15 Ω / □-18 Ω / □; for example, the annealing time can be 30 min, 35 min, or 40 min, and the sheet resistance of the gate material layer 4 after the annealing can be 15 Ω / □, 16 Ω / □, 17 Ω / □, or 18 Ω / □. After the annealing treatment, an oxide layer is formed on at least part of the surface of the gate material layer 4 away from the semiconductor substrate.

[0067] Referring to Figure 5 , the gate material layer 4 is subjected to an etching cleaning treatment to remove the oxide layer.

[0068] Specifically, the process parameters of the etching cleaning treatment of the gate material layer 4 include that the cleaning solution used is a hydrofluoric acid solution, the volume ratio of hydrofluoric acid to water in the hydrofluoric acid solution is 1:(50-100), the cleaning time is 2 min-15 min, and the cleaning temperature is 25℃-35℃. For example, the volume ratio of hydrofluoric acid to water in the hydrofluoric acid solution can be 1:50, 1:75, or 1:100, the cleaning temperature can be 25℃, 30℃, or 35℃, and the cleaning time can be 2 min, 5 min, 10 min, or 15 min; specifically, the greater the proportion of hydrofluoric acid in the hydrofluoric acid solution and / or the higher the cleaning temperature, the shorter the cleaning time; preferably, the cleaning temperature is 24℃-26℃.

[0069] Further, after the etching cleaning treatment, the gate material layer 4 is subjected to a water washing treatment; after the water washing treatment, water stains on the surface of the MOSFET device are removed.

[0070] Specifically, for a semiconductor substrate with a thickness greater than 200 μm, a water stain removal process of nitrogen blowing and then spinning dry or a water stain removal process of nitrogen blowing and then baking is adopted. In the process, the blowing flow rate is 40-50 sccm, and the blowing time is 2-3 min; for example, the blowing flow rate can be 40, 45 or 50 sccm, and the blowing time can be 2, 2.5 or 3 min. The rotation speed of the spinning dry step is 1000-1500 r / min, and the spinning dry time is 10-15 min; for example, the rotation speed of the spinning dry step is 1000, 1200, 1300 or 1500 r / min, and the spinning dry time is 10, 13 or 15 min. The baking temperature is 70-90 °C, the baking time is 30-40 min, and the baking environment is a nitrogen environment; for example, the baking temperature is 70, 80 or 90 °C, the baking time is 30, 35 or 40 min. For a semiconductor substrate with a thickness less than 200 μm, a water stain removal process of nitrogen blowing and then baking is mainly adopted, and the specific process parameters are described above.

[0071] It should be understood that the etching cleaning treatment cannot be performed by using a buffered oxide etch (BOE). The concentration of hydrofluoric acid in the buffered oxide etch is high, which can not only etch silicon oxide but also damage the underlying polysilicon.

[0072] Referring to Figure 6 A patterned first photoresist layer 6 is formed on the gate material layer 4.

[0073] Specifically, the step of forming the patterned first photoresist layer 6 on the gate material layer 4 includes: coating a first initial photoresist layer on the gate material layer 4; and sequentially performing exposure and development on the first initial photoresist layer to transfer the pattern of a photoetching plate to the first initial photoresist layer, thereby forming the patterned first photoresist layer 6. The first photoresist layer 6 is a positive photoresist, and the thickness of the first photoresist layer 6 is 0.5-2 μm; for example, the thickness of the first photoresist layer 6 can be 0.5, 1, 1.5 or 2 μm.

[0074] Further, before the first initial photoresist layer is exposed, the first initial photoresist layer needs to be baked; after the first initial photoresist layer is developed, the first initial photoresist layer is hardened; during the baking and hardening, the oxygen content in the chamber is less than or equal to 50 ppm, and the temperature is 110-130°C, and an oxygen-free oven can be used. By limiting the oxygen content in the chamber to less than or equal to 50 ppm during baking and hardening, the surface of the gate material layer 4 is prevented from being oxidized during baking and hardening, thereby preventing the formation of particle residues between adjacent gate electrodes after the formation of the gate electrode, and preventing the failure of the etching and cleaning process.

[0075] It should be noted that the time interval between the end time of removing the water stains on the surface of the MOSFET device and the start time of coating the first initial photoresist layer on the gate material layer 4 is less than or equal to 2 hours, so as to prevent the surface of the gate material layer 4 from being oxidized due to a long time in an area with high oxygen content; or, after removing the water stains on the surface of the MOSFET device and before coating the first initial photoresist layer on the gate material layer 4, the MOSFET device is placed in an inert environment or a nitrogen environment to prevent the surface of the gate material layer 4 from being oxidized.

[0076] Referring to Figures 7-8 Part of the gate material layer 4 is etched to form a gate electrode layer 41.

[0077] Specifically, the step of etching part of the gate material layer 4 to form a gate electrode layer 41 includes: referring to Figure 7 The gate material layer 4 is etched until the surface of the gate dielectric material layer 3 is exposed, with the first photoresist layer 6 as a mask; referring to Figure 8 After etching the gate material layer 4, the first photoresist layer 6 is removed.

[0078] Further, part of the gate material layer 4 is etched by a dry etching process. The step of etching part of the gate material layer 4 includes main etching and over-etching after main etching; during the etching of part of the gate material layer 4, the concentration of the reaction product is detected by emission spectroscopy to detect the etching endpoint, and the etching endpoint is the etching endpoint of the main etching.

[0079] It should be understood that the step of etching part of the gate material layer 4 is performed in a closed cavity, the cavity is provided with a reaction gas inlet and a product outlet, and during the etching process, the reaction gas enters the closed cavity through the reaction gas inlet, and the reaction product is discharged through the product outlet. Therefore, before the surface of the gate dielectric material layer 3 is exposed, the concentration of the reaction product is stable, and after the surface of the gate dielectric material layer 3 is exposed, the concentration of the reaction product drops sharply, which is the etching endpoint. The etching endpoint detection is beneficial to control the etching process and realize accurate control of the etching depth. At the same time, by performing over-etching after the etching endpoint, the complete removal of the to-be-removed area in the gate material layer 4 is ensured, and the etching effect is improved.

[0080] Further, the over-etching time is 30s-50s. For example, the over-etching time is 30s, 40s or 50s. The plasma in the cavity has a relatively weak bombardment effect on the exposed surface of the gate dielectric material layer 3. If the over-etching time is too long, the bombardment effect of the plasma will damage the exposed surface of the gate dielectric material layer 3; if the over-etching time is too short, the complete removal of the to-be-etched area of the gate material layer cannot be ensured. By limiting the over-etching time, on the one hand, the complete removal effect of the to-be-etched area of the gate material layer is ensured, and on the other hand, the damage degree of the plasma bombardment to the exposed surface of the gate dielectric material layer is reduced.

[0081] Further, the method for removing the first photoresist layer 6 includes strong oxidizing solution stripping, developing liquid stripping, organic solution stripping and microwave plasma stripping. Among them, the strong oxidizing solution stripping can ensure the stripping effect and avoid affecting the deposition effect of the subsequent functional layer, and the process cost is relatively low, so it is the optimal stripping method. The step of strong oxidizing solution stripping includes soaking the MOSFET device in a mixed solution of sulfuric acid and hydrogen peroxide at high temperature, the volume ratio of sulfuric acid and hydrogen peroxide in the mixed solution is 3:1, and then flushing with normal temperature water. The soaking temperature is 100℃-150℃, the total soaking time is 10min-15min, and the water flushing time is 5min-10min. For example, the soaking temperature can be 100℃, 125℃ or 150℃, the total soaking time can be 10min, 12min or 15min, and the water flushing time can be 5min, 8min or 10min. Preferably, the high-temperature soaking includes first soaking and second soaking, and the time of the first soaking is equal to the time of the second soaking.

[0082] Referring to Figure 9 A metal layer 5 is formed above the gate electrode and between adjacent gate electrodes. Specifically, the material of the metal layer 5 includes but is not limited to aluminum.

[0083] Referring to Figure 10A patterned second photoresist layer 7 is formed above the metal layer 5.

[0084] Specifically, the step of forming the patterned second photoresist layer 7 above the metal layer 5 comprises: coating a second initial photoresist layer above the metal layer 5; and sequentially exposing and developing the second initial photoresist layer to transfer the pattern of the photoetching plate to the second initial photoresist layer, thereby forming the patterned second photoresist layer 7. The second photoresist layer 7 can be a positive photoresist with a thickness of 0.5-2 μm.

[0085] Referring to Figure 11 The metal layer 5 is etched to form a contact metal layer 51.

[0086] Specifically, the step of etching the metal layer 5 to form the contact metal layer 51 comprises: etching the metal layer 5 until the surface of the gate dielectric layer 3 is exposed, with the second photoresist layer 7 as a mask; and removing the second photoresist layer 7 after etching the metal layer 5.

[0087] The method for removing the second photoresist layer 7 is an organic solution stripping method. The steps of the organic solution stripping method comprise sequentially performing first, second and third ultrasonic cleaning on the semiconductor device, and the organic solutions used in the first, second and third ultrasonic cleaning include anhydrous ethanol, acetone and isopropyl alcohol. The organic solution stripping method can ensure the stripping effect and control the stripping cost, and meanwhile, the contact metal layer 51 is not damaged.

[0088] It should be understood that, by performing the etching cleaning treatment on the gate material layer 4 after the annealing treatment, the oxide layer is removed to expose the gate material layer 4, thereby avoiding the formation of particle residues between adjacent gate electrodes after the formation of the gate electrodes. Therefore, in the preparation process of the subsequent functional layers by the photolithography and etching processes, the position of the alignment mark can be accurately identified, and the exposure of the subsequent photoresist layer and the preparation process of the subsequent functional layers can be ensured. Specifically, the subsequent functional layers include an isolation dielectric layer, a passivation dielectric layer, a PI glue insulating layer, etc.

[0089] Obviously, the above embodiments are only examples for clearly illustrating the present application, and are not intended to limit the embodiments. Based on the above description, other different forms of changes or modifications can be made by those skilled in the art. Here, all the embodiments are not required to be exhausted, and the obvious changes or modifications derived therefrom are still within the protection scope of the present application.

Claims

1. A method of fabricating a MOSFET device, characterized by, The application relates to a method for manufacturing a MOSFET device. The method comprises the following steps: providing a semiconductor substrate; forming a gate material layer doped with conductive ions on the semiconductor substrate; carrying out annealing treatment on the gate material layer, which makes the gate material layer form an oxide layer away from at least part of the surface of the semiconductor substrate; carrying out etching cleaning treatment on the gate material layer to remove the oxide layer after the annealing treatment; carrying out water washing treatment on the gate material layer to remove water stains on the surface of the MOSFET device; coating a first initial photoresist layer on the gate material layer; the time interval from the end time of removing the water stains to the start time of coating the first initial photoresist layer is less than or equal to 2 hours; or, the MOSFET device is placed in an inert environment or a nitrogen environment after the water stains are removed and before the first initial photoresist layer is coated; sequentially carrying out exposure and development on the first initial photoresist layer to form a patterned first photoresist layer; carrying out etching on the gate material layer with the first photoresist layer as a mask to form a plurality of gate electrode layers; 2. The method of fabricating a MOSFET device of claim 1, wherein, removing the first photoresist layer.

3. The method of fabricating a MOSFET device of claim 1, wherein, The process parameters of the etching cleaning treatment on the gate material layer include that the cleaning solution used is a hydrofluoric acid solution, the volume ratio of hydrofluoric acid to water in the hydrofluoric acid solution is 1: (50-100), the cleaning time is 2-15 min, and the cleaning temperature is 25-35 DEG C. The application further relates to the following steps: baking the first initial photoresist layer before exposure; and hardening the first initial photoresist layer after development; 4. The method of fabricating a MOSFET device of claim 1, wherein, in the baking and hardening process, the oxygen content in the chamber is less than or equal to 50 ppm, and the temperature is 110-130 DEG C. The application further relates to the following steps: forming a gate dielectric material layer on the semiconductor substrate before forming the gate material layer doped with conductive ions on the semiconductor substrate; carrying out etching on part of the gate material layer until the surface of the gate dielectric material layer is exposed; 5. The method of claim 4, wherein the step of forming the gate oxide layer is performed by thermal oxidation. in the process of carrying out etching on part of the gate material layer, the concentration of reaction products is detected by using an emission spectrum method to detect the etching end point.

6. The method of fabricating a MOSFET device of claim 1, wherein, The step of carrying out etching on part of the gate material layer includes main etching and over-etching after the main etching, the etching end point detected by the emission spectrum method is the etching end point of the main etching, and the time of the over-etching is 30-50 s.

7. The method of fabricating a MOSFET device of claim 1, wherein, In the annealing treatment, the annealing temperature is 900-1000 DEG C, the annealing gas includes argon, and the annealing time is 30-40 min. The semiconductor substrate is a semiconductor substrate; or the semiconductor substrate includes a semiconductor substrate and an epitaxial layer on the semiconductor substrate; the semiconductor substrate is a silicon carbide-based substrate; and the epitaxial layer is a silicon carbide-based epitaxial layer.

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