Composite structures of semiconductor wafers, semiconductor wafers and their fabrication methods and applications

Abstract

This invention discloses a composite structure for a semiconductor wafer, a semiconductor wafer, its fabrication method, and its applications. The semiconductor wafer fabrication method includes: thermally oxidizing SiC on the surface of a first wafer to form a first oxide layer; forming a second oxide layer on the surface of a second wafer, and forming a release layer at a selected depth within the second wafer to separate the first semiconductor layer and the second semiconductor layer, with the second semiconductor layer disposed between the release layer and the second oxide layer; bonding the first oxide layer and the second oxide layer; and removing the first semiconductor layer using the release layer. The semiconductor wafer fabrication method provided by this invention avoids the C contamination problem caused by SiC thermal oxidation, improves the quality of the SiC thermally oxidized layer, reduces SiO2 / SiC interface defects, and improves the channel carrier mobility.

Description

Technical Field

[0001] This invention relates to a silicon carbide wafer, and more particularly to a composite structure of a semiconductor wafer, a semiconductor wafer and its manufacturing method and application, belonging to the field of third-generation semiconductor technology. Background Technology

[0002] Traditional SiC gate dielectric layers use thermally oxidized SiO2. The presence of carbon (C) complicates the chemical reaction process during SiC thermal oxidation, generating byproducts such as C, CO, and SiO. This severely impacts the quality of the SiO2 layer and the SiO2 / SiC interface, resulting in extremely low channel mobility for the fabricated SiC MOSFETs, rarely exceeding 20 cm⁻¹. 2 / Vs(while the bulk mobility of SiC can reach 900cm) 2 / Vs), therefore, the impurities and defects generated during the thermal oxidation process will lead to poor channel performance of SiC MOSFETs. Although the impact is small for devices with a BV of more than 1000 volts, the impact on devices with lower voltages is huge and far exceeds the limit.

[0003] Some existing studies use thin-layer thermal gate oxide to improve interface state defects, and then deposit other media such as alumina (Al2O3) to form an Al2O3 / SiO2 / SiC structure. However, the leakage current of Al2O3 / SiC is significantly greater than that of SiO2 / SiC. Even a 1nm thin layer of SiO2 interlayer cannot significantly improve the gate leakage current problem. Therefore, the thermal oxidation impurities of SiC have a great impact on performance and long-term gate reliability.

[0004] For example, high-voltage MOSFETs require thick gate oxide to meet application requirements, such as... Figure 1 As shown, existing SiO2 dielectrics are generated by thermal oxidation of SiC epitaxy. As the gate oxide layer thickens during thermal oxidation, byproducts such as carbon (C) become less likely to bind with oxygen (O). 2 The C element escapes and remains in the SiO2 / SiC interface as a defect. These defects significantly reduce the carrier mobility of the SiC channel, thus causing a decline in high-frequency performance. Summary of the Invention

[0005] The main objective of this invention is to provide a composite structure for a semiconductor wafer, a semiconductor wafer, its fabrication method, and its applications, in order to overcome the shortcomings of the prior art.

[0006] To achieve the aforementioned objectives, the technical solution adopted by this invention includes:

[0007] This invention provides a method for fabricating a semiconductor wafer, comprising:

[0008] The first oxide layer is formed by thermal oxidation of the SiC surface layer of the first wafer.

[0009] A second oxide layer is formed on the surface of the second wafer, and a release layer is formed at a selected depth within the second wafer, thereby separating a first semiconductor layer and a second semiconductor layer within the second wafer. The second semiconductor layer is disposed between the release layer and the second oxide layer.

[0010] The first oxide layer is bonded to the second oxide layer, and the first semiconductor layer is removed using the release layer.

[0011] Furthermore, both the first oxide layer and the second oxide layer are silicon oxide layers.

[0012] Furthermore, the preparation method specifically includes: bringing an oxygen source gas into contact with a silicon carbide material at a temperature of 1200-1400°C to carry out a thermal oxidation reaction, thereby forming a first oxide layer of a predetermined thickness on the surface of the silicon carbide material, wherein the oxygen source gas includes oxygen, oxygen-containing gas, or water vapor.

[0013] After the thermal oxidation reaction is completed, the silicon carbide material is rapidly cooled to below 300°C.

[0014] Furthermore, the thickness of the first oxide layer is greater than 0 and less than 20 angstroms.

[0015] Furthermore, the thickness of the second oxide layer is above 20 angstroms, preferably 20-2000 angstroms.

[0016] Furthermore, the thickness of the second semiconductor layer is 200 angstroms or more, preferably 200-3000 angstroms.

[0017] Furthermore, the first wafer includes a SiC substrate and a SiC epitaxial layer formed on the SiC substrate, wherein the first oxide layer is formed on the surface of the SiC epitaxial layer.

[0018] Furthermore, the second wafer includes a silicon wafer.

[0019] Furthermore, the second oxide layer is formed by thermal oxidation of the surface layer of the second wafer.

[0020] Furthermore, the preparation method specifically includes: forming the release layer at a selected depth within the second wafer by hydrogen ion implantation.

[0021] Furthermore, the preparation method specifically includes: bonding the first oxide layer and the second oxide layer together using a bonding method.

[0022] Furthermore, the preparation method further includes: removing the first semiconductor layer and then removing the stripping layer remaining on the second semiconductor layer; and / or removing the stripping layer bonded to the removed first semiconductor layer, and then using the first semiconductor layer as a donor wafer.

[0023] Furthermore, the wafer fabrication method further includes: after removing the first semiconductor layer, annealing the obtained semiconductor wafer, wherein the annealing is carried out under any one of N2, NO, and N2O gas atmospheres or a mixed gas atmosphere formed by two or more gases, and the annealing temperature is 900-1700℃ and the time is 5-15h.

[0024] This invention also provides a semiconductor wafer comprising:

[0025] First wafer,

[0026] The first silicon oxide layer is formed by thermal oxidation of SiC on the surface of the first wafer.

[0027] Second semiconductor layer,

[0028] Forming a second silicon oxide layer on the second semiconductor layer,

[0029] The first silicon oxide layer is bonded to the second silicon oxide layer.

[0030] Furthermore, the first silicon oxide layer and the second silicon oxide layer are bonded together.

[0031] Furthermore, the thickness of the first silicon oxide layer is greater than 0 and less than 20 angstroms.

[0032] Furthermore, the thickness of the second silicon oxide layer is above 100 angstroms, preferably 100-2000 angstroms.

[0033] Furthermore, the thickness of the second semiconductor layer is 200 angstroms or more, preferably 200-3000 angstroms.

[0034] Furthermore, the first wafer includes a SiC substrate and a SiC epitaxial layer formed on the SiC substrate, wherein the first silicon oxide layer is formed on the surface of the SiC epitaxial layer.

[0035] Furthermore, the second silicon oxide layer is formed by thermal oxidation of the surface layer of the second semiconductor layer.

[0036] Furthermore, the second semiconductor layer is obtained by separating it from the second wafer.

[0037] Furthermore, the second wafer includes a silicon wafer.

[0038] This invention also provides a composite structure for a semiconductor wafer, comprising the aforementioned semiconductor wafer; wherein a second silicon oxide layer is formed on a first surface of the second semiconductor layer, and a release layer and a first semiconductor layer are sequentially bonded to a second surface opposite to the first surface.

[0039] Furthermore, the first semiconductor layer, the release layer, and the second semiconductor layer are all distributed in the second wafer, the second silicon oxide layer is formed on the surface of the first wafer, and the release layer is formed at a predetermined depth within the second wafer.

[0040] Furthermore, the stripping layer is formed by hydrogen ion implantation into the second wafer.

[0041] This invention also provides the use of the semiconductor wafer or the composite structure of the semiconductor wafer in the fabrication of semiconductor chips.

[0042] Compared with the prior art, the advantages of the present invention include:

[0043] 1) The semiconductor wafer fabrication method provided in this embodiment of the invention avoids the C contamination problem caused by SiC thermal oxidation, improves the quality of the SiC thermal oxidation layer, reduces SiO2 / SiC interface defects, and improves the mobility of semiconductor wafer channel carriers.

[0044] 2) The semiconductor wafer fabrication method provided in this embodiment of the invention provides a high-quality thermally oxidized silicon gate dielectric layer for SiC;

[0045] 3) The semiconductor wafer fabrication method provided in this embodiment of the invention allows the residual silicon layer after thinning to be directly bonded to the thermally oxidized silicon gate dielectric layer. It has few defects and can be used to replace the polysilicon gate. Attached Figure Description

[0046] Figure 1 This is a schematic diagram illustrating the structure and fabrication principle of a traditional SiC wafer;

[0047] Figure 2 This is a schematic diagram of the structure of a silicon donor wafer provided in a typical embodiment of the present invention;

[0048] Figure 3 This is a schematic diagram of the silicon carbide-supported wafer structure provided in a typical embodiment of the present invention;

[0049] Figure 4 This is a schematic diagram of the structure of a silicon carbide wafer with high-quality thick gate oxide provided in a typical embodiment of the present invention;

[0050] Figure 5 This is a schematic diagram of the structure of a SiC LDMOS device provided in a typical embodiment of the present invention;

[0051] Figures 6a-6i This is a schematic diagram of the fabrication process of a silicon carbide wafer with high-quality thick gate oxide provided in a typical embodiment of the present invention.

[0052] Figure 7 Channel mobility curves of a SiC MOSFET device with a 10 Å thin gate oxide in Embodiment 1 of the present invention and a SiC MOSFET device with a 100 Å thick gate oxide in Comparative Example 1. Detailed Implementation

[0053] In view of the shortcomings of the prior art, the inventors of this invention, through long-term research and extensive practice, have proposed the technical solution of this invention. The following will further explain and illustrate this technical solution, its implementation process, and its principles.

[0054] Silicon carbide (SiC) is a wide-bandgap, high-thermal-conductivity third-generation semiconductor material widely used in rail transportation, new energy vehicles, power grids, aerospace, radar, microwave base stations, and other fields. For example, SiC MOSFETs, SiC IGBTs, SiC LDMOS, and SiCVDMOS devices are widely used in high-voltage power conversion and power systems. They are mainly used to manufacture devices such as power control units, inverters, DC-DC converters, and power amplifiers.

[0055] This invention provides a method for fabricating a high-quality gate oxide layer (gate oxide) on a SiC wafer. First, the SiC surface layer of a first wafer is thermally oxidized to form an extremely thin first oxide layer. Then, a second oxide layer is formed on the surface of a second wafer. Next, a release layer is formed at a selected depth within the second wafer to separate a first semiconductor layer and a second semiconductor layer within the second wafer. The second semiconductor layer is disposed between the release layer and the second oxide layer. Then, the first oxide layer and the second oxide layer are bonded together to form a thick gate oxide layer. Finally, the first semiconductor layer is removed using the release layer, thereby achieving the fabrication of a high-quality gate oxide layer (gate oxide) on the SiC wafer.

[0056] The fabrication method provided in this invention can significantly improve the carrier mobility at the SiC wafer interface, thereby significantly improving the high-frequency performance of SiC devices (MOSFET, IGBT, VDMOS, and LDMOS, etc.) and providing broader scope for the aforementioned existing commercial applications.

[0057] This invention provides a method for fabricating silicon carbide wafers with high-quality thick gate oxide, which significantly reduces SiO2 / SiC interface defects, improves channel carrier mobility, and thus enhances the high-frequency performance of devices fabricated based on this wafer. Furthermore, this method can achieve arbitrary thicknesses of the SiO2 dielectric layer over a wide range, solving the problems of gate leakage and long-term reliability issues caused by high gate voltage. Moreover, this method can be used to achieve large-scale mass production using existing silicon production line equipment, reducing the challenges of industrialization and widespread adoption.

[0058] The following will further explain the technical solution, its implementation process and principle in conjunction with the accompanying drawings and specific implementation examples. Unless otherwise specified, the epitaxial growth, thinning, polishing and other processes used in the embodiments of the present invention can all be those known to those skilled in the art.

[0059] The inventors of this case discovered that when the surface layer of SiC is oxidized using thermal oxidation, and the thickness of the resulting SiO2 layer is less than 20 angstroms, gas flow and impurities below the SiO2 layer can easily diffuse through it. Byproducts generated during the thermal oxidation process are less likely to remain within the SiO2 layer or the SiO2 / SiC interface, resulting in a very clean SiO2 layer and SiO2 / SiC interface, with a defect density that can be controlled to within 102. 11 cm -2 Below this, carrier mobility can reach 300 cm⁻¹. 2 / Vs, or even higher.

[0060] The method for fabricating a high-quality thick gate oxide silicon carbide wafer provided in this invention involves several steps to create a high-quality thick gate oxide SiO2 layer.

[0061] In a more specific embodiment, a method for fabricating a silicon carbide wafer with high-quality thick gate oxide specifically includes the following steps:

[0062] 1) A first SiO2 layer (or first thermally oxidized SiO2 layer) with a thickness of less than 20 angstroms is formed on the surface of the SiC wafer by thermal oxidation. The SiC wafer after thermal oxidation is called a support wafer or SiC support wafer, and its structure is as follows: Figure 2 As shown;

[0063] 2) A second SiO2 layer (or second thermally oxidized SiO2 layer) with a thickness of 600-1000 angstroms is formed on the surface of a silicon wafer by means of thermal oxidation or thin film deposition (e.g., chemical deposition and physical deposition). Then, hydrogen ions are implanted from the side of the silicon wafer opposite to the second SiO2 layer to form an ion implantation layer at a selected depth on the silicon wafer. This ion implantation layer serves as a release layer for subsequent silicon wafer stripping. The silicon wafer is called a donor wafer or Si donor wafer.

[0064] 3) The first SiO2 layer of the SiC support wafer is brought into contact with the second SiO2 layer of the Si donor wafer, and the SiC support wafer and the Si donor wafer are bonded together. The first and second SiO2 layers combine to form a thick gate oxide layer. Then, at an ambient temperature of 400-600℃, a portion of the silicon wafer is peeled away from the H+ implantation layer (Smart Cut technology), thereby obtaining the desired result. Figure 4 The silicon carbide wafer shown has a high-quality thick gate oxide.

[0065] Specifically, the method for forming a first SiO2 layer with a thickness of less than 20 angstroms on the surface of a SiC wafer by thermal oxidation in this embodiment of the invention may include the following two methods:

[0066] In some more specific implementation examples, a method for thermal oxidation of the surface layer of a SiC wafer includes:

[0067] The SiC wafer is placed in the reaction chamber;

[0068] A protective gas supply mechanism is used to introduce a protective gas into the reaction chamber to isolate oxygen and water vapor. Then, while maintaining a positive atmospheric pressure in the reaction chamber, a heating mechanism is used to rapidly raise the temperature in the reaction chamber to 1200-1400°C. Finally, an oxygen source gas supply mechanism is used to introduce oxygen source gas preheated to 1200-1400°C into the reaction chamber to carry out the thermal oxidation reaction.

[0069] After the thermal oxidation reaction is completed, while keeping the temperature inside the reaction chamber constant, stop feeding oxygen into the reaction chamber, and at the same time feed protective gas preheated to 1200-1400°C into the reaction chamber through the protective gas supply mechanism to purge oxygen from the reaction chamber.

[0070] Heating of the reaction chamber is stopped, and a protective gas at room temperature is introduced into the reaction chamber through a protective gas supply mechanism to rapidly cool the SiC wafer to below 300°C.

[0071] Furthermore, the protective gas includes, but is not limited to, nitrogen and / or inert gases.

[0072] Furthermore, the method specifically includes: maintaining the pressure in the reaction chamber above 1.05 atm, and raising the temperature in the reaction chamber to 1200-1400℃ at a heating rate of 10-50℃ / s.

[0073] Furthermore, the method specifically includes rapidly reducing the temperature of the SiC wafer to below 300°C under vacuum conditions.

[0074] Furthermore, the method specifically includes rapidly reducing the temperature of the SiC wafer to below 300°C at a cooling rate of 100-400°C / s.

[0075] In some more specific implementation examples, a method for thermal oxidation of the surface layer of a SiC wafer includes:

[0076] The SiC wafer is placed in the reaction chamber;

[0077] The reaction chamber is evacuated using a vacuum generator to remove the air from it;

[0078] The SiC wafer is heated in a vacuum environment to rapidly raise its temperature to 1000-1400°C. Then, oxygen source gas preheated to 1000-1400°C is introduced into the reaction chamber by an oxygen source supply mechanism to carry out the thermal oxidation reaction.

[0079] After the thermal oxidation reaction is completed, while keeping the temperature inside the reaction chamber constant, stop feeding oxygen gas into the reaction chamber, and at the same time use a vacuum generator to evacuate the reaction chamber again.

[0080] Heating of the reaction chamber is stopped, and gas as a cooling medium is introduced into the reaction chamber through a cooling medium supply mechanism to rapidly cool the SiC wafer to below 300°C.

[0081] Furthermore, the gas used as the cooling medium is a gas at room temperature.

[0082] Furthermore, the gas used as the cooling medium includes any one or a combination of two or more of nitric oxide, nitrogen, and inert gases, but is not limited thereto.

[0083] Furthermore, the protective gas includes, but is not limited to, nitrogen and / or inert gases.

[0084] Furthermore, the method specifically includes raising the temperature in the reaction chamber to 1000-1400°C at a heating rate of 10-50°C / s.

[0085] Furthermore, the method specifically includes: rapidly cooling the SiC wafer to below 300°C under vacuum conditions.

[0086] Furthermore, the method specifically includes rapidly reducing the temperature of the SiC wafer to below 300°C at a cooling rate of 100-400°C / s.

[0087] This invention forms a high-quality ultrathin SiO2 layer on the SiC epitaxial interface, while the thick SiO2 is provided by a silicon donor wafer. The donor wafer has a 200-3000 angstrom silicon layer remaining on its surface for manufacturing the gate to replace the polysilicon gate. The remaining silicon donor wafer can be reused after CMP (polishing) and is called a new donor wafer.

[0088] Specifically, the thick gate oxide layer of the silicon carbide wafer obtained by this invention is mostly provided by silicon donor wafers, while the ultrathin SiO2 at the interface is obtained by the thermal oxidation of SiC itself. This not only ensures the thick gate oxide requirement for high voltage applications, but also greatly reduces the defect density at the SiO2 / SiC interface, thereby increasing the carrier mobility of the channel. The thermal oxidation of the silicon donor wafer and the final silicon wafer stripping can be carried out using existing silicon wire equipment, thus enabling large-scale mass production.

[0089] The silicon carbide wafer with high-quality thick gate oxide prepared by this invention can be used to manufacture SiC MOSFETs, SiCVDMOS, SiC LDMOS and SiC IGBTs, etc.

[0090] Example 1

[0091] A method for fabricating a silicon carbide wafer with high-quality thick gate oxide specifically includes the following steps:

[0092] 1) Please refer to Figure 6a The silicon carbide wafer is provided, the silicon carbide wafer comprising a silicon carbide substrate and a silicon carbide epitaxial layer stacked sequentially, and the surface of the silicon carbide epitaxial layer is oxidized by thermal oxidation to form a first silicon oxide layer with a thickness of 10 angstroms.

[0093] 2) Please refer to Figure 6b A silicon wafer is provided, and a second silicon oxide layer with a thickness of 800 angstroms is formed by oxidizing the surface of the silicon wafer by thermal oxidation.

[0094] 3) Please refer to Figure 6c Hydrogen ion implantation is performed on the silicon wafer from the side surface opposite to the second silicon oxide layer to a depth of 3000 angstroms, thereby forming a hydrogen ion implantation layer inside the silicon wafer. The hydrogen ion implantation layer separates the silicon wafer to form a first silicon layer and a second silicon layer. The hydrogen ion implantation layer will be used as a stripping layer for peeling off thick silicon wafers or silicon wafers.

[0095] 4) Please refer to Figure 6d and Figure 6eThe silicon wafer processed in step 3) is used as the donor wafer, and the silicon carbide wafer processed in step 1) is used as the support wafer. The donor wafer is flipped and the second silicon oxide layer is aligned with the first silicon oxide layer. Then wafer bonding is performed so that the second silicon oxide layer and the first silicon oxide layer are combined to form a thick gate oxide layer.

[0096] 5) Using Smart Cut technology, the first silicon layer is peeled off from the hydrogen ion implantation layer at 400-600℃ to obtain... Figure 6f The silicon donor wafer (i.e., the first silicon layer and part of the hydrogen ion implantation layer) and the SiC support wafer shown are then subjected to high-temperature rapid annealing to remove residual hydrogen in the thick gate oxide layer, thereby improving the fusion degree of the interface between the first silicon oxide layer and the second silicon oxide layer. The remaining second silicon layer with a thickness of 200-3000 angstroms replaces the polysilicon as the gate. The high-temperature rapid annealing is carried out in any one of the gas atmospheres of N2, NO, and N2O or a mixed gas atmosphere formed by two or more gases. The temperature of the high-temperature rapid annealing is 900-1700℃ and the time is 5-15h.

[0097] 6) The silicon donor wafer obtained in step 5) is processed using methods such as chemical mechanical polishing (CMP) to obtain the following: Figure 6g The silicon wafer shown can be reused as a donor wafer. The SiC support wafer obtained in step 5) is processed using methods such as chemical mechanical polishing (CMP) to remove the residual hydrogen ion implantation layer on the top stripped surface, resulting in the wafer shown. Figure 6h The silicon carbide wafer shown can have its second silicon layer processed into a gate in subsequent processing. If the quality requirements of the device are not high, the CMP process can be omitted, and silicide can be directly generated to improve the resistivity of the gate.

[0098] 7) such as Figure 6i As shown, the second silicon layer on the top layer of the silicon carbide wafer is patterned using etching and other methods to form the gate of the silicon carbide device.

[0099] 8) Based on the epitaxial structure formed in step 7, it is processed to form such as Figure 5The SiC-based enhancement-mode RFLDMOS device shown is as follows: 11 is a SiC-based P-type heavily doped substrate, 12 is a SiC-based P-type epitaxial layer, 21 is a SiC-based N-type drift region, 22 is a SiC-based N-type heavily doped source region, 23 is a SiC-based N-type heavily doped drain region, 25' is a SiC-based P-type well region, 26 is a SiC-based P-type heavily doped region, 31 is a gate oxide layer, 32 is a silicon gate, 33 is a metal SiC compound used to connect the source region and the source region metal electrode, 34 is a gate sidewall, 35 is a field plate, 41 is a conductive channel connecting the source and the substrate (in this example, it is a tungsten plug via), 42 is a contact hole metal, 51 is an insulating dielectric layer, and 61 is a metal electrode.

[0100] The method for fabricating a SiC-based enhancement-mode RF LDMOS device provided in this embodiment of the invention mainly includes the following steps: forming an N-type doped channel region, an offset region, a source region, and a drain region within a SiC-based P-type epitaxial layer, specifically as follows: A SiC wafer is obtained using the method provided in this embodiment of the invention, such as... Figure 5 As shown, the SiC-based p-type epitaxial layer 12 has a thickness of 2-20 μm and is extended on a heavily doped SiC substrate 11. The gate oxide thickness of SiC is 155 Å and the silicon layer thickness is 3000 Å.

[0101] 2) The silicon gate 32 is formed using photolithography and etching;

[0102] 3) Using photolithography and implantation processes, N-type particles are implanted into the SiC-based P-type lightly doped epitaxial layer 12 to form a SiC-based N-type drift region;

[0103] 4) P-type impurities are implanted into the SiC-based P-type lightly doped epitaxial layer 12 using photolithography and implantation processes to form a SiC-based P-type well region 25';

[0104] 5) Using photolithography and implantation processes, N-type impurities are implanted into the SiC-based P-type lightly doped epitaxial layer 12 to form a heavily doped SiC-based N-type heavily doped source region 22 and a SiC-based N-type heavily doped drain region 23.

[0105] Tests revealed that, compared to Si LDMOS devices, the SiC LDMOS device exhibits a 6-fold increase in heat transfer coefficient and a 6-fold increase in breakdown voltage, while maintaining comparable carrier mobility. Therefore, the SiC LDMOS device can operate at higher voltages and frequencies. Furthermore, the SiC LDMOS device boasts higher output power density, amplification efficiency, and linearity, along with excellent heat dissipation performance, thus minimizing its thermal impact on the system.

[0106] Comparative Example 1

[0107] The preparation method of a silicon carbide wafer with high-quality thick gate oxide in Comparative Example 1 is basically the same as that in Example 1, except that: Comparative Example 1 uses thermal oxidation to oxidize the surface layer of the silicon carbide epitaxial layer to form a first silicon oxide layer with a thickness of 100 angstroms.

[0108] The channel mobility curves of SiC LDMOS devices with 10 Å thin gate oxide and 100 Å thick gate oxide, as tested, are shown below. Figure 7 As shown, the electron mobility of the SiC LDMOS devices in Example 1 and Comparative Example 1 is 300 cm⁻¹. 2 / (VS) and from 58cm 2 / (VS), which fully demonstrates that the thermal oxidation of thin gate oxide at the silicon carbide interface is the key to forming a high-quality, low-defect channel.

[0109] Comparative Example 2

[0110] A method for preparing a silicon carbide wafer, such as Figure 1 As shown, the surface of the silicon carbide wafer is directly oxidized using the traditional thermal oxidation method to form a gate oxide layer with a thickness of 800 angstroms; however, in the traditional SiC thermal oxidation process, the following reactions inevitably occur: (a) SiC + O2 → SiO2(s) + C(s); (b) SiC + O2 → SiO(g) + CO.

[0111] Both reactions lead to channel interface defects. In the early stages of SiC thermal oxidation, the typical oxide layer thickness is less than 10 Å. C (carbon), SiO (silicon monoxide), and these byproducts can continue to oxidize. After oxidation, C escapes from the SiC interface in gaseous form, resulting in fewer defects at this stage. However, as thermal oxidation continues until an 800 Å gate oxide layer is formed, a large amount of C remains in the gate oxide, leading to poor gate oxide quality and a channel carrier mobility as low as 20 cm⁻¹. 2 / (VS), thus the devices manufactured on this basis have very poor high-frequency characteristics.

[0112] Comparative Example 3

[0113] The preparation method of silicon carbide wafers in Comparative Example 3 is basically the same as that in the Examples, except that step 1) of Comparative Example 3 is as follows:

[0114] 1) A silicon carbide wafer is provided, the silicon carbide wafer comprising a silicon carbide substrate and a silicon carbide epitaxial layer stacked sequentially, and a first silicon oxide layer with a thickness of 30 angstroms is formed by thermal oxidation treatment on the surface of the silicon carbide epitaxial layer; after testing, the gate oxide layer obtained in Comparative Example 3 has low electron mobility, poor quality and many defects, and the device performance is close to that of the device obtained by conventional methods.

[0115] Comparative Example 4

[0116] The preparation method of silicon carbide wafers in Comparative Example 4 is basically the same as that in the Example, except that step 5) of Comparative Example 4 is as follows: 5) Smart Cut technology is used to peel off the silicon wafer from the hydrogen ion implantation layer at 400-600℃, and the silicon wafer is separated to obtain... Figure 6f The diagram shows a silicon donor wafer and a SiC support wafer, but the separated SiC support wafer is not subjected to high-temperature rapid annealing. Testing showed that the gate oxide layer obtained in Comparative Example 4 had low electron mobility, poor quality, and many defects, but its device performance was close to that obtained by conventional methods.

[0117] It should be noted that the second SiO2 layer in the embodiments of the present invention can be formed by conventional thermal oxidation process, or by chemical deposition and physical deposition, etc. The formation process of the second SiO2 layer is not specifically limited here. In the embodiments of the present invention, hydrogen implantation (Smart Cut) method is mainly used for the top silicon wafer peeling. Of course, those skilled in the art can also use other silicon wafer peeling technology to achieve the peeling of the top silicon wafer, such as porous silicon peeling technology, Sim Split (200810038335.7) technology, etc., which are not specifically limited here.

[0118] The semiconductor wafer fabrication method provided by this invention avoids the C contamination problem caused by SiC thermal oxidation, improves the quality of the SiC thermal oxidation layer, reduces SiO2 / SiC interface defects, and improves the channel carrier mobility; and the semiconductor wafer fabrication method provided by this invention provides a high-quality thermally oxidized silicon gate dielectric layer for SiC.

[0119] The present invention provides a method for fabricating a semiconductor wafer in which the residual silicon layer after thinning treatment can be directly bonded to the thermally oxidized silicon gate dielectric layer. It has few defects and can be used to replace the polysilicon gate.

[0120] It should be understood that the above embodiments are merely illustrative of the technical concept and features of the present invention, and are intended to enable those skilled in the art to understand the content of the present invention and implement it accordingly. They should not be construed as limiting the scope of protection of the present invention. All equivalent changes or modifications made in accordance with the spirit and essence of the present invention should be covered within the scope of protection of the present invention.

Claims

1. A method for fabricating a semiconductor wafer, characterized in that... include: The SiC surface layer of the first wafer is thermally oxidized to form a first oxide layer, the thickness of which is greater than 0 and less than 20 angstroms. The surface of the second wafer is thermally oxidized to form a second oxide layer with a thickness of more than 20 angstroms. A release layer is formed at a selected depth within the second wafer to separate a first semiconductor layer and a second semiconductor layer within the second wafer. The second semiconductor layer is disposed between the release layer and the second oxide layer. The first oxide layer and the second oxide layer are combined, and the first semiconductor layer is removed using the release layer. The second wafer includes a silicon wafer, and both the first oxide layer and the second oxide layer are silicon oxide layers.

2. The preparation method according to claim 1, characterized in that... Specifically, it includes: An oxygen source gas is brought into contact with a silicon carbide material at a temperature of 1200-1400°C to carry out a thermal oxidation reaction, thereby forming a first oxide layer of predetermined thickness on the surface of the silicon carbide material. The oxygen source gas includes oxygen, oxygen-containing gas, or water vapor. After the thermal oxidation reaction is completed, the silicon carbide material is rapidly cooled to below 300°C.

3. The preparation method according to claim 1, characterized in that: The thickness of the second oxide layer is 20-2000 angstroms.

4. The preparation method according to claim 1, characterized in that: The thickness of the second semiconductor layer is more than 200 angstroms.

5. The preparation method according to claim 4, characterized in that: The thickness of the second semiconductor layer is 200-3000 angstroms.

6. The preparation method according to claim 1, characterized in that: The first wafer includes a SiC substrate and a SiC epitaxial layer formed on the SiC substrate, wherein the first oxide layer is formed on the surface of the SiC epitaxial layer.

7. The preparation method according to claim 1, characterized in that... Specifically, it includes: The release layer is formed at a selected depth within the second wafer by hydrogen ion implantation.

8. The preparation method according to claim 1, characterized in that... Specifically, it includes: The first oxide layer and the second oxide layer are bonded together using a bonding method.

9. The preparation method according to claim 1, characterized in that... It also includes: removing the stripping layer remaining on the second semiconductor layer after removing the first semiconductor layer; and / or removing the stripping layer bonded to the removed first semiconductor layer, and then using the first semiconductor layer as a donor wafer.

10. The wafer fabrication method according to claim 1, characterized in that... It also includes: after removing the first semiconductor layer, annealing the obtained semiconductor wafer, wherein the annealing is carried out under any one of the gas atmospheres of N2, NO, and N2O or a mixed gas atmosphere formed by two or more gases, and the annealing temperature is 900-1700℃ and the time is 5-15h.

11. A semiconductor wafer, characterized in that... include: First wafer, A first silicon oxide layer is formed by thermal oxidation of SiC on the surface of a first wafer, and the thickness of the first silicon oxide layer is greater than 0 and less than 20 angstroms; A second semiconductor layer is obtained by separating a second wafer, the second wafer comprising a silicon wafer; A second silicon oxide layer is formed on the second semiconductor layer. The second silicon oxide layer is formed by thermal oxidation of the surface layer of the second semiconductor layer. The thickness of the second silicon oxide layer is greater than 100 angstroms. The first silicon oxide layer is bonded to the second silicon oxide layer.

12. The semiconductor wafer according to claim 11, characterized in that: The first silicon oxide layer and the second silicon oxide layer are bonded together.

13. The semiconductor wafer according to claim 11, characterized in that: The thickness of the second silicon oxide layer is 100-2000 angstroms.

14. The semiconductor wafer according to claim 11, characterized in that: The thickness of the second semiconductor layer is more than 200 angstroms.

15. The semiconductor wafer according to claim 14, characterized in that: The thickness of the second semiconductor layer is 200-3000 angstroms.

16. The semiconductor wafer according to claim 11, characterized in that: The first wafer includes a SiC substrate and a SiC epitaxial layer formed on the SiC substrate, wherein the first silicon oxide layer is formed on the surface of the SiC epitaxial layer.

17. A composite structure for a semiconductor wafer, characterized in that... The semiconductor wafer includes any one of claims 11-16; wherein a second silicon oxide layer is formed on the first surface of the second semiconductor layer, and a release layer and a first semiconductor layer are sequentially bonded to the second surface opposite to the first surface.

18. The composite structure of the semiconductor wafer according to claim 17, characterized in that: The first semiconductor layer, the release layer, and the second semiconductor layer are all distributed in the second wafer. The second silicon oxide layer is formed on the surface of the first wafer, and the release layer is formed at a predetermined depth within the second wafer.

19. The composite structure of the semiconductor wafer according to claim 18, characterized in that: The stripping layer is formed by hydrogen ion implantation into a second wafer.

20. Use of the semiconductor wafer of any one of claims 11-16 or the composite structure of the semiconductor wafer of any one of claims 17-19 in the fabrication of a semiconductor chip.

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