A semiconductor structure and a manufacturing method thereof

Abstract

The present invention provides a semiconductor structure and a manufacturing method thereof. The manufacturing method includes steps of forming a hard mask layer, etching a first trench, forming a first insulating layer, etching a third trench, forming a second insulating layer, and planarizing the second insulating layer. Wherein, before etching the third trench, after forming the first insulating layer, a second isolation layer is removed, a part of the first insulating layer protruding from the first isolation layer forms a raised portion, and a fourth isolation layer covering the upper surface of the first isolation layer and the raised portion is formed. And the fourth isolation layer forms a second trench between two adjacent raised portions. Then, a second photoresist layer is filled in the second trench, and the third trench is etched by using a self-aligned shallow isolation insulating trench etching process. By redesigning the process steps before etching the shallow isolation insulating trench, the present invention eliminates the steps of manufacturing the mask for forming the shallow isolation insulating trench and the alignment step of the mask, reducing the process complexity and manufacturing cost of manufacturing the semiconductor insulating layer.

Description

Technical Field

[0001] The present invention belongs to the technical field of semiconductor integrated circuit manufacturing, and relates to a semiconductor structure and a manufacturing method thereof. Background Art

[0002] With the development of semiconductor integration technology, for the BCD (Bipolar CMOS DMOS) process of monolithic integration technology, due to the large variety of devices in this process, it is necessary to achieve the compatibility of high-voltage devices and low-voltage devices, and also the compatibility of bipolar process and CMOS process. Therefore, the isolation technology of this process is particularly important.

[0003] The BCD process often uses a semiconductor insulating layer to make the bipolar process and the CMOS process compatible. During the manufacturing process of the semiconductor insulating layer, in order to fill the substances in the isolation insulating trenches to form better isolation and better breakdown voltage performance, a combination of deep isolation insulating trenches and shallow isolation insulating trenches is often used. Currently, the manufacturing of deep isolation insulating trenches and shallow isolation insulating trenches requires two photomasks. After forming the deep isolation insulating trenches using the photomask of the deep isolation insulating trench pattern, it is also necessary to align the photomask of the shallow isolation insulating trench pattern, and the error needs to be controlled during alignment, which greatly increases the process complexity and manufacturing cost of manufacturing the insulating layer.

[0004] Therefore, there is an urgent need to find a manufacturing method of an insulating layer that can avoid the error caused by alignment, has a simple process and a low manufacturing cost. Summary of the Invention

[0005] In view of the above-mentioned disadvantages of the prior art, the purpose of the present invention is to provide a manufacturing method of a semiconductor structure, which is used to solve the problems of high cost, inability to avoid alignment error and complex manufacturing process in the manufacturing of semiconductor insulating layers in the prior art.

[0006] To achieve the above purpose and other related purposes, the present invention provides a semiconductor manufacturing method, including the following steps:

[0007] Provide a substrate, and form a hard mask layer on the substrate. The hard mask layer includes a first isolation layer, a second isolation layer and a third isolation layer from bottom to top in sequence;

[0008] Form a first photoresist layer on the upper surface of the hard mask layer, and pattern the hard mask layer;

[0009] Remove the first photoresist layer, and form a plurality of first trenches in the substrate based on the patterned hard mask layer;

[0010] A first insulating layer is formed, which fills into the first trench and covers the upper surface of the hard mask layer. The first insulating layer is planarized until the second isolation layer is exposed, and the second isolation layer is removed. The portion of the first insulating layer protruding from the first isolation layer constitutes a raised portion;

[0011] A fourth isolation layer is formed, which covers the upper surface of the first isolation layer and the raised portion, and the fourth isolation layer forms a second trench between two adjacent raised portions;

[0012] A second photoresist layer is filled into the second trench, and a third trench is formed by self-alignment based on the second photoresist layer. The third trench vertically penetrates the fourth isolation layer, the first isolation layer, and extends into the substrate. The bottom surface of the third trench is higher than the bottom surface of the first trench, and the bottom surface of the third trench exposes the first insulating layer;

[0013] A second insulating layer is formed in the third trench to form a shallow trench isolation structure, and the first insulating layer in the first trench forms a deep trench isolation structure.

[0014] Optionally, the substrate includes a silicon substrate, the material of the first isolation layer includes silicon oxide, the material of the second isolation layer includes silicon nitride, and the material of the third isolation layer includes silicon oxide.

[0015] Optionally, during the formation of the first trench, the third isolation layer is also partially etched.

[0016] Optionally, the thickness of the third isolation layer is greater than the thickness of the first isolation layer.

[0017] Optionally, the method for forming the first trench includes dry etching.

[0018] Optionally, the width-depth ratio of the first trench is greater than 10, and the depth is 8 μm to 12 μm.

[0019] Optionally, the method for planarizing the first insulating layer includes chemical mechanical polishing, and the method for removing the second isolation layer includes wet etching.

[0020] The present invention also provides a semiconductor structure, wherein the semiconductor structure is fabricated by using the manufacturing method of the semiconductor structure described in any one of the above, and includes:

[0021] A substrate;

[0022] A shallow trench isolation structure located in the substrate;

[0023] A deep trench isolation structure is located in the substrate, and the top of the deep trench isolation structure is connected to the bottom of the shallow trench isolation structure.

[0024] Optionally, the depth of the shallow trench isolation structure is greater than one twentieth of the depth of the deep trench isolation structure and less than the depth of the deep trench isolation structure.

[0025] Optionally, the width of the shallow trench isolation structure is greater than the width of the deep trench isolation structure.

[0026] As described above, a semiconductor structure and a manufacturing method thereof according to the present invention re - design the manufacturing process steps of a semiconductor, remove the second isolation layer, make the part of the first insulating layer protruding from the first isolation layer form a convex part, and form a fourth isolation layer, so that the fourth isolation layer covers the upper surface of the first isolation layer and the convex part, and the fourth isolation layer forms a second trench between two adjacent convex parts. Then, a second photoresist layer is filled in the second trench, and then the third trench is etched. The manufacturing of the mask for forming the third trench and the mask alignment steps are omitted, reducing the process complexity and manufacturing cost of forming the insulating layer. In addition, through the combination of the third trench and the first trench, the problem of filling defects at the bottom of the trench can be effectively avoided, improving the breakdown voltage performance of semiconductor devices, and having high industrial utilization value. Description of the Drawings

[0027] Figure 1 It shows a schematic cross - sectional structure diagram of a semiconductor structure according to the present invention.

[0028] Figure 2 It shows a flowchart of a manufacturing method of a semiconductor structure according to the present invention.

[0029] Figure 3 It shows a schematic diagram of a substrate provided by a manufacturing method of a semiconductor structure according to the present invention.

[0030] Figure 4 It shows a schematic diagram of forming a first isolation layer in a manufacturing method of a semiconductor structure according to the present invention.

[0031] Figure 5 It shows a schematic diagram of forming a second isolation layer and a third isolation layer in a manufacturing method of a semiconductor structure according to the present invention.

[0032] Figure 6 It shows a schematic diagram of patterning a hard mask layer in a manufacturing method of a semiconductor structure according to the present invention.

[0033] Figure 7 It shows a schematic diagram of performing a first trench etching on a substrate in a manufacturing method of a semiconductor structure according to the present invention.

[0034] Figure 8Schematic diagram showing the filling of a first insulating layer in a first trench in the manufacturing method of the semiconductor structure according to the present invention.

[0035] Figure 9 Schematic diagram showing the removal of a third isolation layer in the manufacturing method of the semiconductor structure according to the present invention.

[0036] Figure 10 Schematic diagram showing the removal of a second isolation layer in the manufacturing method of the semiconductor structure according to the present invention.

[0037] Figure 11 Schematic diagram showing the formation of a fourth isolation layer in the manufacturing method of the semiconductor structure according to the present invention.

[0038] Figure 12 Schematic diagram showing the filling of a second photoresist layer in the manufacturing method of the semiconductor structure according to the present invention.

[0039] Figure 13 Schematic diagram showing the self-aligned formation of a third trench pattern in the manufacturing method of the semiconductor structure according to the present invention.

[0040] Figure 14 Schematic diagram showing the formation of a third trench in the manufacturing method of the semiconductor structure according to the present invention.

[0041] Figure 15 Schematic diagram showing the filling of a second insulating layer in a third trench in the manufacturing method of the semiconductor structure according to the present invention.

[0042] Figure 16 Schematic diagram showing the planarization of the second insulating layer until the upper surface of the second insulating layer is flush with the upper surface of the substrate in the manufacturing method of the semiconductor structure according to the present invention.

[0043] Element reference numeral description

[0044] 11 Substrate

[0045] 111 First trench

[0046] 1111 First insulating layer

[0047] 112 Second trench

[0048] 1121 Second insulating layer

[0049] S1 - S7 Steps

[0050] 21 Substrate

[0051] 211 First trench

[0052] 2111 First insulating layer

[0053] 212 Third trench

[0054] 2121 Second insulating layer

[0055] 22 Hard mask layer

[0056] 221 First isolation layer

[0057] 222 Second isolation layer

[0058] 223 Third isolation layer

[0059] 224 First photoresist layer

[0060] 225 Fourth isolation layer

[0061] 2251 Protrusion

[0062] 2252 Second trench

[0063] 2253 Second photoresist layer Detailed implementation manners

[0064] The following uses specific specific examples to illustrate the implementation manners of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific implementation manners. Various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0065] Please refer to Figures 1 to 16 . It should be noted that the diagrams provided in this embodiment only illustrate the basic concept of the present invention in a schematic manner. Therefore, only the components related to the present invention are shown in the diagrams, rather than being drawn according to the number, shape, and size of the components in actual implementation. The type, quantity, and ratio of each component in actual implementation can be arbitrarily changed, and the component layout type may also be more complex.

[0066] As Figure 1 shown, it shows a schematic cross-sectional structure diagram of a semiconductor insulating layer. The semiconductor structure includes a substrate 11, a first trench 111, a second trench 112, a first insulating layer 1111, and a second insulating layer 1121. Because Figure 1 in the manufacturing process of the semiconductor, forming the first trench requires a corresponding photomask, and forming the second trench also requires a photomask. Moreover, during the process of forming the second trench, it is necessary to control the error during photomask alignment, which greatly increases the difficulty of manufacturing the insulating layer and the complexity of the process. To address this problem, the present invention is improved through a new process flow design. The technical solution of the present invention will be described below through specific embodiments.

[0067] Embodiment 1

[0068] In this embodiment, a method for manufacturing a semiconductor structure is provided. Please refer to Figure 2 , which shows a flowchart of the method for manufacturing a semiconductor structure, including the following steps:

[0069] S1: Provide a substrate, and form a hard mask layer on the substrate. The hard mask layer includes a first isolation layer, a second isolation layer, and a third isolation layer in sequence from bottom to top;

[0070] S2: Form a first photoresist layer on the upper surface of the hard mask layer, and pattern the hard mask layer;

[0071] S3: Remove the first photoresist layer, and form a plurality of first trenches in the substrate based on the patterned hard mask layer;

[0072] S4: Form a first insulating layer. The first insulating layer fills into the first trenches and covers the upper surface of the hard mask layer. Planarize the first insulating layer until the second isolation layer is exposed, and remove the second isolation layer. The part of the first insulating layer protruding from the first isolation layer constitutes a raised portion;

[0073] S5: Form a fourth isolation layer. The fourth isolation layer covers the upper surface of the first isolation layer and the raised portion, and the fourth isolation layer forms a second trench between two adjacent raised portions;

[0074] S6: Fill a second photoresist layer in the second trench, and form a third trench by self-alignment based on the second photoresist layer. The third trench vertically penetrates the second insulating layer, the first isolation layer, and extends into the substrate. The bottom surface of the third trench is higher than the bottom surface of the first trench, and the bottom surface of the third trench exposes the first insulating layer;

[0075] S7: Form a second insulating layer in the third trench to form a shallow trench isolation structure, and the first insulating layer in the first trench forms a deep trench isolation structure.

[0076] First, please refer to Figures 3 to 5 , and perform the step S1: Provide a substrate 21, and form a hard mask layer 22 on the substrate 21. The hard mask layer 22 includes a first isolation layer 221, a second isolation layer 222, and a third isolation layer 223 in sequence from bottom to top.

[0077] Specifically, as Figure 3 shown, provide a substrate 21, and the substrate 21 includes a silicon substrate or other suitable substrates.

[0078] Specifically, as Figure 4As shown, the first isolation layer 221 is formed on the upper surface of the substrate 21 by chemical vapor deposition, thermal oxidation, or other suitable methods, and the material of the first isolation layer 221 may include silicon oxide.

[0079] Specifically, as Figure 5 shown, the second isolation layer 222 is formed on the first isolation layer 221 by chemical vapor deposition or other suitable methods, and the third isolation layer 223 is formed on the second isolation layer 222 by chemical vapor deposition or other suitable methods, wherein the material of the second isolation layer 222 may include Si3N4, and the material of the third isolation layer 223 may include silicon oxide.

[0080] As an example, the thickness of the third isolation layer 223 is greater than that of the first isolation layer 221. In this embodiment, the combination of the thin first isolation layer 221 and the thick third isolation layer 223 can improve the quality of the formed insulating layer and enhance the breakdown voltage performance of the semiconductor structure.

[0081] Then, please refer to Figure 6 , and perform step S2: forming a first photoresist layer 224 on the upper surface of the hard mask layer 22 and patterning the hard mask layer 22;

[0082] Specifically, first, the first photoresist layer 224 is patterned by lithography processes such as exposure and development to define the pattern of the subsequent first trench 211, and then based on the patterned first photoresist layer 224, the third isolation layer 223, the second isolation layer 222, and the first isolation layer 221 are sequentially etched to pattern the hard mask layer 22.

[0083] Please refer to Figure 7 again, and perform step S3, removing the first photoresist layer 224, and forming a plurality of the first trenches 211 in the substrate 21 based on the patterned hard mask layer 22.

[0084] Specifically, the method for forming the first trench 211 includes dry etching or other suitable methods. In this embodiment, according to the pattern on the hard mask layer 22, the substrate 21 is etched by deep reactive ion etching to obtain the first trench 211.

[0085] Specifically, during the etching process of forming the first trench 211, the third isolation layer 223 is also partially etched, that is, the thickness is reduced.

[0086] As an example, the etching rate of the substrate 21 is greater than that of the third isolation layer 223, and the depth of the first trench 211 is greater than the thickness of the third isolation layer 223 removed. In this embodiment, during the formation of the first trench 211, by adjusting the selectivity between the third isolation layer 223 and the substrate 21 and controlling the thickness of the removed third isolation layer 223, the first trench 211 with a target depth is obtained.

[0087] As an example, the aspect ratio of the first trench 211 is greater than 10, and the depth is 8 μm to 12 μm. In this embodiment, the aspect ratio of the first trench 211 is 11, and the depth is 10 μm.

[0088] Please refer to Figures 8 to 10 , perform the step S4 to form the first insulating layer 2111. The first insulating layer 2111 fills into the first trench 211 and covers the upper surface of the hard mask layer 22. The first insulating layer 2111 is planarized until the second isolation layer 222 is exposed, and the second isolation layer 222 is removed. The part of the first insulating layer 2111 protruding from the first isolation layer 221 constitutes the raised portion 2251.

[0089] Specifically, as Figure 8 shown, the first insulating layer 2111 is formed in the first trench 211 by chemical vapor deposition, physical vapor deposition or other suitable methods. In this embodiment, the first insulating layer 2111 is deposited by chemical vapor deposition until the first trench 211 is filled.

[0090] Specifically, as Figure 9 shown, the first insulating layer 2111 is planarized by chemical mechanical polishing or other suitable methods until the second isolation layer 222 is exposed.

[0091] Specifically, as Figure 10 shown, the second isolation layer 222 is removed by wet etching or other suitable methods. The etching rate of the etching solution used for the second isolation layer 222 is much greater than that for the first insulating layer 2111. When the second isolation layer 222 is completely removed, the top of the first insulating layer 2111 is higher than the first isolation layer 221, and the part of the first insulating layer 2111 protruding from the first isolation layer 221 constitutes the raised portion 2251.

[0092] Please refer to Figure 11, perform the step S5 to form a fourth isolation layer 225, the fourth isolation layer 225 covering the upper surface of the first isolation layer 221 and the protruding portion 2251, and the fourth isolation layer 225 forming the second trench 2252 between two adjacent protruding portions 2251.

[0093] Specifically, the critical dimension of the second trench 2252 can be controlled by adjusting the thickness of the fourth isolation layer 225.

[0094] Refer to again Figures 12 to 14 , perform the step S6, fill a second photoresist layer 2253 in the second trench 2252, and form a third trench 212 by self-alignment based on the second photoresist layer 2253. The third trench 212 penetrates the fourth isolation layer 225 and the first isolation layer 221 in the vertical direction and extends into the substrate 21. The bottom surface of the third trench 212 is higher than the bottom surface of the first trench 211, and the bottom surface of the third trench 212 exposes the first insulating layer 2111.

[0095] Specifically, as Figure 12 shown, fill photoresist in the second trench 2252 to form the second photoresist layer 2253.

[0096] Specifically, as Figure 13 shown, use wet etching or other suitable methods to remove the portion of the fourth isolation layer 225 not covered by the second photoresist 2253 until the upper surface of the protruding portion 2251 is exposed.

[0097] Specifically, as Figure 14 shown, continue to etch the portion of the fourth isolation layer 225, the first isolation layer 221, the first insulating layer 2111 and the substrate 21 not covered by the second photoresist 2253 to obtain the third trench 212. The bottom surface of the third trench 212 is higher than the bottom surface of the first trench 211, and the bottom surface of the third trench 212 exposes the first insulating layer 2111.

[0098] As an example, the width of the third trench 212 is greater than the width of the first trench 211.

[0099] As an example, the depth of the third trench 212 is less than the depth of the first trench 211.

[0100] Refer to again Figures 15 to 16 , perform the step S7, form the second insulating layer 2121 in the third trench 212 to constitute a shallow trench isolation structure, and the first insulating layer 2111 in the first trench 211 constitutes a deep trench isolation structure.

[0101] Specifically, the second photoresist layer 2253 needs to be removed before forming the second insulating layer 2121.

[0102] Specifically, as Figure 15 shown, the second insulating layer 2121 is formed in the third trench 212 by chemical vapor deposition or other suitable methods until the third trench 212 is filled.

[0103] Specifically, as Figure 16 shown, the second insulating layer 2121 is planarized until the upper surface of the second insulating layer 2121 is flush with the upper surface of the substrate 21.

[0104] A semiconductor manufacturing method according to this embodiment redesigns the semiconductor manufacturing process steps. After forming the first insulating layer 2111, the first insulating layer 2111 in the first isolation layer 221 and the second isolation layer 222 is retained, and then a fourth isolation layer 225 with a preset thickness is deposited. The second photoresist layer 2253 is filled in the second trench 2252 formed on the fourth isolation layer 225 to form the pattern of the third trench 212. Finally, the second insulating layer 2121 is formed by a self-alignment process, eliminating the step of manufacturing the mask for the third trench 212 and also eliminating the alignment steps of two masks, simplifying the manufacturing process, reducing the manufacturing cost, effectively avoiding the problem of filling defects at the bottom of the trench, and improving the breakdown voltage performance of semiconductor devices.

[0105] Embodiment 2

[0106] In this embodiment, a semiconductor structure is provided, which can be manufactured by using the manufacturing method of the semiconductor structure in Embodiment 1 or other suitable methods. Please refer to Figure 16 , which shows a schematic diagram of the structure, including a substrate 21, a shallow trench isolation structure, and a deep trench isolation structure. The shallow trench isolation structure and the deep trench isolation structure are both located in the substrate 21, and the top of the deep trench isolation structure is connected to the bottom of the shallow trench isolation structure. In this embodiment, the deep trench isolation structure is composed of the first insulating layer 2111, and the deep trench isolation structure is composed of the second insulating layer 2121.

[0107] As an example, the depth of the shallow trench isolation structure is greater than one-twentieth of the depth of the deep trench isolation structure and less than the depth of the deep trench isolation structure.

[0108] As an example, the width of the shallow trench isolation structure is greater than the width of the deep trench isolation structure.

[0109] In the semiconductor structure of this embodiment, the isolation structure consists of two parts, upper and lower, which can effectively avoid the problem of filling defects at the bottom of the trench and improve the breakdown voltage performance of the semiconductor structure at the same time.

[0110] In summary, in a semiconductor structure and a manufacturing method thereof according to the present invention, by improving the process steps of manufacturing the insulating layer in the semiconductor, the second isolation layer is removed after the first insulating layer is formed, and the part of the first insulating layer protruding from the first isolation layer forms a raised portion. Then, according to the width of the third trench, the thickness of the fourth isolation layer is determined and the second trench is formed between two adjacent raised portions. Then, the second photoresist layer is filled in the second trench, and the third trench is etched by using the self-aligned shallow isolation insulating trench etching process. Finally, the second insulating layer is filled in the third trench, eliminating the mask for forming the shallow isolation insulating trench and the alignment step of the mask, reducing the complexity of the process for manufacturing the insulating layer in the semiconductor and the manufacturing cost. By combining the deep isolation insulating trench and the shallow isolation insulating trench, the problem of filling defects at the bottom of the trench is effectively avoided, and the breakdown voltage performance of the semiconductor structure is improved at the same time. Therefore, the present invention effectively overcomes various drawbacks in the prior art and has high industrial utilization value.

[0111] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the present invention. Any person familiar with this technology can modify or change the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or changes made by those with ordinary knowledge in the technical field without departing from the spirit and technical idea disclosed by the present invention should still be covered by the claims of the present invention.

Claims

1. A method for manufacturing a semiconductor structure, characterized in that, Including the following steps: Providing a substrate, forming a hard mask layer on the substrate, the hard mask layer sequentially including a first isolation layer, a second isolation layer and a third isolation layer from bottom to top; Forming a first photoresist layer on the upper surface of the hard mask layer and patterning the hard mask layer; Removing the first photoresist layer, forming a plurality of first trenches in the substrate based on the patterned hard mask layer; Forming a first insulating layer, the first insulating layer filling into the first trenches and covering the upper surface of the hard mask layer, planarizing the first insulating layer until the second isolation layer is exposed, removing the second isolation layer, and the portion of the first insulating layer protruding from the first isolation layer constitutes a raised portion; Forming a fourth isolation layer, the fourth isolation layer covering the upper surface of the first isolation layer and the raised portion, and the fourth isolation layer forming a second trench between two adjacent raised portions; Filling a second photoresist layer in the second trench and forming a third trench by self-alignment based on the second photoresist layer, the third trench vertically penetrating the fourth isolation layer, the first isolation layer and extending into the substrate, the bottom surface of the third trench being higher than the bottom surface of the first trench, and the bottom surface of the third trench exposing the first insulating layer; Forming a second insulating layer in the third trench to form a shallow trench isolation structure, and the first insulating layer in the first trench forms a deep trench isolation structure.

2. The manufacturing method of the semiconductor structure according to claim 1, wherein: The substrate includes a silicon substrate, the material of the first isolation layer includes silicon oxide, the material of the second isolation layer includes silicon nitride, and the material of the third isolation layer includes silicon oxide.

3. The manufacturing method of the semiconductor structure according to claim 1, characterized in that: During the process of forming the first trenches, the third isolation layer is also partially etched.

4. The method for manufacturing a semiconductor structure according to claim 1, wherein: The thickness of the third isolation layer is greater than the thickness of the first isolation layer.

5. The method for manufacturing a semiconductor structure according to claim 1, wherein: The method of forming the first trenches includes dry etching.

6. The manufacturing method of the semiconductor structure according to claim 1, wherein: The aspect ratio of the first trenches is greater than 10, and the depth is 8 μm to 12 μm.

7. The manufacturing method of the semiconductor structure according to claim 1, characterized in that: The method of planarizing the first insulating layer includes chemical mechanical polishing, and the method of removing the second isolation layer includes wet etching.

8. A semiconductor structure, characterized in that, The semiconductor structure is fabricated by using the manufacturing method of the semiconductor structure according to any one of claims 1-7, including: A substrate; A shallow trench isolation structure located in the substrate; A deep trench isolation structure located in the substrate, and the top of the deep trench isolation structure is connected to the bottom of the shallow trench isolation structure.

9. The semiconductor structure according to claim 8, wherein: The depth of the shallow trench isolation structure is greater than one-twentieth of the depth of the deep trench isolation structure and less than the depth of the deep trench isolation structure.

10. The semiconductor structure according to claim 8, wherein: The width of the shallow trench isolation structure is greater than the width of the deep trench isolation structure.

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