Semiconductor device

Abstract

The semiconductor device of the embodiment includes a first switching element having a first terminal to which a first voltage is applied, a second terminal electrically connected to a first node, and a gate; a second switching element having a first terminal to which a second voltage is applied, a second terminal and a gate electrically connected to the first node; a third switching element having a first terminal to which the second voltage is applied, a second terminal electrically connected to a second node, and a gate electrically connected to the first node; a first current source electrically connected to the first node; a first element electrically connected to the second node; a fourth switching element having a gate electrically connected to the second node; and a first terminal electrically connected to a first terminal of the fourth switching element and outputting a signal based on a voltage of the second node.

Description

[0001] This application claims priority to Japanese Patent Application No. 2021-131590 (filed on August 12, 2021). The entire contents of the basic application are incorporated herein by reference. Technical Field

[0002] This invention primarily relates to semiconductor devices. Background Technology

[0003] A semiconductor device is known to compare the high and low levels of two voltages and output a signal based on the result of the comparison. Summary of the Invention

[0004] The purpose of this invention is to provide a semiconductor device that can suppress the increase in power consumption while suppressing the increase in chip size.

[0005] The semiconductor device of the embodiment includes: a first switching element having a first terminal to which a first voltage is applied, a second terminal electrically connected to a first node, and a gate; a second switching element having a first terminal to which a second voltage is applied, a second terminal electrically connected to the first node, and a gate; a third switching element having a first terminal to which the second voltage is applied, a second terminal electrically connected to a second node, and a gate connected to the first node; a first current source electrically connected to the first node; a first element electrically connected to the second node; a fourth switching element having a gate connected to the second node; and a first terminal electrically connected to the first terminal of the fourth switching element, outputting a signal based on the voltage of the second node. Attached Figure Description

[0006] Figure 1 This is a circuit diagram illustrating an example of the configuration of a semiconductor device for implementing a related embodiment.

[0007] Figure 2 This is a circuit diagram used to illustrate an example of the configuration of the semiconductor device in relation to the first modified example.

[0008] Figure 3 This is a circuit diagram used to illustrate an example of the configuration of the semiconductor device in the second variation.

[0009] Figure 4 This is a circuit diagram used to illustrate an example of the configuration of the semiconductor device in the third variation.

[0010] Figure 5 This is a circuit diagram used to illustrate an example of the configuration of the semiconductor device in the fourth variation.

[0011] Figure 6 This is a circuit diagram used to illustrate an example of the configuration of the semiconductor device in the fifth variation.

[0012] Figure 7 This is a circuit diagram used to illustrate an example of the configuration of the semiconductor device in the sixth variation.

[0013] Figure 8 This is a circuit diagram used to illustrate an example of the configuration of the semiconductor device in the seventh variation. Detailed Implementation

[0014] Hereinafter, embodiments will be described with reference to the accompanying drawings. Furthermore, in the following description, common reference numerals will be used for constituent elements having the same function and configuration.

[0015] 1. Implementation Method

[0016] The semiconductor device of the relevant implementation method will be described.

[0017] 1.1 Composition

[0018] The configuration of the semiconductor device according to the relevant implementation method will be described.

[0019] 1.1.1 Overall Structure of a Semiconductor Device

[0020] use Figure 1 The configuration of the semiconductor device according to the relevant implementation method will be described. Figure 1 This is a circuit diagram illustrating an example of the configuration of a semiconductor device for implementing a related embodiment.

[0021] Semiconductor device 1 is, for example, an IC (Integrated Circuit) chip. Semiconductor device 1 includes a current source 10 and a comparator 11. The current source 10 and the comparator 11 are disposed on the upper surface of a substrate. Furthermore, semiconductor device 1 includes terminals PVDD, PV1, PV2, and POUT. Voltages VDD, V1, and V2 are respectively applied to terminals PVDD, PV1, and PV2 from an external power source (not shown). A signal S is output from terminal POUT to an external load 2 of semiconductor device 1. Voltage VDD is the voltage used in driving semiconductor device 1. Voltages V1 and V2 are the voltages of the comparison objects within semiconductor device 1. Signal S is a signal based on the comparison result of voltages V1 and V2.

[0022] The comparison unit 11 is a circuit that compares the high and low levels of voltages V1 and V2.

[0023] The current source 10 is a circuit that supplies current based on voltage VDD to the comparator 11.

[0024] 1.1.2 Circuit Structure of Semiconductor Devices

[0025] Next use Figure 1 The circuit configuration of the semiconductor device 1 according to the relevant embodiment will be described.

[0026] 1.1.2.1 Current Source

[0027] First, the circuit configuration of current source 10 will be explained.

[0028] The current source 10 includes switching elements Qs1 and Qs2, and a resistor Rs1. Switching element Qs1 is a P-channel MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor). Switching element Qs2 is an N-channel MOSFET.

[0029] A voltage VDD is applied to the source of switching element Qs1 via terminal PVDD. The drain and gate of switching element Qs1 are connected to node N1. A current based on voltage VDD flows through switching element Qs1.

[0030] Terminal 1 of resistor Rs1 is connected to node N1. Terminal 2 of resistor Rs1 is connected to node N2.

[0031] The drain and gate of switching element Qs2 are connected to node N2. The source of switching element Qs2 is grounded. The current flowing through switching element Qs1 is supplied to switching element Qs2 through resistor Rs1. That is, the current flowing into switching element Qs2 is based on voltage VDD.

[0032] 1.1.2.2 Comparison Section

[0033] Next, the configuration of the comparison section 11 of the relevant implementation method will be described.

[0034] The comparator unit 11 includes switching elements Q1, Q2, Q3, Q4, Q5, and Q6, a resistor R1, and diodes D1 and D2. Switching elements Q1, Q2, Q4, and Q5 are P-channel MOSFETs. Switching elements Q3 and Q6 are N-channel MOSFETs.

[0035] A voltage V1 is applied to the source of switching element Q1 via terminal PV1. The drain and gate of switching element Q1 are commonly connected to diode D1. That is, switching element Q1, which is diode connected, is located between terminal PV1 and diode D1. As a result, switching element Q1 operates in the saturation region, and current I1 flows through switching element Q1.

[0036] The anode of diode D1 is connected to the drain and gate of switching element Q1. The cathode of diode D1 is connected to node N3.

[0037] A voltage V2 is applied to the source of switching element Q2 via terminal PV2. The drain and gate of switching element Q2 are connected to node N4. That is, switching element Q2, which is diode-connected, is located between terminal PV2 and node N4. Therefore, switching element Q2 operates in the saturation region, and a current I2 flows through it. The gate length, channel width, and current-voltage characteristics of switching element Q2 are the same as those of switching element Q1.

[0038] The anode of diode D2 is connected to node N4. The cathode of diode D2 is connected to node N3. The current-voltage characteristic of diode D2 is the same as that of diode D1.

[0039] Switching element Q3 and switching element Qs2 of current source 10 form a current mirror circuit. The drain of switching element Q3 is connected to node N3. The source of switching element Q3 is grounded. The gate of switching element Q3 is connected to current source 10 via node N2. In switching element Q3, a constant current IS flows through it under the action of current source 10. The constant current IS is the sum of currents I1 and I2.

[0040] Switching element Q4 and switching element Q2 form a current mirror circuit. Specifically, the source of switching element Q4 is connected to terminal PV2. The drain of switching element Q4 is connected to node N5. The gate of switching element Q4 is connected to node N4. A current IM flows through switching element Q4. Here, the gate length, channel width, and current-voltage characteristics of switching element Q4 are the same as those of switching element Q2. Therefore, current IM is the mirror current of current I2.

[0041] Switching element Q5 and switching element Qs1 of current source 10 form a current mirror circuit. That is, a voltage VDD is applied to the source of switching element Q5 via terminal PVDD. The drain of switching element Q5 is connected to terminal POUT. The gate of switching element Q5 is connected to current source 10 via node N1. A constant current flows through switching element Q5 under the action of current source 10.

[0042] The drain of switching element Q6 is connected to terminal POUT. The source of switching element Q6 is grounded. The gate of switching element Q6 is connected to node N5. The threshold voltage of switching element Q6 is the same as the voltage of node N5 when the current IM is half of the constant current IS. That is, when the current IM is more than half of the constant current IS, switching element Q6 is in the on state. Furthermore, when the current IM is less than half of the constant current IS, switching element Q6 is in the off state.

[0043] Terminal 1 of resistor R1 is connected to node N5. Terminal 2 of resistor R1 is grounded.

[0044] Furthermore, the constant current IS flowing into the switching element Q3 is such that, when the current I1 is approximately equal to the constant current IS (when almost no current I2 flows), the voltage between the gate and source of the switching element Q1 is lower than the rated voltage RVGS1 of the switching element Q1. Similarly, the constant current IS is such that, when the current I2 is approximately equal to the constant current IS (when almost no current I1 flows), the voltage between the gate and source of the switching element Q2 is lower than the rated voltage RVGS2 of the switching element Q2. The semiconductor device 1 is configured such that constant current IS flows through the switching element Q3.

[0045] 1.2 Actions

[0046] The operation of the semiconductor device 1 using the relevant implementation method will be described.

[0047] During the operation of the semiconductor device 1, a voltage VDD is applied to the terminal PVDD. As a result, constant currents based on the voltage VDD flow through the switching elements Q3 and Q5 of the comparator section 11.

[0048] In addition, voltages V1 and V2 are applied to terminals PV1 and PV2, respectively. As a result, currents I1 and I2 flow through switching elements Q1 and Q2, respectively.

[0049] When voltage V1 is higher than voltage V2, current I1 is greater than half of the constant current IS (IS / 2), and current I2 is less than half of the constant current IS. Furthermore, when voltage V1 is lower than voltage V2, current I1 is less than half of the constant current IS, and current I2 is more than half of the constant current IS.

[0050] Through the current mirror circuit including switching elements Q2 and Q4, a current IM equal to the current I2 flows through switching element Q4. That is, when voltage V1 is higher than voltage V2, the current IM is less than half of the constant current IS. Furthermore, when voltage V1 is lower than voltage V2, the current IM is more than half of the constant current IS.

[0051] As described above, the voltage at node N5 is configured such that when the current IM is half of the constant current IS, it is equal to the threshold voltage of switching element Q6. Therefore, when voltage V1 is higher than voltage V2, switching element Q6 is in the off state. Thus, for terminal POUT, voltage VDD is supplied via switching element Q5, and a "H" level signal S is output from terminal POUT. Furthermore, when voltage V1 is lower than voltage V2, switching element Q6 is in the on state. Therefore, terminal POUT is grounded via switching element Q6, and a "L" level signal S is output from terminal POUT.

[0052] 1.3 Effects of this implementation method

[0053] According to the implementation method, it is possible to suppress the increase in chip size while suppressing the increase in power consumption. The effects of the implementation method are explained below.

[0054] The semiconductor device 1 according to the embodiment includes: a switching element Q1 having a source for which a voltage V1 is applied, and a drain and a gate connected to node N3; a switching element Q2 having a source for which a voltage V2 is applied, and a drain and a gate connected to node N3; and a switching element Q3 having a drain connected to node N3. With this configuration, currents I1 and I2 can be suppressed to below a constant current IS. Therefore, regardless of the voltages V1 and V2, the upper limit of the gate-source voltage of switching elements Q1 and Q2 can be set based on the constant current IS. Therefore, the rise in the gate-source voltage of switching elements Q1 and Q2 can be suppressed without using components such as resistors to divide voltages V1 and V2. Therefore, compared to using components such as resistors, the increase in power consumption and the increase in chip size due to the increase in components can be suppressed.

[0055] Furthermore, when the gate-source voltage of a switching element corresponding to the current flowing through it is not uniquely determined, it is possible that the gate-source voltage of the switching element exceeds its rated voltage, thereby damaging the switching element. As one method to avoid this situation, it is known to reduce the voltage applied to the switching element by incorporating elements such as resistors to divide the voltage applied to the gate or source of the switching element. However, according to this method, the power consumption and chip size of the semiconductor device may increase due to the increased number of components included in the semiconductor device.

[0056] According to the embodiment, regardless of the voltages V1 and V2 applied to the sources of switching elements Q1 and Q2, the upper limits of the gate-source voltages of switching elements Q1 and Q2 can be suppressed to be lower than the rated voltages RVGS1 and RVGS2 of the switching elements, respectively. Therefore, even without a voltage divider or similar mechanism used for comparison, damage to switching elements Q1 and Q2 can be suppressed in the semiconductor device 1. Thus, the increase in the number of components such as resistors is suppressed. Consequently, the increase in power consumption of the semiconductor device 1 can be suppressed while the increase in chip size is also suppressed.

[0057] Furthermore, in cases where components such as resistors are included to divide the voltage applied to the gate or source of a switching element, the semiconductor device may, for example, have resistors with large resistance values ​​to suppress the increase in current consumption. However, generally, as the resistance value increases, the size of the resistor also increases, thus increasing the chip size. Therefore, there is a trade-off between suppressing the increase in current consumption and suppressing the increase in chip size. According to the embodiment, since the increase in resistance can be suppressed, the increase in chip size can be suppressed while suppressing the increase in current consumption that depends on the size of the resistor.

[0058] Furthermore, when a resistor is included to divide the voltage applied to the gate or source of a switching element, the semiconductor device may experience an increase in current consumption depending on temperature due to the temperature characteristics of the resistor. According to the embodiment, since the increase in resistance can be suppressed, the increase in temperature-dependent current consumption can also be suppressed.

[0059] Furthermore, according to the embodiment, the semiconductor device 1 includes: a diode D1 having an anode connected to the drain and gate of the switching element Q1 and a cathode connected to node N3; and a diode D2 having an anode connected to the drain and gate of the switching element Q2 and a cathode connected to node N3. That is, between the switching element Q1 and node N3, current flows from the switching element Q1 to node N3 via diode D1. Furthermore, between the switching element Q2 and node N3, current flows from the switching element Q2 side to node N3 via diode D2. Therefore, it is possible to suppress the backflow of current from node N3 to the voltage source V1 and the backflow of current from node N3 to the voltage source V2.

[0060] Furthermore, in a P-channel switching element, a body diode exists between the drain and the source. The anode of the body diode is connected to the drain of the corresponding switching element. The cathode of the body diode is connected to the source of the corresponding switching element. Therefore, when current is supplied to the drain side of the switching element, it is possible for current to flow (reverse flow) from the drain side to the source side of the switching element through the body diode. According to the embodiment, diodes D1 and D2 can suppress the supply of current from node N3 to the drain of switching element Q1 and the supply of current from node N3 to the drain of switching element Q2, respectively. Therefore, reverse current flow through the body diode of switching element Q1 and reverse current flow through the body diode of switching element Q2 can be suppressed.

[0061] 2. Variations

[0062] Furthermore, the above-described embodiments can be modified in various ways.

[0063] The following describes a modified semiconductor device. The structure and operation of the modified semiconductor device will be described focusing on the differences from the semiconductor device of the embodiment. The modified semiconductor device achieves the same effects as the embodiment.

[0064] 2.1 First Variation

[0065] In the above embodiments, an example is shown in which diodes D1 and D2 are provided to suppress the reverse current through switching element Q1 and the reverse current through switching element Q2, but this is not a limitation. For example, the reverse current to the voltage source of voltage V1 and the voltage source of voltage V2 can be suppressed by including switching elements instead of diodes D1 and D2.

[0066] use Figure 2 The configuration of the semiconductor device 1 in the first modified example will be described. Figure 2 This is a circuit diagram illustrating an example of the configuration of the semiconductor device 1 in the first modification. Furthermore, the configuration of the current source 10 in the semiconductor device 1 of the first modification is the same as that in the embodiment, so its description is omitted. Hereinafter, the configuration of the comparison section 11 in the first modification, which differs from the configuration of the comparison section 11 in the embodiment, will be described.

[0067] The comparison section 11 of the first modification includes switching elements Q7, Q8, and Q9. Switching elements Q7, Q8, and Q9 are P-channel MOSFETs.

[0068] The drain of switching element Q1 is connected to switching element Q7. The gate of switching element Q1 is connected to node N3.

[0069] The drain of switching element Q2 is connected to switching element Q8. The gate of switching element Q2 is connected to node N3.

[0070] The gate of switching element Q4 is connected to node N3. The drain of switching element Q4 is connected to switching element Q9.

[0071] The drain of switching element Q7 is connected to the drain of switching element Q1. The source and gate of switching element Q7 are connected to node N3.

[0072] The drain of switching element Q8 is connected to the drain of switching element Q2. The source and gate of switching element Q8 are connected to node N3.

[0073] The drain of switching element Q9 is connected to the drain of switching element Q4. The source of switching element Q9 is connected to node N5. The gate of switching element Q9 is connected to node N3.

[0074] The other configurations are substantially the same as those of the comparison section 11 in the relevant embodiments, except that they do not include diodes D1 and D2.

[0075] The operation of the first variation is substantially the same as that of the related implementation, so its description is omitted.

[0076] According to the first modification, in the current path between terminal PV1 and node N3, the body diode of switch element Q7 is configured such that its orientation is different from that of the body diode of switch element Q1. Furthermore, in the current path between terminal PV2 and node N3, the body diode of switch element Q8 is configured such that its orientation is opposite to that of the body diode of switch element Q2. Additionally, in the current path between terminal PV2 and node N5, the body diode of switch element Q9 is configured such that its orientation is different from that of the body diode of switch element Q4. With this configuration, similar to the embodiment, reverse current to the voltage source of voltage V1 or voltage V2 can be suppressed.

[0077] Furthermore, according to the first modification, the voltage drop of the diode's forward voltage can be suppressed. Therefore, the voltage drop at node N3, for example, can be suppressed, and the constant current IS can be increased compared to the case including the diode. Consequently, the decrease in the reliability of the comparator 11 can be suppressed.

[0078] 2.2 Second Variation

[0079] In the first variation, the drains of switching element Q1, Q2, and Q4 are connected to the drains of their respective switching elements, but this is not a limitation. The comparator 11 may also be configured such that the sources of switching element Q1, Q2, and Q4 are connected to the sources of their respective switching elements.

[0080] use Figure 3 The configuration of the semiconductor device 1 in the second modified example will be described. Figure 3 This is a circuit diagram illustrating one example of the configuration of the semiconductor device 1 in the second modification. Furthermore, the configuration of the current source 10 in the semiconductor device 1 of the second modification is the same as that in the embodiment, so its description is omitted. Hereinafter, the differences between the configuration of the comparison section 11 in the second modification and the configuration of the comparison section 11 in the embodiment will be mainly described.

[0081] The comparison section 11 of the second modification includes switching elements Q10, Q11, and Q12. Switching elements Q10, Q11, and Q12 are P-channel MOSFETs.

[0082] The source of switching element Q1 is connected to switching element Q10. The gate and drain of switching element Q1 are connected to node N3.

[0083] The source of switching element Q2 is connected to switching element Q11. The gate and drain of switching element Q2 are connected to node N3.

[0084] The source of switching element Q4 is connected to switching element Q12. The gate of switching element Q4 is connected to node N3. The drain of switching element Q4 is connected to node N5.

[0085] The source of switching element Q10 is connected to the source of switching element Q1. The drain of switching element Q10 is connected to terminal PV1. The gate of switching element Q10 is connected to node N3.

[0086] The source of switching element Q11 is connected to the source of switching element Q2. The drain of switching element Q11 is connected to terminal PV2. The gate of switching element Q11 is connected to node N3.

[0087] The source of switching element Q12 is connected to the source of switching element Q4. The drain of switching element Q12 is connected to terminal PV2. The gate of switching element Q12 is connected to node N3.

[0088] The other configurations are substantially the same as those of the comparison section 11 in the relevant embodiments, except that they do not include diodes D1 and D2.

[0089] The operation of the second variation is substantially the same as that of the implementation and the first variation, so its description is omitted.

[0090] With this configuration, similar to the embodiment and the first modification, reverse current flow to the voltage source of voltage V1 or voltage V2 can be suppressed. Furthermore, similar to the first modification, a decrease in the reliability of the comparator 11 can be suppressed.

[0091] 2.3 Third variation

[0092] In the above embodiment, the gate and drain of switching element Q2 and the gate of switching element Q4 are shown to be at the same potential, but it is not limited to this. The comparison unit 11 may also include a configuration that controls the drain of switching element Q4 to be at the same potential as the gate and drain of switching element Q2, except for the gate of switching element Q4.

[0093] use Figure 4 The configuration of the semiconductor device 1 in the third modified example will be described. Figure 4This is a circuit diagram illustrating one example of the configuration of the semiconductor device 1 in the third modification. Furthermore, the configuration of the current source 10 in the semiconductor device 1 of the third modification is the same as that in the embodiment, so its description is omitted. Hereinafter, the differences between the configuration of the comparison section 11 in the third modification and the configuration of the comparison section 11 in the embodiment will be mainly described.

[0094] The comparison section 11 of the third variation includes an operational amplifier AMP and a switching element Q13. The switching element Q13 is a P-channel MOSFET.

[0095] The inverting input terminal (-) of the operational amplifier AMP is connected to node N6. Node N6 is connected to the drain of the switching element Q4. The non-inverting input terminal (+) of the operational amplifier AMP is connected to node N4. The output terminal of the operational amplifier AMP is connected to the switching element Q13.

[0096] The source of switching element Q13 is connected to node N6 of the operational amplifier. The drain of switching element Q13 is connected to node N5. The gate of switching element Q13 is connected to the output terminal of the operational amplifier AMP.

[0097] In the above configuration, the operational amplifier AMP controls the output voltage from the output terminal of the operational amplifier AMP based on the voltage applied to node N4 on the non-inverting input terminal (+) and the voltage applied to node N6 on the inverting input terminal (-), thereby controlling the state (on and off state) of the switching element Q13. Thus, the operational amplifier AMP is controlled such that the voltage at node N4 and the voltage at node N6 are equal.

[0098] The other configurations are substantially the same as those of the comparison section 11 in the relevant embodiments.

[0099] The operation of the third variation is substantially the same as that of the related implementation, so its description is omitted.

[0100] According to the third variation, the operational amplifier AMP is controlled such that the voltage at node N4 is equal to the voltage at node N6. That is, the drain voltage of switching element Q2 is made the same as the drain voltage of switching element Q4. As a result, in the current mirror circuit composed of switching elements Q2 and Q4, the comparator 11 can suppress the increase of errors in currents I2 and IM. Therefore, the output error signal S can be suppressed.

[0101] 2.4 Fourth Variation

[0102] In the above embodiment, the comparator 11 is shown as including a resistor R1 as a load, but it is not limited to this. The comparator 11 may also include a diode instead of a resistor R1 as a load.

[0103] use Figure 5 The configuration of the semiconductor device 1 in the fourth variation will be described. Figure 5 This is a circuit diagram illustrating one example of the configuration of the semiconductor device 1 in the fourth modification. Furthermore, the configuration of the current source 10 in the semiconductor device 1 of the fourth modification is the same as that in the embodiment, so its description is omitted. Hereinafter, the configuration of the comparison section 11 in the fourth modification, which differs from the configuration of the comparison section 11 in the embodiment, will be described.

[0104] The comparison section 11 of the fourth variation includes diode D3.

[0105] The anode of diode D3 is connected to node N5. The cathode of diode D3 is grounded.

[0106] The other components are substantially the same as those of the comparison section 11 in the relevant embodiment, except that the resistor R1 is not included.

[0107] The operation of the fourth variation is substantially the same as that of the relevant implementation, so its description is omitted.

[0108] This configuration achieves the same effect as the implementation method, the first modification, the second modification, and the third modification.

[0109] 2.5 Fifth Variation

[0110] In the above-described embodiments, first modifications, second modifications, third modifications, and fourth modifications, the signal S output from terminal POUT is determined based on the state of switching element Q6. However, this is not a limitation. The signal S output from terminal POUT may also be determined based on the state of switching element Q5 in addition to the state of switching element Q6.

[0111] use Figure 6 The configuration of the semiconductor device 1 in the fifth modified example will be described. Figure 6 This is a circuit diagram illustrating an example of the configuration of the semiconductor device 1 in the fifth modification. Hereinafter, the configuration of the semiconductor device 1 in the fifth modification, which differs from the configuration of the semiconductor device 1 in the relevant embodiments, will be described.

[0112] In the fifth variation, the gate of the switching element Q5 in the comparison section 11 is connected to node N5 instead of the current source 10. The absolute value of the threshold voltage of the switching element Q5 is the same as the absolute value of the difference between the voltage at node N5 and the voltage VDD when the current IM is half of the constant current IS. That is, when the current IM is less than half of the constant current IS, the switching element Q5 is in the on state. Furthermore, when the current IM is more than half of the constant current IS, the switching element Q5 is in the off state.

[0113] The other configurations are substantially the same as those of the comparison section 11 in the relevant embodiments.

[0114] Next, the operation of the semiconductor device 1 in the fifth modified example will be explained.

[0115] In the semiconductor device 1 of the fifth modification, for example, when voltage V1 is higher than voltage V2 (current IM is less than half of constant current IS), switching element Q5 is in the on state and switching element Q6 is in the off state. Therefore, for terminal POUT, voltage VDD is supplied via switching element Q5, and a signal S of level "H" is output from terminal POUT. Furthermore, when voltage V1 is lower than voltage V2 (current IM is more than half of constant current IS), switching element Q5 is in the off state and switching element Q6 is in the on state. Therefore, terminal POUT is grounded via switching element Q6, and a signal S of level "L" is output from terminal POUT.

[0116] The other actions are the same as those in the relevant implementation methods.

[0117] With this configuration, the same effect as the implementation method, the first modification, the second modification, the third modification and the fourth modification can be achieved.

[0118] 2.6 Sixth Variation

[0119] In the above-described embodiments, first modifications, second modifications, third modifications, fourth modifications, and fifth modifications, the comparison of the levels of voltages V1 and V2 is shown, but the invention is not limited to this. The semiconductor device 1 may also be configured to compare the levels of voltages VDD and V2. That is, the semiconductor device determines the level of voltage V2 based on voltage VDD.

[0120] use Figure 7 The configuration of the semiconductor device 1 in the sixth modified example will be described. Figure 7This is a circuit diagram illustrating one example of the configuration of the semiconductor device 1 in the sixth modification. Furthermore, the configuration of the current source 10 in the semiconductor device 1 of the sixth modification is the same as that in the embodiment, so its description is omitted. Hereinafter, the differences between the configuration of the comparison section 11 in the sixth modification and that in the embodiment will be described.

[0121] In the comparison section 11 of the sixth variation, the source of switching element Q1 and the source of switching element Q5 are connected together to the terminal PVDD of current source 10. Therefore, a voltage VDD is applied to the source of switching element Q1 instead of the voltage V1 in the previous embodiment.

[0122] The other components are the same as those of the comparison section 11 in the relevant embodiments, so their descriptions are omitted.

[0123] Next, the operation of the semiconductor device 1 in the sixth modification will be explained.

[0124] In the operation of the semiconductor device 1 in the sixth variation, voltage VDD is compared with voltage V2. Other than this, the operation is substantially the same as that in the relevant embodiment.

[0125] Therefore, when voltage V2 is lower than voltage VDD, a signal S at the "H" level is output from terminal POUT. Furthermore, when voltage V2 is higher than voltage VDD, a signal S at the "L" level is output from terminal POUT.

[0126] With this configuration, the same effect as the implementation method, the first modification, the second modification, the third modification, the fourth modification, and the fifth modification can be achieved.

[0127] 2.7 Example 7 (Modification)

[0128] In the sixth variation, the semiconductor device 1 compares the levels of voltages VDD and V2, but it is not limited to this. The semiconductor device 1 can also be configured to compare the levels of voltages V1 and VDD. That is, the semiconductor device determines the level of voltage V1 based on voltage VDD.

[0129] use Figure 8 The configuration of the semiconductor device 1 in the seventh modification will be described. Figure 8 This is a circuit diagram illustrating one example of the configuration of the semiconductor device 1 in the seventh modification. Furthermore, the configuration of the current source 10 in the semiconductor device 1 of the seventh modification is the same as that in the embodiment, so its description is omitted. Hereinafter, the configuration of the comparison section 11 in the seventh modification, which differs from the configuration of the comparison section 11 in the embodiment, will be described.

[0130] In the seventh variation, the source of the switching element Q2 in the comparison section 11 is connected to the terminal PVDD of the current source 10. Therefore, a voltage VDD is applied to the source of the switching element Q2 instead of the voltage V2 in the previous embodiment.

[0131] The other components are the same as those of the comparison section 11 in the relevant embodiments, so their descriptions are omitted.

[0132] Next, the operation of the semiconductor device 1 in the seventh modification will be explained.

[0133] In the operation of the semiconductor device 1 in the seventh modification, voltage V1 is compared with voltage VDD. Other than this, the operation is substantially the same as that in the relevant embodiment.

[0134] Therefore, when voltage V1 is higher than voltage VDD, a signal S at the "H" level is output from terminal POUT. Furthermore, when voltage V1 is lower than voltage VDD, a signal S at the "L" level is output from terminal POUT.

[0135] With this configuration, the same effect as the implementation method, the first modification, the second modification, the third modification, the fourth modification, the fifth modification, and the sixth modification can be achieved.

[0136] 3. Other

[0137] Furthermore, in the above-described embodiments and the first to seventh modifications, examples were given assuming that the current-voltage characteristics, gate lengths, and channel widths of switching elements Q1, Q2, and Q4 are identical, but the description is not limited to this. The current-voltage characteristics, gate lengths, and channel widths of switching element Q4 may also differ from those of switching elements Q1 and Q2. In this case, the current IM flowing through switching element Q4 becomes a constant multiple (other than an equal multiple) of the current I2 flowing through switching element Q2.

[0138] Several embodiments of the present invention have been described, but these embodiments are merely illustrative and not intended to limit the scope of the invention. These embodiments can be implemented in a wide variety of other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included in the scope or spirit of the invention, and are included in the scope of the invention as described in the claims and its equivalents.

Claims

1. A semiconductor device, wherein, have: The first switching element has: a first terminal to which a first voltage is applied, a second terminal electrically connected to a first node, and a gate; The second switching element has: a first terminal to which a second voltage is applied, a second terminal electrically connected to the first node, and a gate; The third switching element has: a first terminal to which the second voltage is applied, a second terminal electrically connected to the second node, and a gate connected to the first node; The first current source is electrically connected to the first node mentioned above; The first component is electrically connected to the second node mentioned above; The fourth switching element has a first terminal, a gate connected to the second node mentioned above, and a second terminal to which a ground voltage is applied; as well as The first terminal is electrically connected to the first terminal of the fourth switching element and outputs a signal based on the voltage of the second node. The first element is a first resistor having a first terminal connected to the second node and a second terminal to which a ground voltage is applied, or the first element is a third diode having an anode connected to the second node and a cathode to which a ground voltage is applied.

2. The semiconductor device of claim 1, wherein, The aforementioned semiconductor device also includes: The first diode is disposed between the first switching element and the first node, and has: an anode connected to the second terminal and the gate of the first switching element, and a cathode connected to the first node; as well as The second diode is disposed between the second switching element and the first node, and has an anode connected to the second terminal and gate of the second switching element and the gate of the third switching element, and a cathode connected to the first node.

3. The semiconductor device as claimed in claim 1, wherein, The first terminal of the aforementioned first switching element is the source, and the second terminal of the aforementioned first switching element is the drain. The first terminal of the aforementioned second switching element is the source, and the second terminal of the aforementioned second switching element is the drain. The first terminal of the third switching element is the source, and the second terminal of the third switching element is the drain.

4. The semiconductor device of claim 3, wherein, The aforementioned semiconductor device also includes: The fifth switching element is disposed between the first switching element and the first node, and has: a drain connected to the drain of the first switching element, and a source and a gate connected to the first node together with the gate of the first switching element. The sixth switching element is disposed between the second switching element and the first node, and has: a drain connected to the drain of the second switching element, and a source and a gate connected to the first node together with the gate of the second switching element. as well as The seventh switching element is disposed between the third switching element and the second node, and has: a drain connected to the drain of the third switching element, a gate connected to the first node together with the gate of the third switching element, and a source connected to the second node.

5. The semiconductor device of claim 3, wherein, The aforementioned semiconductor device also includes: The eighth switching element has: a source connected to the source of the first switching element, a gate connected to the first node together with the gate of the first switching element, and a drain to which the first voltage is applied. The 9th switching element has: a source connected to the source of the 2nd switching element, a gate connected to the 1st node together with the gate of the 2nd switching element, and a drain to which the 2nd voltage is applied. as well as The 10th switching element has: a source connected to the source of the 3rd switching element, a gate connected to the 1st node together with the gate of the 3rd switching element, and a drain to which the 2nd voltage is applied.

6. The semiconductor device of claim 1, wherein, The aforementioned semiconductor device also includes: The 11th switching element has: a gate, a first terminal connected to the second terminal of the third switching element, and a second terminal connected to the second node. as well as An operational amplifier has: an inverting input terminal connected to the second terminal of the third switching element and the first terminal of the eleventh switching element, a non-inverting input terminal connected to the first node, and an output terminal connected to the gate of the eleventh switching element.

7. The semiconductor device of claim 1, wherein, The aforementioned semiconductor device includes a 12th switching element, which has: a gate, a first terminal to which a third voltage is applied, and a second terminal connected to the first terminal. The gate of the 12th switching element is connected to the 2nd node.

8. The semiconductor device of claim 1, wherein, The aforementioned semiconductor device also includes: The 12th switching element has a first terminal, a gate, and a second terminal; and The 13th switching element has a first terminal, a gate, and a second terminal. The first terminal of the first switching element or the first terminal of the second switching element is connected to the first terminal of the 12th switching element and the first terminal of the 13th switching element. The first terminal is connected to the second terminal of the 12th switching element. The gate of the 12th switching element is connected to the gate of the 13th switching element and the second terminal of the 13th switching element. The second terminal of the 13th switching element is connected to the 14th switching element, which forms a current mirror with the 1st current source.

9. The semiconductor device of claim 1, wherein, The first terminal of the fourth switching element is the drain, and the second terminal of the fourth switching element is the source.

10. The semiconductor device of claim 7 or 8, wherein, The first terminal of the aforementioned 12th switching element is the source, and the second terminal of the aforementioned 12th switching element is the drain.

11. The semiconductor device of claim 8, wherein, The aforementioned 14th switching element has a first terminal, a second terminal, and a gate. The aforementioned first current source is a 15th switching element having a first terminal, a second terminal, and a gate. The first terminal of the aforementioned 15th switching element is connected to the aforementioned first node. A ground voltage is applied to the second terminal of the aforementioned 15th switching element. The gate of the 15th switching element is connected to the gate of the 14th switching element. The first terminal of the aforementioned 14th switching element is connected to the second terminal of the aforementioned 13th switching element. A ground voltage is applied to the second terminal of the aforementioned 14th switching element.

12. The semiconductor device of claim 11, wherein, The first terminal of the aforementioned 15th switching element is the drain, and the second terminal of the aforementioned 15th switching element is the source.

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