Signal relay device and method with frequency correction mechanism

Abstract

The present invention provides a signal relay device with a frequency correction mechanism, comprising: a clock generation circuit, a frequency generation circuit, a clock measurement circuit, a frequency adjustment circuit, and a transmission circuit. The clock generation circuit generates a clock source signal. The frequency generation circuit receives the clock source signal and generates a target frequency signal based on a conversion parameter. The clock measurement circuit measures a first frequency deviation of the source frequency of the clock source signal relative to a first preset frequency based on an external reference clock signal. When the first frequency deviation is not within a first preset range, the frequency adjustment circuit adjusts the conversion parameter of the frequency generation circuit based on the first frequency deviation so that the target frequency of the target frequency signal is within a second preset range relative to a second frequency deviation of a second preset frequency. The transmission circuit transmits a signal based on the target frequency signal.

Description

Technical Field

[0001] The present invention relates to signal relay technology, and in particular to a signal relay device and method with a frequency correction mechanism. Background Art

[0002] In electronic devices, signal transmission technology is increasingly demanding higher speeds. For example, the HDMI 2.1 specification defines a new Fixed Rate Link (FRL) transmission mode to increase transmission bandwidth. Before signal transmission begins, a handshake is performed to check whether the signal quality meets HDMI 2.1 requirements at high speeds. If a fixed rate link connection is established, bandwidth can reach up to 12Gbps.

[0003] In such situations, when signal relay devices are used for high-speed data transmission, they often require a clock using quartz oscillation technology to maintain transmission accuracy. However, this configuration increases costs. Balancing accuracy and cost becomes a major challenge in signal relay device design. Summary of the Invention

[0004] In view of the problems in the prior art, an object of the present invention is to provide a signal relay device and method with a frequency correction mechanism to improve the prior art.

[0005] The present invention includes a signal relay device with a frequency correction mechanism, comprising: a clock generation circuit, a frequency generation circuit, a clock measurement circuit, a frequency adjustment circuit, and a transmission circuit. The clock generation circuit is configured to generate a clock source signal. The frequency generation circuit is configured to receive the clock source signal and generate a target frequency signal based on a conversion parameter. The clock measurement circuit is configured to measure a first frequency deviation of the source frequency of the clock source signal relative to a first preset frequency based on an external reference clock signal. The frequency adjustment circuit is configured to adjust the conversion parameter of the frequency generation circuit based on the first frequency deviation when the first frequency deviation is not within a first preset range, so that the target frequency of the target frequency signal is within a second preset range relative to a second frequency deviation of a second preset frequency. The transmission circuit is configured to transmit a signal based on the target frequency signal.

[0006] The present invention also includes a signal relay method with a frequency correction mechanism, which is applied to a signal relay device, including: causing a clock generating circuit to generate a clock source signal; causing a frequency generating circuit to receive the clock source signal and generate a target frequency signal according to a conversion parameter; causing a clock measuring circuit to measure a first frequency deviation of the source frequency of the clock source signal relative to a first preset frequency according to an external reference clock signal; causing a frequency adjustment circuit to adjust a conversion parameter of the frequency generating circuit according to the first frequency deviation when the first frequency deviation is not within a first preset range, so that a second frequency deviation of the target frequency signal relative to a second preset frequency is within a second preset range; and causing a transmission circuit to transmit a signal according to the target frequency signal.

[0007] The features, implementation and effects of the present invention are described in detail below with reference to the accompanying drawings for preferred embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1A as well as Figure 1B They are respectively module diagrams of an electronic device according to an embodiment of the present invention;

[0009] Figure 2 A more detailed circuit diagram of a signal relay device according to an embodiment of the present invention;

[0010] Figure 3 is a schematic diagram showing a clock source signal and an external reference clock signal according to an embodiment of the present invention; and

[0011] Figure 4 The flowchart of a signal relay method with a frequency correction mechanism according to an embodiment of the present invention is shown. DETAILED DESCRIPTION

[0012] An object of the present invention is to provide a signal relay device and method with a frequency correction mechanism, which adjusts the frequency deviation of the target frequency signal of the frequency generating circuit according to the frequency deviation of the clock source signal, thereby maintaining the accuracy of the clock signal in a low-cost situation without using quartz oscillation technology to set the clock.

[0013] Please also refer to Figure 1A as well as Figure 1B . Figure 1A as well as Figure 1B They are module diagrams of an electronic device 100 according to an embodiment of the present invention.

[0014] exist Figure 1A In the embodiment of the present invention, the electronic device 100 includes a circuit board 110 , a signal receiving chip 120 , and a signal relay device 130 with a frequency correction mechanism. The signal receiving chip 120 and the signal relay device 130 are disposed on the circuit board 110 .

[0015] The electronic device 100 can communicate with another electronic device (not shown) including a signal transmission chip 140 according to a transmission interface specification such as, but not limited to, one of High Definition Multimedia Interface (HDMI), DisplayPort (DP), and Universal Serial Bus (USB) Type-C.

[0016] exist Figure 1A In the embodiment, the signal relay device 130 is disposed between the signal receiving chip 120 and the signal transmission chip 140, and is configured to relay and transmit signals between the signal receiving chip 120 and the signal transmission chip 140. For example, the electronic device 100 including the signal receiving chip 120 operates as a signal receiving end (sink), and may be, for example, but not limited to, a device such as a television or a monitor. Another electronic device including the signal transmission chip 140 operates as a signal transmission end (source), and may be, for example, a laptop computer or a DVD player. Therefore, the signal receiving chip 120 receives and processes the signal from the signal transmission chip 140 through the signal relay device 130, for example, but not limited to, processing and displaying the image signal.

[0017] The signal relay device 130 includes a transmission circuit TX and a receiving circuit RX. Figure 1A As shown, the signal relay device 130 can receive a signal from the signal transmission chip 140 through the receiving circuit RX via a path shown by a dotted line, and transmit the signal to the signal receiving chip 120 through the transmitting circuit TX.

[0018] In contrast, Figure 1B In the embodiment of the present invention, the electronic device 100 includes a circuit board 110 , a signal transmission chip 140 , and a signal relay device 130 with a frequency correction mechanism. The signal transmission chip 140 and the signal relay device 130 are disposed on the circuit board 110 .

[0019] The electronic device 100 can communicate with another electronic device (not shown) including the signal receiving chip 120 according to a transmission interface specification such as, but not limited to, one of High Definition Multimedia Interface, DisplayPort, and Universal Serial Bus Type-C.

[0020] exist Figure 1BIn the embodiment, the signal relay device 130 is also disposed between the signal receiving chip 120 and the signal transmission chip 140, and is configured to relay and transmit signals between the signal receiving chip 120 and the signal transmission chip 140. For example, the electronic device 100 including the signal transmission chip 140 operates as a signal transmission end, and may be, for example, but not limited to, a laptop computer or a DVD player. Another electronic device including the signal receiving chip 120 operates as a signal receiving end, and may be, for example, but not limited to, a television or a monitor. Therefore, the signal transmission chip 140 transmits a signal through the signal relay device 130 to be received from the signal receiving chip 120 for processing, for example, but not limited to, processing and displaying an image signal.

[0021] Similarly, the signal relay device 130 includes a transmission circuit TX and a receiving circuit RX. Figure 1B As shown, the signal relay device 130 can receive a signal from the signal transmission chip 140 through the receiving circuit RX via a path shown by a dotted line, and transmit the signal to the signal receiving chip 120 through the transmitting circuit TX.

[0022] The signal relay device 130 can perform signal relay transmission according to the transmission interface specifications of the signal receiving chip 120 and the signal transmitting chip 140, thereby avoiding signal attenuation caused by long connection lines (e.g., HDMI lines) or circuit board traces between the signal receiving chip 120 and the signal transmitting chip 140.

[0023] For example, the signal relay device 130 can relay signals according to a transmission interface specification of one of the High Definition Multimedia Interface, DisplayPort, and Universal Serial Bus Type-C. In various embodiments, the signal relay device 130 can be implemented, for example, but not limited to, a retimer or a redriver.

[0024] It should be noted that the above configuration of the signal relay device 130 between the signal receiving chip 120 and the signal transmitting chip 140 is merely an example. In other embodiments, the signal relay device 130 may also be configured between any two circuits included in the electronic device 100 as required.

[0025] The structure and operation of the signal relay device 130 will be described in more detail below.

[0026] Please refer to Figure 2 . Figure 2 FIG. 1 is a more detailed circuit diagram of the signal relay device 130 according to an embodiment of the present invention.

[0027] like Figure 2As shown, in addition to the transmission circuit TX and the receiving circuit RX, the signal relay device 130 further includes: a clock generation circuit 200 , a frequency generation circuit 210 , a clock measurement circuit 220 and a frequency adjustment circuit 230 .

[0028] The clock generation circuit 200 is configured to generate a clock source signal CKS. The frequency generation circuit 210 is configured to receive the clock source signal CKS and generate a target frequency signal FQS based on a conversion parameter CP. More specifically, the frequency generation circuit 210 is configured to upconvert the clock signal CKS having a source frequency based on the conversion parameter CP to generate a target frequency signal FQS having a target frequency. The transmission circuit TX is configured to transmit a signal based on the target frequency signal FQS.

[0029] It should be noted that, in one embodiment, the clock generation circuit 200 , the frequency generation circuit 210 , the clock measurement circuit 220 , and the frequency adjustment circuit 230 may also be integrated with the circuits included in the transmission circuit TX to become part of the transmission circuit TX. The present invention is not limited thereto.

[0030] In the absence of temperature fluctuations, the source frequency of the clock source signal CKS is maintained at a first predetermined frequency, while the target frequency of the target clock signal FQS is maintained at a second predetermined frequency. In a numerical example, the first predetermined frequency may be, for example, but not limited to, 27 megahertz (MHz), and the second predetermined frequency may be, for example, but not limited to, 3 gigahertz (GHz), 8 gigahertz, or 12 gigahertz, depending on the application.

[0031] In one embodiment, the clock generation circuit 200 may be, for example, but not limited to, an inductor-capacitor oscillator (LCtank) circuit, which generates the clock source signal CKS using a non-quartz oscillation technique. However, non-quartz oscillation techniques are susceptible to temperature fluctuations, causing the source frequency of the clock source signal CKS to deviate from the first predetermined frequency. If the conversion parameter CP remains unchanged, the target frequency of the target frequency signal FQS generated by the frequency generation circuit 210 will also deviate from the second predetermined frequency.

[0032] When the transmission circuit TX of the signal relay device 130 performs signal relay transmission according to the target frequency signal FQS through the aforementioned transmission interface specifications (e.g., HDMI, DP, or USB Type-C), the target frequency of the target frequency signal FQS may deviate too greatly from the second preset frequency and fail to comply with the specifications of these transmission interface specifications.

[0033] The clock measurement circuit 220 is configured to measure a first frequency deviation of the source frequency of the clock source signal CKS relative to a first predetermined frequency based on an external reference clock signal CKE. The external reference clock signal CKE is provided by a component disposed on the circuit board 110 and outside the signal relay device 130, such as but not limited to Figure 1A The signal receiving chip 120 shown in FIG. 1 , or Figure 1B The signal transmission chip 140 shown in FIG.

[0034] In one embodiment, the fluctuation range of the average frequency of the external reference clock signal CKE within a predetermined time period is less than a predetermined value. More specifically, unlike the jitter-free clock signal generated by quartz oscillation technology, the external reference clock signal CKE only needs to be generally stable over a period of time, and jitter is allowed.

[0035] In one embodiment, the clock measurement circuit 220 calculates the frequency offset by comparing the clock counts of the clock source signal CKS and the external reference clock signal CKE, wherein the clock counts can be obtained by counting the number of rising edges of each clock signal.

[0036] Please refer to Figure 3 . Figure 3 FIG. 1 is a schematic diagram illustrating a clock source signal CKS and an external reference clock signal CKE according to an embodiment of the present invention.

[0037] like Figure 3 As shown, the clock source signal CKS has a cycle length Tcks (equivalent to the inverse of the source frequency Fcks) and a plurality of cycles Cycle_cks. The external reference clock signal CKE has a cycle length Tcke (equivalent to the inverse of the source frequency Fcke) and a plurality of cycles Cycle_cke. If the frequency ratio between the clock source signal CKS and the external reference clock signal CKE is M / N, then the relationship between the two can be expressed as:

[0038] Tcke*Cycle_cke(N)=Tcks*Cycle_cks(M) (Formula 1)

[0039] In a numerical example, the source frequency of the clock source signal CKS is 27 MHz, and the reference frequency of the external reference clock signal CKE is 14.318 MHz. If the measured external reference clock signal CKE is 8000 cycles, then its relationship with the clock source signal CKS is as follows:

[0040] (1 / 14.318)*8000=(1 / Fcks)*Cycle_cks(Formula 2)

[0041] Therefore, if the measured cycle number Cycle_cks is 15086, the source frequency Fcks of the clock source signal CKS is exactly 27 MHz. If the measured cycle number Cycle_cks is 15091, the source frequency Fcks of the clock source signal CKS is 27.009 MHz, which is 333 ppm off, or more than 300 ppm.

[0042] The frequency adjustment circuit 230 is configured to adjust the conversion parameter CP of the frequency generation circuit 210 based on the first frequency offset when the first frequency offset is not within the first predetermined range, so as to ensure that the second frequency offset of the target frequency signal FQS relative to the target frequency is within the second predetermined range. More specifically, the frequency adjustment circuit 230 can adjust the target frequency of the target frequency signal FQS to a value that is neither too high nor too low relative to the second predetermined frequency when the source frequency of the clock source signal CKS is too high or too low relative to the first predetermined frequency.

[0043] Among them, with respect to the target frequency, "within the second preset range" means complying with the transmission interface specification and being within the allowable range specified by the specification. For example, in the HDMI 2.1 standardized protocol, the error requirement for the timing of the transmission end is no more than 300 Hz per million Hz (300ppm (parts per million)). Other HDMI, DP or USBType-C transmission interface specifications also have corresponding allowable ranges, which will not be repeated here. Correspondingly, if the above-mentioned "second preset range" refers to an error requirement of no more than 300 Hz per million Hz, then with respect to the source frequency of the clock source signal CKS, "within the first preset range" may also refer to an error requirement of no more than 300 Hz per million Hz.

[0044] In one embodiment, the frequency adjustment circuit 230 is, for example, but not limited to, an 8051 control chip or other chip capable of executing software or firmware. When the measured first frequency offset is not within a first predetermined range, the clock measurement circuit 220 issues an interrupt signal IS to the frequency adjustment circuit 230. In one embodiment, the interrupt signal IS may include information about the first frequency offset, enabling the frequency adjustment circuit 230 to calculate a parameter adjustment PA based on the first frequency offset and subsequently adjust the conversion parameter CP of the frequency generation circuit 210 based on the parameter adjustment PA.

[0045] After adjusting the conversion parameter CP, the frequency generating circuit 210 can make the second frequency offset of the target frequency signal FQS relative to the target frequency fall within a second preset range, thereby making the signal relay transmission performed by the transmitting circuit TX comply with the corresponding transmission interface specification.

[0046] In one embodiment, when the first frequency offset is within the first predetermined range, the frequency adjustment circuit 230 does not adjust the conversion parameter CP.

[0047] Therefore, the signal relay device of the present invention can measure a first frequency deviation of the source frequency of the clock source signal relative to a first predetermined frequency. If the first frequency deviation is outside the first predetermined range, the device adjusts the conversion parameters of the frequency generation circuit to maintain a second frequency deviation of the target frequency signal relative to the target frequency within a second predetermined range. This device can maintain clock signal accuracy without requiring the use of quartz oscillation technology to set the clock at a low cost.

[0048] Please refer to Figure 4 . Figure 4 FIG. 4 is a flow chart showing a signal relay method 400 with a frequency correction mechanism according to an embodiment of the present invention.

[0049] In addition to the aforementioned devices, the present invention also discloses a signal relay method 400, which is used in, for example, but not limited to Figure 2 In the signal relay device 130. An embodiment of the signal relay method 400 is as follows Figure 4 As shown, the following steps are included:

[0050] In step S410 , the clock generating circuit 200 generates a clock source signal CKS.

[0051] In step S420 , the frequency generating circuit 210 receives the clock source signal CKS and generates the target frequency signal FQS according to the conversion parameters.

[0052] In step S430 , the clock measurement circuit 220 measures a first frequency offset of the source frequency of the clock source signal CKS relative to a first predetermined frequency according to the external reference clock signal CKE.

[0053] In step S440 , the first frequency offset is determined to be outside the first predetermined range. In one embodiment, the clock measurement circuit 220 determines whether the first frequency offset is outside the first predetermined range and transmits an interrupt signal IS to the frequency adjustment circuit 230 .

[0054] In step S450, when the first frequency offset is not within the first preset range, the frequency adjustment circuit 230 adjusts the conversion parameter CP of the frequency generation circuit 210 according to the first frequency offset, so that the second frequency offset of the target frequency signal relative to the second preset frequency is within the second preset range.

[0055] In step S460 , the frequency adjustment circuit 230 does not adjust the conversion parameter CP when the first frequency offset is within a first predetermined range.

[0056] In step S470 , after the process executes step S450 or step S460 , the transmission circuit TX is enabled to perform signal transmission according to the target frequency signal FQS.

[0057] It should be noted that the above embodiment is only an example. In other embodiments, those skilled in the art with ordinary knowledge can make changes and modifications without departing from the spirit of the present invention.

[0058] In summary, the signal relay device and method of the present invention can adjust the frequency deviation of the target frequency signal of the frequency generating circuit according to the frequency deviation of the clock source signal, thereby maintaining the accuracy of the clock signal at a low cost without using quartz oscillation technology to set the clock.

[0059] Although the embodiments of the present invention are described above, these embodiments are not intended to limit the present invention. A person skilled in the art with ordinary knowledge in this technical field may make changes to the technical features of the present invention based on the explicit or implicit contents of the present invention. These changes may fall within the scope of patent protection sought by the present invention. In other words, the scope of patent protection of the present invention shall be based on the definition of the claims.

[0060] Description of reference numerals:

[0061] 100: Electronic devices

[0062] 110: Circuit board

[0063] 120: Signal receiving chip

[0064] 130: Signal relay device

[0065] 140: Signal transmission chip

[0066] 200: Clock generation circuit

[0067] 210: Frequency generation circuit

[0068] 220: Clock measurement circuit

[0069] 230: Frequency adjustment circuit

[0070] 400: Signal relay method

[0071] S410~S470: Steps

[0072] CKE: external reference clock signal

[0073] CKS: clock source signal

[0074] CP: Conversion parameter

[0075] FQS: Target Frequency Signal

[0076] IS: interrupt signal

[0077] PA: parameter adjustment amount

[0078] RX: receiving circuit

[0079] Tcke, Tcks: cycle length

[0080] Cycle_cke, Cycle_cks: cycles

[0081] TX: Transmit circuit

Claims

1. A signal relay device with a frequency correction mechanism, comprising: a clock generating circuit configured to generate a clock source signal; a frequency generating circuit configured to receive the clock source signal and generate a target frequency signal according to a conversion parameter; a clock measurement circuit configured to measure a first frequency deviation of a source frequency of the clock source signal relative to a first predetermined frequency according to an external reference clock signal; a frequency adjustment circuit configured to adjust the conversion parameter of the frequency generation circuit according to the first frequency offset when the first frequency offset is not within a first preset range, so that a target frequency of the target frequency signal is within a second preset range relative to a second frequency offset of a second preset frequency; as well as A transmission circuit is configured to perform a signal transmission according to the target frequency signal.

2. The signal relay device according to claim 1, characterized in that: The clock measurement circuit generates an interrupt signal to the frequency adjustment circuit when the first frequency offset is not within the first preset range.

3. The signal relay device according to claim 1, wherein: The frequency adjustment circuit is configured to calculate and generate a parameter adjustment value according to the first frequency offset value, and further adjust the conversion parameter of the frequency generation circuit according to the parameter adjustment value.

4. The signal relay device according to claim 1, wherein: The clock generating circuit generates the clock source signal according to a non-quartz oscillation technology.

5. The signal relay device according to claim 1, wherein: A variation range of an average frequency of the external reference clock signal within a preset time is smaller than a preset value.

6. The signal relay device according to claim 1, wherein: The signal relay device is disposed on a circuit board and between a signal transmission chip and a signal receiving chip. One of the signal transmission chip and the signal receiving chip is disposed on the circuit board and provides the external reference clock signal.

7. The signal relay device according to claim 6, characterized in that: The signal relay device further includes a receiving circuit for performing signal relay transmission between the signal transmission chip and the signal receiving chip through the transmission circuit and the receiving circuit.

8. The signal relay device according to claim 1, wherein: The signal relay device performs signal relay transmission according to a transmission interface specification of one of the high-definition multimedia interface, display port and universal serial bus.

9. The signal relay device according to claim 1, wherein: The signal relay device is a retimer or a redriver.

10. A signal relay method with a frequency correction mechanism, applied in a signal relay device, comprising: enabling a clock generating circuit to generate a clock source signal; enabling a frequency generating circuit to receive the clock source signal and generate a target frequency signal according to a conversion parameter; enabling a clock measurement circuit to measure a first frequency deviation of a source frequency of the clock source signal relative to a first preset frequency according to an external reference clock signal; causing a frequency adjustment circuit to adjust the conversion parameter of the frequency generation circuit according to the first frequency offset when the first frequency offset is not within a first preset range, so that a target frequency of the target frequency signal is within a second preset range relative to a second frequency offset of a second preset frequency; and A transmission circuit is enabled to perform signal transmission according to the target frequency signal.

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