A semiconductor memory device and a forming method

Abstract

The present application relates to the technical field of semiconductor, especially to a semiconductor memory device and a forming method, the semiconductor memory device comprises a substrate; a plurality of active region structures defined on the substrate; a shallow trench isolation provided in the substrate, the shallow trench isolation surrounds the plurality of active region structures; a plurality of wire structures extending along a first direction in parallel to each other, the wire structure comprises a first region and a second region, the first region is located above the active region structure, and the second region is located above the shallow trench isolation; in a direction perpendicular to the substrate, the first region has a greater depth than the second region. In this way, the row hammer effect can be avoided.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of semiconductor technology, and in particular to a semiconductor memory device and a forming method. BACKGROUND

[0002] With the development of dynamic random access memory (DRAM) manufacturing process, in order to make DRAM have higher density, thereby reducing the size of each memory cell in DRAM, a buried word line structure is usually used.

[0003] However, the existing trench gate still has some problems. When the size of the memory continues to shrink, the buried word line cuts through the passing gate area between the two active regions, and during repeated reading and writing, accumulated parasitic electrons are generated in the active regions on both sides. When the parasitic electrons flow to the source / drain electrode electrically connected to the bit line through the bottom of another buried word line adjacent to the row of buried word lines, it will cause data reading and writing errors of the column bit line, which is called row hammer effect. SUMMARY

[0004] Embodiments of the present application provide a semiconductor memory device and a forming method to solve the row hammer effect problem.

[0005] The specific technical solutions provided by the embodiments of the present application are as follows:

[0006] A semiconductor memory device, comprising:

[0007] a substrate;

[0008] a plurality of active region structures defined on the substrate;

[0009] a shallow trench isolation provided in the substrate, the shallow trench isolation surrounding the plurality of active region structures;

[0010] a plurality of wire structures extending in parallel with each other along a first direction, the wire structures comprising a first region and a second region, the first region being located above the active region structures, and the second region being located above the shallow trench isolation; in a direction perpendicular to the substrate, the first region has a greater depth than the second region.

[0011] Optionally, the first region of the wire structure further comprises a gate structure located at the bottom of the first region of the wire structure, the gate structure comprising a barrier layer and a first sub-conductive layer, the barrier layer being located on part of the sidewall and the bottom surface of the bottom of the first region of the wire structure, and the first sub-conductive layer being provided in the barrier layer.

[0012] Optionally, the first region of the wire structure further comprises an insulating sidewall and a second sub-conductive layer, the insulating sidewall is located on the part of sidewall of the first region of the wire structure above the bottom barrier layer, the second sub-conductive layer is arranged in the insulating sidewall, and the insulating sidewall is arranged around the second sub-conductive layer.

[0013] Optionally, the first region of the wire structure further comprises a third sub-conductive layer, the third sub-conductive layer is arranged on the insulating sidewall and the second sub-conductive layer, and is connected with the second region of the wire structure.

[0014] Optionally, the semiconductor storage device further comprises a covering layer, the covering layer is filled in the interior of the second region and covers the third sub-conductive layer.

[0015] Optionally, the depth of the first region is 1 / 2-3 / 4 of the depth of the second region.

[0016] Optionally, the barrier layer comprises a metal nitride.

[0017] Optionally, the material of the first sub-conductive layer, the second sub-conductive layer and the third sub-conductive layer is the same.

[0018] Optionally, the thickness of the barrier layer is greater than the thickness of the insulating sidewall.

[0019] Optionally, the third sub-conductive layer is provided with an adhesion layer, and the adhesion layer comprises titanium nitride.

[0020] A forming method of a semiconductor storage device comprises:

[0021] providing a substrate;

[0022] forming active region structures and shallow trench isolations on the substrate, and the shallow trench isolations surround the plurality of active region structures;

[0023] performing first etching on the active region structures and the shallow trench isolations to form a plurality of wire grooves extending in parallel along a first direction, and the etching rate of the active region structures is greater than the etching rate of the shallow trench isolations in the first etching;

[0024] forming a wire structure in the plurality of wire grooves, the wire structure comprises a first region and a second region, the first region is located above the active region structures, and the second region is located above the shallow trench isolations; and the depth of the first region is greater than the depth of the second region.

[0025] Optionally, forming the wire structure in the plurality of wire grooves comprises:

[0026] depositing a barrier layer on the sidewall of the wire structure;

[0027] depositing a first sub-conductive layer in the barrier layer;

[0028] etching back the barrier layer and the first sub-conductive layer to retain a portion of the barrier layer and the first sub-conductive layer at the bottom of the first region, forming a gate structure, wherein the barrier layer is on the sidewall and bottom surface of the bottom of the first region of the wire structure, and the first sub-conductive layer is disposed in the barrier layer.

[0029] Optionally, the first etching includes forming a plurality of first mask structures in the first direction above the active region structure and the shallow trench isolation, and etching the active region structure and the shallow trench isolation according to the first mask structures, wherein the first mask structures have a first width.

[0030] Optionally, forming the wire structure in the plurality of wire trenches further includes:

[0031] After forming the gate structure, depositing an insulating material;

[0032] etching back the insulating material to fill the trench above the gate structure;

[0033] forming a plurality of second mask structures in the first direction above the insulating material, wherein the second mask structures have a second width, and the second width is less than the first width;

[0034] etching the insulating material according to the second mask structures to form an insulating sidewall above the barrier layer of the first region;

[0035] filling a second sub-conductive layer in the insulating sidewall, wherein the second sub-conductive layer is disposed in the insulating sidewall.

[0036] Optionally, forming the wire structure in the plurality of wire trenches further includes:

[0037] depositing a fourth sub-conductive layer on the insulating sidewall and the second sub-conductive layer, wherein the fourth sub-conductive layer fills the wire trench.

[0038] Optionally, forming the wire structure in the plurality of wire trenches further includes:

[0039] forming a plurality of third mask structures in the first direction above the fourth sub-conductive layer, wherein the third mask structures have a third width, and the third width is less than the second width;

[0040] etching the fourth sub-conductive layer according to the third mask structures to form a third sub-conductive layer, wherein the third sub-conductive layer has a width that is less than or equal to the third width of the third mask structures.

[0041] Optionally, after forming the conductive line structure in the plurality of conductive line grooves, a cover layer is deposited on the active region structure, the shallow trench isolation, and the third sub-conductive layer.

[0042] Optionally, the first region depth is 1 / 2-3 / 4 of the second region depth.

[0043] Optionally, the barrier layer comprises a metal nitride.

[0044] Optionally, the first sub-conductive layer, the second sub-conductive layer, and the third sub-conductive layer are made of the same material.

[0045] The semiconductor storage device in the embodiments of the present application comprises a substrate; a plurality of active region structures defined on the substrate; a shallow trench isolation provided in the substrate, the shallow trench isolation surrounding the plurality of active region structures; and a plurality of conductive line structures extending along a first direction in parallel to each other, the conductive line structure comprising a first region and a second region, the first region being above the active region structure, and the second region being above the shallow trench isolation, in a direction perpendicular to the substrate, the first region depth being greater than the second region depth. In this way, since the first region depth is greater than the second region depth, and the active region structures are not connected to each other, the row hammer effect problem can be avoided. BRIEF DESCRIPTION OF DRAWINGS

[0046] Figure 1 FIG. 1 is a structural schematic diagram of a semiconductor storage device in the embodiments of the present application;

[0047] Figure 2 FIG. 2 is a flowchart of a forming method of a semiconductor storage device in the embodiments of the present application;

[0048] Figure 3 FIG. 3 is a first schematic diagram of a semiconductor storage device in the embodiments of the present application;

[0049] Figure 4 FIG. 4 is a second schematic diagram of a semiconductor storage device in the embodiments of the present application;

[0050] Figure 5 FIG. 5 is a third schematic diagram of a semiconductor storage device in the embodiments of the present application;

[0051] Figure 6 FIG. 6 is a fourth schematic diagram of a semiconductor storage device in the embodiments of the present application;

[0052] Figure 7 FIG. 7 is a fifth schematic diagram of a semiconductor storage device in the embodiments of the present application;

[0053] Figure 8 FIG. 8 is a sixth schematic diagram of a semiconductor storage device in the embodiments of the present application;

[0054] Figure 9 Seventh schematic diagram of a semiconductor memory device in an embodiment of the application;

[0055] Figure 10 Eighth schematic diagram of a semiconductor memory device in an embodiment of the application;

[0056] Figure 11 Ninth schematic diagram of a semiconductor memory device in an embodiment of the application;

[0057] Figure 12 Tenth schematic diagram of a semiconductor memory device in an embodiment of the application;

[0058] Figure 13 Eleventh schematic diagram of a semiconductor memory device in an embodiment of the application;

[0059] Figure 14 Top view of a semiconductor memory device in an embodiment of the application;

[0060] Figure 15 AA' cross-sectional schematic diagram in an embodiment of the application;

[0061] Figure 16 BB' cross-sectional schematic diagram in an embodiment of the application.

[0062] Explanation of main element symbols

[0063] 10 substrate

[0064] 11 active region structure

[0065] 12 shallow trench isolation

[0066] 13 first mask structure

[0067] 14 third mask structure

[0068] 15 wire trench

[0069] 16 fifth mask structure

[0070] 17 fourth mask structure

[0071] 20 first region

[0072] 21 gate structure

[0073] 22 barrier layer

[0074] 23 first sub-conductive layer

[0075] 24 insulating sidewall

[0076] 25 second sub-conductive layer

[0077] 26 third sub-conductive layer

[0078] 27 fourth sub-conductive layer

[0079] 30 second region

[0080] 40 cover layer

[0081] 90 first direction

[0082] 91 second direction

[0083] 92 third direction DETAILED DESCRIPTION

[0084] The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only some of the embodiments of the present application, but not all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative work fall within the scope of the present application.

[0085] Dynamic random access memory (DRAM) is a kind of volatile memory, which includes an array region composed of a plurality of memory cells and a peripheral region composed of a control circuit. Each memory cell includes a transistor electrically connected to a capacitor, and the storage or release of charge in the capacitor is controlled by the transistor to achieve the purpose of storing data. The control circuit can be positioned to each memory cell to control the access of its data through the word line and the bit line which cross the array region and are electrically connected to each memory cell.

[0086] In the related art, in order to enable the DRAM to have higher density, a buried word line (WL) structure is generally used to reduce the size of each memory cell in the DRAM.

[0087] However, the trench gate in the related art still has some problems. When the size of the memory continues to be shrunk, the buried word line cuts through the passing gate region between two active regions, and during repetitive reading and writing, accumulated parasitic electrons are generated in the two active regions on both sides. When the parasitic electrons flow to the source / drain electrically connected to a bit line through the bottom of another buried word line adjacent to the row of buried word lines, it will cause the data of the column of bit lines to be wrong, thereby causing the row hammer problem.

[0088] To solve the above problems, the embodiment of the present application provides a semiconductor memory device, which comprises a substrate, a plurality of active region structures defined on the substrate, a shallow trench isolation arranged in the substrate, the shallow trench isolation surrounding the plurality of active region structures, a plurality of wire structures extending in parallel to each other along a first direction, the wire structure comprising a first region and a second region, the first region being above the active region structure, the second region being above the shallow trench isolation, and the depth of the first region being greater than the depth of the second region in a direction perpendicular to the substrate. In this way, data errors between adjacent bit lines can be avoided, thereby avoiding row hammer effect problems.

[0089] Based on the above embodiment, referring to Figure 1 As shown in the structure schematic diagram of the semiconductor memory device in the embodiment of the present application, the semiconductor memory device comprises a substrate 10, for example, a semiconductor substrate 10 composed of silicon. Then, based on the substrate 10, a plurality of active region structures 11 are defined on the substrate 10, that is, the surface of the substrate 10 is connected with the surface of the active region structure 11. The upper surface of the substrate 10 is connected with the plurality of active region structures 11, and the shape of each active region structure 11 is an island-shaped column. The substrate 10 is arranged with a shallow trench isolation 12, which surrounds the plurality of active region structures 11. The shallow trench isolation 12 is used to isolate the plurality of active region structures 11, that is, each active region structure 11 is isolated from each other by the shallow trench isolation 12, and each active region structure 11 is not connected with each other. In addition, the semiconductor memory device comprises a plurality of wire structures, and the plurality of wire structures extend in parallel to each other along a first direction 90. Each wire structure comprises a first region 20 and a second region 30, the first region 20 is above the active region structure 11, the second region 30 is above the shallow trench isolation 12, and the first region 20 and the second region 30 are etched along a direction perpendicular to the substrate 10. The depth of the first region 20 is greater than the depth of the second region 30.

[0090] In the embodiment of the present application, the first region 20 of the wire structure comprises a gate structure 21, an insulating sidewall 24, a second sub-conductive layer 25 and a third sub-conductive layer 26. The gate structure 21 is located at the bottom of the first region 20 of the wire structure, and the bottom of the gate structure 21 is connected with the bottom surface of the first region 20. The insulating sidewall 24 is located at the sidewall above the blocking layer 22 at the bottom of the first region 20 of the wire structure. The second sub-conductive layer 25 is arranged in the insulating sidewall 24, and the insulating sidewall 24 surrounds the second sub-conductive layer 25. That is, the insulating sidewall 24 is deposited on the sidewall surface of the first region 20 of the wire structure, and surrounds the second sub-conductive layer 25. In the preferred embodiment of the present application, the insulating sidewall 24 completely wraps the second sub-conductive layer 25. The bottom of the second sub-conductive layer 25 is connected with the top surface of the gate structure 21, and the top surface of the second sub-conductive layer 25 and the insulating inner wall are flush with the opening edge of the first region 20. The third sub-conductive layer 26 covers the insulating sidewall 24 and the second sub-conductive layer 25, and is connected with the second region 30 of the wire structure.

[0091] The gate structure 21 comprises a blocking layer 22 and a first sub-conductive layer 23. The blocking layer 22 is located at the sidewall at the bottom of the first region 20 of the wire structure. The first sub-conductive layer 23 is arranged in the blocking layer 22. That is, the blocking layer 22 is deposited on the sidewall and the bottom surface at the bottom of the first region 20 of the wire structure. The bottom of the first sub-conductive layer 23 is connected with the bottom surface of the first region 20 of the wire structure, and is arranged in the blocking layer 22. In the preferred embodiment of the present application, the blocking layer 22 completely wraps the first sub-conductive layer 23.

[0092] In addition, in the embodiment of the present application, the semiconductor storage device further comprises a covering layer 40, which is filled in the interior of the second region 30 and covers the third sub-conductive layer 26.

[0093] It should be noted that, in the embodiment of the present application, the blocking layer 22 comprises a metal nitride, and the material of the insulating sidewall 24 is silicon nitride. The materials of the first sub-conductive layer 23, the second sub-conductive layer 25 and the third sub-conductive layer 26 are tungsten or polysilicon. The material of the first sub-conductive layer 23, the second sub-conductive layer 25 and the third sub-conductive layer 26 is the same. Of course, the materials of the structures in the embodiment of the present application are not limited.

[0094] It should be further noted that the depth of the first region 20 and the depth of the second region 30 can be set by oneself, but the depth of the first region 20 is greater than the depth of the second region 30, for example, the depth of the first region 20 is 1 / 2-3 / 4 of the depth of the second region 30; the height of the gate structure 21 can be set by oneself, for example, the height of the gate structure 21 is 1 / 4 of the depth of the first region 20; the height of the insulating side wall 24 and the second sub-conductive layer 25 can be set by oneself, for example, the height of the insulating side wall 24 and the second sub-conductive layer 25 is 1 / 4 of the depth of the first region 20, and the thickness of the barrier layer 22 is greater than the thickness of the insulating side wall 24. The thickness of the barrier layer 22 is 3-5 nm, and the thickness of the insulating side wall 24 is 5-10 nm, of course, the depth and thickness in the embodiment of the present application are not limited.

[0095] Further, in the embodiment of the present application, an adhesion layer (not shown in the figure) is provided on the third sub-conductive layer 26, and the adhesion layer includes titanium nitride, and the material of the adhesion layer is not limited in the embodiment of the present application.

[0096] In the embodiment of the present application, the semiconductor storage device includes a substrate, a plurality of active region structures defined on the substrate, a shallow trench isolation provided in the substrate, the shallow trench isolation surrounds the plurality of active region structures, a plurality of wire structures extending along a first direction in parallel to each other, the wire structure includes a first region and a second region, the first region is located above the active region structure, the second region is located above the shallow trench isolation, and in a direction perpendicular to the substrate, the depth of the first region is greater than the depth of the second region. In this way, since the depth of the first region is greater than the depth of the second region, the influence of the adjacent active region structure when the bit line structure of the adjacent active region structure in the same direction is powered on can be avoided, thereby weakening the influence of the row hammer effect.

[0097] Based on the above embodiment, the forming method of the semiconductor storage device provided in the embodiment of the present application is described in detail below, referring to Figure 2 The flow chart of the forming method of the semiconductor storage device in the embodiment of the present application is shown, and specifically includes:

[0098] Step 200: providing a substrate.

[0099] In the embodiment of the present application, a substrate is provided.

[0100] The material of the substrate is silicon, but the material of the substrate is not limited in the embodiment of the present application.

[0101] Step 210: forming an active region structure and a shallow trench isolation on the substrate, and the shallow trench isolation surrounds the plurality of active region structures.

[0102] In the embodiment of the present application, the active region structure is formed on the substrate, and after the active region structure is obtained, the shallow trench isolation is formed around the active region structure. Therefore, the formed shallow trench isolation surrounds the plurality of active region structures.

[0103] In the embodiment of the present application, a possible implementation of forming the active region structure and the shallow trench isolation is provided, and the step 210 in the embodiment of the present application is described in detail below, specifically including:

[0104] S1: forming a plurality of fourth mask structures on the substrate along the second direction, and the plurality of fourth mask structures are horizontally arranged.

[0105] In the embodiment of the present application, first, a plurality of fifth mask structures are formed above the substrate, wherein each fifth mask structure extends along the second direction, and the fifth mask structures are horizontally arranged. Referring to Figure 3 As shown in FIG. 1, it is a first schematic diagram of the semiconductor storage device in the embodiment of the present application, and specifically, a plurality of fifth mask layer structures 16 are formed on the upper surface of the substrate 10, and each fifth mask layer structure 16 is horizontally arranged on the substrate 10 along the second direction 91.

[0106] It should be noted that the lower surface of the plurality of fifth mask structures 16 is connected with the upper surface of the substrate 10.

[0107] Then, the plurality of fifth mask structures are etched along the third direction, so as to form a plurality of fourth mask structures, and the fourth mask structures are arranged in a staggered manner. The third direction is perpendicular to the second direction. Referring to Figure 4 As shown in FIG. 2, it is a second schematic diagram of the semiconductor storage device in the embodiment of the present application, and since the third direction 92 is perpendicular to the second direction 91, after this etching, the fourth mask structures 17 arranged in a staggered manner can be formed. That is, the plurality of fourth mask structures 17 arranged in a staggered manner are arranged on the substrate 10.

[0108] S2: etching the substrate downward along the first direction to form a plurality of active region structures.

[0109] In the embodiment of the present application, the substrate is etched downward along the first direction to form a plurality of active region structures. That is, in the embodiment of the present application, the substrate part except the plurality of fourth mask structures is etched downward along the first direction, so as to form the active region structure. Each active region structure includes the substrate and the fourth mask structure, and the fourth mask structure is connected with the top of the substrate. Referring to Figure 5As shown in the figure, the lower half of each active region structure 11 is the substrate 10, and the upper half is the fourth mask structure 17, and the upper surface of the substrate 10 is connected with the lower surface of the fourth mask structure 17.

[0110] It should be noted that in the present etching process, the fourth mask structure 17 does not need to be etched, and only the part of the substrate 10 without the fourth mask structure 17 is etched.

[0111] S3: Forming a shallow trench isolation around the plurality of active region structures.

[0112] In the embodiment of the present application, the isolation material is filled on the substrate until the upper end surface of the isolation material is flush with the upper end surface of the active region structure, so as to form a shallow trench isolation around the plurality of active region structures. Referring to Figure 6 As shown in the figure, the substrate 10 includes the active region structure 11 and the shallow trench isolation 12, and the upper end surface of the shallow trench isolation 12 is flush with the upper end surface of the active region structure 11, and each active region structure 11 is isolated from each other by the shallow trench isolation 12.

[0113] In the embodiment of the present application, the material of the shallow trench isolation 12 is not limited.

[0114] Step 220: performing a first etching on the active region structure and the shallow trench isolation to form a plurality of wire grooves extending along the first direction in parallel, and the etching rate of the active region structure is greater than the etching rate of the shallow trench isolation in the first etching.

[0115] In the embodiment of the present application, first, a plurality of first mask structures are formed above the active region structure and the shallow trench isolation along the first direction, and then the active region structure and the shallow trench isolation are etched according to the first mask structure, so as to form a plurality of wire grooves extending along the first direction in parallel. Referring to Figure 7 As shown in the figure, the substrate 10 includes the active region structure 11 and the shallow trench isolation 12, and the upper end surface of the shallow trench isolation 12 is flush with the upper end surface of the active region structure 11, and each active region structure 11 is isolated from each other by the shallow trench isolation 12. Figure 8As shown, it is the sixth schematic view of the semiconductor storage device in the embodiment of the present application, the first direction 90 is the vertical direction, the etching is performed on the active region structure 11 and the shallow trench isolation 12 along the vertical direction, that is, the etching is performed on the active region structure 11 and the shallow trench isolation 12 along the vertical direction downward, and the etching rate of the active region structure 11 is greater than the etching rate of the shallow trench isolation 12, thereby forming a plurality of wire grooves 15 extending along the first direction 90.

[0116] The width of the first mask structure 13 is the first width, for example, the first direction 90 can be the vertical direction, the etching rate of the active region structure 11 and the etching rate of the shallow trench isolation 12 can be set by itself, for example, the depth of the wire groove 15 obtained after etching is 1 / 2 of the height of the active region structure 11, but the depth is not limited in the embodiment of the present application.

[0117] For example, it is assumed that the height of the active region structure is 90 nm, and the depth of the wire groove is 1 / 2 of the height of the active region structure, so the depth of the wire groove obtained by etching is 45 nm.

[0118] It should be noted that in the embodiment of the present application, when the first etching is performed, the etching rate of the active region structure is greater than the etching rate of the shallow trench isolation.

[0119] Step 230: forming a wire structure in the plurality of wire grooves, the wire structure comprising a first region and a second region, the first region being located above the active region structure, and the second region being located above the shallow trench isolation; the first region having a greater depth than the second region.

[0120] In the embodiment of the present application, the wire structure is formed in the plurality of wire grooves, and the generated wire structure comprises a first region and a second region, the first region is located above the active region structure, and the second region is located above the shallow trench isolation, and the first region has a greater depth than the second region.

[0121] Specifically, the wire structure in the embodiment of the present application comprises a first region and a second region, the first region of the wire structure comprises a gate structure, an insulating sidewall and a second sub-conductive layer, and the steps of forming the gate structure in the embodiment of the present application are described in detail below, specifically comprising:

[0122] S1: depositing a barrier layer on the sidewall of the wire structure.

[0123] In the embodiment of the present application, the barrier layer is deposited in the wire structure by a preset deposition method.

[0124] It should be noted that the barrier layer is deposited in the entire wire structure.

[0125] S2: depositing a first sub-conductive layer in the barrier layer.

[0126] In this embodiment, a first sub-conductive layer is deposited within the barrier layer using a preset deposition method.

[0127] S3: Etch back the barrier layer and the first sub-conductive layer, retaining a portion of the barrier layer and the first sub-conductive layer located at the bottom of the first region to form a gate structure.

[0128] The barrier layer is located on a portion of the sidewall and bottom surface of the bottom of the first region of the conductor structure, and the first sub-conductive layer is disposed within the barrier layer.

[0129] In this embodiment, a barrier layer is deposited within the conductor structure, and a first sub-conductive layer is deposited within the barrier layer. Then, the barrier layer and the first sub-conductive layer are etched downwards using a predetermined etching method, while retaining a portion of the barrier layer and the first sub-conductive layer at the bottom of the first region, thereby forming a gate structure containing the barrier layer and the first sub-conductive layer. That is, a gate structure containing the barrier layer and the first sub-conductive layer is formed at the bottom of the conductor trench.

[0130] For example, see Figure 9 As shown, this is the seventh schematic diagram of a semiconductor memory device in an embodiment of this application. First, a barrier layer is deposited within the conductive wire structure, and then a first sub-conductive layer is deposited within the barrier layer. The barrier layer and the first sub-conductive layer are then etched back to form a structure as shown. Figure 9 The gate structure has a barrier layer 22 on a portion of the sidewall at the bottom of the first region 20, and a first sub-conductive layer 23 is disposed within the barrier layer 22, with the barrier layer 22 completely surrounding the first sub-conductive layer 23, thereby forming a gate structure 21. That is, the gate structure 21 includes the barrier layer 22 and the first sub-conductive layer 23.

[0131] The barrier layer comprises a metal nitride, such as titanium nitride or tantalum nitride, with titanium nitride being widely used as the barrier layer for tungsten embolization. The thickness of the barrier layer is 3 nm to 5 nm.

[0132] It should be noted that when depositing to form a barrier layer, chemical vapor deposition (CVD) or physical vapor deposition (PVD) can be used. A preferred embodiment in this application is to use PVD deposition to form the barrier layer because the titanium nitride film formed by PVD deposition has a higher quality.

[0133] The titanium nitride can be deposited by using inorganic chemical reagents such as TiCl4 and NH3 at a temperature of 400-700 DEG C: 6TiCl4+8NH3→6TiN+24HCl+N2. The higher the deposition temperature, the higher the quality of the TiN film, and the lower the chlorine concentration in the film, thereby reducing the corrosion effect of chlorine.

[0134] The material of the first sub-conductive layer includes but is not limited to metal or metal alloy, for example, tungsten, aluminum, copper and alloys thereof, and the present application is not limited thereto.

[0135] The first direction is a vertical direction.

[0136] In the present application, the first area of the wire structure further includes an insulating side wall and a second sub-conductive layer. The steps of forming the insulating side wall and the second sub-conductive layer in the present application are described in detail below, which specifically include:

[0137] S1: After forming the gate structure, deposit an insulating material.

[0138] In the present application, after forming the gate structure, the insulating material is deposited in the wire structure by a preset deposition method.

[0139] S2: Etch back the insulating material to fill the trench above the gate structure.

[0140] In the present application, the insulating material is etched back to fill the trench above the gate structure.

[0141] It should be noted that the insulating material can completely fill the trench above the gate structure, or partially fill the trench above the gate structure, and the present application is not limited thereto.

[0142] S3: Form a plurality of second mask structures above the insulating material along the first direction, the second mask structure having a second width, and the second width being smaller than the first width.

[0143] In the present application, a plurality of second mask structures are formed above the insulating material along the first direction.

[0144] The second mask structure is used to form an insulating side wall, and the width of the second mask structure is a second width, which is smaller than the first width, so that the width of the formed insulating side wall is greater than the width of the barrier layer.

[0145] S4: Etch the insulating material according to the second mask structure to form an insulating side wall above the barrier layer in the first area.

[0146] In this embodiment of the application, according to the second mask structure, the insulating material is etched along the first direction to form an insulating sidewall located above the bottom barrier layer of the first region, so that the insulating material wraps around the surface of the portion of the sidewall above the bottom barrier layer of the first region of the wire structure.

[0147] The insulating sidewall can be made of silicon nitride, for example. The thickness of the insulating sidewall is greater than the thickness of the barrier layer. The thickness of the insulating sidewall is 5 nm to 10 nm. When depositing to form an insulating material, CVD or PVD deposition can be used. This application does not limit this.

[0148] S3: Fill the insulating sidewall with a second sub-conductive layer.

[0149] The second sub-conductive layer is disposed within the insulating sidewall, and the insulating sidewall surrounds the second sub-conductive layer.

[0150] In this embodiment, after an insulating sidewall is deposited and formed on the sidewall of the first region of the conductor structure, the insulating sidewall and the first region of the conductor structure constitute a hollow structure. Then, a second sub-conductive layer is filled into the formed hollow structure so that the second sub-conductive layer completely fills the first region of the conductor structure. See reference. Figure 10 The diagram shown is an eighth schematic of a semiconductor memory device according to an embodiment of this application. An insulating sidewall 24 is deposited and formed in the first region 20. A second sub-conductive layer 25 is filled in the insulating sidewall 24 and the first region 20. At this time, the second sub-conductive layer 25 is disposed in the insulating sidewall 24, and the insulating sidewall 24 surrounds the second sub-conductive layer 25. It should be noted that, in a preferred embodiment of this application, when the second sub-conductive layer 25 is filled inside the insulating sidewall 24, the second sub-conductive layer 25 completely fills the first region 20. That is, during filling, the second sub-conductive layer 25 is flush with the opening edge of the first region 20.

[0151] The material of the second sub-conductive layer includes, but is not limited to, metals or metal alloys, such as tungsten, aluminum, copper and their alloys, etc., but the embodiments of the application do not impose any restrictions on this.

[0152] It should be noted that the etching gases for silicon, silicon oxide, and silicon nitride in this embodiment can be SF6 / CF4 / Cl2 / CHF3 / O2 / Ar or a mixed gas to achieve a certain selectivity ratio; the insulating sidewall material is silicon nitride, and the silicon nitride sidewall deposition method can be ALD deposition, and the ALD reaction gas can be NH3 or a N2 / H2 mixed reaction gas; the barrier layer material is titanium nitride; the capping layer material is silicon nitride, and silicon nitride can be deposited using LPCVD or the reaction gas can be SiH4 or SiH2Cl2; the isolation layer material is silicon oxide, and silicon oxide deposition can be ALD, and the reaction gas can be LTO520 / O2 or N zero / O2.

[0153] The material of the barrier layer is titanium nitride, and can also be titanium, tantalum, tantalum nitride, tungsten nitride, or a combination thereof, but is not limited thereto. The material of the first sub-conductive layer, the material of the second sub-conductive layer, and the material of the third sub-conductive layer are the same. The materials of the first sub-conductive layer, the second sub-conductive layer, and the third sub-conductive layer can be aluminum, copper, gold, a work function metal, or a low-resistance metal, but are not limited thereto.

[0154] In addition, it should be noted that the first region depth is 1 / 2-3 / 4 of the second region depth, the height of the gate structure is 1 / 4 of the first region depth, and the height of the insulating sidewall and the second sub-conductive layer is 1 / 4 of the first region depth, but is not limited thereto.

[0155] Further, in the embodiments of the present application, when the wire structure is formed in the plurality of wire grooves, the method further includes:

[0156] A fourth sub-conductive layer is deposited on the insulating sidewall and the second sub-conductive layer, and the fourth sub-conductive layer fills the wire groove.

[0157] In the embodiments of the present application, the fourth sub-conductive layer is deposited above the insulating sidewall and above the second sub-conductive layer, that is, the wire groove is filled by the fourth sub-conductive layer, so that the third sub-conductive layer and the second sub-conductive layer are connected to each other. For example, referring to Figure 11 Fig. 9 is a ninth schematic view of a semiconductor storage device according to an embodiment of the present application, in which the third sub-conductive layer 26 is filled, so that the third sub-conductive layer 26 completely fills the wire groove 15.

[0158] Further, in the embodiments of the present application, in order to reduce the interference between the word lines, after the exposed sub-conductive layer is obtained, the fourth sub-conductive layer is etched, so that the width of the fourth sub-conductive layer is reduced, the underlying insulating sidewall and the second sub-conductive layer are exposed, and the second sub-conductive layer and the fourth sub-conductive layer are connected in series, thereby obtaining the third sub-conductive layer, and specifically includes:

[0159] S1: A plurality of third mask structures along the first direction are formed above the fourth sub-conductive layer, and the width of the third mask structure is less than the second width.

[0160] In the embodiments of the present application, a plurality of third mask structures along the first direction are formed above the fourth sub-conductive layer along the first direction, and the plurality of third mask structures are used to form the third sub-conductive layer.

[0161] For example, referring to Figure 12As shown, this is the tenth schematic diagram of a semiconductor memory device in this application embodiment. After the fourth sub-conductive layer 26 completely fills the wire trench, the active region structure 11 and the shallow trench isolation 12 are etched downward along the first direction 90, that is, the dielectric layer within the active region structure 11 is etched. When the upper surfaces of the active region structure 11 and the shallow trench isolation 12 are flush with the upper surface of the fourth sub-conductive layer 26, the following is obtained: Figure 12 The semiconductor memory device, and a plurality of third mask structures (not shown in the figure) formed above the fourth sub-conductive layer 26.

[0162] The width of the third mask structure is smaller than that of the second mask structure.

[0163] S2: The fourth sub-conductive layer is etched according to the third mask structure to form the third sub-conductive layer, wherein the width of the third sub-conductive layer is less than or equal to the width of the third mask structure.

[0164] In this embodiment, the fourth sub-conductive layer is etched according to the third mask structure to form the third sub-conductive layer.

[0165] For example, see Figure 13 The diagram shown is an eleventh structural schematic of a semiconductor memory device in an embodiment of this application. The fourth sub-conductive layer is etched according to the third mask structure (not shown in the diagram) to reduce its width, thereby forming the third sub-conductive layer 27. This etching of the fourth sub-conductive layer to reduce its width and form the third sub-conductive layer reduces interference between word lines.

[0166] The following is a schematic description of a top view of a semiconductor memory device in an embodiment of this application. (See attached image.) Figure 14 The image shown is a top view of a semiconductor memory device according to an embodiment of this application, including an active region structure 11, an insulating sidewall 24, a second sub-conductive layer 25, and a third sub-conductive layer 27, wherein the second sub-conductive layer 25 and the third sub-conductive layer 27 are connected.

[0167] along Figure 16 The AA' direction is used to obtain the cross-section in the AA' direction. The AA' cross-section of the semiconductor memory device in the embodiments of this application is illustrated below. See reference. Figure 15 As shown, this is a schematic cross-sectional view of AA' in an embodiment of this application. A shallow trench isolation 12 is defined on the substrate 10. The first region includes a gate structure 21, an insulating sidewall 24, and a second sub-conductive layer 25. The gate structure 21 includes a barrier layer 22 and a first sub-conductive layer 23. A third sub-conductive layer 27 is provided on the insulating sidewall 24 and the second sub-conductive layer 25.

[0168] along Figure 16In the direction of BB' in the figure, a cross section in the direction of BB' is obtained, and the following will be a schematic description of the cross section of the semiconductor storage device in the embodiment of the present application, with reference to Figure 16 As shown in the figure, it is a schematic diagram of the cross section of BB' in the embodiment of the present application, and the first area of the wire structure is composed of the gate structure 21, the insulating side wall 24 and the second sub-conductive layer 25, the gate structure 21 is composed of the barrier layer 22 and the first sub-conductive layer 23, and the third sub-conductive layer 27 is arranged on the insulating side wall 24 and the second sub-conductive layer 25.

[0169] Further, after the third sub-conductive layer is formed, a covering layer is deposited on the active region structure, the shallow trench isolation and the third sub-conductive layer. That is, the active region structure, the shallow trench isolation and the third sub-conductive layer are completely covered. For example, as shown in the figure, the active region structure 11, the shallow trench isolation 12 and the third sub-conductive layer 27 are completely covered by the covering layer. Figure 1

[0170] In the embodiment of the present application, a substrate is provided; an active region structure and a shallow trench isolation are formed on the substrate, and the shallow trench isolation surrounds a plurality of active region structures; a first etching is performed on the active region structure and the shallow trench isolation to form a plurality of wire grooves extending along a first direction in parallel to each other, and the etching rate of the active region structure is greater than the etching rate of the shallow trench isolation in the first etching; a conductive material is filled into the plurality of wire grooves to form a wire structure, and the wire structure includes a first area and a second area, the first area is located above the active region structure, and the second area is located above the shallow trench isolation; and the depth of the first area is greater than the depth of the second area. In this way, since the etching depth of the first area is greater than the etching depth of the second area, the first areas are not connected to each other through the shallow trench isolation, and thus when the problem of charge loss or electric leakage occurs, the data of one or more cells in the adjacent row can be prevented from being wrong, and the influence of the row hammer effect is weakened.

[0171] Obviously, those skilled in the art can make various modifications and variations to the present application without departing from the spirit and scope of the present application. Thus, if these modifications and variations of the present application fall within the scope of the claims of the present application and their equivalent technologies, the present application also intends to include these modifications and variations.​

Claims

1. A semiconductor memory device, characterized in that, include: Substrate; Multiple active region structures are defined on the substrate; Shallow trench isolation is disposed within the substrate, the shallow trench isolation surrounding the plurality of active region structures; Multiple conductive structures extend parallel to each other along a first direction. Each conductive structure includes a first region and a second region. The first region is located above the active region structure, and the second region is located above the shallow trench isolation. In a direction perpendicular to the substrate, the depth of the first region is greater than the depth of the second region. The first region of the wire structure further includes a gate structure located at the bottom of the first region of the wire structure. The gate structure includes a barrier layer and a first sub-conductive layer. The barrier layer is located on a portion of the sidewall and bottom surface at the bottom of the first region of the wire structure, and the first sub-conductive layer is disposed within the barrier layer. The first region of the conductor structure further includes an insulating sidewall and a second sub-conductive layer. The insulating sidewall is a portion of the sidewall above the barrier layer in the first region of the conductor structure. The second sub-conductive layer is disposed within the insulating sidewall and surrounds the second sub-conductive layer. The first region of the conductor structure further includes a third sub-conductive layer, which covers the insulating sidewall and the second sub-conductive layer and is connected to the second region of the conductor structure. Along the second direction, the width of the first sub-conductive layer is greater than the width of the second sub-conductive layer, and the width of the second sub-conductive layer is greater than the width of the third sub-conductive layer, wherein the second direction is parallel to the extension direction of the substrate and the active region structure.

2. The semiconductor memory device as claimed in claim 1, characterized in that, The semiconductor memory device further includes a cover layer that fills the interior of the second region and covers the third sub-conductive layer.

3. The semiconductor memory device as claimed in claim 1, characterized in that, The depth of the first zone is 1 / 2 to 3 / 4 of the depth of the second zone.

4. The semiconductor memory device as claimed in claim 1, characterized in that, The barrier layer comprises a metal nitride.

5. The semiconductor memory device as claimed in claim 1, characterized in that, The first sub-conductive layer, the second sub-conductive layer, and the third sub-conductive layer are made of the same material.

6. The semiconductor memory device as claimed in claim 1, characterized in that, The thickness of the barrier layer is greater than the thickness of the insulating sidewall.

7. The semiconductor memory device as claimed in claim 1, characterized in that, An adhesion layer is provided on the third sub-conductive layer, and the adhesion layer includes titanium nitride.

8. A method for forming a semiconductor memory device as described in any one of claims 1-7, characterized in that, include: Provide a substrate; An active region structure and a shallow trench isolation are formed on the substrate, the shallow trench isolation surrounding the plurality of active region structures; The active region structure and the shallow trench isolation are etched for the first time to form a plurality of wire trenches that extend parallel to each other along a first direction. The etching rate of the active region structure in the first etching is greater than the etching rate of the shallow trench isolation. A conductor structure is formed in the plurality of conductor trenches. The conductor structure includes a first region and a second region. The first region is located above the active region structure, and the second region is located above the shallow trench isolation. The depth of the first region is greater than the depth of the second region.

9. The method for forming a semiconductor memory device as claimed in claim 8, characterized in that, Forming a conductor structure in the plurality of conductor trenches includes: A barrier layer is deposited on the sidewall of the conductor structure to form a barrier layer; A first sub-conductive layer is deposited within the barrier layer; The barrier layer and the first sub-conductive layer are etched back, leaving a portion of the barrier layer and the first sub-conductive layer at the bottom of the first region to form a gate structure. The barrier layer is located on a portion of the sidewall and bottom surface at the bottom of the first region of the wire structure, and the first sub-conductive layer is disposed within the barrier layer.

10. The method for forming a semiconductor memory device as claimed in claim 8, characterized in that, The first etching includes forming a plurality of first mask structures along a first direction above the active region structure and the shallow trench isolation, and etching the active region structure and the shallow trench isolation according to the first mask structures, wherein the width of the first mask structure is a first width.

11. The method for forming a semiconductor memory device as claimed in claim 10, characterized in that, Forming the conductor structure in the plurality of conductor trenches further includes: After the gate structure is formed, an insulating material is deposited; The insulating material is etched back to fill the trench above the gate structure; A plurality of second mask structures are formed above the insulating material along a first direction, wherein the width of the second mask structure is a second width, and the second width is smaller than the first width; The insulating material is etched according to the second mask structure to form an insulating sidewall located above the barrier layer in the first region; A second sub-conductive layer is filled within the insulating sidewall, wherein the second sub-conductive layer is disposed within the insulating sidewall.

12. The method for forming a semiconductor memory device as claimed in claim 11, characterized in that, Forming the conductor structure in the plurality of conductor trenches further includes: A fourth sub-conductive layer is deposited on the insulating sidewall and the second sub-conductive layer, the fourth sub-conductive layer filling the conductor trench.

13. The method for forming a semiconductor memory device as claimed in claim 12, characterized in that, Forming the conductor structure in the plurality of conductor trenches further includes: A plurality of third mask structures are formed above the fourth sub-conductive layer along a first direction, wherein the width of the third mask structure is smaller than the second width; The fourth sub-conductive layer is etched according to the third mask structure to form the third sub-conductive layer, wherein the width of the third sub-conductive layer is less than or equal to the width of the third mask structure.

14. The method for forming a semiconductor memory device as claimed in claim 13, characterized in that, Also includes: After forming the conductor structure in the plurality of conductor trenches, a capping layer is deposited on the active region structure, the shallow trench isolation, and the third sub-conductive layer.

15. The method for forming a semiconductor memory device as claimed in claim 8, characterized in that, The depth of the first zone is 1 / 2 to 3 / 4 of the depth of the second zone.

16. The method for forming a semiconductor memory device as claimed in claim 9, characterized in that, The barrier layer comprises a metal nitride.

17. The method for forming a semiconductor memory device as claimed in claim 13, characterized in that, The first sub-conductive layer, the second sub-conductive layer, and the third sub-conductive layer are made of the same material.

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