Semiconductor structure and method of manufacturing the same
By dividing the embedded word lines of DRAM into two parts and using an isolation layer and a low dielectric constant layer to separate adjacent memory cells, the problem of row hammer effect is solved, and the stability and reliability of the memory are improved.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- CHANGXIN MEMORY TECH INC
- Filing Date
- 2022-01-06
- Publication Date
- 2026-06-05
Smart Images
Figure CN116456712B_ABST
Abstract
Description
Technical Field
[0001] This application belongs to the field of semiconductor technology, specifically relating to a semiconductor structure and its fabrication method. Background Technology
[0002] DRAM (Dynamic Random Access Memory) is a common type of system memory. Each memory cell includes a transistor and a corresponding capacitor, with the amount of charge stored in the capacitor representing 0 and 1. To prevent data errors caused by leakage, the capacitor needs to be refreshed periodically. To improve the integration density of DRAM and speed up the operation of each memory cell, as well as to meet the strong demand for DRAM from markets such as PCs, smartphones, and tablets, buried word line DRAM (BNN) structures have been developed in recent years to meet these needs.
[0003] In related technologies, when a row in a memory matrix is activated and repeatedly refreshed, it can generate noise or interference to neighboring rows, causing errors in the data of one or more cells in the neighboring rows. This phenomenon is known as the Row Hammer Effect. Summary of the Invention
[0004] The purpose of this application is to provide a semiconductor structure and its fabrication method to solve the hammering effect in semiconductor devices.
[0005] According to a first aspect of the embodiments of this application, a method for fabricating a semiconductor structure is provided, the method comprising:
[0006] Provide substrate;
[0007] A first word line structure in a first direction is formed in the substrate;
[0008] The substrate is etched downwards to form a columnar active region, the depth of which is greater than the depth of the first word line structure.
[0009] An isolation layer is filled between the columnar active regions;
[0010] Etch the first character line structure and isolation layer to form a first character line groove in a first direction, the first character line groove penetrating the columnar active area;
[0011] A low dielectric constant layer, a first conductive layer, and an insulating layer are formed in the first word line trench, and the first conductive layer is electrically connected to the first word line structure.
[0012] In some optional embodiments of this application, a first word line structure in a first direction is formed on the substrate, including:
[0013] The substrate is etched to form a second word line trench in a first direction;
[0014] The first character line structure is formed within the groove of the second character line.
[0015] In some alternative embodiments of this application, etching the substrate to form a second word line trench in a first direction includes:
[0016] A first word line mask is deposited on a substrate, and the trenches exposed by the first word line mask extend in a first direction;
[0017] Using the first word line mask as a mask, the substrate is etched to form a second word line trench in the first direction.
[0018] In some optional embodiments of this application, before forming the first word line structure within the second word line trench, the method for fabricating the semiconductor structure further includes:
[0019] A gate oxide layer is deposited in the second word line trench, and the gate oxide layer covers the second word line trench;
[0020] A barrier layer is deposited on the gate oxide layer.
[0021] In some optional embodiments of this application, forming a first character line structure within the second character line groove includes:
[0022] A first word line metal layer is deposited within the second word line trench; the first word line metal layer fills the second word line trench and covers the upper surface of the substrate;
[0023] The first word line metal layer is planarized so that the upper surface of the first word line metal layer is flush with the upper surface of the substrate, forming the first word line structure.
[0024] In some optional embodiments of this application, the first word line structure is etched downwards to the substrate to form a columnar active region, including:
[0025] Deposit a linear mask on the first character line structure;
[0026] Partial etching of the linear mask to form an island-shaped mask;
[0027] The substrate is etched using an island-shaped mask to form a columnar active region.
[0028] In some alternative embodiments of this application, an isolation layer is filled around the columnar active region, including:
[0029] An isolation material is filled around the columnar active region, and the isolation material covers the upper surface of the island mask;
[0030] The isolation material is planarized to form an isolation layer, the upper surface of which is flush with the upper surface of the columnar active region.
[0031] In some optional embodiments of this application, etching the first word line structure and the isolation layer along the second direction to form a first word line trench in the first direction includes:
[0032] A second character line mask is formed on the surface of the first character line structure and the isolation layer, and the trenches exposed by the second character line mask extend in the first direction;
[0033] The first word line structure and isolation layer are etched using the second word line mask as a mask to form the first word line trench that passes through multiple columnar active areas and isolation layers.
[0034] In some optional embodiments of this application, after etching the first word line structure and the isolation layer along the second direction to form the first word line trench, the method for fabricating the semiconductor structure further includes:
[0035] Remove the second word line mask and part of the isolation layer so that the upper surface of the isolation layer is flush with the upper surface of the columnar active area.
[0036] In some optional embodiments of this application, depositing a first conductive layer and an insulating layer in the first word line trench includes:
[0037] A first word line conductive layer is deposited in the first word line trench, and the upper surface of the first word line conductive layer is lower than the upper surface of the columnar active region;
[0038] An insulating layer is deposited on the first word line conductive layer, with the upper surface of the insulating layer flush with the upper surface of the columnar active region.
[0039] In some alternative embodiments of this application, the low dielectric constant layer includes an air gap, and a low dielectric constant layer, a first conductive layer, and an insulating layer are formed in the first word trench, including:
[0040] A sacrificial layer is deposited on the inner wall of the first character line groove;
[0041] A first conductive layer is deposited within the first character line trench;
[0042] Remove the sacrificial layer to create an air gap;
[0043] An insulating layer is deposited above the first conductive layer to seal the air gap.
[0044] According to a second aspect of the embodiments of this application, a semiconductor structure is provided, the semiconductor structure including:
[0045] Substrate, including columnar active regions;
[0046] The first character line structure is formed in the columnar active region, and the depth of the columnar active region is greater than the depth of the first character line structure. The upper surface of the first character line structure is lower than the upper surface of the columnar active region.
[0047] An isolation layer fills the spaces between columnar active regions;
[0048] A first conductive layer is located above the first word line structure and extends along a first direction through the columnar active region and the isolation layer. The first conductive layer is electrically connected to the first word line structure.
[0049] A low dielectric constant layer is formed on the sidewall of the first conductive layer;
[0050] An insulating layer is deposited on the surface of the first conductive layer.
[0051] In some alternative embodiments of this application, the low dielectric constant layer includes an air gap.
[0052] In some alternative embodiments of this application, the depth of the columnar active region is greater than the depth of the first word line structure.
[0053] In some alternative embodiments of this application, the top surface of the low dielectric constant layer is flush with or higher than the upper surface of the first conductive layer.
[0054] In some optional embodiments of this application, the first conductive layer includes a plurality of spaced-apart first conductive structures, the width of the first word line structure in the second direction is less than or equal to the width of the first conductive structure in the second direction, and the second direction is perpendicular to the first direction.
[0055] In some alternative embodiments of this application, the top surface of the first character line structure is higher than the bottom surface of the first groove.
[0056] According to a third aspect of the embodiments of this application, a memory is provided, which may include a semiconductor structure as described in any of the second aspects of the embodiments.
[0057] The above-mentioned technical solution of this application has the following beneficial technical effects:
[0058] The method of this application divides the embedded word line into two parts. The first word line structure exists only in the columnar source region, and there is no first word line structure in the isolation layer between the columnar source regions. The word line conductive layers of different active regions are connected by the first conductive layer. Such a structure separates adjacent memory cells by the filled isolation layer and the low dielectric constant layer, making it difficult for electrons to migrate from one memory cell to an adjacent memory cell, thereby reducing the row hammering effect caused by electron migration. Attached Figure Description
[0059] Figure 1This is a flowchart of a method for fabricating a semiconductor structure in an exemplary embodiment of this application;
[0060] Figure 2 This is a schematic diagram of the structure forming the second character line groove in an exemplary embodiment of this application;
[0061] Figure 3 This is a schematic diagram of the structure forming the first word line structure in an exemplary embodiment of this application;
[0062] Figure 4 This is a schematic diagram of the structure forming a linear mask in an exemplary embodiment of this application;
[0063] Figure 5 This is a schematic diagram of the structure forming the columnar character line structure in an exemplary embodiment of this application;
[0064] Figure 6 This is a schematic diagram of the structure forming the columnar active region in an exemplary embodiment of this application;
[0065] Figure 7 This is a schematic diagram of the structure of the filling isolation layer in an exemplary embodiment of this application;
[0066] Figure 8 This is a schematic diagram of the structure forming the second word line mask in an exemplary embodiment of this application;
[0067] Figure 9 This is a schematic diagram of the structure forming the first character line groove in an exemplary embodiment of this application;
[0068] Figure 10 This is a schematic diagram of a semiconductor structure in an exemplary embodiment of this application;
[0069] Figure 11 This is a cross-sectional view of a semiconductor structure in an exemplary embodiment of this application. Detailed Implementation
[0070] To make the objectives, technical solutions, and advantages of this application clearer, the application will be further described in detail below with reference to specific embodiments and accompanying drawings. It should be understood that these descriptions are merely exemplary and not intended to limit the scope of this application. Furthermore, descriptions of well-known structures and technologies are omitted in the following description to avoid unnecessarily obscuring the concepts of this application.
[0071] The accompanying drawings illustrate layer structure diagrams according to embodiments of this application. These drawings are not to scale, and some details have been enlarged for clarity, and some details may have been omitted. The shapes of the various regions and layers shown in the drawings, as well as their relative sizes and positional relationships, are merely exemplary and may deviate from reality due to manufacturing tolerances or technical limitations. Furthermore, those skilled in the art can design regions / layers with different shapes, sizes, and relative positions as needed.
[0072] Obviously, the described embodiments are only a part of the embodiments of this application, not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without inventive effort are within the scope of protection of this application.
[0073] In the description of this application, it should be noted that the terms "first", "second", and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.
[0074] Furthermore, the technical features involved in the different embodiments of this application described below can be combined with each other as long as they do not conflict with each other.
[0075] The method for preparing the semiconductor structure provided in this application will be described in detail below with reference to the accompanying drawings, through specific embodiments and application scenarios.
[0076] like Figure 1 As shown, in a first aspect of this application, a method for fabricating a semiconductor structure is provided, the method including:
[0077] S110: Provides substrate 1101;
[0078] S120: A first word line structure 1102 in a first direction is formed in the substrate 1101;
[0079] S130: Etch the substrate 1101 downward to form a columnar active region 1103, the depth of which is greater than the depth of the first word line structure 1102.
[0080] S140: Fill the space between the columnar active regions 1103 with an isolation layer 1109;
[0081] S150: Etch the first word line structure 1102 and the isolation layer 1109 to form a first word line groove 1111 in the first direction. The first word line groove 1111 penetrates the columnar active region.
[0082] S160: A low dielectric constant layer, a first conductive layer 1104 and an insulating layer 1105 are formed in the first word line trench 1111, and the first conductive layer 1104 is electrically connected to the first word line structure 1102.
[0083] The above embodiment method forms a columnar active region 1103 by etching down to the substrate 1101, dividing the buried word line into two parts. The first word line structure 1102 exists only in the columnar source region 1103, and the first word line structure 1102 does not exist in the isolation layer 1109. The word line conductive layers of different active regions are connected by the first conductive layer 1104. This makes it difficult for electrons to migrate from one memory cell to an adjacent memory cell by the filled isolation layer 1109 and the low dielectric constant layer, thereby reducing the row hammering effect caused by electron migration.
[0084] To illustrate this more clearly, the following describes each of the above steps:
[0085] The first step is S110: providing a substrate.
[0086] In one embodiment, the substrate material includes, but is not limited to, silicon crystal or germanium crystal, silicon on insulator (SOI) structure or epitaxial layer structure on silicon, compound semiconductor (e.g., silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, or indium dysprosium), alloy semiconductor (e.g., SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, GaInAsP, or combinations thereof).
[0087] The next step is step S120: forming a first word line structure in a first direction in the substrate 1101.
[0088] like Figure 2-3As shown, in one embodiment, the formation process of the first word line structure may include: etching the substrate 1101 to form a second word line trench (not shown) in a first direction; and forming a first word line structure 1102 within the second word line trench. The etching of the substrate to form the second word line trench in the first direction may include: depositing a first word line mask on the substrate, the trench exposed by the first word line mask extending in the first direction; and etching the substrate using the first word line mask as a mask to form the second word line trench in the first direction. The first word line mask may be a photoresist layer. After forming the photoresist layer on the substrate 1101, the photoresist layer is exposed to obtain a photoresist pattern. Openings 1106 are formed between the photoresist patterns, exposing the substrate 1101. The substrate is etched using the photoresist pattern as a mask to form the second word line trench in the first direction. Then, a SiO2 layer is deposited in the second word line trench as a gate oxide layer, followed by the deposition of TiN as a metal barrier layer, and then W is deposited as the first word line metal layer. Finally, the surface is planarized to obtain the first word line structure 1102.
[0089] The next step is step S130: etching the substrate downwards to form a columnar active region, the depth of which is greater than the depth of the first word line structure.
[0090] In one embodiment, the process of forming the columnar active region may include: depositing linear SiN material as a mask 1107 on the first word line structure, such as... Figure 4 As shown, a linear mask is partially etched to form an island mask 1108, wherein the partially etched linear mask can cut the linear SiN material through a mask containing an array of holes. Next, the first word line structure 1102 is etched using the island mask 1108 as a mask to form a columnar word line structure as shown. Figure 5 As shown, the substrate is then etched to form columnar active regions 1103, as follows. Figure 6 As shown.
[0091] The next step is step S140: filling the space between the columnar active regions 1103 with an isolation layer 1109.
[0092] In one embodiment, there are multiple columnar active regions 1103, and filling an isolation layer 1109 around the columnar active regions 1103 may include: filling an isolation material between the multiple columnar active regions 1103, the isolation material covering the upper surface of the island mask; planarizing the isolation material to form the isolation layer 1109, the upper surface of the isolation layer 1109 being flush with the upper surface of the columnar active regions 1103, such as... Figure 7 As shown. The insulating material can be SiO2. Planarization can be achieved using CMP polishing technology to improve the precision and performance of the finished product.
[0093] The next step is step S150: etching the first word line structure 1102 and the isolation layer 1109 to form a first word line groove 1111 in the first direction, the first word line groove 1111 penetrating the columnar active area.
[0094] In one embodiment, forming the first word line trench may include: forming a second word line mask 1110 on the surface of the first word line structure and the isolation layer, such as... Figure 8 As shown, the trench extension direction exposed by the second word line mask 1110 is the first direction; the first word line structure 1102 and the isolation layer 1109 are etched using the second word line mask 1110 as a mask to form the first word line trench 1111 in the isolation layer. The first word line trench 1111 may include the second word line mask formed on the surface of the first word line structure and the isolation layer, and the trench extension direction exposed by the second word line mask is the first direction; the first word line structure and the isolation layer are etched using the second word line mask as a mask to form the first word line trench 1111 in the isolation layer, and the first word line trench 1111 penetrates the columnar active region, such as... Figure 9 As shown, the etching depth can be 1 / 3 to 2 / 3 of the word line depth, specifically 1 / 2 of the word line depth.
[0095] Finally, in step S160: a low dielectric constant layer, a first conductive layer 1104 and an insulating layer 1105 are formed in the first word line trench 1111, and the first conductive layer 1104 is electrically connected to the first word line structure 1102.
[0096] In one embodiment, a low dielectric constant layer can be deposited in the first word line trench 1111. The material of the low dielectric constant layer can be SiCOH, with a thickness of 3 to 8 nm and a dielectric constant of 2.8 or less. This makes it less likely to cause parasitic capacitance between the first conductive layers 1104, and the hardness is 0.2 to 2 GPa, which can provide good insulation and protection against breakdown.
[0097] In one embodiment, the low dielectric constant layer includes an air gap. Forming the low dielectric constant layer, the first conductive layer, and the insulating layer in the first word line trench includes: depositing a sacrificial layer (not shown) in the first word line trench 1111; depositing a first conductive layer 1104 in the first word line trench 1111; removing the sacrificial layer to form an air gap; and depositing an insulating layer 1105 over the first conductive layer 1104, the insulating layer sealing the air gap.
[0098] In one embodiment, the sacrificial layer material can be hydrocarbons, silicon oxide, BACL, etc. The top and bottom sacrificial layers are removed using an ashing process, wet etching process, or dry etching process to form air gaps. Alternatively, plasma etching can be used to remove the top and bottom sacrificial layers and form air gaps. For example, using etching gases such as O2 and H2 combined with plasma bombardment, the O2 and H2 are converted into water vapor. Combined with plasma sputtering, the sacrificial layer is gradually washed away from top to bottom. Simultaneously, O2 and H2 cause the first conductive layer 1104 to continuously undergo redox reactions, protecting the first conductive layer 1104 from plasma bombardment and sputtering. This creates air gaps on both sides of the first conductive layer 1104. An insulating layer is then deposited to obtain a semiconductor structure with air gaps. The air gaps can reduce the parasitic capacitance between the first conductive layers 1104.
[0099] In one embodiment, forming a first word line structure 1102 in a first direction in a substrate 1101 may include:
[0100] The substrate 1101 is etched to form a second word line trench in a first direction;
[0101] The first character line structure 1102 is formed within the groove of the second character line.
[0102] In one embodiment, etching the substrate to form a second word line trench in a first direction may include:
[0103] A first word line mask is deposited on a substrate, and the trenches exposed by the first word line mask extend in a first direction;
[0104] Using the first word line mask as a mask, the substrate is etched to form a second word line trench in the first direction.
[0105] In one embodiment, before forming the first word line structure 1102 within the second word line trench, the method for fabricating the semiconductor structure may further include:
[0106] A gate oxide layer is deposited in the second word line trench, and the gate oxide layer covers the second word line trench;
[0107] A barrier layer is deposited on the gate oxide layer, the barrier layer covering the bottom surface and sidewalls of the gate oxide layer.
[0108] In one embodiment, forming a first character line structure 1102 within the second character line groove may include:
[0109] A first word line metal layer is deposited within the second word line trench; the first word line metal layer fills the second word line trench and covers the upper surface of the substrate;
[0110] The first word line metal layer is planarized so that the upper surface of the first word line metal layer is flush with the upper surface of the substrate, forming the first word line structure.
[0111] In one embodiment, etching the substrate 1101 downwards to form a columnar active region 1103 may include:
[0112] A linear mask 1107 is deposited on the first character line structure 1102;
[0113] Partial etching of the linear mask 1107 to form an island mask 1108;
[0114] The substrate 1101 is etched using an island-shaped mask 1108 to form a columnar active region 1103.
[0115] In one embodiment, filling the spacer layer 1109 between the columnar active regions 1103 may include:
[0116] An isolation material is filled between the columnar active regions 1103, and the isolation material covers the upper surface of the island mask;
[0117] The isolation material is planarized to form an isolation layer 1109, the upper surface of which is flush with the upper surface of the columnar active region 1103. The planarization operation specifically employs CMP (Chemical Mechanical Polishing) to planarize the surface.
[0118] In one embodiment, etching the first word line structure 1102 and the isolation layer 1109 to form a first word line trench 1111 in a first direction may include:
[0119] A second character line mask is formed on the surface of the first character line structure 1102 and the isolation layer 1109, and the trenches exposed by the second character line mask extend in the first direction;
[0120] The first word line structure 1102 and the isolation layer 1109 are etched using the second word line mask as a mask to form the first word line trench 1111 that passes through multiple columnar active areas and the isolation layer.
[0121] In one embodiment, after etching the first word line structure and the isolation layer to form the first word line trench 1111, the method for fabricating the semiconductor structure may further include:
[0122] Remove the second word line mask and part of the isolation layer 1109 so that the upper surface of the isolation layer 1109 is flush with the upper surface of the columnar active region 1103.
[0123] In one embodiment, depositing a first conductive layer 1104 and an insulating layer 1105 in the first word line trench 1111 may include:
[0124] A first conductive layer 1104 is deposited in the first word line trench 1111, and the upper surface of the first conductive layer 1104 is lower than the upper surface of the columnar active region 1103.
[0125] An insulating layer 1105 is deposited on the first conductive layer 1104, and the upper surface of the insulating layer 1105 is flush with the upper surface of the columnar active region 1103.
[0126] Then, a first conductive layer 1104 is deposited to connect the first word line metal layer in the first word line structure, and then an insulating layer 1105 is deposited on top, such as... Figure 10 As shown, the materials for the first conductive layer and the first word line metal layer can both be tungsten metal, and the material for the insulating layer can be SiN. In one embodiment, the material for the first word line metal layer can be polysilicon (dual gate poly), which avoids interference through the word line and reduces GIDL (gate-induce drain leakage).
[0127] It should be noted that in the embodiments of this application, the etching gas can be SF6 / CF4 / Cl2 / CHF3 / O2 / Ar or a mixture of gases to achieve a certain selectivity.
[0128] Silicon nitride (SiN) sidewall deposition can be performed using ALD (atomic layer deposition) technology, and the ALD reaction gas can be NH3 or a N2 / H2 mixed reaction gas.
[0129] The silicon nitride (SiN) capping layer can be applied using LPCVD, and the reaction gas can be SiH4 or SiH2Cl2; LPCVD stands for Low Pressure Chemical Vapor Deposition High Temperature Oxidation.
[0130] SiO2 deposition can be performed using ALD SiO2 deposition, and the reaction gases can be silane and O2.
[0131] like Figure 11 As shown, in a second aspect of the embodiments of this application, a semiconductor structure is provided, which may include:
[0132] Substrate 1101 includes columnar active region 1103;
[0133] The first character line structure 1102 is formed in the columnar active region 1103, and the depth of the columnar active region is greater than the depth of the first character line structure 1102. The upper surface of the first character line structure 1102 is lower than the upper surface of the columnar active region 1103, and AA` is the first direction.
[0134] Isolation layer 1109 fills the spaces between columnar active regions;
[0135] The first conductive layer 1104 is located above the first word line structure and extends along the first direction through the columnar active region and the isolation layer. The first conductive layer is electrically connected to the first word line structure 1102, and BB' is the second direction.
[0136] An insulating layer 1105 is deposited on the surface of the first conductive layer 1104.
[0137] In this embodiment, the embedded word line of the semiconductor structure is divided into two parts. The first word line structure exists only in the columnar active region 1103, and there is no first word line structure in the isolation layer 1109 between the columnar active regions 1103. The word line conductive layers of different active regions are connected by the first conductive layer 1104. This structure separates adjacent memory cells by the filled isolation layer 1109, making it difficult for electrons to migrate from one memory cell to an adjacent memory cell, thereby reducing the row hammering effect caused by electron migration.
[0138] The substrate materials in this embodiment include, but are not limited to, silicon crystals or germanium crystals, silicon-on-insulator (SOI) structures or epitaxial layer structures on silicon, compound semiconductors (e.g., silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, or indium dysprosium), and alloy semiconductors (e.g., SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, GaInAsP, or combinations thereof). The isolation layer can be made of SiO2, the first conductive layer can be made of tungsten (W), and the insulating layer can be made of SiN.
[0139] In one embodiment, a dielectric layer is further formed between the insulating layer 1109 and the first conductive layer 1104. The dielectric layer can be made of SiCOH material, with a thickness of 3-8 nm, a dielectric constant of 2.8 or less, which is not prone to causing parasitic capacitance, and a hardness of 0.2-2 GPa, which can provide good insulation and protection against breakdown.
[0140] In one embodiment, the depth of the columnar active region 1103 may be greater than the depth of the first word line structure.
[0141] In one embodiment, there are multiple columnar active regions 1103, and the top surface of the first word line structure can be higher than the bottom surface of the first conductive layer 1104. In this way, the first conductive layer 1104 can connect the first word line structures of adjacent columnar source regions 1103.
[0142] In a third aspect of this application, a memory is provided, including the semiconductor structure described above. In this semiconductor structure, the first word line structure exists only in the columnar active region 1103, and the isolation layer 1109 does not contain the first word line structure; the first word line structures 1102 of different columnar active regions 1103 are connected by a first conductive layer 1104; this structure separates adjacent memory cells by the filled isolation layer 1109 and a low-dielectric-constant layer, making it difficult for electrons to migrate from one memory cell to a neighboring memory cell, thereby reducing the row hammering effect caused by electron migration.
[0143] The embodiments of this application have been described above with reference to the accompanying drawings. However, this application is not limited to the specific embodiments described above. The specific embodiments described above are merely illustrative and not restrictive. Those skilled in the art can make many other forms under the guidance of this application without departing from the spirit and scope of the claims, and all of these forms are within the protection scope of this application.
Claims
1. A method for fabricating a semiconductor structure, characterized in that, include: Provide substrate; A first word line structure in a first direction is formed in the substrate; The substrate is etched downwards to form a columnar active region, the depth of which is greater than the depth of the first word line structure; An isolation layer is filled between the columnar active regions; The first word line structure and the isolation layer are etched to form a first word line groove in the first direction, and the first word line groove penetrates the columnar active region. A low dielectric constant layer, a first conductive layer, and an insulating layer are formed in the first word line trench, wherein the first conductive layer is electrically connected to the first word line structure.
2. The method for preparing a semiconductor structure according to claim 1, characterized in that, The formation of a first word line structure in a first direction on the substrate includes: The substrate is etched to form a second word line trench in a first direction; The first character line structure is formed within the second character line groove.
3. The method for preparing a semiconductor structure according to claim 2, characterized in that, The etching of the substrate to form a second word line trench in a first direction includes: A first word line mask is deposited on the substrate, wherein the trenches exposed by the first word line mask extend in the first direction; Using the first word line mask as a mask, the substrate is etched to form a second word line trench in a first direction.
4. The method for preparing a semiconductor structure according to claim 2, characterized in that, Before forming the first word line structure within the second word line trench, the method for fabricating the semiconductor structure further includes: A gate oxide layer is deposited in the second word line trench, the gate oxide layer covering the second word line trench; A barrier layer is deposited on the gate oxide layer.
5. The method for preparing a semiconductor structure according to claim 2, characterized in that, The process of forming the first character line structure within the second character line groove includes: A first word line metal layer is deposited within the second word line trench; the first word line metal layer fills the second word line trench and covers the upper surface of the substrate; The first word line metal layer is planarized so that the upper surface of the first word line metal layer is flush with the upper surface of the substrate, forming the first word line structure.
6. The method for preparing a semiconductor structure according to claim 1, characterized in that, The etching of the first word line structure downwards to the substrate to form a columnar active region includes: A linear mask is deposited on the first character line structure; The linear mask is partially etched to form an island-shaped mask; The substrate is etched using the island-shaped mask to form a columnar active region.
7. The method for preparing a semiconductor structure according to claim 6, characterized in that, The filling of an isolation layer around the columnar active region includes: An insulating material is filled around the columnar active region, and the insulating material covers the upper surface of the island-shaped mask; The isolation material is planarized to form an isolation layer, the upper surface of which is flush with the upper surface of the columnar active region.
8. The method for preparing a semiconductor structure according to claim 1, characterized in that, The etching of the first character line structure and the isolation layer to form the first character line trench in the first direction includes: A second character line mask is formed on the surface of the first character line structure and the isolation layer, and the trench exposed by the second character line mask extends in the first direction; The first word line structure and the isolation layer are etched using the second word line mask as a mask to form a first word line trench that passes through multiple columnar active areas and the isolation layer.
9. The method for preparing a semiconductor structure according to claim 8, characterized in that, After etching the first word line structure and the isolation layer to form the first word line trench in the first direction, the method for fabricating the semiconductor structure further includes: Remove the second word line mask and part of the isolation layer so that the upper surface of the isolation layer is flush with the upper surface of the columnar active region.
10. The method for preparing a semiconductor structure according to claim 1, characterized in that, The deposition of a first conductive layer and an insulating layer in the first word trench includes: A first word line conductive layer is deposited in the first word line trench, and the upper surface of the first word line conductive layer is lower than the upper surface of the columnar active region. An insulating layer is deposited on the first word line conductive layer, the upper surface of the insulating layer being flush with the upper surface of the columnar active region.
11. The method for preparing a semiconductor structure according to claim 1, characterized in that, The low dielectric constant layer includes an air gap, and the formation of the low dielectric constant layer, the first conductive layer, and the insulating layer in the first word trench includes: A sacrificial layer is deposited on the inner wall of the first character line groove; A first conductive layer is deposited within the first word line trench; Remove the sacrificial layer to create an air gap; An insulating layer is deposited over the first conductive layer, the insulating layer sealing the air gap.
12. A semiconductor structure, characterized in that, include: Substrate, including columnar active regions; The first character line structure is formed in the columnar active region, and the depth of the columnar active region is greater than the depth of the first character line structure, and the upper surface of the first character line structure is lower than the upper surface of the columnar active region. An isolation layer is formed between the columnar active regions; A first conductive layer is located above the first word line structure and extends along a first direction through the columnar active region and the isolation layer, and the first conductive layer is electrically connected to the first word line structure. A low dielectric constant layer is formed on the sidewall of the first conductive layer; An insulating layer is deposited on the surface of the first conductive layer.
13. The semiconductor structure according to claim 12, characterized in that, The low dielectric constant layer includes air gaps.
14. The semiconductor structure according to claim 12, characterized in that, The top surface of the low dielectric constant layer is flush with or higher than the upper surface of the first conductive layer.
15. The semiconductor structure according to claim 12, characterized in that, The first conductive layer includes a plurality of spaced-apart first conductive structures, the width of the first word line structure in the second direction is less than or equal to the width of the first conductive structure in the second direction, and the second direction is perpendicular to the first direction.
16. A memory, characterized in that, Includes the semiconductor structure as described in any one of claims 12-15.