Semiconductor Structure and Method for Fabricating the Same

Abstract

This application relates to the field of semiconductor technology and proposes a semiconductor structure and a manufacturing method thereof. The manufacturing method of the semiconductor structure includes: providing a substrate; forming a first insulating layer on the substrate; forming a first metal layer on the first insulating layer; forming a second insulating layer on the first insulating layer and embedding the first metal layer in the second insulating layer; preprocessing the upper surface of the second insulating layer to planarize the second insulating layer; forming a second metal layer on the upper surface of the planarized second insulating layer. Before forming the second metal layer, by preprocessing the upper surface of the second insulating layer, it is ensured that the upper surface of the second insulating layer has a high flatness, thereby ensuring that the bottom of the second metal layer formed on the upper surface of the second insulating layer tends to be horizontal, and thus improving the performance of the formed semiconductor structure.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and particularly to a semiconductor structure and a manufacturing method thereof. Background Art

[0002] In the related art, a common-mode inductor is realized by using dual RDL (Redistribution Layer) rewiring. Due to the structural limitations of the RDL coil, a bulge will appear in the dielectric layer on the top layer of the RDL coil, which affects the growth of the second RDL, and the formed second RDL is severely distorted. Summary of the Invention

[0003] This application provides a semiconductor structure and a manufacturing method thereof to improve the performance of the semiconductor structure.

[0004] According to the first aspect of this application, a manufacturing method of a semiconductor structure is provided, including:

[0005] Providing a substrate;

[0006] Forming a first insulating layer on the substrate;

[0007] Forming a first metal layer on the first insulating layer;

[0008] Forming a second insulating layer on the first insulating layer and embedding the first metal layer in the second insulating layer;

[0009] Preprocessing the upper surface of the second insulating layer to planarize the second insulating layer;

[0010] Forming a second metal layer on the upper surface of the planarized second insulating layer.

[0011] In an embodiment of this application, preprocessing the upper surface of the second insulating layer includes:

[0012] Removing a part of the second insulating layer and avoiding exposing the first metal layer.

[0013] In an embodiment of this application, before preprocessing the second insulating layer, the thickness of the second insulating layer above the first metal layer is h, and the thickness of the removed second insulating layer is not less than h / 3.

[0014] In an embodiment of this application, removing a part of the second insulating layer includes:

[0015] Forming a groove on the second insulating layer, and the groove is directly opposite to the first metal layer.

[0016] In an embodiment of this application, removing a part of the second insulating layer further includes:

[0017] Baking the second insulating layer with the formed groove to planarize the second insulating layer.

[0018] In one embodiment of the present application, the difference between the thickness of the second insulating layer before baking and the thickness of the second insulating layer after baking is greater than the depth of the groove.

[0019] In one embodiment of the present application, forming a groove in the second insulating layer includes:

[0020] Forming a mask plate above the second insulating layer, the mask plate is formed with a graphic area, and the graphic area is disposed opposite to the first metal layer;

[0021] After exposure and development processing, the second insulating layer in the exposed area is dissolved and peeled off to form a groove.

[0022] In one embodiment of the present application, the graphic area is processed into a grid shape.

[0023] In one embodiment of the present application, the first insulating layer includes a polymer layer, and the second insulating layer includes a polymer layer.

[0024] In one embodiment of the present application, the first metal layer and the second metal layer are overlapped.

[0025] In one embodiment of the present application, the line width of the first metal layer is not greater than 10 um, and the line pitch of the first metal layer is not greater than 10 um.

[0026] In one embodiment of the present application, the line width of the second metal layer is not greater than 10 um, and the line pitch of the second metal layer is not greater than 10 um.

[0027] In one embodiment of the present application, the method for manufacturing a semiconductor structure further includes:

[0028] Forming a third insulating layer on the upper surface of the second insulating layer, and embedding the second metal layer in the third insulating layer.

[0029] According to the second aspect of the present application, there is provided a semiconductor structure, including the semiconductor structure obtained by the method for manufacturing the semiconductor structure as described above.

[0030] The method for manufacturing the semiconductor structure according to the embodiment of the present application sequentially forms a first insulating layer, a first metal layer, a second insulating layer, and a second metal layer on a substrate, and before forming the second metal layer, by preprocessing the upper surface of the second insulating layer, it is ensured that the upper surface of the second insulating layer has a high flatness, so as to ensure that the bottom of the second metal layer formed on the upper surface of the second insulating layer tends to be horizontal, thereby improving the performance of the formed semiconductor structure. Description of the Drawings

[0031] By considering the following detailed description of the preferred embodiments of the present application in conjunction with the accompanying drawings, various objectives, features, and advantages of the present application will become more apparent. The accompanying drawings are only exemplary illustrations of the present application and are not necessarily drawn to scale. In the drawings, the same reference numerals always denote the same or similar components. Among them:

[0032] Figure 1 is a schematic flow diagram of a method for fabricating a semiconductor structure shown according to an exemplary embodiment;

[0033] Figure 2 is a schematic structural diagram of forming a first insulating layer in a method for fabricating a semiconductor structure shown according to an exemplary embodiment;

[0034] Figure 3 is a schematic structural diagram of forming a first metal layer in a method for fabricating a semiconductor structure shown according to an exemplary embodiment;

[0035] Figure 4 is a schematic structural diagram of forming a second insulating layer in a method for fabricating a semiconductor structure shown according to an exemplary embodiment;

[0036] Figure 5 is a schematic structural diagram of forming a mask in a method for fabricating a semiconductor structure shown according to an exemplary embodiment;

[0037] Figure 6 is a schematic structural diagram of a graphic region of a mask shown according to an exemplary embodiment;

[0038] Figure 7 is a schematic structural diagram of forming a developed portion in a method for fabricating a semiconductor structure shown according to an exemplary embodiment;

[0039] Figure 8 is a schematic structural diagram of forming a groove in a method for fabricating a semiconductor structure shown according to an exemplary embodiment;

[0040] Figure 9 is a schematic structural diagram of forming a second insulating layer in a method for fabricating a semiconductor structure shown according to an exemplary embodiment;

[0041] Figure 10 is a schematic structural diagram of forming a second metal layer in a method for fabricating a semiconductor structure shown according to an exemplary embodiment;

[0042] Figure 11 is a schematic structural diagram of forming a third insulating layer in a method for fabricating a semiconductor structure shown according to an exemplary embodiment;

[0043] Figure 12It is a schematic structural diagram of forming a second metal layer according to a manufacturing method of a semiconductor structure shown in another exemplary embodiment;

[0044] Figure 13 It is a schematic structural diagram of forming a third insulating layer according to a manufacturing method of a semiconductor structure shown in another exemplary embodiment.

[0045] The description of the reference numerals is as follows:

[0046] 10. Substrate; 20. First insulating layer; 30. First metal layer; 40. Second insulating layer; 41. Groove; 42. Developed part; 50. Second metal layer; 60. Mask; 61. Pattern area; 70. Third insulating layer. Detailed embodiments

[0047] Typical embodiments embodying the features and advantages of the present application will be described in detail in the following description. It should be understood that the present application can have various variations in different embodiments, all of which do not depart from the scope of the present application, and the descriptions and drawings therein are for illustrative purposes in essence and not for limiting the present application.

[0048] In the following description of different exemplary embodiments of the present disclosure, reference is made to the accompanying drawings, which form a part of the present disclosure, and in which different exemplary structures, systems, and steps for implementing various aspects of the present disclosure are shown by way of example. It should be understood that other specific solutions of components, structures, exemplary devices, systems, and steps can be used, and structural and functional modifications can be made without departing from the scope of the present disclosure. Moreover, although terms such as "above", "between", "inside", etc. may be used in this specification to describe different exemplary features and elements of the present disclosure, these terms are used herein only for convenience, for example, according to the directions in the examples of the drawings. Nothing in this specification should be construed as requiring a specific three-dimensional direction of the structure to fall within the scope of the present disclosure.

[0049] An embodiment of the present application provides a manufacturing method of a semiconductor structure. Please refer to Figure 1 , the manufacturing method of the semiconductor structure includes:

[0050] S101. Provide a substrate 10;

[0051] S103. Form a first insulating layer 20 on the substrate 10;

[0052] S105. Form a first metal layer 30 on the first insulating layer 20;

[0053] S107. Form a second insulating layer 40 on the first insulating layer 20, and embed the first metal layer 30 in the second insulating layer 40;

[0054] S109, preprocess the upper surface of the second insulating layer 40 to planarize the second insulating layer 40;

[0055] S1011, form a second metal layer 50 on the upper surface of the planarized second insulating layer 40.

[0056] The manufacturing method of the semiconductor structure according to an embodiment of the present application sequentially forms a first insulating layer 20, a first metal layer 30, a second insulating layer 40, and a second metal layer 50 on a substrate 10. Before forming the second metal layer 50, by preprocessing the upper surface of the second insulating layer 40, it is ensured that the upper surface of the second insulating layer 40 has a high flatness, so as to ensure that the bottom of the second metal layer 50 formed on the upper surface of the second insulating layer 40 tends to be horizontal, thereby improving the performance of the formed semiconductor structure.

[0057] It should be noted that after forming the first metal layer 30 on the first insulating layer 20, a second insulating layer 40 is formed on the first insulating layer 20. A first metal layer 30 is located below the first part of the second insulating layer 40, while there is no first metal layer 30 below the second part. Considering that the materials of the second insulating layer 40 and the first insulating layer 20 can be the same or relatively similar, directly forming the second insulating layer 40 on the first insulating layer 20 will not affect the second insulating layer 40. However, considering that there are significant differences in the material properties between the second insulating layer 40 and the first metal layer 30, directly forming the second insulating layer 40 on the first metal layer 30 will have a greater impact on the second insulating layer 40. During the subsequent baking and curing process of the second insulating layer, different shrinkage amounts will occur between the part of the second insulating layer 40 directly opposite to the first metal layer 30 and the part of the second insulating layer 40 not directly opposite to the first metal layer 30, so that the upper surface of the second insulating layer 40 is uneven. In this embodiment, by preprocessing the upper surface of the second insulating layer 40, the upper surface of the second insulating layer 40 has a high flatness, so as to ensure that problems such as bending and deformation will not occur in the subsequently formed second metal layer 50.

[0058] In one embodiment, preprocessing the upper surface of the second insulating layer 40 includes baking the second insulating layer 40. Specifically, when preprocessing the upper surface of the second insulating layer 40, a polishing (Chemical Mechanical Polishing, CMP) process can be used to grind and flatten the upper surface of the second insulating layer 40, or an etching process can be used to process the upper surface of the second insulating layer 40, so as to ensure that the upper surface of the second insulating layer 40 has a high flatness. Then, the part of the second insulating layer 40 directly opposite to the first metal layer 30 can be appropriately removed. Finally, the second insulating layer 40 can be baked to cure the second insulating layer 40 and make the upper surface of the second insulating layer 40 have a high flatness.

[0059] In one embodiment, the pretreatment of the upper surface of the second insulating layer 40 includes: removing a part of the second insulating layer 40 while avoiding exposing the first metal layer 30. On the basis of ensuring a high flatness of the upper surface of the second insulating layer 40, the first metal layer 30 and the second metal layer 50 can be isolated by the second insulating layer 40.

[0060] It should be noted that removing a part of the second insulating layer 40 can be understood as removing the material of the second insulating layer 40, for example, using etching to remove the material. Or removing a part of the second insulating layer 40 can be understood as performing a shrinkage treatment on the second insulating layer 40, that is, the material of the second insulating layer 40 is not removed, but the density of the second insulating layer 40 is increased, so that the overall thickness of the second insulating layer 40 changes (similar to the change in volume). For example, the local or segmented treatment of the second insulating layer 40 is performed by using a baking process, so that the local or overall thickness of the second insulating layer 40 changes, so as to ensure a high flatness of the upper surface of the second insulating layer 40. Specifically, the local baking can be performed on the second insulating layer 40 directly opposite to the first metal layer 30 to shrink the raised second insulating layer 40, so that the upper surface of the second insulating layer 40 has a high flatness. Or, the second insulating layer 40 directly opposite to the first metal layer 30 can be baked at a relatively high temperature, while the baking temperature at other positions is relatively low, so as to make the upper surface of the second insulating layer 40 have a high flatness.

[0061] In one embodiment, before the pretreatment of the second insulating layer 40, the thickness of the second insulating layer 40 above the first metal layer 30 is h, and the removed thickness of the second insulating layer 40 is not less than h / 3, so as to ensure that the second insulating layer 40 has enough removal amount, and thus ensure that the second insulating layer 40 has a high flatness after pretreatment.

[0062] Optionally, the removed thickness of the second insulating layer 40 is 45h% - 55h%. On the basis of ensuring that the second insulating layer 40 has enough removal amount, the second insulating layer 40 will not be over-removed, avoiding the problem of insufficient insulation between the first metal layer 30 and the second metal layer 50.

[0063] In one embodiment, removing a part of the second insulating layer 40 includes: forming a groove 41 on the second insulating layer 40, and the groove 41 is directly opposite to the first metal layer 30, that is, the second insulating layer 40 directly opposite to the first metal layer 30 is thinned, which is convenient for ensuring the flatness of the second insulating layer 40 after the subsequent overall treatment of the second insulating layer 40.

[0064] It should be noted that after the groove 41 is formed on the second insulating layer 40, the second insulating layer 40 needs to be further processed so that the upper surface of the second insulating layer 40 has sufficient flatness. Subsequently, a baking process can also be adopted to ensure the planarization of the upper surface of the second insulating layer 40. That is, the shrinkage amount of the second insulating layer 40 directly opposite to the first metal layer 30 is less than the shrinkage amount of the second insulating layer 40 not directly opposite to the first metal layer 30, thereby ensuring the planarization of the upper surface of the second insulating layer 40.

[0065] In one embodiment, the part of the second insulating layer 40 removed further includes: baking the second insulating layer 40 on which the groove 41 is formed to planarize the second insulating layer 40, that is, causing the second insulating layer 40 to shrink. And since the shrinkage amount of the second insulating layer 40 directly opposite to the first metal layer 30 will be less than the shrinkage amount of the second insulating layer 40 not directly opposite to the first metal layer 30, the finally formed second insulating layer 40 can have a high flatness.

[0066] In one embodiment, the difference between the thickness of the second insulating layer 40 before baking and the thickness of the second insulating layer 40 after baking is greater than the depth of the groove 41, that is, the second insulating layer 40 corresponding to the bottom wall of the groove 41 also shrinks, thereby ensuring that the upper surface of the second insulating layer 40 after baking has a high flatness and ensuring that the second insulating layer 40 has good insulating ability.

[0067] In one embodiment, forming the groove 41 on the second insulating layer 40 includes: forming a mask plate 60 above the second insulating layer 40. The mask plate 60 is formed with a graphic area 61 and the graphic area 61 is arranged opposite to the first metal layer 30; after exposure and development processing, the second insulating layer 40 in the exposed area is dissolved and peeled off to form the groove 41.

[0068] Specifically, as shown in Figure 2 a first insulating layer 20 is formed on the substrate 10. The first insulating layer 20 can adopt processes in related technologies, such as Physical Vapor Deposition (PVD) process, Chemical Vapor Deposition (CVD) process or Atomic Layer Deposition (ALD) process, etc.

[0069] In this embodiment, a polyimide film (PI photoresist) is coated, exposed, developed and cured to form the first insulating layer 20. The pattern of the first metal layer 30 is made by means of PR (Photo Resist) coating, exposure and development, and then the first metal layer 30 is formed by electroplating, such as Figure 3As shown. A second PI photoresist is coated on the first insulating layer 20, and is exposed, developed, and cured to form a second insulating layer 40, as Figure 4 shown. A mask 60 is formed above the second insulating layer 40. The mask 60 has a pattern area 61, and the pattern area 61 is disposed opposite to the first metal layer 30, as Figure 5 shown. After exposure, a developed portion 42 as shown in Figure 7 is formed on the second insulating layer 40. After the developing process, a groove 41 as shown in Figure 8 is formed on the second insulating layer 40, and after baking, a second insulating layer 40 as shown in Figure 9 is formed, that is, the upper surface of the formed second insulating layer 40 has a high flatness.

[0070] It should be noted that by providing the mask 60, the second insulating layer 40 corresponding to the pattern area 61 is exposed, and subsequently, after developing, a part of the second insulating layer 40 at the exposed position is removed, thereby forming the groove 41. After baking, the upper surface of the second insulating layer 40 has a high flatness. Then, by using the PR (Photo Resist) coating, exposure, and developing methods, the pattern of the second metal layer 50 is made, and then the second metal layer 50 is formed by electroplating, as Figure 10 and Figure 12 shown.

[0071] In one embodiment, as Figure 6 shown, the pattern area 61 is processed into a grid shape, and by increasing or decreasing the density or spacing of the grids, the ultraviolet dose (UV dose) of the exposure is changed, so as to achieve the purpose of precise control and ensure the reliable formation of the groove 41 subsequently.

[0072] In one embodiment, the pattern area 61 may not be processed into a grid shape, and the ultraviolet light is irradiated normally for exposure, and after developing, the developer is removed to form the groove 41.

[0073] In one embodiment, the manufacturing method of the semiconductor structure further includes: forming a third insulating layer 70 on the upper surface of the second insulating layer 40, and embedding the second metal layer 50 in the third insulating layer 70, as Figure 11 and Figure 13 shown, thereby ensuring reliable insulation protection for the second metal layer 50.

[0074] In one embodiment, the substrate 10 may be formed of a silicon-containing material. The substrate 10 may be formed of any suitable material, for example, including at least one of silicon, single crystal silicon, polycrystalline silicon, amorphous silicon, silicon germanium, single crystal silicon germanium, polycrystalline silicon germanium, and carbon-doped silicon.

[0075] In one embodiment, the first insulating layer 20 includes a polymer layer, and the first insulating layer 20 can be a polymer dielectric layer. The material of the polymer layer can include but is not limited to polyimide (PI), polybenzoxazole (PBO), or other suitable materials. In some embodiments, the material of the polymer layer can also include but is not limited to photocurable materials or can be formed from photocurable materials, such as photoresist or the like.

[0076] Correspondingly, the second insulating layer 40 includes a polymer layer, and the second insulating layer 40 can be a polymer dielectric layer. The material of the polymer layer can include but is not limited to polyimide (PI), polybenzoxazole (PBO), or other suitable materials. In some embodiments, the material of the polymer layer can also include but is not limited to photocurable materials or can be formed from photocurable materials, such as photoresist or the like.

[0077] The third insulating layer 70 includes a polymer layer, and the third insulating layer 70 can be a polymer dielectric layer. The material of the polymer layer can include but is not limited to polyimide (PI), polybenzoxazole (PBO), or other suitable materials. In some embodiments, the material of the polymer layer can also include but is not limited to photocurable materials or can be formed from photocurable materials, such as photoresist or the like.

[0078] In one embodiment, the first metal layer 30 and the second metal layer 50 are overlapped, and the first metal layer 30 and the second metal layer 50 are isolated by the second insulating layer 40. The first metal layer 30 and the second metal layer 50 can be used to connect the inductor.

[0079] It should be noted that the first metal layer 30 and the second metal layer 50 are overlapped, that is, the orthographic projections of the first metal layer 30 and the second metal layer 50 on the substrate 10 can be at least partially coincident, as Figure 10 and Figure 11 shown. Alternatively, the orthographic projections of the first metal layer 30 and the second metal layer 50 on the substrate 10 can be non - coincident, as Figure 12 and Figure 13 shown. The first metal layer 30 and the second metal layer 50 can ultimately facilitate the connection to the inductor, that is, the first metal layer 30 can connect one end of the inductor, and the second metal layer 50 can connect the other end of the inductor.

[0080] Optionally, the second metal layer 50 is formed directly above the first metal layer 30, so that the first metal layer 30 and the second metal layer 50 are completely facing each other, thus facilitating the connection to the inductor.

[0081] In some embodiments, the first metal layer 30 is a first RDL (Redistribution Layer), and the first RDL may include, but is not limited to, gold (Au), silver (Ag), nickel (Ni), copper (Cu), other metals or alloys, or a combination of two or more of the above.

[0082] Correspondingly, the second metal layer 50 is a second RDL, and the second RDL may include, but is not limited to, gold (Au), silver (Ag), nickel (Ni), copper (Cu), other metals or alloys, or a combination of two or more of the above.

[0083] In one embodiment, the line width of the first metal layer 30 is not greater than 10 um, and the line pitch of the first metal layer 30 is not greater than 10 um. Since both the line width and the line pitch of the first metal layer 30 are small, problems such as bending are likely to occur. Since the first metal layer 30 is directly formed on the first insulating layer 20, and the first insulating layer 20 is integrally formed on the substrate 10, the overall flatness of the first insulating layer 20 can be ensured to be relatively high. Therefore, the first insulating layer 20 does not need to be pretreated. In some embodiments, it is not excluded to perform the above-mentioned pretreatment on the second insulating layer 40 on the first insulating layer 20.

[0084] In one embodiment, the line width of the second metal layer 50 is not greater than 10 um, and the line pitch of the second metal layer 50 is not greater than 10 um. Since both the line width and the line pitch of the second metal layer 50 are small, problems such as bending are likely to occur. And since the first metal layer 30 and the first insulating layer 20 are covered under the second insulating layer 40, the shrinkage amount of the second insulating layer 40 will have a large difference, so the flatness of the upper surface of the second insulating layer 40 is relatively poor. Therefore, the upper surface of the second insulating layer 40 is pretreated to ensure the flatness of the upper surface of the second insulating layer 40, so as to ensure that the bottom of the subsequently formed second metal layer 50 tends to be horizontal and has no large arc shape.

[0085] The manufacturing method of the semiconductor in the present application can form a dual RDL redistribution. The PI between the two layers of RDL serves as a dielectric layer. Since the line width and the line pitch of the RDL redistribution are very small, the PI on the top layer of the first RDL will bulge, affecting the growth of the second RDL. However, in the present application, by pretreating the PI, the flatness of the PI is ensured, thereby ensuring that the formed second RDL wiring does not have a peeling phenomenon. The dual RDL redistribution formed by the manufacturing method of the semiconductor in the present application can be applied to a common mode inductance chip, that is, a common mode inductance is realized by using the dual RDL redistribution.

[0086] One embodiment of the present application further provides a semiconductor structure, including the semiconductor structure obtained by the manufacturing method of the above-mentioned semiconductor structure.

[0087] A semiconductor structure according to an embodiment of the present application includes a first insulating layer 20, a first metal layer 30, a second insulating layer 40, and a second metal layer 50. Before forming the second metal layer 50, the upper surface of the second insulating layer 40 is pre-treated to ensure that the upper surface of the second insulating layer 40 has a high flatness, so as to ensure that the bottom of the second metal layer 50 formed on the upper surface of the second insulating layer 40 tends to be horizontal and has no large arc shape, thereby improving the performance of the formed semiconductor structure.

[0088] In one embodiment, the semiconductor structure further includes a sensor, and the sensor is connected to the first metal layer 30 and the second metal layer 50. The first metal layer 30 is the first RDL, and the second metal layer 50 is the second RDL.

[0089] Those skilled in the art will readily conceive of other embodiments of the present application after considering the specification and practicing the invention disclosed herein. The present application is intended to cover any variations, uses, or adaptations of the present application, which follow the general principles of the present application and include known common knowledge or conventional technical means in the technical field not disclosed in the present application. The specification and example embodiments are only regarded as exemplary, and the true scope and spirit of the present application are pointed out by the appended claims.

[0090] It should be understood that the present application is not limited to the exact structures described above and shown in the drawings, and various modifications and changes can be made without departing from its scope. The scope of the present application is only limited by the appended claims.

Claims

1. A method for fabricating a semiconductor structure, characterized in that, Comprising: Providing a substrate; Forming a first insulating layer on the substrate; Forming a first metal layer on the first insulating layer; Forming a second insulating layer on the first insulating layer and embedding the first metal layer in the second insulating layer; Pretreating the upper surface of the second insulating layer to planarize the second insulating layer, specifically including: removing a part of the second insulating layer to form a groove on the second insulating layer, the groove being directly opposite to the first metal layer and the groove avoiding exposing the first metal layer; Forming a second metal layer on the upper surface of the planarized second insulating layer.

2. The manufacturing method of the semiconductor structure according to claim 1, characterized in that, Before pretreating the second insulating layer, the thickness of the second insulating layer above the first metal layer is h, and the thickness of the removed second insulating layer is not less than h / 3.

3. The manufacturing method of the semiconductor structure according to claim 1, characterized in that, Removing the part of the second insulating layer further includes: Baking the second insulating layer forming the groove to planarize the second insulating layer.

4. The manufacturing method of the semiconductor structure according to claim 3, characterized in that, The difference between the thickness of the second insulating layer before baking and the thickness of the second insulating layer after baking is greater than the depth of the groove.

5. The method for manufacturing a semiconductor structure according to any one of claims 3 to 4, characterized in that, Forming a groove on the second insulating layer includes: Forming a mask plate above the second insulating layer, the mask plate having a pattern area and making the pattern area opposite to the first metal layer; After exposure and development processing, dissolving and removing the second insulating layer in the exposed area to form the groove.

6. The manufacturing method of the semiconductor structure according to claim 5, characterized in that, The pattern area is processed into a grid shape.

7. The method for fabricating a semiconductor structure according to claim 1, wherein, The first insulating layer includes a polymer layer, and the second insulating layer includes a polymer layer.

8. The manufacturing method of the semiconductor structure according to claim 1, wherein, The first metal layer and the second metal layer are overlapped.

9. The method for fabricating a semiconductor structure according to claim 1, wherein, The line width of the first metal layer is not greater than 10 um, and the line pitch of the first metal layer is not greater than 10 um.

10. The manufacturing method of the semiconductor structure according to claim 1, wherein, The line width of the second metal layer is not greater than 10 um, and the line pitch of the second metal layer is not greater than 10 um.

11. The method for manufacturing a semiconductor structure according to claim 1, wherein, Further comprising: Forming a third insulating layer on the upper surface of the second insulating layer and embedding the second metal layer in the third insulating layer.

12. A semiconductor structure, characterized in that, Including a semiconductor structure obtained by the manufacturing method of the semiconductor structure according to any one of claims 1 to 11.

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