Semiconductor structure and preparation method thereof

Abstract

The present disclosure relates to a semiconductor structure and a method for preparing the same. The semiconductor structure includes: a substrate, a conductive pattern layer, a support layer, and a redistribution layer. The conductive pattern layer is disposed on the substrate. The support layer covers the conductive pattern layer and has a via. The redistribution layer is disposed on the support layer, and the redistribution layer includes: a test pad located at least within the via. The test pad includes a plurality of test contact portions and a plurality of recesses that are alternately arranged and interconnected, wherein the recesses are in corresponding contact with the portion of the conductive pattern layer located within the via. The semiconductor structure and the method for preparing the same provided by the present disclosure can not only prevent the yield of the semiconductor structure from being damaged due to wafer acceptance testing, but also facilitate further miniaturization of the size of the semiconductor structure.

Description

Technical Field

[0001] The present disclosure relates to the technical field of semiconductor integrated circuit manufacturing, and in particular to a semiconductor structure and a preparation method thereof. Background Art

[0002] With the rapid development of semiconductor technology, the redistribution layer (RDL) has been widely used in the chip packaging field. However, in the field of dynamic random access memory (DRAM), the top metal layer connected to the redistribution layer is easily damaged during wafer acceptance testing (WAT), resulting in a decrease in DRAM yield. In addition, as the size of integrated circuits in DRAM continues to shrink, it is difficult to find a large space in the DRAM for the layout of the redistribution layer. Therefore, the application of the redistribution layer in DRAM-related fields has been limited. Summary of the Invention

[0003] Based on this, the embodiments of the present disclosure provide a semiconductor structure and a method for preparing the same, which can not only prevent the yield of the semiconductor structure from being damaged due to wafer acceptance testing, but also facilitate further miniaturization of the semiconductor structure size.

[0004] To achieve the above objectives, in one aspect, some embodiments of the present disclosure provide a semiconductor structure. The semiconductor structure includes: a substrate, a conductive pattern layer, a support layer, and a redistribution layer. The conductive pattern layer is disposed on the substrate. The support layer covers the conductive pattern layer and has a via. The redistribution layer is disposed on the support layer, and the redistribution layer includes: a test pad located at least within the via. The test pad includes a plurality of test contact portions and a plurality of recesses that are arranged alternately and interconnected, wherein the recesses are in contact with corresponding portions of the conductive pattern layer located within the via.

[0005] In some embodiments, a gap between tops of two adjacent test contact portions is smaller than a gap between bottoms of two adjacent test contact portions.

[0006] In some embodiments, tops of two adjacent test contact portions are in contact with each other.

[0007] In some embodiments, the semiconductor structure further comprises: a plurality of spacers located within the via hole; wherein a space is formed between any two adjacent spacers; and a test pad covers the spacers and the space, with the test contact portion of the test pad correspondingly located on a surface of the spacer facing away from the substrate, and the recess of the test pad correspondingly located within the space.

[0008] For example, the spacers include long strip spacers, a plurality of long strip spacers are arranged in parallel and spaced apart, and both ends of the long strip spacers along the length direction are respectively connected to the sidewalls of the via hole.

[0009] For example, the spacers include block-shaped spacers, and a plurality of block-shaped spacers are distributed in an array.

[0010] Optionally, the width of the orthographic projection of the spacer on the substrate has a value range of 6 μm to 10 μm.

[0011] In other embodiments, the semiconductor structure further comprises: a spacer located in the via hole and hollowed out into a grid shape, the test pad covers the spacer, the test contact portion is correspondingly located on a surface of the spacer facing away from the substrate, and the recess is correspondingly located in the hollowed-out area of ​​the spacer.

[0012] In some embodiments, the surface of the spacer facing away from the substrate is flush with the surface of the support layer facing away from the substrate.

[0013] Optionally, the material of the spacer or the support layer includes at least one of silicon oxide, silicon nitride or an organic insulating material.

[0014] In some embodiments, the shape of the orthographic projection of the via hole on the substrate includes: rectangle, square, circle, or ellipse. The minimum size of the orthographic projection of the via hole on the substrate is greater than or equal to 10 μm.

[0015] In some embodiments, a maximum dimension of an orthographic projection of the test pad on the substrate is greater than or equal to 50 μm.

[0016] In some embodiments, a distance between a surface of the test contact portion facing away from the conductive pattern layer and the conductive pattern layer is greater than or equal to 5 μm.

[0017] In some embodiments, the redistribution layer further includes a bonding pad coupled to the test pad, wherein an orthographic projection of the bonding pad on the substrate is outside an orthographic projection of the test pad on the substrate.

[0018] On the other hand, some embodiments of the present disclosure provide a method for preparing a semiconductor structure, which is used to prepare the semiconductor structure in some of the above embodiments. The method for preparing the semiconductor structure includes the following steps.

[0019] A substrate is provided, and a conductive pattern layer is formed on the substrate.

[0020] A support layer is formed on the conductive pattern layer, and a via hole is formed in the support layer.

[0021] A redistribution layer is formed on the support layer, the redistribution layer includes a test pad located at least in the via hole; the test pad includes a plurality of test contact portions and a plurality of recesses that are arranged alternately and interconnected, wherein the recesses are in corresponding contact with the portion of the conductive pattern layer located in the via hole.

[0022] In some embodiments, before forming the redistribution layer on the support layer, the preparation method further includes: forming a plurality of spacers within the vias; wherein a gap exists between any two adjacent spacers. Forming the redistribution layer on the support layer includes: forming test contacts on at least the surfaces of the spacers facing away from the substrate, and forming recesses within the gaps.

[0023] For example, forming a plurality of spacers in the via hole includes forming a plurality of long strip spacers arranged in parallel and spaced apart in the via hole, wherein both ends of the long strip spacers along the length direction are respectively connected to the sidewalls of the via hole.

[0024] For example, forming a plurality of spacers in the via hole includes: forming a plurality of block-shaped spacers distributed in an array in the via hole.

[0025] In other embodiments, before forming the redistribution layer on the support layer, the preparation method further includes: forming spacers hollowed out into a grid pattern within the vias. Forming the redistribution layer on the support layer includes: forming test contacts on at least a surface of the spacers facing away from the substrate, and forming recesses within the hollowed-out regions of the spacers.

[0026] In some embodiments, the vias and spacers are formed through a single patterning process.

[0027] In some embodiments, forming a redistribution layer on the supporting layer further includes: forming a bonding pad on the supporting layer, wherein an orthographic projection of the bonding pad on the substrate is outside an orthographic projection of the test pad on the substrate.

[0028] In the semiconductor structure and fabrication method provided by the embodiments of the present disclosure, the test pad is composed of multiple test contacts and multiple recesses arranged alternately and interconnected, so that the test contacts within the test pad are arranged in an elevated grid. This allows the test pads in the redistribution layer to be directly located in the area where the vias RDV are located, eliminating the need for additional space to accommodate the test pads, thereby facilitating further miniaturization of the semiconductor structure.

[0029] Furthermore, when the probe is used to contact the test pad to perform a wafer acceptance test, the probe contacts the test contact portion, the test contact portion is interconnected with the recess, and the recess contacts the conductive pattern layer, effectively enabling the probe to test the electrical properties of the conductive pattern layer. Since the probe is typically inserted into the test pad at a certain angle, in the disclosed embodiment, the test contact portions in the test pad are arranged in an overhead grid pattern, ensuring that the tip of the probe is only inserted into the test contact portion, or into the air gap between adjacent test contact portions, thereby preventing the pressure of the probe from acting on the conductive pattern layer and causing deformation, short circuits, or fractures in the conductive pattern layer. This, in turn, prevents the yield of the semiconductor structure from being damaged by the wafer acceptance test, thereby improving the yield of the semiconductor structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the conventional technology, the following briefly introduces the drawings required for use in the embodiments or the conventional technology descriptions. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0031] Figure 1 is a schematic cross-sectional view of a semiconductor structure provided in one embodiment;

[0032] Figure 2 is a schematic cross-sectional view of another semiconductor structure provided in an embodiment;

[0033] Figure 3 is a schematic cross-sectional view of another semiconductor structure provided in an embodiment;

[0034] Figure 4 A schematic diagram of the distribution of a spacer in a via hole provided in one embodiment;

[0035] Figure 5 A schematic diagram of the distribution of another spacer in a via hole provided in an embodiment;

[0036] Figure 6 A schematic diagram of the distribution of another spacer in a via hole provided in an embodiment;

[0037] Figure 7 is a schematic flow chart of a method for preparing a semiconductor structure provided in one embodiment;

[0038] Figure 8 is a schematic diagram of preparing a conductive pattern layer provided in one embodiment;

[0039] Figure 9 A schematic diagram of preparing a via and a spacer provided in one embodiment;

[0040] Figure 10 A schematic diagram of another method for preparing a via and a spacer provided in one embodiment;

[0041] Figure 11 is a schematic diagram of preparing a redistribution layer provided in one embodiment;

[0042] Figure 12 Schematic diagram of preparing a dielectric layer provided in one embodiment.

[0043] Description of reference numerals:

[0044] 100-semiconductor structure, 1-substrate, 2-conductive pattern layer, 21-signal line, 3-support layer,

[0045] 31-silicon oxide layer, 32-silicon nitride layer, 33-organic material layer, RDV-via,

[0046] 4-rewiring layer, 41-test pad, 411-test contact portion, 412-recess, 42-bonding pad,

[0047] 40-conductive layer, 401-titanium layer, 402-aluminum layer, 403-titanium layer, 5-spacer,

[0048] 6-patterned dielectric layer, 61-silicon nitride layer, 62-organic material layer, 7-probe, 8-adhesion layer,

[0049] D-the distance from the surface of the test contact portion facing away from the conductive pattern layer to the conductive pattern layer,

[0050] L is the distance between adjacent spacers, W is the width of the spacer's orthographic projection on the substrate, H is the hollow area of ​​the spacer 5, and D is the width of the spacer's orthographic projection on the substrate. a -The long side dimension of the orthographic projection of the via on the substrate, D b -The broadside dimension of the orthographic projection of the via on the substrate. DETAILED DESCRIPTION

[0051] To facilitate understanding of the present application, the present application will be described more fully below with reference to the accompanying drawings. The accompanying drawings provide embodiments of the present application. However, the present application may be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided to make the disclosure of the present application more thorough and comprehensive.

[0052] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application pertains. The terms used herein in the specification of this application are for the purpose of describing specific embodiments only and are not intended to limit this application.

[0053] It should be understood that when an element or layer is referred to as being “on,” “adjacent,” “connected to,” or “coupled to” another element or layer, it can be directly on, adjacent, connected, or coupled to the other element or layer, or intervening elements or layers may be present. In contrast, when an element is referred to as being “directly on,” “directly adjacent to,” “directly connected to,” or “directly coupled to” another element or layer, there are no intervening elements or layers present.

[0054] Spatially relative terms such as "under," "beneath," "beneath," "under," "above," "above," etc., may be used herein to describe the relationship of an element or feature shown in the figures to other elements or features. It should be understood that in addition to the orientations shown in the figures, spatially relative terms also include different orientations of the device in use and operation. For example, if the device in the drawings is turned over, the element or feature described as "under" or "beneath" or "beneath" the other elements will be oriented as "above" the other elements or features. Thus, the exemplary terms "under" and "under" can include both upper and lower orientations. In addition, the device can also include alternative orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptors used herein are interpreted accordingly.

[0055] As used herein, the singular forms "a," "an," and "the" may also include the plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "include," "comprising," "having," and the like specify the presence of stated features, integers, steps, operations, components, parts, or combinations thereof, but do not preclude the presence or addition of one or more other features, integers, steps, operations, components, parts, or combinations thereof. Also, in this specification, the term "and / or" includes any and all combinations of the relevant listed items.

[0056] Embodiments of the invention are described herein with reference to cross-sectional views that are schematic illustrations of idealized embodiments (and intermediate structures) of the present application, and variations from the illustrated shapes due to, for example, manufacturing techniques and / or tolerances are anticipated. Accordingly, embodiments of the present application should not be limited to the specific shapes of the regions illustrated herein, but rather include deviations in shapes due to, for example, manufacturing techniques. The regions shown in the figures are schematic in nature, and their shapes do not represent the actual shapes of the regions of the device and do not limit the scope of the present application.

[0057] Wafer acceptance testing (WAT) involves performing electrical measurements on each chip on a wafer to verify that the chip's manufacturing process meets standards at each stage. WAT includes various tests, such as chemical, physical, and performance tests, to confirm whether the chip meets design specifications or contract requirements.

[0058] For example, for a wafer acceptance test of a dynamic random access memory, a redistribution layer can be provided in the dynamic random access memory, and the conductive pattern layer that needs to be electrically tested can be electrically led out using the redistribution layer to facilitate measurement.

[0059] Based on this, see Figure 1 and Figure 2 Some embodiments of the present disclosure provide a semiconductor structure 100. The semiconductor structure 100 includes: a substrate 1, a conductive pattern layer 2, a support layer 3, and a redistribution layer 4. The conductive pattern layer 2 is arranged on the substrate 1. The support layer 3 covers the conductive pattern layer 2 and has a via RDV. The redistribution layer 4 is arranged on the support layer 3, and the redistribution layer 4 includes: a test pad 41 located at least within the via RDV. The test pad 41 includes a plurality of test contact portions 411 and a plurality of recesses 412 that are arranged alternately and interconnected, wherein the recesses 412 are in corresponding contact with the portion of the conductive pattern layer 2 located within the via RDV.

[0060] It should be noted that in the disclosed embodiments, substrate 1 is a substrate provided with electrical devices such as transistors and / or memory cells. The disclosed embodiments do not specifically limit the electrical devices contained in substrate 1. Redistribution layer 4 is used to connect to conductive pattern layer 2. Conductive pattern layer 2 refers to the top conductive layer, such as a top metal layer, that exists on substrate 1 before redistribution layer 4 is formed. The pattern of conductive pattern layer 2 can be customized according to actual needs. Conductive pattern layer 2 may include, for example, multiple signal lines 21.

[0061] The supporting layer 3 covers the conductive pattern layer 2. The material of the supporting layer 3 can be at least one of silicon oxide, silicon nitride or an organic insulating material. For example, the supporting layer 3 is a single thin film or a stack of multiple thin films.

[0062] Optional, such as Figure 1 As shown, the support layer 3 includes an organic material layer, such as a Tetraethylorthosilicate (TEOS) layer, to ensure that the support layer 3 has a certain thickness.

[0063] Optional, such as Figure 2As shown, the support layer 3 includes a silicon oxide layer 31, a silicon nitride layer 32, and an organic material layer 33, which are stacked in sequence in a direction away from the substrate 1. The organic material layer 33 is, for example, an ethyl orthosilicate layer, and the silicon oxide layer 31 can be prepared by performing a high-density plasma (HDP) process on ethyl orthosilicate. The thickness of the organic material layer 33 is greater than the thickness of the silicon oxide layer 31 and / or the silicon nitride layer 32. For example, the thickness of the organic material layer 33 is greater than or equal to 4 μm, for example, 4 μm, 4.5 μm, or 5 μm. The thickness of the silicon oxide layer 31 is greater than or equal to 0.5 μm, for example, 0.5 μm, 0.8 μm, or 1 μm. The thickness of the silicon nitride layer 32 is greater than or equal to 0.5 μm, for example, 0.5 μm, 0.6 μm, or 0.8 μm.

[0064] The via RDV penetrates the support layer 3 in a direction perpendicular to the substrate 1, so that a portion of the pattern of the conductive pattern layer 2 can be exposed within the via RDV. In some examples, the orthographic projection of the via RDV on the substrate 1 can be rectangular, square, circular, or elliptical, but is not limited thereto. For example, the orthographic projection of the via RDV on the substrate 1 can also be an irregular shape.

[0065] In addition, the size of the via RDV can be set according to actual needs. For example, the minimum size of the orthographic projection of the via RDV on the substrate 1 is greater than or equal to 10 μm, for example, 10 μm or 20 μm, to ensure that the portion of the conductive pattern layer 2 exposed within the via RDV can meet the requirement of good electrical connection between the conductive pattern layer 2 and the redistribution layer 4. Here, the minimum size of the orthographic projection of the via RDV on the substrate 1 refers to the minimum value of the orthographic projection of the via RDV on the substrate 1 among the dimensions in different directions.

[0066] The redistribution layer 4 is used to change the position of the initial contact points of the conductive pattern layer 2. It can be formed through a wafer-level metal routing process and a bumping process, so that the semiconductor structure 100 can be adapted for different packaging formats. The present embodiment only details the test pads 41 and bonding pads 42 in the redistribution layer 4. For details of the redistribution layer 4 other than the test pads 41 and bonding pads 42, please refer to the relevant art.

[0067] Please continue reading Figure 1 and Figure 2 The redistribution layer 4 includes test pads 41 and bonding pads 42. The test pads 41 are used for wafer acceptance testing of the semiconductor structure 100, while the bonding pads 42 are used to couple the semiconductor structure 100 to external electrical components. The number of test pads 41 and bonding pads 42 can be set based on actual needs, and the bonding pads 42 are coupled to the test pads 41 accordingly.

[0068] In some examples, the test pad 41 is formed at least within the via RDV. For example, the portion of the redistribution layer 4 located within the via RDV is the test pad 41; or, for another example, the portion of the redistribution layer 4 located within the via RDV and the portion connected to the periphery of the redistribution layer 4 together constitute the test pad 41.

[0069] In some examples, the bonding pad 42 is coupled to the test pad 41, and the orthographic projection of the bonding pad 42 on the substrate 1 is located outside the orthographic projection of the corresponding test pad 41 on the substrate 1. For example, the test pad 41 is disposed within the via RDV; the bonding pad 42 is connected to the test pad 41, and the bonding pad 42 is disposed outside the via RDV and has a certain distance from the boundary of the via RDV.

[0070] Please combine Figure 1 and Figure 2 It is understood that the test pad 41, the bonding pad 42, and the portion interconnected therebetween may be formed by a conductive layer 40 in the redistribution layer 4, wherein the conductive layer 40 is, for example, a single metal layer or a stack of multiple metal layers. In one example, the conductive layer 40 in the redistribution layer 4 is a stack of a titanium (Ti) layer 401 and an aluminum (Al) layer 402, or a stack of a titanium (Ti) layer 401, an aluminum (Al) layer 402, and a titanium (Ti) layer 403, wherein the thickness of the aluminum layer 402 is greater than the thickness of the titanium layer 401 and / or the titanium layer 403.

[0071] Please continue reading Figure 1 and Figure 2 The test pad 41 is at least located in the via RDV and is composed of a plurality of test contact portions 411 and a plurality of recesses 412 that are alternately arranged and interconnected. The number of test contact portions 411 and recesses 412 in the test pad 41 can be selected and set according to actual needs. The test contact portion 411 is used to contact the probe 7 during the wafer acceptance test. The test contact portion 411 refers to the portion of the test pad 41 that is not lower than the surface of the support layer 3 facing away from the substrate 1. The recess 412 is in corresponding contact with the portion of the conductive pattern layer 2 located in the via RDV. The recess 412 refers to the portion of the test pad 41 that is not higher than the surface of the support layer 3 facing away from the substrate 1.

[0072] When the test pad 41 employs a titanium (Ti) layer 401-aluminum (Al) layer 402-titanium (Ti) layer 403 structure, the thickness of the aluminum layer 402 in the recess 412 is related to the inner shape and size of the recess 412. For example, the thickness of the aluminum layer 402 in the recess 412 is greater than or equal to 1 μm, such as 1 μm, 1.2 μm, or 1.3 μm; the thickness of the titanium layer 401 and / or the titanium layer 403 in the recess 412 is greater than or equal to 0.1 μm, such as 0.1 μm, 0.3 μm, or 0.5 μm. Accordingly, the thickness of the aluminum layer 402 in the test contact portion 411 and the thickness of the aluminum layer 402 in the bonding pad 42 can be larger, such as greater than or equal to 4 μm, such as 4 μm, 4.5 μm, 4.8 μm, or 5 μm.

[0073] In the embodiment of the present disclosure, the test pad 41 is composed of a plurality of test contact portions 411 and a plurality of recesses 412 that are alternately arranged and interconnected, so that the test contact portions 411 in the test pad 41 are arranged in an overhead grid shape. In this way, the test pad 41 in the redistribution layer 4 can be directly set in the area where the via RDV is located without the need to reserve additional space to accommodate the test pad, so as to facilitate further miniaturization of the size of the semiconductor structure 100. In addition, in the process of using the probe pen 7 to contact the test pad 41 to perform the wafer acceptance test, the probe pen 7 contacts the test contact portion 411, the test contact portion 411 is interconnected with the recess 412, and the recess 412 contacts the conductive pattern layer 2, which can well realize the test of the electrical properties of the conductive pattern layer 2 by the probe pen 7. Since the probe pen 7 is usually inserted into the test pad 4 at a certain angle, in the embodiment of the present disclosure, the test contact portions 411 in the test pad 41 are arranged in an overhead grid shape, which can ensure that the tip of the probe pen 7 is only inserted into the test contact portion 411 or into the air gap between adjacent test contact portions 411, thereby avoiding the pressure of the probe pen 7 acting on the conductive pattern layer 2 and causing deformation, short circuit or breakage of the conductive pattern layer 2, thereby avoiding the yield of the semiconductor structure 100 from being damaged due to wafer acceptance testing, thereby improving the yield of the semiconductor structure 100.

[0074] It should be added that, in some embodiments, adjacent test contact portions 411 may also be electrically connected, for example Figure 3 As shown in FIG, the tops of two adjacent test contact portions 411 are in contact. This allows the test pad 41 to have a larger test contact area, ensuring good electrical contact between the probe 7 and the test pad 41. Furthermore, the test contact surface of the test pad 41 is free of air gaps, further preventing the tip of the probe 7 from penetrating the conductive pattern layer 2.

[0075] In other embodiments, the gap between the tops of two adjacent test contact portions 411 is smaller than the gap between the bottoms of two adjacent test contact portions 411 , for example Figure 2 As shown in . That is, the top of the test contact portion 411 has a protrusion toward the adjacent test contact portion 411, and the maximum protrusion size of the protrusion is greater than a threshold. Optionally, the maximum protrusion size of the protrusion on the top of the test contact portion 411 is greater than 0.5μm, for example, 0.6μm, 0.7μm, 0.8μm or 1μm. In this way, the test pad 41 can have a larger test contact area to ensure good electrical contact performance between the probe pen 7 and the test pad 41. In addition, the test contact surface of the test pad 41 has only a small air gap, which can further prevent the tip of the probe pen 7 from being inserted into the conductive pattern layer 2.

[0076] The test pad 41 in the embodiment of the present disclosure adopts the above structure, which can be implemented in various ways.

[0077] See also Figure 1 、 Figure 2 and Figure 3 In some embodiments, the semiconductor structure 100 further includes spacers 5 located in the vias RDV. The number, shape, and distribution of the spacers 5 can be set accordingly according to the shape and distribution of the test contact portions 411 . Figure 1 and Figure 2 It is only used to illustrate that the spacers 5 are disposed in the via holes RDV, and does not limit the number and size of the spacers 5 .

[0078] In one possible implementation, see Figure 4 and Figure 5 The semiconductor structure 100 includes a plurality of spacers 5 located within the via RDV, wherein a gap L is formed between any two adjacent spacers 5. The test pad 41 covers the spacers 5 and the gap L. The test contact portion 411 of the test pad 41 is located on a surface of the spacer 5 facing away from the substrate 1, and the recess 412 of the test pad 41 is located within the gap L.

[0079] For example, Figure 4 As shown, the orthographic projection of the via RDV on the substrate 1 is a rectangle. The spacers 5 include long strip-shaped spacers. A plurality of long strip-shaped spacers are arranged in parallel and spaced apart, and the two ends of the long strip-shaped spacers along the length direction are respectively connected to the side walls of the via RDV.

[0080] In addition, optionally, the minimum size of the orthographic projection of the via hole RDV on the substrate 1 is greater than or equal to 10 μm. For example, the orthographic projection of the via hole RDV on the substrate 1 is a rectangle with a long side dimension D of a Larger than the widthwise dimension D b , then the widthwise dimension D bGreater than or equal to 10 μm, such as 10 μm, 15 μm, or 20 μm. Accordingly, the width W of the orthographic projection of the long strip spacer on the substrate 1 ranges from 6 μm to 10 μm, such as 6 μm, 8 μm, or 10 μm. The interval L between two adjacent block spacers ranges from 6 μm to 10 μm, such as 6 μm, 8 μm, or 10 μm.

[0081] For example, Figure 5 As shown, the orthographic projection of the via RDV on the substrate 1 is a rectangle. The spacers 5 include block-shaped spacers, and a plurality of block-shaped spacers are distributed in an array.

[0082] In addition, optionally, the minimum size of the orthographic projection of the via hole RDV on the substrate 1 is greater than or equal to 10 μm. For example, the orthographic projection of the via hole RDV on the substrate 1 is a rectangle with a long side dimension D of a Larger than the widthwise dimension D b , then the widthwise dimension D b The width W of the orthographic projection of the block spacer on the substrate 1 is greater than or equal to 10 μm, and is 10 μm, 15 μm, or 20 μm. Accordingly, the width W of the orthographic projection of the block spacer on the substrate 1 is in the range of 6 μm to 10 μm, for example, 6 μm, 8 μm, or 10 μm. The distance L between two adjacent block spacers is in the range of 6 μm to 10 μm, for example, 6 μm, 8 μm, or 10 μm.

[0083] In another possible implementation, see Figure 6 The semiconductor structure 100 includes a spacer 5 located within the via RDV and hollowed out into a grid-like shape. A test pad 41 covers the spacer 5. The test contact portion 411 is located on the surface of the spacer 5 facing away from the substrate 1. The recess 412 is located within the hollowed-out region H of the spacer 5. The orthographic projection of the hollowed-out region H on the substrate 1 can be configured based on actual needs, such as a strip or block.

[0084] In some embodiments, the surface of the spacer 5 facing away from the substrate 1 is flush with the surface of the supporting layer 3 facing away from the substrate 1, which facilitates making the multiple test contact portions 411 of the test pad 41 have the same thickness to ensure that the surface of each test contact portion 411 facing away from the substrate 1 is flush.

[0085] In some embodiments, the material of the spacer 5 includes at least one of silicon oxide, silicon nitride, or an organic insulating material.

[0086] In the case that the material of the spacer 5 is the same as that of the supporting layer 3 , the spacer 5 and the via RDV in the supporting layer 3 can be formed through a single patterning process, thereby simplifying the manufacturing process of the semiconductor structure 100 .

[0087] It is understood that the redistribution layer 4 adopts the structure of some of the above embodiments to facilitate further miniaturization of the semiconductor structure 100. Therefore, the size design of the test pads 41 in the redistribution layer 4 needs to take into account both the size of the semiconductor structure 100 and the electrical property measurement requirements of the conductive pattern layer 2.

[0088] In some embodiments, the maximum size of the orthographic projection of the test pad 41 on the substrate 1 is greater than or equal to 50 μm, for example, 50 μm, 60 μm, or 80 μm.

[0089] Optionally, the portion of the redistribution layer 4 located in the via RDV is a test pad 41 , and the maximum size of the orthographic projection of the via RDV on the substrate 1 is greater than or equal to 50 μm, for example, 50 μm, 60 μm, or 80 μm.

[0090] Optionally, the portion of the redistribution layer 4 located within the via RDV and the portion connected to the peripheral side of the aforementioned portion together constitute a test pad 41, and the maximum size of the positive projection of the via RDV on the substrate 1 is less than 50μm, for example, 45μm, 40μm or 35μm.

[0091] In some embodiments, a distance D between the surface of the test contact portion 411 facing away from the conductive pattern layer 2 and the conductive pattern layer 2 is greater than or equal to 5 μm, for example, 5 μm, 6 μm, or 8 μm.

[0092] In addition, please refer to Figure 1 、 Figure 2 and Figure 3 The semiconductor structure 100 further includes a patterned dielectric layer 6 disposed on the redistribution layer 4. The test pads 41 and the bonding pads 42 in the redistribution layer 4 are exposed within openings in the patterned dielectric layer 6. Thus, the shapes of the test pads 41 and the bonding pads 42 can be accurately defined by the pattern of the patterned dielectric layer 6.

[0093] In some embodiments, see Figure 2 The material of the patterned dielectric layer 6 can be at least one of silicon oxide, silicon nitride, or an organic insulating material. The patterned dielectric layer 6 can be a single thin film layer or a stack of multiple thin films. When the patterned dielectric layer 6 comprises an organic material layer, the patterned dielectric layer 6 can also planarize the surface of the semiconductor structure 100.

[0094] For example, the patterned dielectric layer 6 includes a silicon nitride layer 61 and an organic material layer 62, which are stacked in sequence in a direction away from the substrate 1. The organic material layer 62 is, for example, a polyimide (PI) layer. The thickness of the organic material layer 62 is greater than that of the silicon nitride layer 61. For example, the minimum thickness of the organic material layer 62 is greater than or equal to 1.5 μm, such as 1.5 μm, 1.7 μm, 3 μm, or 5 μm; the maximum thickness of the organic material layer 62 is greater than or equal to 5.5 μm, such as 5.5 μm, 6 μm, 7 μm, or 8 μm. The thickness of the silicon nitride layer 61 is greater than or equal to 0.2 μm, such as 0.2 μm, 0.3 μm, or 0.5 μm.

[0095] Also, please continue reading Figure 2 In some embodiments, the semiconductor structure 100 further includes an adhesion layer 8 located between the redistribution layer 4 and the patterned dielectric layer 6 to enhance adhesion between the patterned dielectric layer 6 and the redistribution layer 4. Optionally, the adhesion layer 8 is a titanium nitride (TiN) layer. Thus, when the conductive layer 40 in the redistribution layer 4 includes the titanium layer 403, the adhesion layer 8 can be obtained by nitriding the titanium layer 403.

[0096] See also Figure 7 Some embodiments of the present disclosure further provide a method for preparing a semiconductor structure, which is used to prepare the semiconductor structure 100 in some of the above embodiments. The method for preparing the semiconductor structure includes the following steps.

[0097] S100 , providing a substrate, and forming a conductive pattern layer on the substrate.

[0098] S200 , forming a support layer on the conductive pattern layer, and forming via holes in the support layer.

[0099] S300, forming a redistribution layer on the support layer, the redistribution layer including a test pad at least located in the via hole; the test pad includes a plurality of test contact portions and a plurality of recesses that are arranged alternately and interconnected, wherein the recesses are in contact with the portion of the conductive pattern layer located in the via hole.

[0100] In the embodiments of the present disclosure, the technical effects that can be achieved by the method for preparing the semiconductor structure are the same as those of the semiconductor structures in some of the aforementioned embodiments and will not be described in detail here.

[0101] In some embodiments, S100 is as follows Figure 8As shown, substrate 1 is a substrate provided with electrical devices such as transistors and / or memory cells. The present disclosure does not specifically limit the electrical devices included in substrate 1. Conductive pattern layer 2 refers to the top conductive layer formed on substrate 1, such as a top metal layer. The pattern of conductive pattern layer 2 can be set according to actual needs. Conductive pattern layer 2 may include, for example, multiple signal lines 21.

[0102] In some embodiments, see Figure 9 and Figure 10 , S200, forming a support layer 3 on the conductive pattern layer 2, and forming a via hole RDV in the support layer 3. The material of the support layer 3 can be at least one of silicon oxide, silicon nitride or an organic insulating material. The support layer 3 can be a single layer thin film or a stack of multiple layers of thin films. For example, please combine Figure 2 and Figure 9 、 Figure 10 It is understood that the supporting layer 3 includes a silicon oxide layer 31, a silicon nitride layer 32 and an organic material layer 33 which are stacked in sequence in a direction away from the substrate 1, wherein the organic material layer 33 is, for example, an ethyl orthosilicate layer, and the silicon oxide layer 31 can be prepared by performing a high-density plasma (HDP) process on the ethyl orthosilicate material.

[0103] In addition, the via RDV passes through the supporting layer 3 in a direction perpendicular to the substrate 1, and part of the pattern of the conductive pattern layer 2 can be exposed in the via RDV. Optionally, the shape of the orthographic projection of the via RDV on the substrate 1 can be rectangular, square, circular or elliptical. Of course, it is also allowed that the shape of the orthographic projection of the via RDV on the substrate 1 adopts an irregular shape. Moreover, the size of the via RDV can be set according to actual needs. For example, the minimum size of the orthographic projection of the via RDV on the substrate 1 is greater than or equal to 10μm, for example, 10μm or 20μm, to ensure that the part of the pattern of the conductive pattern layer 2 exposed in the via RDV can meet the requirement of good electrical connection between the conductive pattern layer 2 and the redistribution layer 4. Here, the minimum size of the orthographic projection of the via RDV on the substrate 1 refers to: the orthographic projection shape of the via RDV on the substrate 1 is the minimum value among the sizes in each different direction.

[0104] In some embodiments, before performing S300, the method for fabricating a semiconductor structure further includes forming spacers within the via hole, so as to form a test contact portion and a recess in the test pad using the spacers. The number, shape, and distribution of the spacers may be set accordingly based on the shape and distribution of the test contact portion.

[0105] In one possible implementation, please combine Figure 4 、 Figure 5 and Figure 9It is understood that before forming the redistribution layer 4 on the support layer 3, the method for preparing the semiconductor structure further includes: forming a plurality of spacers 5 in the via hole RDV; wherein, there is a gap L between any two adjacent spacers 5. Figure 9 and Figure 11 It is understood that forming the redistribution layer 4 on the supporting layer 3 in S300 includes: forming a test contact portion 411 at least on the surface of the spacer 5 facing away from the substrate 1 , and forming a recess 412 in the aforementioned interval L.

[0106] For example, Figure 4 As shown, multiple spacers 5 are formed within the via hole RDV, including multiple long strip-shaped spacers arranged in parallel and spaced apart within the via hole RDV, with both ends of the long strip spacers connected to the sidewalls of the via hole RDV along the length direction. The structure of the via hole RDV and the long strip spacers can be found in the relevant descriptions of some of the aforementioned embodiments.

[0107] For example, Figure 5 As shown, forming a plurality of spacers 5 in the via hole RDV includes forming a plurality of block-shaped spacers distributed in an array in the via hole RDV. Here, the structures of the via hole RDV and the block-shaped spacers can refer to the relevant descriptions in some of the above embodiments.

[0108] Furthermore, in some embodiments, Figure 9 As shown, the via RDV and the spacer 5 can be formed through a single patterning process. The patterning process is, for example, a photolithography process. In this way, the material of the spacer 5 is the same as that of the support layer 3, and the surface of the spacer 5 facing away from the substrate 1 can be flush with the surface of the support layer 3 facing away from the substrate 1. This not only simplifies the fabrication process of the semiconductor structure 100, but also facilitates subsequent alignment of the multiple test contact portions 411 of the test pad 41 with the same thickness, ensuring that the surfaces of each test contact portion 411 facing away from the substrate 1 are flush.

[0109] In another possible implementation, please combine Figure 6 and Figure 10 It is understood that before forming the redistribution layer 4 on the support layer 3, the method for preparing the semiconductor structure 100 further includes: forming a spacer 5 hollowed out into a grid shape in the via hole RDV. Figure 10 and Figure 11 It is understood that forming the redistribution layer 4 on the supporting layer 3 in S300 includes: forming a test contact portion 411 at least on a surface of the spacer 5 facing away from the substrate 1 , and forming a recess 412 in the hollow region H of the spacer 5 .

[0110] In the embodiment of the present disclosure, the spacer 5 can be formed after the via hole RDV is formed, and the material of the spacer 5 can be different from the material of the support layer 3. Of course, when the material of the spacer 5 is the same as that of the support layer 3, the spacer 5 can also be formed through a single patterning process together with the via hole HDV in the support layer 3.

[0111] See also Figure 11 In some embodiments, forming a redistribution layer 4 on the support layer 3 further includes: forming a bonding pad 42 on the support layer 3, wherein the orthographic projection of the bonding pad 42 on the substrate 1 is located outside the orthographic projection of the test pad 41 on the substrate. For example, the test pad 41 is disposed within the via RDV; the bonding pad 42 is connected to the test pad 41, and the bonding pad 42 is disposed outside the via RDV and has a certain distance from the boundary of the via RDV. In addition, the structures of the test pad 41 and the bonding pad 42 can be found in the relevant descriptions of some of the aforementioned embodiments and will not be described in detail here.

[0112] It is understood that the test pad 41, the bonding pad 42, and the portion interconnected therebetween can be formed by a conductive layer in the redistribution layer 4, which can be, for example, a single metal layer or a stack of multiple metal layers. In one example, the conductive layer in the redistribution layer 4 is a stack of a titanium (Ti) layer and an aluminum (Al) layer, or a stack of a titanium (Ti) layer, an aluminum (Al) layer, and a titanium (Ti) layer, wherein the thickness of the aluminum layer is greater than the thickness of the titanium layer.

[0113] Based on this, see Figure 12 The method for preparing the semiconductor structure further includes: forming a patterned dielectric layer 6 on the surface of the redistribution layer 4 facing away from the substrate 1, so as to accurately define the shapes of the test pad 41 and the bonding pad 42 by using the pattern of the patterned dielectric layer 6.

[0114] Alternatively, the material of the patterned dielectric layer 6 may be at least one of silicon oxide, silicon nitride, or an organic insulating material. The patterned dielectric layer 6 may be a single thin film layer or a stack of multiple thin films. When the patterned dielectric layer 6 comprises an organic material layer, the patterned dielectric layer 6 may also planarize the surface of the semiconductor structure 100.

[0115] In an example, combine Figure 2 It is understood that the semiconductor structure 100 further includes an adhesion layer 8 located between the redistribution layer 4 and the patterned dielectric layer 6 to enhance the adhesion between the patterned dielectric layer 6 and the redistribution layer 4. Accordingly, forming the patterned dielectric layer 6 on the surface of the redistribution layer 4 facing away from the substrate 1 includes: forming an adhesion material layer and a dielectric material layer in a stacked manner on the surface of the redistribution layer 4 facing away from the substrate 1, and performing a patterning process on the adhesion material layer and the dielectric material layer to obtain the adhesion layer 8 and the patterned dielectric layer 6.

[0116] Optionally, the adhesion material layer includes a titanium nitride material layer. In the case where the conductive layer in the redistribution layer 4 includes a titanium layer, the adhesion material layer can be obtained by nitriding the titanium layer.

[0117] The technical features of the above-mentioned embodiments can be combined arbitrarily. To make the description concise, not all possible combinations of the technical features of the above-mentioned embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0118] The above-described embodiments merely represent several implementation methods of the present application. While the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that a person of ordinary skill in the art may make various modifications and improvements without departing from the spirit of the present application, and these modifications and improvements fall within the scope of protection of the present application. Therefore, the scope of protection of the present patent application shall be determined by the appended claims.

Claims

1. A semiconductor structure, characterized in that include: substrate; a conductive pattern layer, disposed on the substrate; a supporting layer, covering the conductive pattern layer and having a via hole; and a redistribution layer disposed on the support layer; the redistribution layer comprising: a test pad located at least within the via hole; the test pad comprising a plurality of test contact portions and a plurality of recesses disposed alternately and interconnected, wherein the recesses are in contact with a portion of the conductive pattern layer located within the via hole; Wherein, the gap between the tops of two adjacent test contact portions is smaller than the gap between the bottoms of two adjacent test contact portions.

2. The semiconductor structure according to claim 1, wherein: The semiconductor structure further includes: a plurality of spacers located in the via hole; wherein, There is a gap between any two adjacent spacers; The test pad covers the spacer and the gap, the test contact portion is correspondingly located on a surface of the spacer facing away from the substrate, and the recess is correspondingly located in the gap.

3. The semiconductor structure according to claim 2, wherein: The spacers include long strip spacers; a plurality of the long strip spacers are arranged in parallel and spaced apart, and both ends of the long strip spacers along the length direction are respectively connected to the side walls of the via hole; Alternatively, the spacer comprises a block-shaped spacer; The plurality of block-shaped spacers are distributed in an array.

4. The semiconductor structure according to claim 3, wherein: The width of the orthographic projection of the spacer on the substrate has a value range of 6 μm to 10 μm.

5. The semiconductor structure according to claim 1, wherein: The semiconductor structure further includes: a spacer located in the via hole and hollowed out into a grid shape; The test pad covers the spacer, the test contact portion is correspondingly located on a surface of the spacer facing away from the substrate, and the recess is correspondingly located in a hollow area of ​​the spacer.

6. The semiconductor structure according to claim 2 or 5, characterized in that: The surface of the spacer facing away from the substrate is flush with the surface of the support layer facing away from the substrate.

7. The semiconductor structure according to claim 2 or 5, characterized in that: The material of the spacer or the support layer includes at least one of silicon oxide, silicon nitride or an organic insulating material.

8. The semiconductor structure according to claim 1, wherein: The shape of the orthographic projection of the via hole on the substrate includes: rectangle, square, circle or ellipse; The minimum size of the orthographic projection of the via hole on the substrate is greater than or equal to 10 μm.

9. The semiconductor structure according to claim 1, wherein: The maximum size of the orthographic projection of the test pad on the substrate is greater than or equal to 50 μm.

10. The semiconductor structure according to claim 1, wherein: A distance between a surface of the test contact portion facing away from the conductive pattern layer and the conductive pattern layer is greater than or equal to 5 μm.

11. The semiconductor structure according to claim 1, wherein: The redistribution layer further includes a bonding pad coupled to the test pad; an orthographic projection of the bonding pad on the substrate is outside an orthographic projection of the test pad on the substrate.

12. A method for preparing a semiconductor structure, characterized in that: include: providing a substrate, and forming a conductive pattern layer on the substrate; forming a supporting layer on the conductive pattern layer, and forming a via hole in the supporting layer; forming a redistribution layer on the support layer, the redistribution layer including a test pad located at least within the via hole; the test pad including a plurality of test contact portions and a plurality of recesses disposed alternately and interconnected, wherein the recesses are in contact with a portion of the conductive pattern layer located within the via hole; Wherein, the gap between the tops of two adjacent test contact portions is smaller than the gap between the bottoms of two adjacent test contact portions.

13. The method for preparing a semiconductor structure according to claim 12, wherein: Before forming the redistribution layer on the support layer, the preparation method further comprises: forming a plurality of spacers in the via hole; wherein a gap exists between any two adjacent spacers; The forming of the redistribution layer on the supporting layer includes: forming the test contact portion at least on the surface of the spacer facing away from the substrate, and forming the recess in the gap.

14. The method for preparing a semiconductor structure according to claim 13, wherein: The step of forming a plurality of spacers in the via hole comprises: A plurality of long strip spacers are formed in the via hole and arranged in parallel and spaced apart from each other, wherein both ends of the long strip spacers along the length direction are respectively connected to the side walls of the via hole; Alternatively, a plurality of block-shaped spacers distributed in an array are formed in the via hole.

15. The method for preparing a semiconductor structure according to claim 12, wherein: Before forming the redistribution layer on the support layer, the preparation method further comprises: forming a spacer hollowed out into a grid shape in the via hole; The forming of the redistribution layer on the supporting layer includes: forming the test contact portion at least on the surface of the spacer facing away from the substrate, and forming the recess in the hollow area of ​​the spacer.

16. The method for preparing a semiconductor structure according to claim 13 or 15, characterized in that: The via hole and the spacer are formed through a single patterning process.

17. The method for preparing a semiconductor structure according to claim 12, wherein: The forming of a redistribution layer on the supporting layer further comprises: A bonding pad is formed on the support layer, wherein an orthographic projection of the bonding pad on the substrate is outside an orthographic projection of the test pad on the substrate.

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