Power amplifier circuit

Abstract

A power amplifier circuit includes a first input, a first amplification circuit, and a first matching circuit. The first amplification circuit generates a first output signal and a second output signal based on an input signal. The first matching circuit combines the first output signal and the second output signal to generate an output signal. The first input is applied with a first bias voltage. The first amplification circuit includes a first transistor and a second transistor. A first electrode of the first transistor is coupled to the first input, a second electrode of the first transistor is applied with a second bias voltage, and the first transistor generates the first output signal based on the first bias voltage and the second bias voltage. A first electrode of the second transistor is coupled to the first input, a second electrode of the second transistor is applied with a third bias voltage, and the second transistor generates the second output signal based on the first bias voltage and the third bias voltage.

Description

TECHNICAL FIELD

[0001] The present invention relates to an amplifier circuit, and more particularly, to a push-pull common-gate power amplifier circuit. BACKGROUND

[0002] Amplifier circuits are often used in communication systems to increase the output power of a signal. An amplifier circuit generally takes its energy source from a power supply, controls the waveform of the output signal to be consistent with the input signal, and increases its amplitude, thereby generating a larger amplitude signal at the output in proportion.

[0003] Generally speaking, the design of an amplifier circuit needs to make a trade-off between power consumption and linearity. For example, a nonlinear amplifier circuit usually has a higher power amplifier efficiency (abbreviated as PAE), while a linear amplifier circuit usually has a relatively lower power amplifier efficiency.

[0004] Therefore, how to make an amplifier circuit achieve an optimal balance between linearity and amplification efficiency through proper design is an issue worth attention in the field of circuit design. SUMMARY

[0005] One object of the present invention is to provide an amplifier circuit design with good linearity and power amplifier efficiency.

[0006] According to one embodiment of the present invention, a power amplifier circuit includes a first input terminal, a first amplification circuit, and a first matching circuit. The first input terminal is configured to receive an input signal. The first amplification circuit is coupled to the first input terminal and configured to receive the input signal and generate a first output signal at a first terminal and a second output signal at a second terminal according to the input signal. The first matching circuit is coupled to the first amplification circuit and configured to combine the first output signal and the second output signal to generate an output signal. The first input terminal is applied with a first bias voltage, and the first amplification circuit is a push-pull amplification circuit including a first transistor and a second transistor. The first terminal of the first transistor is coupled to the first input terminal, the second terminal is applied with a second bias voltage, and the third terminal is coupled to the first terminal of the first amplification circuit. The first transistor generates the first output signal at the first terminal according to the first bias voltage and the second bias voltage in response to the input signal. The first terminal of the second transistor is coupled to the first input terminal, the second terminal is applied with a third bias voltage, and the third terminal is coupled to the second terminal of the first amplification circuit. The second transistor generates the second output signal at the second terminal according to the first bias voltage and the third bias voltage in response to the input signal.

[0007] According to another embodiment of the present application, a power amplifier circuit includes a first circuit subunit including an input terminal, an amplification circuit, and a matching circuit. The input terminal is configured to receive an input signal. The amplification circuit is coupled to the input terminal and configured to receive the input signal and generate a first output signal at a first terminal and a second output signal at a second terminal in response to the input signal. The matching circuit is coupled to the amplification circuit and configured to combine the first output signal and the second output signal to generate an output signal. The input terminal is applied with a first bias voltage, and the amplification circuit is a push-pull amplification circuit including an NMOS transistor and a PMOS transistor. The first terminal of the NMOS transistor is coupled to the input terminal, the second terminal is applied with a second bias voltage, and the third terminal is coupled to the first terminal of the amplification circuit. The NMOS transistor generates the first output signal at the first terminal in response to the input signal according to the first bias voltage and the second bias voltage. The first terminal of the PMOS transistor is coupled to the input terminal, the second terminal is applied with a third bias voltage, and the third terminal is coupled to the second terminal of the amplification circuit. The PMOS transistor generates the second output signal at the second terminal in response to the input signal according to the first bias voltage and the third bias voltage. BRIEF DESCRIPTION OF DRAWINGS

[0008] Figure 1 An exemplary circuit diagram of a power amplifier circuit according to a first embodiment of the present application is shown.

[0009] Figure 2 An exemplary circuit diagram of a power amplifier circuit according to a second embodiment of the present application is shown.

[0010] Figure 3 A positive phase output signal waveform diagram according to the second embodiment of the present application is shown.

[0011] Figure 4 A negative phase output signal waveform diagram according to the second embodiment of the present application is shown.

[0012] Figure 5 An exemplary circuit diagram of a power amplifier circuit according to a third embodiment of the present application is shown.

[0013] Figure 6 An exemplary circuit diagram of a power amplifier circuit according to a fourth embodiment of the present application is shown. DETAILED DESCRIPTION

[0014] Figure 1An example circuit diagram of a power amplifier circuit according to a first embodiment of the present invention is shown. The power amplifier circuit 100 may include an input terminal IN, an amplifier circuit 110, and a matching circuit 120. The input terminal IN is used to receive an input signal Iin, wherein the input signal Iin may be a current signal. The amplifier circuit 110 is coupled to the input terminal IN, used to receive the input signal Iin, and generates a first output signal Idn at a first terminal N1 of the amplifier circuit 110 and a second output signal Idp at a second terminal N2 of the amplifier circuit 110 based on the input signal Iin. The matching circuit 120 is coupled to the amplifier circuit 110 to match the output impedance of the power amplifier circuit 100 with the impedance of the antenna. According to an embodiment of the present invention, the matching circuit 120 may be further used to combine the first output signal Idn and the second output signal Idp to generate an output signal Io'. The output signal Io' may be further coupled to the antenna terminal via a coupling circuit coupled to the antenna. The coupling effect generates the final output signal Io provided to the antenna.

[0015] According to an embodiment of the present invention, in addition to receiving the input signal Iin, the input terminal IN can be subjected to a first bias voltage V. BIAS_1 (Not shown in the figure), and the amplifier circuit 120 can be subjected to a second bias voltage V. BIAS_2 With the third bias voltage V BIAS_3 By adjusting the first bias voltage V BIAS_1 Second bias voltage V BIAS_2 With the third bias voltage V BIAS_3 Depending on the voltage level, amplifier circuit 110 can be biased into Class A, Class B, or Class C amplification operation. For example, but not limited to, in one embodiment of the invention, by setting the aforementioned voltage level, amplifier circuit 110 can function as a Class B amplifier.

[0016] According to one embodiment of the present invention, the amplifier circuit 110 may be a push-pull amplifier circuit and may include transistors T1 and T2, such as metal-oxide-semiconductor field-effect transistors (MOSFETs). Transistors T1 and T2 may be of different types; for example, in one embodiment of the present invention, transistor T1 is an N-type MOS transistor (NMOS transistor) and transistor T2 is a P-type MOS transistor (PMOS transistor). Transistor T1 includes a first terminal, a second terminal, and a third terminal. The first terminal of transistor T1 is coupled to the input terminal IN, and the second terminal is subjected to a second bias voltage V. BIAS_2 The third terminal is coupled to the first terminal N1 of amplifier circuit 120. Transistor T2 includes a first terminal, a second terminal, and a third terminal. The first terminal of transistor T2 is coupled to the input terminal IN, and the second terminal is subjected to a third bias voltage V.BIAS_3 The third terminal of the transistor T2 is coupled to the second terminal N2 of the amplifier circuit 110.

[0017] In an embodiment of the present application, the first, second and third terminals of the transistors T1 and T2 can be source, gate and drain, respectively. Since the source of the transistor T1 is coupled to the input terminal IN and the gate is biased at a predetermined voltage, the amplifier circuit 120 can be a common gate amplifier circuit. In addition, since the first and second terminals of the transistor T1 are biased at the first bias voltage V BIAS_1 and the second bias voltage V BIAS_2 , respectively, and in an embodiment of the present application, the second bias voltage V BIAS_1 is higher than the first bias voltage V BIAS_3 , the first bias voltage V BIAS_2 is higher than the third bias voltage V BIAS_1 , and the third bias voltage V BIAS_1 is higher than the fourth bias voltage V BIAS_3 , the transistors T2 and T1 can operate in different signal periods, respectively, in the operation of the power amplifier circuit 100.

[0018] Referring to the example waveforms shown in FIG. 1, the input signal Iin can be a single frequency signal having a predetermined frequency, for example, Asin(ωt), where A is the amplitude and ω is the angular frequency corresponding to the predetermined frequency. It is noted that the application of the power amplifier circuit proposed in the present application is not limited to receiving a single frequency signal. For example, the input signal of a practical communication system circuit can be a modulated signal. Figure 1 According to an embodiment of the present application, the transistor T2 can operate in the first half of the signal period in response to the input signal Iin according to the first bias voltage V BIAS_1 and the third bias voltage V BIAS_3 , to generate the second output signal Idp at the second terminal. Similarly, the transistor T1 can operate in the second half of the signal period in response to the input signal Iin according to the first bias voltage V BIAS_1 and the second bias voltage V BIAS_2 , to generate the first output signal Idn at the first terminal. The first output signal Idn and the second output signal Idp can each include a fundamental tone frequency component and even harmonic frequency components of the predetermined frequency, for example, the expansions shown in Equations (1) and (2):

[0019]

[0020]

[0021]

[0022] ​According to an embodiment of the present application, the matching circuit 120 can include a plurality of inductors. For example, the matching circuit 120 can include two inductors coupled in parallel, where a first inductor is coupled between the first terminal Nl and the first output terminal OUTl, and a second inductor is coupled between the second terminal N2 and the second output terminal OUT2. Furthermore, according to an embodiment of the present application, the two inductors can be spread with a capacitor, such as the one or more capacitors shown coupled between the first inductor and the second inductor. With this design, the first output signal Idn and the second output signal Idp can be combined into an output signal Io' by the matching circuit 120, and the alternating current (AC) components in the first output signal Idn and the second output signal Idp can be added together. By the operation of adding, such as shown by the dashed arrow in the figure, the even harmonic frequency components in Equations (1) and (2) can be attenuated, or even eliminated, so that the output signal Io' can have attenuated even harmonic frequency components compared to the output signals Idn and Idp, or can not include even harmonic frequency components as shown in Equation (3).

[0023] Io' = Idp + Idn = A sin(ωt) = Iin Equation (3)

[0024] The output signal Io' can be further coupled to an antenna terminal via a coupling circuit, such as an inductor, coupled to the antenna. Assuming that Nnp represents the number of turns of the inductor coupled to the antenna, and No represents the number of turns of the first / second inductor, the output signal Io provided to the antenna can be represented as Equation (4):

[0025]

[0026] where the even harmonic frequency components have been eliminated, and the output signal Io can be a result of linear amplification of the input signal Iin.

[0027] According to an embodiment of the present application, the matching circuit 120 can receive a supply voltage VDD. As shown, the first output terminal OUTl can be coupled to the supply voltage VDD, and the second output terminal OUT2 can be coupled to ground. The first bias voltage V BIAS_1 may be set to half of the supply voltage VDD, or close to half of the supply voltage. For example, V BIAS_1 = VDD / 2, or slightly increased or decreased from this value. Furthermore, in embodiments of the present application, the second bias voltage V BIAS_2 may be substantially equal to (i.e., equal to or close to) a threshold voltage Vthl of the transistor Tl, such as V BIAS_1 = VDD / 2 + Vthl, or slightly increased or decreased from this value. Similarly, the first bias voltage V BIAS_2 may be substantially equal to (i.e., equal to or close to) a threshold voltage Vth2 of the transistor T2, such as V BIAS_1 = VDD / 2 - Vth2, or slightly increased or decreased from this value.BIAS_1 The third bias voltage V BIAS_3 The voltage difference can be substantially equal to a threshold voltage Vth2 of the transistor T2, for example, V BIAS_3 = VDD / 2 + Vth2, or slightly increased or decreased based on this value.

[0028] In an embodiment of the present application, the cascode amplifier circuit is operated in class B by setting the bias voltage levels, so that the power amplifier circuit 100 can have linear and efficient amplification operation. It is noted that the power amplifier circuit 100 proposed in the present application is not limited to operate in class B. As mentioned above, the amplification circuit 110 can also be biased in class A or class C. For example, in another embodiment of the present application, the third bias voltage V BIAS_3 is higher than the first bias voltage V BIAS_1 , the first bias voltage V BIAS_1 is higher than the second bias voltage V BIAS_2 , so that the amplification circuit 110 is biased in class C. That is, by setting the corresponding voltage levels, the amplification circuit 110 can function as a class C amplifier.

[0029] Furthermore, by the design of the matching circuit 120 as described above, the even harmonic frequency components can be eliminated, so as not to be coupled to the antenna terminal.

[0030] Furthermore, in an embodiment of the present application, by the aforementioned circuit design, the node voltage across of the power amplifier circuit 100 will not exceed the rated supply voltage VDD during operation. For example, as the amplitude of the input signal Iin becomes large, even if the operation of the transistors T1 / T2 enters the triode region, since the third terminal (e.g., drain) and the first terminal (e.g., source) will swing together, the maximum voltage difference (e.g., Vds) between the third terminal and the first terminal of the transistors T1 and T2 will at most reach the size of the voltage VDD, and will not exceed the voltage VDD. That is, the maximum voltage difference Vds can be limited to not exceed the voltage VDD. Therefore, the power amplifier circuit 100 has good reliability.

[0031] In addition, in the embodiments of the present application, the amplification circuit 110 can have a linear voltage swing Vswing, for example, Vswing = Iin * RL, where RL is the load impedance seen from the third terminal of the two transistors, thus the voltage swing Vswing at the third terminal of the transistors Tl and T2 of the power amplifier circuit 100 can exceed half of the supply voltage (e.g., VDD / 2). That is, the voltage swing Vswing is not limited to less than half of the supply voltage as in conventional amplifier circuits, thus the power amplifier circuit 100 has good linearity. In addition, the power gain of the power amplifier circuit 100 is gm * RL, where gm is the transconductance of the transistors, thus the power amplifier circuit 100 also has good power amplification gain.

[0032] In addition, since the parasitic capacitances of the transistors Tl and T2 have complementary characteristics, for example, when the parasitic capacitance Cgs between the second terminal (e.g., gate) and the first terminal (e.g., source) of the transistor N2 increases as the input signal amplitude increases, the parasitic capacitance Cgs of the transistor Nl correspondingly decreases, thus the overall parasitic capacitance variation is small. When the capacitance variation is small, the phase variation of the signal is correspondingly small, thus the power amplifier circuit 100 has good Amplitude Modulation to Phase Modulation (i.e., AM / PM) linearity. The parasitic capacitance Cgd between the second terminal (e.g., gate) and the third terminal (e.g., drain) of the transistors Tl and T2 also has the same characteristics.

[0033] In the first embodiment of the present application, the input signal Iin can be a single-ended signal. Thus, Figure 1 The structure of a single-ended power amplifier circuit is shown. In other embodiments of the present application, the input signal Iin can also be a differential signal, and the power amplifier circuit proposed by the present application can be modified to a differential power amplifier circuit based on the aforementioned single-ended circuit structure, or can be further modified to a circuit structure including multiple stages of differential amplifiers. For example, the input end IN, the amplification circuit 110, and one of the matching circuits 120 of the power amplifier circuit 100 can be regarded as a circuit subunit, and the power amplifier circuit of the present application can include more than one circuit subunit having the same, similar, or symmetrical circuit structure.

[0034] Figure 2 An example circuit diagram of a power amplifier circuit according to the second embodiment of the present application is shown. The power amplifier circuit 200 can include circuit subunits 210 and 220. Among them, the circuit subunit 210 and Figure 1The power amplifier circuit 100 shown can have the same or similar circuit structure, and thus the same parts are not described again. The input end IN1 of the circuit subunit 210 is used to receive the non-inverted part of the input signal, such as the non-inverted input signal Iin+ shown in the figure, and the amplification circuit thereof generates two corresponding non-inverted output signals Io_n+ and Io_p+ at the first end N1 and the second end N2, respectively, according to the non-inverted input signal Iin+, and the matching circuit thereof combines the non-inverted output signals Io_n+ and Io_p+ to generate the non-inverted part of the output signal Io'. Similarly, the input end IN2 of the circuit subunit 220 is used to receive the inverted part of the input signal, such as the inverted input signal Iin- shown in the figure, wherein the non-inverted input signal Iin+ and the inverted input signal Iin- have a phase difference of 180 degrees. The circuit subunit 220 generates two corresponding inverted output signals Io_n- and Io_p- at the third end N3 and the fourth end N4, respectively, according to the inverted input signal Iin- through the amplification circuit thereof, and combines the inverted output signals Io_n- and Io_p- through the matching circuit thereof to generate the inverted part of the output signal Io'.

[0035] The input ends IN1 and IN2 can be coupled to the input center point INC together, and the matching circuit of the circuit subunit 210 and the matching circuit of the circuit subunit 220 can be coupled to the output center point OUTC together, while the circuit subunit 210 and the circuit subunit 220 are coupled in parallel between the input center point INC and the output center point OUTC. In the embodiment of the present application, the circuit subunit 210 and the circuit subunit 220 have symmetrical circuit structures, wherein the same elements can be coupled in the same way in the circuit subunit 210 and the circuit subunit 220, and the circuit subunit 210 and the circuit subunit 220 can be symmetrically coupled between the input center point INC and the output center point OUTC. Therefore, as to the amplification operation and the circuit characteristics of the circuit subunit 210 and the circuit subunit 220, the description of the circuit subunit 200 can be directly referred to, and thus is not described again. Figure 1

[0036] In this embodiment, the output center point OUTC can be coupled to the power supply voltage VDD, and the input ends IN1 and IN2 can be respectively applied with the first bias voltage V BIAS_1 (Not shown in the figure). It should be noted that the first bias voltage V BIAS_1 can also be applied at the input center point INC, and this change does not affect the operation of the power amplifier circuit 200. In addition, it can be understood that the capacitors coupled between the first output end OUT1 and the second output end OUT2 in the circuit subunit 200 can be combined into one capacitor coupled between the output center point OUTC and the ground in the circuit subunit 210. Figure 1 Figure 2

[0037] Figure 3 ​​​A positive phase output signal waveform diagram according to the second embodiment of the present application is shown. Figure 4 A negative phase output signal waveform diagram according to the second embodiment of the present application is shown. The portion with larger amplitude is the fundamental frequency component, and the portion with smaller amplitude is the even order harmonic frequency component, for example, the second harmonic in equation (1) and equation (2) As shown in Figure 3 , the fundamental frequency component of the positive phase output signals Io_n+ and Io_p+ are in phase, and the second harmonic frequency component are in opposite phase, thus, the positive phase portion of the output signal Io' generated by combining the positive phase output signals Io_n+ and Io_p+ can only remain the fundamental frequency component. Similarly, the fundamental frequency component of the negative phase output signals Io_n- and Io_p- are in phase, and the second harmonic frequency component are in opposite phase, thus, the negative phase portion of the output signal Io' generated by combining the negative phase output signals Io_n- and Io_p- can only remain the fundamental frequency component.

[0038] In the first and second embodiments of the present application, the power amplifier circuit only includes one stage of amplifier. In other embodiments of the present application, the power amplifier circuit can include multiple stages of cascade amplifiers.

[0039] Figure 5 An exemplary circuit diagram of a power amplifier circuit according to the third embodiment of the present application is shown. The power amplifier circuit 500 can include a pre-amplifier 510 and two stages of differential amplifiers, which can have a cascade structure coupled in series between the pre-amplifier 510 and the antenna. The first and second stages of differential amplifiers can have the same circuit structure, which can be the same as the power amplifier circuit 200 shown in Figure 2 , for example, the circuit sub-units 210 and 220 can form any stage of differential amplifier, thus, the amplification operation and circuit characteristics of the power amplifier circuit 500 can be directly referred to the description of Figure 1 and Figure 2 , which will not be repeated here.

[0040] In the third embodiment of the present application, the power amplifier circuit only includes one amplification path. In other embodiments of the present application, the power amplifier circuit can include multiple amplification paths arranged in parallel.

[0041] Figure 6An exemplary circuit diagram of a power amplifier circuit according to the fourth embodiment of the present application is shown. In this embodiment, the power amplifier circuit 600 can include two rows of configured amplification paths, in which a preamplifier 610 and two stages of differential amplifiers can be disposed on a first amplification path, and a preamplifier 620 and another two stages of differential amplifiers can be disposed on a second amplification path. That is, the circuit and / or circuit structure disposed on the second amplification path of the power amplifier circuit 600 can be the same as that disposed on the first amplification path. Moreover, the output signals generated on the first amplification path and the output signals generated on the second amplification path can eventually be combined into a merged output signal to further enhance the energy of the output signal. For example, the two output signals can be coupled together to an antenna terminal to generate an output signal eventually provided to an antenna.

[0042] In summary, in the embodiments of the present application, by means of the circuit design and the bias level setting, the power amplifier circuit proposed by the present application can have linear and high-efficiency amplification operation.

[0043] The above merely provides the preferred embodiments of the present application, and any equivalent changes and modifications made within the scope of the claims of the present application shall fall within the scope of the present application.

[0044] [Symbol Description]

[0045] 100, 200, 500, 600: power amplifier circuit

[0046] 110: amplification circuit

[0047] 120: matching circuit

[0048] 210, 220: circuit subunit

[0049] 510: preamplifier

[0050] Iin, Iin+, Iin-: input signal

[0051] Idn, Idp, Io', Io, Io_n+, Io_p+, Io_n-, Io_p-: output signal

[0052] IN, IN1, IN2: input terminal

[0053] INC: input center point

[0054] N1, N2, N3, N4: end point

[0055] OUT1, OUT2: output terminal

[0056] OUTC: output center point

[0057] T1, T2: transistor

[0058] V BIAS_1 , V BIAS_2 , V BIAS_3 : bias voltage

[0059] VDD: voltage

Claims

1. A power amplifier circuit, comprising: a first input terminal to receive an input signal; a first amplification circuit coupled to the first input terminal to receive the input signal and to generate a first output signal at a first terminal and a second output signal at a second terminal in response to the input signal; and a first matching circuit coupled to the first amplification circuit to combine the first output signal and the second output signal to generate an output signal, wherein the first input terminal is applied with a first bias voltage, and the first amplification circuit is a push-pull amplification circuit, comprising: a first transistor including a first terminal coupled to the first input terminal, a second terminal applied with a second bias voltage, and a third terminal coupled to the first terminal of the first amplification circuit, the first transistor generating the first output signal at the first terminal in response to the input signal according to the first bias voltage and the second bias voltage; and a second transistor including a first terminal coupled to the first input terminal, a second terminal applied with a third bias voltage, and a third terminal coupled to the second terminal of the first amplification circuit, the second transistor generating the second output signal at the second terminal in response to the input signal according to the first bias voltage and the third bias voltage.

2. The power amplifier circuit of claim 1, wherein the second bias voltage is higher than the first bias voltage, and the first bias voltage is higher than the third bias voltage.

3. The power amplifier circuit of claim 1, wherein the first transistor is an N-type transistor, the second transistor is a P-type transistor, and the first amplification circuit functions as a class-B amplifier.

4. The power amplifier circuit of claim 1, wherein the input signal is a single-ended signal.

5. The power amplifier circuit of claim 1, wherein the input signal is a differential signal, the first input terminal is to receive a first portion of the input signal, the first matching circuit combines the first output signal and the second output signal to generate a first portion of the output signal, and the power amplifier circuit further comprises: a second input terminal to receive a second portion of the input signal; a second amplification circuit coupled to the second input terminal to receive the second portion of the input signal and to generate a third output signal at a third terminal and a fourth output signal at a fourth terminal in response to the second portion of the input signal; and a second matching circuit coupled to the second amplification circuit to combine the third output signal and the fourth output signal to generate a second portion of the output signal.

6. The power amplifier circuit of claim 5, wherein the first input terminal and the second input terminal are commonly coupled to an input center point, the first matching circuit and the second matching circuit are commonly coupled to an output center point, and the first amplification circuit and the first matching circuit and the second amplification circuit and the second matching circuit are coupled in parallel between the input center point and the output center point.

7. The power amplifier circuit of claim 6, wherein the first input terminal, the second input terminal, the first amplification circuit, the second amplification circuit, the first matching circuit and the second matching circuit form a first differential amplifier, the power amplifier circuit further comprising a second differential amplifier having the same circuit structure as the first differential amplifier, and the first differential amplifier and the second differential amplifier have a cascode structure.

8. The power amplifier circuit of claim 1, wherein the input signal is a single frequency signal having a predetermined frequency, the first output signal and the second output signal each include a fundamental frequency component and an even harmonic frequency component of the predetermined frequency, and the output signal does not include the even harmonic frequency component of the predetermined frequency.

9. The power amplifier circuit of claim 1, wherein the third bias voltage is higher than the first bias voltage, and the first bias voltage is higher than the second bias voltage.

10. A power amplifier circuit, comprising: a first circuit subunit, comprising: an input terminal configured to receive an input signal; an amplification circuit coupled to the input terminal and configured to receive the input signal and generate a first output signal at a first terminal and a second output signal at a second terminal according to the input signal; and a matching circuit coupled to the amplification circuit and configured to combine the first output signal and the second output signal to generate an output signal, wherein the input terminal is applied with a first bias voltage, and the amplification circuit is a push-pull amplification circuit, comprising: a NMOS transistor comprising a first terminal, a second terminal and a third terminal, the first terminal is coupled to the input terminal, the second terminal is applied with a second bias voltage, the third terminal is coupled to the first terminal of the amplification circuit, the NMOS transistor generates the first output signal at the first terminal according to the first bias voltage and the second bias voltage in response to the input signal; and a PMOS transistor comprising a first terminal, a second terminal and a third terminal, the first terminal is coupled to the input terminal, the second terminal is applied with a third bias voltage, the third terminal is coupled to the second terminal of the amplification circuit, the PMOS transistor generates the second output signal at the second terminal according to the first bias voltage and the third bias voltage in response to the input signal.

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