envelope detection

Abstract

Embodiments of the invention relate to envelope detection. In one embodiment, an envelope detection device comprises: an input terminal configured to receive an amplitude modulated radio frequency signal; a first resistive element and a first MOS transistor connected in parallel between the input terminal and a first node configured to receive a reference potential; a first capacitive element connected between a gate of the first MOS transistor and the first node; an envelope detection circuit connected to the input terminal and configured to supply a voltage representative of an envelope of the amplitude modulated signal; and a circuit for controlling the first MOS transistor, the circuit being configured to supply a first current to the gate of the first MOS transistor only when the voltage is less than a first threshold value, and to draw a second current from the gate of the first MOS transistor only when the voltage is higher than a second threshold value, the second threshold value being higher than the first threshold value.

Description

[0001] Cross Reference to Related Applications

[0002] This application claims the benefit of French Application No. 2108777, filed August 19, 2021, which is incorporated herein by reference. TECHNICAL FIELD

[0003] The present disclosure relates generally to electronic circuits, and, more specifically, to a device for detecting the envelope of an amplitude modulated signal. BACKGROUND

[0004] Receivers of amplitude modulated radio frequency signals are known. For example, the radio frequency signal is modulated in OOK (“on-off keying”). For example, the radio frequency signal has a frequency in the range 100 kHz to 10 GHz.

[0005] In order to obtain the data transmitted via the amplitude modulation of the radio frequency signal, these known radio frequency receivers comprise an envelope detection device. The purpose of the envelope detection is to supply a signal representative of the envelope of the amplitude modulated radio frequency signal, which signal is representative of the transmitted data. SUMMARY

[0006] Embodiments provide an envelope detection device. Various embodiments provide an envelope detection device that overcomes all or part of the drawbacks of known envelope detection devices, for example in the case where these envelope detection devices are implemented in a receiver of wireless amplitude modulated radio frequency signals.

[0007] One embodiment provides an envelope detection device comprising:

[0008] an input terminal configured to receive an amplitude modulated radio frequency signal;

[0009] a resistive element and a first MOS transistor connected in parallel between the input terminal and a first node configured to receive a reference potential;

[0010] a first capacitive element connected between the gate of the first MOS transistor and the first node;

[0011] an envelope detection circuit connected to the input terminal and configured to supply a voltage representative of the envelope of the amplitude modulated signal; and

[0012] a circuit for controlling the first MOS transistor configured to:

[0013] - supply a first current to the gate of the first MOS transistor only when the voltage is less than a first threshold; and

[0014] - draw a second current from the gate of the first MOS transistor only when the voltage is higher than a second threshold, the second threshold being higher than the first threshold.

[0015] According to one embodiment, the gain of the envelope detection circuit is equal to K times the square of the signal.

[0016] According to one embodiment, the envelope detection circuit has a negative gain.

[0017] According to one embodiment, the control circuit comprises:

[0018] - a first circuit configured to supply a first current to the gate of the first MOS transistor only when the voltage is less than a first threshold; and

[0019] - a second circuit configured to draw a second current from the gate of the first MOS transistor only when the voltage is higher than a second threshold.

[0020] According to one embodiment, the second circuit is further configured to supply a third current to the gate of the first MOS transistor only when the voltage is less than the second threshold.

[0021] According to one embodiment, the third current is of the same order of magnitude as the second current, for example equal to the second current.

[0022] According to one embodiment, the first current is at least 10 times the second current.

[0023] According to one embodiment, the control circuit further comprises a switch connected in parallel with the first capacitive element.

[0024] According to one embodiment, the first circuit comprises:

[0025] - a first differential pair having a first input configured to receive the voltage and a second input configured to receive the first threshold;

[0026] - a first current source configured to bias the first differential pair; and

[0027] - at least one first current mirror configured to supply the first current from the current flowing through the first differential pair to the gate of the first transistor when the voltage is less than the first threshold, wherein the second circuit comprises:

[0028] - a second differential pair comprising a first input configured to receive the voltage and a second input configured to receive the second threshold;

[0029] - a second current source configured to bias the second differential pair;

[0030] - at least one second current mirror configured to draw the second current from the current flowing through the second differential pair from the gate of the first transistor when the voltage is higher than the second threshold; and

[0031] - at least one third current mirror configured to supply a third current from a current flowing through the second differential pair to the gate of the first transistor when the voltage is less than a second threshold value.

[0032] According to one embodiment, the first circuit comprises:

[0033] - a first differential pair having a first input configured to receive the voltage and a second input configured to receive a first threshold value;

[0034] - a first current source configured to bias the first differential pair; and

[0035] - at least one first current mirror configured to supply a first current from a current flowing through the first differential pair to the gate of the first transistor when the voltage is less than the first threshold value, wherein the second circuit comprises:

[0036] - a second differential pair comprising a first input configured to receive the voltage and a second input configured to receive a second threshold value;

[0037] - a second current source configured to bias the second differential pair; and

[0038] - at least one second current mirror configured to draw a second current from the gate of the first transistor from a current flowing in the second differential pair when the voltage is higher than the second threshold value.

[0039] According to one embodiment, the first current is of the same order of magnitude as the second current, for example equal to the second current.

[0040] According to one embodiment, the envelope detection circuit comprises:

[0041] a MOS transistor having a first conductive terminal coupled to the input terminal;

[0042] a voltage source configured to apply a constant bias voltage to the gate of the MOS transistor of the envelope detection circuit; and

[0043] a capacitive element and a resistive element connected in parallel between the second conductive terminal of the MOS transistor of the envelope detection circuit and a second node configured to receive a supply potential.

[0044] According to one embodiment, the second conductive terminal of the MOS transistor of the detection circuit is coupled, preferably connected, to the output of the envelope detection circuit, the output being configured to deliver a voltage.

[0045] One embodiment provides a wake-up radio frequency receiver comprising a device such as described.

[0046] According to one embodiment, the receiver further comprises:

[0047] the antenna for receiving the radio frequency signal; and

[0048] an impedance matching network coupling the antenna to the input terminal of the envelope detection device. BRIEF DESCRIPTION OF DRAWINGS

[0049] The above features and advantages and other features and advantages will be described in the following description with reference to the drawings, in which:

[0050] Figure 1 One embodiment of a radio frequency receiver is schematically shown;

[0051] Figure 2 One example of an embodiment of a device of the radio frequency receiver of Figure 1

[0052] One example of an embodiment of a device of the radio frequency receiver of Figure 3 Figure 2 One example of an embodiment of a circuit of the device of

[0053] Figure 4 Another example of another embodiment of the device of Figure 2

[0054] One example of an embodiment of a circuit of the device of Figure 5 Figure 2 One example of an embodiment of a circuit of the radio frequency receiver of

[0055] Figure 6 Figure 1 One example of an embodiment of a circuit of the radio frequency receiver of DETAILED DESCRIPTION

[0056] Similar features are marked with similar reference numerals in the various figures. In particular, structural and / or functional features common among the various embodiments can have the same reference numerals and can be arranged as the same structural, dimensional and material properties.

[0057] For the sake of clarity, only steps and elements that are useful in understanding the embodiments described herein are explained and described in detail. In particular, common techniques for recovering data transmitted via an amplitude modulated signal from an envelope of a radio frequency signal are not elaborated on, the described embodiments being compatible with these common techniques.

[0058] Unless otherwise stated, when referring to two elements being connected together, this means a direct connection without any intermediate elements other than a conductor, and when referring to two elements being coupled together, this means that the two elements can be coupled via one or more other elements or they can be connected. ​​​

[0059] In the following disclosure, unless otherwise stated, reference is made to the orientation shown in the figures when reference is made to absolute position qualifiers such as the terms "front", "back", "top", "bottom", "left", "right", or to relative position qualifiers such as the terms "above", "below", "upper", "lower", or to directional qualifiers such as "horizontal", "vertical".

[0060] The expressions "about", "approximately", "substantially" and "around" mean within 10%, preferably within 5%, unless otherwise stated.

[0061] Unless otherwise stated, in the rest of the specification, current is positive. In other words, unless otherwise stated, a circuit drawing current from a node means that the current is positive and flows from the node to the circuit drawing it. Similarly, unless otherwise stated, a circuit supplying current to a node means that the current is positive and flows from the circuit to the node it supplies.

[0062] When a radio frequency receiver receives a radio frequency signal on its antenna, the signal is transmitted through, for example, an impedance matching network and / or a filter to the input of the first stage of the radio frequency receiver, for example, to the input of an envelope detection device.

[0063] The radio frequency signal received by the first stage of the receiver corresponds to an amplitude modulated radio frequency signal, also called useful signal, on which possible interfering radio frequency signals are superimposed. The peak-to-peak amplitude of the useful signal supplied to the input of the first stage can vary greatly, for example, depending on the transmission conditions of the useful signal between the transmitter and the receiver of the useful signal, such as, for example, the distance between the transmitter and the receiver, it can be in the range 2mV to 3.5V.

[0064] In addition, the peak-to-peak amplitude of the interfering signal present on the input of the first stage can be much greater than the amplitude of the useful signal. For example, the power of the interfering signal is up to +30dB greater than the power of the useful signal.

[0065] A method for recovering data transmitted via a useful signal comprises generating a voltage representative of the envelope of the radio frequency signal present on the input of the first stage, that is to say, a voltage whose level varies as a function of the amplitude of the envelope of the radio frequency signal. However, the difference between the high and low levels of the voltage representative of the envelope should be large enough to be able to identify when the voltage is at a low level and when the voltage is at a high level, thus recovering the amplitude modulation of the useful signal and therefore the data transmitted via this useful signal.

[0066] Strong variations of the peak-to-peak amplitude of the wanted signal received by the first stage of the radio receiver and the possible presence of interfering signals cause problems. For example, the peak-to-peak amplitude of the wanted signal can be too high to cause saturation problems and / or the presence of interfering signals can hamper the correct decoding of the wanted signal.

[0067] Moreover, it is generally desirable that these radio frequency receivers consume little power, in particular when they are implemented in embarked applications powered by a battery. This is in particular true for radio frequency receivers called wake-up radio receivers, WuR, which are configured to detect whether a wake-up signal is transmitted on a radio frequency band of interest. Indeed, these wake-up receivers are constantly listening or observing the band of interest while waiting for the wake-up signal.

[0068] Herein is provided an envelope detection device which is particularly low in power consumption. Moreover, the provided envelope detection device implements an automatic gain control, AGC, function. This automatic gain control function enables to supply an envelope signal, that is to say a voltage representative of the envelope of an amplitude modulated radio frequency signal, with sufficiently different high and low levels so as to enable the recovery of data transmitted via the wanted signal while avoiding saturation of this voltage representative of the envelope due to variations of the peak-to-peak amplitude of the wanted signal and / or due to the presence of interfering signals on the input of the envelope detection device.

[0069] The envelope detection device provided herein is in particular suitable for example as a first stage of a radio frequency receiver, that is to say a first active stage of the receiver after an antenna, possibly an impedance matching network and / or a possible band pass filter coupling the antenna to the input of the envelope detection device.

[0070] According to one embodiment, the provided envelope detection device comprises a MOS ("Metal Oxide Semiconductor") transistor (for example with N-channel, NMOS) assembled with a common source on the input of the envelope detection device, and an envelope detection circuit. The automatic gain control function is implemented thanks to the MOS transistor which enables to reduce the power of the signal on the input of the device by drawing current from the input of the device, thereby enabling to avoid saturation of the detection circuit. The control of the gate voltage of the MOS transistor is implemented by a transistor control circuit based on a comparison of the output voltage of the envelope detection circuit with a first threshold value, and of this same voltage with a second threshold value. The results of these two comparisons determine the current that the MOS transistor should draw from the input of the envelope detection device by adapting the control of the MOS transistor accordingly. This enables to set the peak-to-peak amplitude of the signal on the input of the envelope detection device to a value such that the envelope detection circuit is not saturated.

[0071] According to one embodiment, the gain of the envelope detection circuit is equal to K times the square of the average peak-to-peak amplitude of the signal on the input of the envelope detection device. Thus, when the average peak-to-peak amplitude of the useful signal on the input of the device is small, the envelope of the signal on the input of the device is sufficiently amplified for the high and low levels of the output voltage of the detectors which are far enough from each other.

[0072] Figure 1 An embodiment of a radio frequency receiver 1 is schematically illustrated (in Figure 1 partially in Fig. 1), and more particularly an embodiment of an envelope detection device 10 of this receiver 1 is illustrated. Preferably, the receiver 1 is a wake-up radio frequency receiver or an active radio frequency receiver.

[0073] The receiver 1 is a wireless receiver of an amplitude modulated radio frequency signal 2, for example according to OOK modulation.

[0074] The receiver 1 comprises an antenna 3 configured to receive the radio frequency signal 2. In the example of Fig. 1, the antenna is coupled to the input RFin of the device 10 through an optional impedance matching network IMP. In another example not illustrated, a filter associated or not associated with the network IMP is provided between the antenna 3 and the input RFin. The device 10 thus forms a first active stage of the radio frequency receiver 1. Figure 1

[0075] The input RFin of the device 10 is configured to receive an amplitude modulated radio frequency signal Vin. Indeed, when a radio frequency transmitter (not illustrated in Fig. 1) transmits an amplitude modulated radio frequency signal for the receiver 1, a useful signal Vut is present in the signal Vin. In addition, an interference signal Vint received by the antenna 3 can be superimposed with the useful signal Vut in the signal Vin. Thus, the signal Vin is equal to the sum of the useful signal Vut and the interference signal Vint. Figure 1

[0076] The device 10 comprises a resistive element Rl and a MOS transistor Tl connected in parallel between the input terminal RFin and a node 100. The resistive element Rl for example makes it possible to achieve an impedance matching on the input RFin. The MOS transistor has an N channel (NMOS). The node 100 is configured to receive a reference potential GND, for example a ground potential. As an example, the source of the transistor Tl is coupled to, preferably connected to, the node 100, and the drain of the transistor Tl is coupled to, preferably connected to, the terminal RFin.

[0077] The device 10 comprises a capacitive element Cl coupling the gate of the transistor Tl to the node 100. For example, a first electrode of the capacitive element Cl is coupled to, preferably connected to, the node 100, and a second electrode of the capacitive element Cl is coupled to, preferably connected to, the gate of the transistor Tl.

[0078] ​​The device 10 comprises an envelope detection circuit DET. The circuit DET is connected to the terminal RFin. By way of example, the circuit DET comprises an input 104 connected to the terminal RFin. The circuit DET is configured to deliver a voltage Vout representative of the envelope of the signal Vin, that is to say, of the envelope signal Vout. By way of example, the voltage Vout is available on an output 106 of the circuit DET.

[0079] Preferably, the circuit DET is also connected to a node 108 configured to receive a supply potential Vdd, for example positive and referenced to the potential GND. The circuit DET is then associated in series with the parallel of the transistor Tl and the resistive element Rl between the node 108 and 100.

[0080] According to one embodiment, the gain of the circuit DET is proportional to the square of the peak-to-peak amplitude of the signal Vin. In other words, the gain is equal to K*Vin 2 , K being a proportionality coefficient. Thus, even if the average peak-to-peak amplitude of the useful signal Vut is low, for example of the order of 2 mV peak-to-peak, the peak-to-peak amplitude of the voltage Vout is sufficient to be processed by a processing circuit (not shown) of the receiver 1, which is in particular configured to sample the voltage Vout on one bit. Figure 1

[0081] According to one embodiment, the gain of the circuit DET is negative. In other words, in the embodiment where the gain of the circuit DET is equal to K*Vin 2 , the proportionality coefficient K is negative.

[0082] The device 10 also comprises an AGC circuit for controlling the transistor Tl. The AGC circuit and the MOS transistor Tl implement an automatic gain control function based on the comparison of the voltage Vout with two threshold values VtL and VtH. More particularly, depending on the result of the comparison of the voltage Vout with the threshold values VtL and VtH, the AGC circuit controls the transistor Tl to adapt the current I drawn by the transistor Tl from the input RFin, so as to adapt the power of the signal Vin in such a way that the circuit DET does not saturate.

[0083] The AGC circuit is configured to supply a current Il to the gate of the MOS transistor only when the voltage Vout is less than the threshold value VtL Figure 1 ​The current II supplies the gate of the transistor Tl, thus making it possible to avoid saturation of the circuit DET, for example in the case where an interference signal Vint, superimposed on the useful signal Vut of the signal Vin, has a peak-to-peak amplitude greater than the peak-to-peak amplitude of the amplitude-modulated useful signal, for example in the case where the power of the signal Vint is greater than the power of the signal Vut by up to 30 dB.

[0084] The current II supplies the gate of the transistor Tl, thus making it possible to avoid saturation of the circuit DET, for example in the case where an interference signal Vint, superimposed on the useful signal Vut of the signal Vin, has a peak-to-peak amplitude greater than the peak-to-peak amplitude of the amplitude-modulated useful signal, for example in the case where the power of the signal Vint is greater than the power of the signal Vut by up to 30 dB.

[0085] The AGC circuit is also configured to draw the current I2 from the gate of the transistor Tl only when the voltage Vout is higher than the threshold VtH, the threshold VtH being higher than the threshold VtL. This makes it possible for the device 10 to modify the peak-to-peak voltage of the signal Vin, i.e. the power of the signal Vin, to maximize the peak-to-peak amplitude of the voltage Vout without causing saturation of the circuit DET, for example especially in the case where the signal Vin does not comprise an interference signal Vint having a power greater than the power of the useful signal Vut, for example by up to 30 dB. In other words, the AGC circuit is configured to decrease the gate-source voltage of the transistor Tl when the power of the signal Vin is less than a first threshold, by comparing the voltage Vout with the threshold VtH, and more particularly, for example, by detecting that the voltage Vout is higher than the threshold VtH, to implement detection that the power of the signal Vin is less than the first threshold.

[0086] According to one embodiment, in order to modify the power of the signal Vin, the circuit AGC is also configured to supply the current I3 to the gate of the transistor Tl only when the voltage Vout is less than the threshold VtH. According to one embodiment, the current I3 then has the same order of magnitude as the current I2, for example equal to the current I2. In other words, the AGC circuit is configured to increase the gate-source voltage of the transistor Tl when the power of the signal Vin exceeds a first threshold, by comparing the voltage Vout with the threshold VtH, and more particularly, for example, by detecting that the voltage Vout is less than the threshold VtH, to implement detection that the power of the signal Vin exceeds the first threshold.

[0087] Therefore, in the absence of the interfering signal Vint, the power of the signal Vin is maintained at a value determined by the threshold VtH, through the control of the transistor Tl by the currents I2 and I3.

[0088] In such an embodiment, preferably the current II is greater than the current I2, for example at least 10 times the current I2. Therefore, the device 10 reacts quickly to the increase in the peak-to-peak voltage of the signal Vin due to the presence of the interfering signal Vint.

[0089] Preferably, the value of the capacitive element CI is chosen to be sufficiently large for the currents I2 and I3 drawn from and supplied to the gate of the transistor Tl, respectively, so as not to cause a rapid and significant modification of the voltage across the element CI, or, in other words, so that the voltage across the capacitive element CI is substantially constant in the absence of sudden changes in the power of the signal Vin due to the presence of the interfering signal. By way of example, the ratio between the current II and the capacitive value of the element CI, as well as the ratio between the current I3 and the capacitive value of the element CI, are both less than 150.

[0090] In such an embodiment, the discharging of the capacitor CI by the current I2 is longer than the charging of the capacitor CI by the current II, which can cause problems, for example when the signal Vin comprises an interfering signal Vint that suddenly disappears. Preferably, the AGC circuit then comprises a circuit for resetting the voltage across the capacitive element CI. By way of example, the resetting circuit corresponds to a switch connected in parallel to the capacitive element CI. By way of example, the resetting of the voltage across the capacitive element is implemented at the beginning of each new frame emitted by the signal 2 received from the antenna 3 of the receiver 1. By way of example, the beginning of the frame is identified by detecting the switching of the voltage Vout from a substantially constant value (due to the fact that there is no useful signal Vut on the input RFin (no frame)) to a value that switches between a high level and a low level (due to the fact that there is a useful signal Vut on the input RFin (emission of a frame via the signal 2)).

[0091] According to another embodiment, in order to control the power of the signal Vin in the absence of the interfering signal Vint, the AGC circuit is not configured to supply the current I3. In such an embodiment, the currents II and I2 are of the same order of magnitude, preferably equal. Therefore, the voltage on the gate of the transistor Tl remains substantially constant when the voltage Vout is between the thresholds VtH and VtL. The provision of the currents II and I2 of the same order of magnitude makes it possible to have a symmetrical behaviour with respect to the charging and discharging rate of the capacitive element CI, and therefore with respect to the presence and disappearance of the interfering signal Vint. In this case, the AGC circuit can not comprise a circuit for resetting the voltage across the capacitive element CI.

[0092] Based on about Figure 1 The provided functional instructions, the implementation of device 1, and especially the implementation of circuits DET and AGC, are within the capabilities of those skilled in the art.

[0093] Figure 2 Showing more details Figure 1 An example of an embodiment of the AGC circuit of device 10.

[0094] The AGC circuit includes an input 200 and an output 202. The input 200 is configured to receive a voltage Vout, and the output 202 is coupled to, and preferably connected to, a voltage Vout. Figure 1 The gate of transistor T1 in device 10.

[0095] exist Figure 2 In an example of an embodiment, the AGC circuit includes circuit 206 and circuit 208.

[0096] Circuit 206 is configured to supply current Il to output 202 only when voltage Vout is less than threshold VtL, and therefore to transistor Tl. Figure 1 ) gate.

[0097] As an example, circuit 206 includes an input configured to receive a voltage Vout, an input configured to receive a threshold VtL, and an output coupled to, and preferably connected to, output 202. The output of circuit 206 is configured to supply current I1 to output 202 only when the voltage Vout is less than the threshold VtL.

[0098] Circuit 208 is configured to draw current I2 from output 202 only when voltage Vout is higher than threshold VtH, and therefore from Figure 1 The gate of transistor T1 draws current I2.

[0099] As an example, circuit 208 includes an input configured to receive a voltage Vout, an input configured to receive a threshold VtH, and an output coupled to, and preferably connected to, output 202. The output of circuit 208 is configured to draw current I2 from output 202 only when the voltage Vout is higher than the threshold VtH.

[0100] According to one embodiment, such as Figure 2 As illustrated, the AGC circuit is also configured to supply current I3 only when the voltage Vout is less than the threshold VtH. As an example, circuit 208, or in other words, the output of circuit 208, is therefore also configured to supply current I3 at output 202 only when the voltage Vout is less than the threshold VtH.

[0101] Moreover, according to the embodiment in which the AGC circuit is configured to supply the current I3 only when the voltage Vout is lower than the threshold VtH, the AGC circuit comprises a circuit RST for resetting the voltage across the capacitive element CI, for example a switch RST connected between the output 202 and a node 100 at a potential GND. Figure 1

[0102] In another embodiment, not illustrated, in which the AGC circuit does not supply the current I3, therefore the circuit 208 is configured to not supply a current to the output 202 or to draw a current from the output 202 when the voltage Vout is lower than the threshold VtH. Preferably, therefore, the AGC circuit does not comprise the circuit RST.

[0103] Based on the functional description of these circuits made with respect to Figure 2 The implementation of the circuits 206 and 208 is within the capabilities of a person skilled in the art, based on the functional description of these circuits made with respect to

[0104] Figure 3 An example of an implementation of the circuits 206 and 208 based on a current source, on a switch and on a comparator controlling the switch is illustrated.

[0105] In this example, the circuit 206 comprises a current source 300 supplying a current II, a switch 302 coupling the current source 300 to the output of the circuit 206, and a comparator 304 configured to deliver a binary signal 306 for controlling the switch 302. The binary state of the signal 306 depends on the result of the comparison of the signal Vout with the threshold VtL. The comparator 304 is configured to turn on the switch 302 when the voltage Vout is lower than the threshold VtL, and to turn it off otherwise.

[0106] In this example, the circuit 208 comprises a current source 308 drawing a current I2, a switch 310 coupling the current source 308 to the output of the circuit 208, and a comparator 312 configured to deliver a binary signal 314 for controlling the switch 310. The binary state of the signal 314 depends on the result of the comparison of the signal Vout with the threshold VtH. The comparator 312 is configured to turn on the switch 310 when the voltage Vout is higher than the threshold VtH, and to turn it off otherwise.

[0107] ​In this example, the circuit 208 is further configured to supply the current I3 to the output 202 only when the voltage Vout is less than the threshold VtH. To this end, the circuit 208 further comprises a current source 316 configured to supply the current I3 and a switch 318 coupling the current source 316 to the output of the circuit 208. The switch 318 is controlled by the signal 314. The comparator 312 is configured to turn on the switch 318 in case the voltage Vout is less than the threshold VtH, and to turn it off otherwise.

[0108] In another example, not illustrated, the circuit 208 does not supply or sink any current when the voltage Vout is less than the threshold VtH. In this case, the elements 316 and 318 can be omitted.

[0109] The skilled person is able to implement other examples of the circuits 206 and 208 based on a current source selectively coupled to the output of the circuit through a switch controlled by the output signal of a comparator comparing the voltage Vout to the thresholds VtL and VtH.

[0110] Figure 4 Further details are shown with respect to Figure 2 An example of another embodiment of the circuits 206 and 208 of the described AGC circuit. Figure 4 The embodiment of corresponds to the case where the AGC circuit is configured to supply the current I3 in case the voltage Vout is less than the voltage VtH.

[0111] In this example of the embodiment, the circuit 206 comprises a differential pair Diffl, a current source Sl for biasing the differential pair Diffl with a current I1', and at least one current mirror Mirrorl.

[0112] The differential pair Diffl is configured to implement the comparison of the voltage Vout to the threshold VtL. For example, the differential pair Diff1 has an input configured to receive the threshold VtL and an input configured to receive the voltage Vout. More specifically, the differential pair Diff1 is configured such that when the voltage Vout is less than the threshold VtL, the current I1' flows through a first branch of the differential pair Diff1, and when the voltage Vout is higher than the threshold VtL, the current I1' flows through a second branch of the differential pair, it being understood that, as known in differential pairs, when the voltage Vout is very close to or equal to the threshold VtL, a part of the current I1' flows through the second branch.

[0113] The current mirror(s) Mirrorl is configured to supply a current II from the current flowing through one branch of the differential pair Diffi, in this example, from the current flowing through the first branch of the differential pair Diffi. More specifically, the current mirror(s) Mirrorl is configured to supply a current II at the output of the circuit 206, and thus at the output 202 of the AGC circuit. Thus, when the voltage Vout is less than the threshold VtL, for example substantially less than the threshold VtL, the current in the first branch of the differential pair Diffi is equal to the current II', and the current II supplied by the current mirror(s) Mirrorl is a multiple of the current II', and when the voltage Vout is higher than the threshold VtL, the current in the first branch of the differential pair Diffi is zero, and the current II supplied by the current mirror(s) Mirrorl is zero, or in other words, the circuit 206 does not supply a current II.

[0114] As an example, in Figure 4 the current source SI is connected between the node 400 and the node 108, which is at the potential Vdd in this example. In Figure 4 the example, the first branch of the differential pair Diffi comprises a MOS transistor 402, which has a P-channel (PMOS) in this example, with a source connected to the node 400 and a gate configured to receive the voltage Vout, and the second branch of the differential pair Diffi comprises a MOS transistor 404, which has a P-channel in this example, with a source connected to the node 400 and a gate configured to receive the voltage or threshold VtL. In this example, the drains of the transistors 402 and 404 are coupled to the node 100, which is at the potential GND. In this example, the circuit 206 comprises two current mirrors Mirrorl, respectively with Figure 4The drain of transistor 402 is coupled to node 100 through MOS transistor 406 of current mirror Mirror 11, which also includes MOS transistor 408 mirror assembled with transistor 406. As an example, transistors 406 and 408 have N-channel. Current mirror Mirror 12 includes MOS transistor 410 in series with transistor 408 between nodes 108 and 100, transistors 408 and 410 being on opposite sides of nodes 100 and 108, respectively. Current mirror Mirror 12 includes MOS transistor 412 mirror assembled with transistor 410 and configured to supply current II on the output of circuit 206, and thus on output 202 of the AGC circuit, transistor 412 being connected between node 108 and output 202, for example. As an example, transistors 410 and 412 have P-channel. As an example, the drain of transistor 404 is coupled to node 100 through MOS transistor 414 diode assembled, for example, with N-channel.

[0115] In Figure 4 In an example of an embodiment of circuit 208, circuit 208 includes differential pair Diff2, current source S2 for biasing differential pair Diff2 with current I23', at least one current mirror Mirror2 and at least one current mirror Mirror3.

[0116] Differential pair Diff2 is configured to implement a comparison of voltage Vout with threshold VtH. For example, differential pair Diff2 has an input configured to receive threshold VtH and an input configured to receive voltage Vout. More specifically, differential pair Diff2 is configured so that when voltage Vout is less than threshold VtH, current I23' flows through a first branch of differential pair Diff2, and when voltage Vout is higher than threshold VtH, current I23' flows through a second branch of differential pair Diff2, it being understood that, as is known in differential pairs, when voltage Vout is very close to or equal to threshold VtH, a part of current I23' flows through the first branch and another part of current I23' flows through the second branch.

[0117] One or more current mirrors Mirror2 are configured to draw current I2 from the current flowing through one branch of the differential pair Diff2; in this example, they draw current I2 from the current flowing through the first branch of the differential pair Diff2. More specifically, one or more current mirrors Mirror2 are configured to draw current I2 from the output of circuit 208, and therefore from the output 202 of the AGC circuit, which is itself connected to the gate of transistor T1. Thus, when the voltage Vout is above the threshold VtH, the current in the second branch of the differential pair Diff2 is equal to the current I23', and the current I2 drawn by one or more current mirrors Mirror2 is a multiple of the current I23'. Conversely, when the voltage Vout is less than the threshold VtH, the current in the second branch of the differential pair Diff2 is zero, and the current I2 drawn by one or more current mirrors Mirror2 is zero, or in other words, circuit 208 does not draw current I2.

[0118] One or more current mirrors Mirror3 are configured to supply current I3 from the current flowing through one branch of the differential pair Diff2, in this example, from the current flowing through the first branch of the differential pair Diff2. More specifically, one or more current mirrors Mirror3 are configured to supply current I3 to the output of circuit 208, and thus to the output 202 of the AGC circuit, which is itself connected to the gate of transistor T1. Therefore, when the voltage Vout is less than the threshold VtH, the current in the first branch of the differential pair Diff2 is equal to the current I23', and the current I3 supplied by one or more current mirrors Mirror3 is a multiple of the current I23'. Conversely, when the voltage Vout is greater than the threshold VtH, the current in the first branch of the differential pair Diff2 is zero, and the current I3 supplied by one or more current mirrors Mirror3 is zero, or in other words, circuit 208 does not supply current I3.

[0119] As an example, in Figure 4 In this example, current source S2 is connected between node 420 and node 108, which is at potential Vdd. Figure 4 In this example, the first branch of the differential pair Diff2 includes a MOS transistor 422, which in this example has a P-channel, a source connected to node 420, and a gate configured to receive a voltage Vout. The second branch of the differential pair Diff2 includes a MOS transistor 424, which in this example has a P-channel, a source connected to node 420, and a gate configured to receive a voltage or threshold voltage VtH. In this example, the drains of transistors 422 and 424 are coupled to node 100 at potential GND. In this example, circuit 208 includes a current mirror Mirror3, which has...Figure 4 the output 202 of the AGC circuit, the transistor 432 being connected for example between the node 108 and the output 202. As an example, the transistors 430 and 432 have a P-channel. As an example, the drain of the transistor 242 is coupled to the node 100 through a MOS transistor 440 of a current mirror Mirror 2. The current mirror Mirror 2 comprises a MOS transistor 442 mirror assembled with the transistor 440 and is configured to draw a current I2 from the output of the circuit 208, and thus from the output 202 of the AGC circuit, the transistor 442 being connected for example between the node 100 and the output 202. As an example, the transistors 440 and 442 have an N-channel.

[0120] Although in the example of Figure 4 the current source S1 of the circuit 206 is connected between the node 108 and 400 and the transistors 402 and 404 have a P-channel, it is within the capabilities of a person skilled in the art to implement the circuit 206 in the case where the current source S1 is connected between the node 100 and 400 and the transistors 402 and 404 have an N-channel and their drains are coupled to the node 108. More specifically, in this case, the first branch of the differential pair Diff1 comprises the transistor 404 and the second branch of the differential pair Diff1 comprises the transistor 402. Moreover, the drain of the transistor 404 is thus coupled to the node 108 through the current mirror(s) Mirror 1 which are modified accordingly to supply the current I1 from the current in the first branch of the differential pair when the voltage Vout is less than the threshold VtL, in particular by providing that the drain of the transistor 404 is coupled to the node 108 through a MOS transistor of the current mirror Mirror 1 and for this no longer be the case of the transistor 402.

[0121] Although in the example of Figure 4In the example, the current source S2 of circuit 208 is connected between nodes 108 and 420, and transistors 422 and 424 have P-channels. However, in the case where the current source S2 is connected between nodes 100 and 420, and transistors 422 and 424 have N-channels and their drains are coupled to node 108, the implementation of circuit 208 is within the capabilities of those skilled in the art. More specifically, in this case, the first branch of differential pair Diff2 includes transistor 424, and the second branch of differential pair Diff2 includes transistor 422. In this configuration, the drain of transistor 424 is coupled to node 108 via one or more current mirrors Mirror3, which are correspondingly modified to supply current I3 from the first branch of the differential pair Diff2 when the voltage Vout is less than the threshold VtH, and the drain of transistor 422 is coupled to node 108 via one or more current mirrors Mirror2, which are correspondingly modified to draw current I2 from the second branch of the differential pair Diff2 when the voltage Vout is greater than the threshold VtH.

[0122] Figure 5 More details are shown about Figure 2 An example of yet another embodiment of circuits 206 and 208 of the described ACG circuit. Only emphasis is given here. Figure 4 and Figure 5 The differences between them.

[0123] Figure 5 The embodiment corresponds to the case where the AGC circuit is configured not to supply current I3 when the voltage Vout is less than the threshold VtH.

[0124] therefore, Figure 5 Circuit 208 does not include the current mirror Mirror3. In Figure 5 In the example, the drain of transistor 422 is coupled to node 100 via a diode-assembled MOS transistor 450.

[0125] also, Figure 5 The AGC circuit does not have a switch RST.

[0126] Regarding Figure 4 Similar to what is shown, based on Figure 5 Examples of circuits 206 and 208 illustrated herein, implemented when current source S1 is connected between nodes 100 and 420 and transistors 422 and 424 have N-channels, and / or when current source S2 is connected between nodes 100 and 400 and transistors 402 and 404 have N-channels, will be within the capabilities of those skilled in the art.

[0127] Figure 6 Fig. illustrates about Figure 1 An example of an embodiment of the circuit DET is described.

[0128] In Figure 6 The circuit DET comprises a MOS transistor T2, a voltage source VI and a filter Fl.

[0129] The transistor T2, for example with N-channel, has a first conductive terminal, for example its source, coupled to, preferably connected to, an input terminal 104 of the circuit DET, and thus to an input terminal RFin of the device 10. Figure 1 A second conductive terminal of the transistor T2, for example its drain, configured to deliver a voltage Vout, is coupled to, preferably connected to, an output 106 of the circuit DET, and further, through the filter Fl, to a node 108.

[0130] The voltage source VI is configured to deliver a constant voltage Vbias to the gate of the transistor T2. For example, the voltage source VI has a first terminal coupled to, preferably connected to, the gate of the transistor T2, and a second terminal coupled to, preferably connected to, the node 100 configured to receive the potential GND.

[0131] The filter Fl couples the output 106 to the node 108 configured to receive the potential Vdd, or in other words, the filter Fl couples the second conductive terminal of the transistor T2 to the node 108. The filter Fl is a low-pass filter configured to suppress high frequencies and to retain only low frequencies, i.e. the envelope of the useful signal.

[0132] In Figure 6 An example, the filter Fl comprises a capacitive element C2 in parallel with a resistive element R2 between the output 106 and the node 108.

[0133] Various embodiments and variants have been described. The person skilled in the art will understand that certain features of these different embodiments and variants can be combined, and will think of other variants.

[0134] In particular, although examples of embodiments of the device 10, of the AGC circuit and of the circuits 206 and 208 have been described when the potential Vdd is positive with respect to the potential GND, it will be within the capabilities of the person skilled in the art to adapt these examples of embodiments to the case where the potential Vdd is negative, by replacing the NMOS transistors T1 with PMOS transistors, more generally by replacing all the NMOS and PMOS transistors with PMOS and NMOS transistors, respectively.

[0135] Finally, actual implementation of the described embodiments and variations is within the ability of one skilled in the art based on the functional indications given above. In particular, other implementation examples of the circuits AGC, DET, 206, 208, 210, and 212 are within the ability of one skilled in the art beyond those described by way of example with respect to Figure 2 , Figure 3 , Figure 4 , Figure 5 and Figure 6 .

[0136] While the application has been described with reference to illustrative embodiments, the description is not intended to be construed in a limiting sense. Various modifications and combinations of the illustrative embodiments, as well as other embodiments of the application, will be apparent to persons skilled in the art upon reference to the description. It is therefore intended that the appended claims encompass any such modifications or embodiments.

Claims

1. An envelope detection device, comprising: an input terminal configured to receive an amplitude modulated radio frequency signal; a first resistive element and a first MOS transistor connected in parallel between the input terminal and a first node configured to receive a reference potential; a first capacitive element connected between a gate of the first MOS transistor and the first node; an envelope detection circuit connected to the input terminal and configured to supply a voltage representative of an envelope of the amplitude modulated radio frequency signal; and a control circuit for controlling the first MOS transistor, the control circuit being configured to: supply a first current to the gate of the first MOS transistor only when the voltage is less than a first threshold value; and draw a second current from the gate of the first MOS transistor only when the voltage is higher than a second threshold value, the second threshold value being higher than the first threshold value.

2. The device of claim 1, wherein a gain of the envelope detection circuit is equal to K times a square of the amplitude modulated radio frequency signal.

3. The device of claim 1, wherein the envelope detection circuit has a negative gain.

4. The device of claim 1, wherein the control circuit comprises: a first circuit configured to supply the first current to the gate of the first MOS transistor only when the voltage is less than the first threshold value; and a second circuit configured to draw the second current from the gate of the first MOS transistor only when the voltage is higher than the second threshold value.

5. The device of claim 4, wherein the second circuit is further configured to supply a third current to the gate of the first MOS transistor only when the voltage is less than the second threshold value.

6. The device of claim 5, wherein the third current is of the same order of magnitude as the second current.

7. The device of claim 6, wherein the third current is equal to the second current.

8. The device of claim 5, wherein the first current is at least 10 times the second current.

9. The device of claim 5, wherein the control circuit further comprises a switch connected in parallel with the first capacitive element.

10. The device of claim 5, wherein the first circuit comprises: a first differential pair having a first input configured to receive the voltage and a second input configured to receive the first threshold value; a first current source configured to bias the first differential pair; and at least one first current mirror configured to supply the first current from a current flowing through the first differential pair to the gate of the first MOS transistor when the voltage is less than the first threshold value.

11. The device of claim 10, wherein the second circuit comprises: a second differential pair including a first input configured to receive the voltage and a second input configured to receive the second threshold value; a second current source configured to bias the second differential pair; and at least one second current mirror configured to draw the second current from the gate of the first MOS transistor when the voltage is higher than the second threshold value. ​ ​ ​ ​ at least one second current mirror configured to draw the second current from the gate of the first MOS transistor from a current flowing through the second differential pair when the voltage is above the second threshold.

12. The apparatus of claim 11, wherein the second circuit comprises: at least one third current mirror configured to supply the third current to the gate of the first MOS transistor from a current flowing through the second differential pair when the voltage is below the second threshold.

13. The apparatus of claim 4, wherein the first circuit comprises: a first differential pair having a first input configured to receive the voltage and a second input configured to receive the first threshold; a first current source configured to bias the first differential pair; and at least one first current mirror configured to supply the first current to the gate of the first MOS transistor from a current flowing through the first differential pair when the voltage is below the first threshold.

14. The apparatus of claim 13, wherein the second circuit comprises: a second differential pair comprising a first input configured to receive the voltage and a second input configured to receive the second threshold, a second current source configured to bias the second differential pair; and at least one second current mirror configured to draw the second current from the gate of the first MOS transistor from a current flowing through the second differential pair when the voltage is above the second threshold.

15. The apparatus of claim 4, wherein the first current and the second current are of the same order of magnitude.

16. The apparatus of claim 15, wherein the first current is equal to the second current.

17. The apparatus of claim 1, wherein the envelope detection circuit comprises: a second MOS transistor having a first conductive terminal coupled to the input terminal; a voltage source configured to apply a constant bias voltage to a gate of the second MOS transistor of the envelope detection circuit; and a second capacitive element and a second resistive element connected in parallel between a second conductive terminal of the second MOS transistor of the envelope detection circuit and a second node configured to receive a supply potential.

18. The apparatus of claim 17, wherein the second conductive terminal of the second MOS transistor of the detection apparatus is connected to an output of the envelope detection circuit, the output configured to supply the voltage.

19. A wake-up radio frequency receiver, comprising: the apparatus of claim 1.

20. The wake-up radio frequency receiver of claim 19, further comprising: an antenna for receiving a radio frequency signal; and an impedance matching network coupling the antenna to the input terminal of the envelope detection apparatus.

21. The wake-up radio frequency receiver of claim 20, wherein the envelope detection apparatus is configured to supply the voltage to a control input of a radio frequency receiver.

22. The wake-up radio frequency receiver of claim 21, wherein the radio frequency receiver comprises: a radio frequency amplifier having an input configured to receive the radio frequency signal and an output configured to supply an amplified radio frequency signal; a mixer having a first input configured to receive the amplified radio frequency signal and a second input configured to receive a local oscillator signal; a low pass filter having an input coupled to an output of the mixer and an output configured to supply a baseband signal; and a baseband amplifier having an input coupled to the output of the low pass filter and an output configured to supply a digital signal.

23. The wake-up radio frequency receiver of claim 22, wherein the envelope detection apparatus is configured to supply the voltage to the control input of the radio frequency receiver.

24. The wake-up radio frequency receiver of claim 23, wherein the envelope detection apparatus is configured to supply the voltage to the control input of the radio frequency receiver when the envelope detection apparatus detects a presence of the radio frequency signal in the input terminal of the envelope detection apparatus.

25. The wake-up radio frequency receiver of claim 24, wherein the envelope detection apparatus is configured to supply the voltage to the control input of the radio frequency receiver when the envelope detection apparatus detects a presence of the radio frequency signal in the input terminal of the envelope detection apparatus and the envelope detection apparatus detects a presence of the local oscillator signal in the input terminal of the envelope detection apparatus.

26. The wake-up radio frequency receiver of claim 25, wherein the envelope detection apparatus is configured to supply the voltage to the control input of the radio frequency receiver when the envelope detection apparatus detects a presence of the radio frequency signal in the input terminal of the envelope detection apparatus, the envelope detection apparatus detects a presence of the local oscillator signal in the input terminal of the envelope detection apparatus, and the envelope detection apparatus detects a presence of the digital signal in the input terminal of the envelope detection apparatus.

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