Current load circuit for testing power supply circuit and chip

Abstract

A current load circuit and a chip for testing a power supply circuit are disclosed. The current load circuit includes a control circuit and a load generation circuit. The control circuit is configured to generate a reset signal according to a clock signal. The load generation circuit is coupled to the control circuit and has a plurality of load configurations. The load generation circuit is configured to alternately provide one of the plurality of load configurations as a current load of the load generation circuit according to the clock signal and the reset signal, and receive a first portion of a supply current provided by the power supply circuit according to the current load to output an indication signal for indicating a performance of the power supply circuit.

Description

TECHNICAL FIELD

[0001] The present invention relates to a circuit and a chip, and more particularly, to a circuit and a chip for testing a power supply circuit. BACKGROUND

[0002] In electronic devices, the performance of a power supply circuit has a significant impact on the performance of the electronic devices. However, the performance of the power supply circuit is difficult to be effectively simulated and tested before the power supply circuit is installed into the electronic devices. If the performance of the power supply circuit is not sufficient to make the electronic devices operate normally, the electronic devices may face the cost of time and money for debugging or redesign. Therefore, how to effectively test the performance of the power supply circuit has become a problem to be solved in the art. SUMMARY

[0003] The present invention discloses a current load circuit for testing a power supply circuit, comprising a control circuit and a load generation circuit. The control circuit is used to generate a reset signal according to a clock signal. The load generation circuit is coupled to the control circuit and has a plurality of load configurations. The load generation circuit is used to alternately provide one of the plurality of load configurations as a current load of the load generation circuit according to the clock signal and the reset signal, and receive a first portion of supply current provided by the power supply circuit according to the current load, so as to output an indication signal for indicating the performance of the power supply circuit.

[0004] The present invention discloses a current load circuit for testing a power supply circuit, comprising a first load generation circuit, a second load generation circuit and a control circuit. The first load generation circuit has a plurality of first load configurations, and is used to alternately switch one of the plurality of first load configurations according to a clock signal to receive a first portion of supply current provided by the power supply circuit and output a first indication signal for indicating the performance of the power supply circuit during startup. The second load generation circuit has a plurality of second load configurations, and is used to alternately switch one of the plurality of second load configurations according to a clock period of the clock signal to receive a second portion of supply current provided by the power supply circuit and output a second indication signal for indicating the performance of the power supply circuit during startup. The control circuit is used to determine the time interval of the startup of the first load generation circuit and the second load generation circuit according to the clock signal.

[0005] A chip for testing a power supply circuit includes a phase-locked loop and a current load circuit. The phase-locked loop is coupled to the power supply circuit to generate a clock signal. The current load circuit is coupled to the power supply circuit. The current load circuit includes a load generation circuit. The load generation circuit is configured to alternately provide one of a plurality of load configurations as a current load of the load generation circuit in response to the clock signal and a reset signal. The current load circuit outputs an indication signal indicative of a performance of the power supply circuit in response to the current load and a supply current received from the power supply circuit.

[0006] The current load circuit and the chip of the present disclosure combine different current load configurations to generate a load circuit capable of generating a step current and a random current, thereby testing the performance of the power supply circuit. BRIEF DESCRIPTION OF DRAWINGS

[0007] Various embodiments of the application are described herein with reference to the following figures. It should be noted that the figures can not be drawn to scale. In fact, the dimensions of some of the elements can be exaggerated relative to other elements for the purposes of explanation. Furthermore, the same reference numerals are used in different figures to denote the same or similar parts.

[0008] Figure 1 A schematic diagram of a chip according to some embodiments of the present disclosure.

[0009] Figure 2 A schematic diagram of a current load circuit according to some embodiments of the present disclosure.

[0010] Figure 3 A schematic diagram of a control circuit according to some embodiments of the present disclosure.

[0011] Figure 4 A schematic diagram of a chip according to other embodiments of the present disclosure.

[0012] Figure 5 A waveform diagram of a supply current according to other embodiments of the present disclosure. DETAILED DESCRIPTION

[0013] Figure 1 A schematic diagram of a chip 10 according to some embodiments of the present disclosure. The chip 10 uses a current load circuit 200 to test a device under test (DUT) 100 and generates an indication signal Si indicative of a performance of the DUT 100 in providing a supply current I. In some embodiments, the DUT 100 is a power supply circuit. In further embodiments, the DUT 100 is a low-dropout regulator (LDO). As shown in FIG. 1, the chip 10 includes a phase-locked loop (PLL) 100, a current load circuit 200, and a control circuit 300. Figure 1As shown, DUT 100 is mounted on chip 10, and the supply current I is transmitted to the current load circuit 200 through chip 10 itself, rather than through other packages or printed circuit boards. Therefore, the supply current I transmitted from DUT 100 to the current load circuit 200 has smaller parasitic resistance, parasitic capacitance, and / or parasitic inductance, resulting in less interference in the supply current I received by the current load circuit 200, thereby improving the accuracy of the current load circuit 200 in testing DUT 100.

[0014] Chip 10 also includes a phase-locked loop 300 and a control interface 400. The phase-locked loop 300 is powered by the supply current I0 provided by DUT 100 and is used to generate a clock signal CLK, which is transmitted to the current load circuit 200 for its use. The control interface 400 is used to receive an indication signal Si and provide a reset signal Sr0. In some embodiments, the control interface 400 is used to transmit the indication signal Si to a display (…). Figure 1 (No illustration) The display shows the performance of the DUT 100 in providing the supply current I to the outside. For example, the indicator signal Si can indicate whether the DUT 100 has passed a performance test. This performance test can test (but is not limited to) whether the supply current I provided by the DUT 100 meets a predetermined performance specification, such as whether the supply current I can be maintained within a predetermined range. When the indicator signal Si indicates that the DUT 100 has passed the performance test, the display can show that the performance of the DUT 100 in providing the supply current I meets the predetermined performance specification. When the indicator signal Si indicates that the DUT 100 has failed the performance test, the display can show that the performance of the DUT 100 in providing the supply current I does not meet the predetermined performance specification. In some embodiments, the control interface 400 is used to receive external commands to manipulate the reset signal Sr0 and transmit the reset signal Sr0 to the current load circuit 200, the details of which will be described later.

[0015] The current load circuit 200 has different current loads and switches between them according to the clock signal CLK and the reset signal Sr0. Corresponding to different current loads, the current load circuit 200 can draw different amounts of supply current I from the DUT 100. Based on the supply current I supplied by the DUT 100, the current load circuit 200 generates an indication signal Si to indicate the performance of the DUT 100 in providing the supply current I.

[0016] For example, the current load circuit 200 can gradually (e.g., by approximately the same value each time) increase the current load from 0 to a certain value within a time interval; by adjusting the time interval, the current load circuit 200 can change the slew rate of the DUT 100 to provide the supply current I. Or for another example, the current load circuit 200 can randomly switch between different current loads to simulate a situation in which other electronic devices (e.g., a central processing unit) draw the supply current I; thereby the ability of the DUT 100 to randomly provide the supply current I can be observed.

[0017] The current load circuit 200 includes a load generation circuit 210 and a control circuit 220. The control circuit 220 generates a reset signal Sr1 according to a clock signal CLK and a reset signal Sr0. The load generation circuit 210 has a plurality of load configurations, which are turned on and off by the reset signal Sr1, and are used to alternately provide one of the load configurations as a current load of the load generation circuit 210 according to the clock signal CLK. For example, the load configurations can be alternately provided as the current load of the load generation circuit 210. When the clock signal CLK is at a signal level, one of the load configurations can be provided as the current load of the load generation circuit 210. When the clock signal CLK is at another signal level, another one of the load configurations can be provided as the current load of the load generation circuit 210. In addition, the load generation circuit 210 receives the supply current I according to the current load to output an indication signal Si.

[0018] Reference Figure 2 . Figure 2 A schematic diagram of the load generation circuit 210 is shown in FIG. 2. The load generation circuit 210 includes a flip-flop FF1, a flip-flop FF2, a flip-flop FF3, an inverter serial IN1, an inverter serial IN2, an inverter serial IN3, and a judging circuit 215. The inverter serial IN1, the inverter serial IN2, and the inverter serial IN3 are coupled between the flip-flop FF1 and the flip-flop FF2, between the flip-flop FF2 and the flip-flop FF3, and between the flip-flop FF3 and the flip-flop FF1, respectively. The judging circuit 215 is coupled to the output Q of the flip-flop FF1, the flip-flop FF2, and the flip-flop FF3, respectively. In some embodiments, the flip-flop FF1, the flip-flop FF2, and the flip-flop FF3 are D-type flip-flops. The inverter serial IN1, the inverter serial IN2, and the inverter serial IN3 each have an odd number of inverters connected in series to invert a received signal. In some embodiments, the inverter serial IN1, the inverter serial IN2, and the inverter serial IN3 each have three inverters connected in series.

[0019] During the operation of the load generation circuit 210, the flip-flop FF1, the flip-flop FF2, the flip-flop FF3, the inverter serial IN1, the inverter serial IN2, and the inverter serial IN3 all consume power provided by the supply current I to operate. In order to make the figure simple, Figure 2 the paths related to receiving the supply current I are omitted, and the supply current I is not shown in Figure 2 .

[0020] The flip-flop FF1 has an input end D, an output end Q, a clock receiving end C, and a reset end R. The flip-flop FF1 is opened or closed by receiving the reset signal Sr1 through the reset end R. When the reset signal Sr1 has a first logic level, the flip-flop FF1 is opened to operate and consumes power provided by the supply current I. When the reset signal Sr1 has a second logic level, the flip-flop FF1 is closed and stops consuming power provided by the supply current I. When the flip-flop FF1 is opened, the flip-flop FF1 outputs the signal input by the input end D to the output end Q according to the clock signal CLK received by the clock receiving end C to generate the load signal S1. In some embodiments, the first logic level represents a digital logic 0, and the second logic level represents a digital logic 1.

[0021] The flip-flop FF1, the flip-flop FF2, and the flip-flop FF3 are the same and are used to generate the load signal S1, the load signal S2, and the load signal S3 at the output end, respectively. As Figure 2 shown in the figure, the inverter serial IN1 inverts the load signal S1 and transmits it to the receiving end D of the flip-flop FF2, and the flip-flop FF2 outputs the received signal in the next clock cycle to generate the load signal S2. Because the load generation circuit 210 includes three inverter serials IN1-IN3, when the operations of the flip-flops FF1-FF3 converge, each flip-flop FF1-FF3 generates the signal opposite to the signal in the previous clock cycle at the output end Q in the next clock cycle, and the load signals S1-S3 should have the same logic level in the same clock cycle. In other words, when the power provided by the supply current I is sufficient to make the flip-flop 1, the flip-flop FF2, the flip-flop FF3, the inverter serial IN1, the inverter serial IN2, and the inverter serial IN3 operate without timing failure caused by too low voltage, the load signals S1, the load signal S2, and the load signal S3 sequentially have the same logic level.

[0022] On the contrary, when the voltage provided by the supply current I is insufficient to cause the flip-flop FF1, the flip-flop FF2, the flip-flop FF3, the inverter serial IN1, the inverter serial IN2 and the inverter serial IN3 to operate normally, causing timing failure, then in the same clock cycle, the load signal S1 and the load signal S2 can have different logic levels, the load signal S2 and the load signal S3 can have different logic levels, and / or the load signal S3 and the load signal S1 can have different logic levels.

[0023] Because the flip-flop FF1, the flip-flop FF2, the flip-flop FF3, the inverter serial IN1, the inverter serial IN2 and the inverter serial IN3 consume different power when outputting different logic levels, that is, have multiple different load configurations. Therefore, the load generation circuit 210 as a whole alternately uses multiple different load configurations as the current load of the load generation circuit 210 when the flip-flop FF1, the flip-flop FF2 and the flip-flop FF3 are activated according to the clock cycle of the clock signal CLK.

[0024] The judgment circuit 215 is used to judge whether the operation of the load generation circuit 210 is timing failure according to the load signal S1, the load signal S2 and the load signal S3, and further judge whether the performance of the DUT 100 supplying the supply current I is qualified (that is, whether the performance test of the DUT 100 is passed). The judgment circuit 215 includes an exclusive OR gate XOR1, an exclusive OR gate XOR2 and an OR gate OR. The exclusive OR gate XOR1 is used to perform exclusive OR logic operation on the load signal S1 and the load signal S2 to generate an operation signal Sc1, and the exclusive OR gate XOR2 is used to perform exclusive OR logic operation on the load signal S2 and the load signal S3 to generate an operation signal Sc2. The OR gate OR is used to perform OR logic operation on the operation signal Sc1 and the operation signal Sc2 to generate an indication signal Si.

[0025] When the load signal S1, the load signal S2 and the load signal S3 sequentially have the same logic level, the operation signal Sc1 and the operation signal Sc2 both have a first logic level (logic 0), so that the indication signal Si has a first logic level (logic 0), which indicates that the performance of the DUT 100 is qualified. When the load signal S1 and the load signal S2 have different logic levels, the load signal S2 and the load signal S3 have different logic levels, and / or the load signal S3 and the load signal S1 have different logic levels, the operation signal Sc1 and / or the operation signal Sc2 have a second logic level (logic 1), so that the indication signal Si has a second logic level, which indicates that the performance of the DUT 100 is not qualified. That is, when any one of the operation signal Sc1 and the operation signal Sc2 has a second logic level, the indication signal Si has a second logic level.

[0026] Reference Figure 3 .Figure 3 This is a schematic diagram of control circuit 220. Control circuit 220 includes a counter circuit CNT, a random number generator PN, and a selector MUX. The counter circuit CNT is used to calculate the number of cycles of the clock signal CLK to generate an enable signal Se1. The random number generator PN is used to randomly generate an enable signal Se2. The selector MUX is used to select whether to output the enable signal Se1 or the enable signal Se2 as a reset signal Sr1.

[0027] The counter circuit CNT is controlled to turn on and off by a reset signal Sr0. When on, the counter circuit CNT calculates the number of cycles of the clock signal CLK based on a setting signal St, where the setting signal St indicates a predetermined number of cycles to be calculated. In some embodiments, the setting signal St is transmitted to the control circuit 220 through the control interface 400, but this application is not limited thereto. When the number of cycles of the clock signal CLK reaches the predetermined number, the counter circuit CNT generates an enable signal Se1.

[0028] In some embodiments, the random number generator PN may be a pseudo-random number generator, but is not limited thereto. The random number generator PN includes flip-flops FF4, FF5, FF6, FF7, and FF8, and an XOR gate. Flip-flops FF4 to FF8 and... Figure 2 The triggers FF1~FF3 in the circuit are the same. For example... Figure 3 As shown, flip-flops FF4 to FF8 are connected in series, and an XOR gate is connected between the outputs Q of flip-flops FF8 and FF4. Flip-flops FF4 to FF8 are controlled to turn on and off by a reset signal Sr0. When flip-flops FF4 to FF8 are activated, they generate signals S4, S5, S6, S7, and S8 at their outputs according to the clock signal CLK. The operation of flip-flops FF4 to FF8, combined with the XOR gate, continuously updates signals S4 to S8 according to the clock signal CLK, generating pseudo-randomly varying signals S4 to S8 within a certain number of clock cycles. The random number generator PN outputs signals S4 to S8 as an enable signal Se2.

[0029] The selector MUX receives enable signals Se1 and Se2, and selects one of the enable signals Se1 and Se2 according to the selection signal Ss to output the reset signal Sr1.

[0030] In some embodiments, the control circuit 220 includes only a counter circuit CNT. The control circuit 220 directly outputs the enable signal Se1 generated by the counter circuit CNT as a reset signal Sr1.

[0031] In some embodiments, the current load circuit 200 includes a plurality of load generation circuits, such as load generation circuit 210 and load generation circuit 211, which are arranged in parallel as shown in Figure 4 In some embodiments, the load generation circuits 210 and 211 are identical and have the same plurality of load configurations. The control circuit 220 generates a plurality of reset signals Sr1 to control the load generation circuits 210 and 211, respectively. In some embodiments, reference can be made to Figure 3 together with FIG. 2, the set signal St indicates two different predetermined numbers, the counter circuit CNT calculates the different cycle numbers according to the set signal St and generates two enable signals Se1, and the control circuit 220 outputs the two enable signals Se1 as two different reset signals Sr1. The control circuit 220 controls the load generation circuits 210 and 211 to be sequentially turned on and switched to the same current load in a fixed time, so that the total supply current I drawn by the load generation circuits 210 and 211 gradually increases (e.g., by approximately the same value each time) in the fixed time. In other words, the control circuit 220 controls the time interval during which the load generation circuits 210 and 211 are turned on according to the clock signal CLK and the set signal St. According to the above operation, the time interval during which the load generation circuits 210 and 211 are turned on is determined by the plurality of reset signals Sr1, thereby determining the transient rate of the supply current I.

[0032] Reference can also be made to Figure 5 Figure 5 ​The waveform graph of the supply current I drawn by the load generation circuits 210 and 211 under different current loads is shown, in which the horizontal axis is time T and the vertical axis is supply current I. The time interval dt1 represents the time interval from when the control circuit 220 turns on the load generation circuit 210 to when the load generation circuit 211 is turned on. When the control circuit 220 changes the original time interval dt1 to the time interval dt2, the supply current I can be observed in terms of the current CL1 and the current CL2, which represent the current changes of the supply current I corresponding to sequentially turning on the load generation circuits 210 and 211 based on the time interval dt1 and the time interval dt2, respectively. In the case where the time interval dt1 is less than the time interval dt2, the transient rate of the current CL1 can be greater than the transient rate of the current CL2. In this embodiment, between the time point t1 and the time point t1', the current CL1 can be at (or substantially at) a current level, which is the current level of the supply current I in a steady state after the load generation circuit 210 and the load generation circuit 211 are turned on. Similarly, between the time point t2 and the time point t2', the current CL2 can be at (or substantially at) a current level, which is the current level of the supply current I in a steady state after the load generation circuit 210 and the load generation circuit 211 are turned on.

[0033] In other embodiments, the selector MUX in the control circuit 220 selects the enable signal Se2 as the reset signal Sr1, and accordingly controls the load generation circuits 210 and 211. Since the enable signal Se2 is randomly generated, the load generation circuits 210 and 211 as a whole have a random current load when turned on, as shown by the current CL3 in Figure 5

[0034] The above description merely illustrates some features of the embodiments of the present application, and enables those skilled in the art to fully understand the various aspects of the present application. Those skilled in the art can easily utilize the present application as a basis to design or modify other processes and structures, to achieve the same purposes and / or achieve the same advantages as the embodiments described herein. Those skilled in the art should understand that these equivalent embodiments still belong to the spirit and scope of the present application, and can be variously changed, replaced and modified without departing from the spirit and scope of the present application.

[0035]

Symbol Description

[0036] 10: chip ​

[0037] 100: device under test

[0038] 200: current load circuit

[0039] 210: load generation circuit

[0040] 211: load generation circuit

[0041] 215: determination circuit

[0042] 220: control circuit

[0043] 300: phase-locked loop

[0044] 400: control interface

[0045] C: clock receiving end

[0046] CL1: current

[0047] CL2: current

[0048] CL3: current

[0049] CLK: clock signal

[0050] CNT: counter circuit

[0051] D: input end

[0052] dt1: time interval

[0053] dt2: time interval

[0054] FF1: flip-flop

[0055] FF2: flip-flop

[0056] FF3: flip-flop

[0057] FF4: flip-flop

[0058] FF5: flip-flop

[0059] FF6: flip-flop

[0060] FF7: flip-flop

[0061] FF8: flip-flop

[0062] I: supply current

[0063] I0: supply current

[0064] IN1: inverting serial

[0065] IN2: inverting serial

[0066] IN3: inverting serial

[0067] MUX: multiplexer

[0068] OR: OR gate

[0069] PN: pseudo random number generator

[0070] Q: output

[0071] R: reset

[0072] S1: load signal

[0073] S2: load signal

[0074] S3: load signal

[0075] S4: signal

[0076] S5: signal

[0077] S6: signal

[0078] S7: signal

[0079] S8: signal

[0080] Sc1: operation signal

[0081] Sc2: operation signal

[0082] Se1: enable signal

[0083] Se2: enable signal

[0084] Si: indication signal

[0085] Sr0: reset signal

[0086] Sr1: reset signal

[0087] Ss: selection signal

[0088] St: set signal

[0089] T: time

[0090] t1: time point

[0091] t1': time point

[0092] t2: time point

[0093] t2': time point

[0094] XNOR: XNOR gate

[0095] XOR1: XOR gate

[0096] XOR2: XOR gate

Claims

1. A current load circuit for testing a power supply circuit, characterized in that, Include: A control circuit for generating a first reset signal based on a clock signal; and A first load generating circuit is coupled to the control circuit and has multiple first load configurations. The first load generating circuit is used to alternately provide one of the multiple first load configurations as a first current load of the first load generating circuit according to the clock signal and the first reset signal, and to receive a first portion of a supply current provided by the power supply circuit according to the first current load, so as to output an indication signal for indicating the performance of the power supply circuit. The first load generating circuit includes: A first flip-flop, a second flip-flop, and a third flip-flop are used to generate a first load signal, a second load signal, and a third load signal respectively based on the clock signal and the first reset signal; A first inverting serial converter, a second inverting serial converter, and a third inverting serial converter are respectively coupled between the first flip-flop and the second flip-flop, between the second flip-flop and the third flip-flop, and between the third flip-flop and the first flip-flop; and A judgment circuit, coupled to the first flip-flop, the second flip-flop, and the third flip-flop, is used to generate the indication signal based on the first load signal, the second load signal, and the third load signal, wherein the judgment circuit includes: A first XOR gate is used to perform an XOR logic operation on the first load signal and the second load signal to generate a first operation signal: A second XOR gate is used to perform the XOR logic operation on the second load signal and the third load signal to generate a second operation signal: and An OR gate is used to perform an OR logic operation on the first arithmetic signal and the second arithmetic signal to generate the indication signal.

2. The current load circuit as described in claim 1, characterized in that, The control circuit is further used to generate a second reset signal based on the clock signal, and the current load circuit also includes: A second load generating circuit, coupled to the control circuit and having a plurality of second load configurations, the second load generating circuit being activated according to the second reset signal, and alternately using one of the plurality of second load configurations as a second current load of the second load generating circuit according to the clock cycle of the clock signal, and receiving a second portion of the supply current provided by the power supply circuit according to the second current load, wherein a transient rate of the supply current is determined at least according to the first reset signal and the second reset signal.

3. The current load circuit as described in claim 2, characterized in that, The control circuit includes: A counter circuit is used to calculate the number of cycles of a clock signal, wherein when the number of cycles of the clock signal reaches a first predetermined value, the counter circuit generates a first enable signal as the first reset signal to reset the first current load, and when the number of cycles of the clock signal reaches a second predetermined value, the counter circuit generates a second enable signal as the first reset signal to reset the second current load.

4. The current load circuit as described in claim 3, characterized in that, The control circuit includes: A counter circuit is used to calculate the number of cycles of a clock signal, wherein when the number of cycles of the clock signal reaches a first predetermined value, the counter circuit generates a first enable signal, and when the number of cycles of the clock signal reaches a second predetermined value, the counter circuit generates a second enable signal. A random number generator is used to randomly generate a third enable signal and a fourth enable signal based on the clock signal; and A selector is configured to output the first enable signal and the second enable signal as the first reset signal and the second reset signal respectively according to a selection signal, or to output the third enable signal and the fourth enable signal as the first reset signal and the second reset signal respectively according to the selection signal.

5. A current load circuit for testing a power supply circuit, characterized in that, Include: A first load generating circuit has multiple first load configurations, which, upon startup, alternately switches to one of the multiple first load configurations according to a clock signal to receive a first portion of a supply current provided by the power supply circuit, and outputs a first indication signal to indicate the performance of the power supply circuit. A second load generating circuit has multiple second load configurations, which, upon startup, alternately switches to one of the multiple second load configurations according to the clock cycle of the clock signal to receive a second portion of the supply current provided by the power supply circuit, and outputs a second indication signal to indicate the performance of the power supply circuit accordingly. and A control circuit is used to determine the time interval between the start-up of the first load generating circuit and the second load generating circuit based on the clock signal. The control circuit is further configured to generate a first reset signal and a second reset signal based on the clock signal, and The first load generating circuit alternately switches to one of the plurality of first load configurations according to the clock signal to serve as a first current load of the first load generating circuit, and the second load generating circuit alternately switches to one of the plurality of second load configurations according to the clock signal to serve as a second current load of the second load generating circuit. The first load generating circuit includes: A first flip-flop, a second flip-flop, and a third flip-flop are used to generate a first load signal, a second load signal, and a third load signal respectively based on the clock signal and the first reset signal; A first inverting serial converter, a second inverting serial converter, and a third inverting serial converter are respectively coupled between the first flip-flop and the second flip-flop, between the second flip-flop and the third flip-flop, and between the third flip-flop and the first flip-flop; and A first judgment circuit, coupled to the first flip-flop, the second flip-flop and the third flip-flop, is used to generate the first indication signal based on the first load signal, the second load signal and the third load signal.

6. The current load circuit as described in claim 5, characterized in that, The first determination circuit includes: A first XOR gate is used to perform an XOR logic operation on the first load signal and the second load signal to generate a first operation signal: A second XOR gate is used to perform the XOR logic operation on the second load signal and the third load signal to generate a second operation signal: and An OR gate is used to perform an OR logic operation on the first operation signal and the second operation signal to generate the first indication signal.

7. A chip for testing a power supply circuit, characterized in that, Include: A phase-locked loop, coupled to the power supply circuit, is used to generate a clock signal; and A current load circuit is coupled to the power supply circuit, wherein the current load circuit includes: A load generating circuit is used to alternately provide one of a plurality of load configurations as a current load of the load generating circuit according to a clock signal and a reset signal, wherein the current load circuit outputs an indication signal to indicate the performance of the power supply circuit according to the current load and a supply current provided by the power supply circuit. The load generating circuit includes: A first flip-flop, a second flip-flop, and a third flip-flop are used to generate a first load signal, a second load signal, and a third load signal respectively based on the clock signal and the first reset signal; A first inverting serial converter, a second inverting serial converter, and a third inverting serial converter are respectively coupled between the first flip-flop and the second flip-flop, between the second flip-flop and the third flip-flop, and between the third flip-flop and the first flip-flop; and A judgment circuit, coupled to the first flip-flop, the second flip-flop, and the third flip-flop, is used to generate the indication signal based on the first load signal, the second load signal, and the third load signal, wherein the judgment circuit includes: A first XOR gate is used to perform an XOR logic operation on the first load signal and the second load signal to generate a first operation signal: A second XOR gate is used to perform the XOR logic operation on the second load signal and the third load signal to generate a second operation signal: and An OR gate is used to perform an OR logic operation on the first arithmetic signal and the second arithmetic signal to generate the indication signal.

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