LDO regulation circuit and method based on adaptive power transistor

Abstract

The embodiment of the specification provides a kind of LDO regulating circuit and method based on adaptive power transistor, wherein the circuit includes: voltage difference time converter VDTC, connect with charge pump CP, for comparing output voltage VOUT with reference voltage VREF, according to the pulse signal of comparison result generation;Charge pump CP, connect with the sub-power tube in adaptive power transistor and non-negative gain stage, for generating pull-up or pull-down current according to the pulse signal;Miller compensation capacitor, across the output of first gain stage and output voltage VOUT, for separating the main secondary node of entire circuit;Undercut improvement circuit, connect output voltage VOUT and main power tube gate, for detecting the dramatic change of output voltage VOUT and generating pulse signal after exceeding threshold range;Adaptive power transistor, connect after the output of first gain stage, for adaptive control switch according to load current condition, provide stable output voltage in wider current load range.

Description

[0001] LDO regulating circuit and method based on adaptive power transistor TECHNICAL FIELD

[0002] The present document relates to the technical field of integrated circuits, and in particular to an LDO regulating circuit and method based on adaptive power transistor. BACKGROUND

[0003] At present, in the field of integrated circuits, LDO, i.e. low dropout linear regulator, is widely used in various low-power occasions, especially in high-performance analog circuits and radio frequency circuits which are relatively sensitive to noise. The LDO has the characteristics of simple internal structure, few external components, small output ripple and noise, etc.

[0004] In related technologies, in the case of low power supply voltage, close to or lower than the threshold voltage, the LDO circuit has the following defects: due to the limitation of the required headroom voltage of the error amplifier, the traditional analog LDO function will be degraded; the digital LDO output that can work at low power supply voltage will generate a large ripple.

[0005] In summary of the above analysis of the development status of the technical field, there is a lack of a circuit in the prior art that can provide a higher stable output voltage in a wider input voltage range under the constraint of very low voltage difference. SUMMARY

[0006] The purpose of the present application is to provide an LDO regulating circuit and method based on adaptive power transistor, which aims to solve the above problems in the prior art.

[0007] According to a first aspect of the embodiments of the present disclosure, the present application provides an LDO regulating circuit based on adaptive power transistor, comprising:

[0008] A voltage difference time converter VDTC is connected with the charge pump CP, used for comparing the output voltage VOUT with the reference voltage VREF, and generating a first control pulse signal UP or a second control pulse signal DN according to the comparison result;

[0009] The charge pump CP is connected with the auxiliary power transistor and the non-negative gain stage in the adaptive power transistor, used for generating a pull-up or pull-down current according to the first control pulse signal UP or the second control pulse signal DN, and adjusting the power transistor gate voltage V01;

[0010] The Miller compensation capacitor is connected between the output of the first gain stage composed of the voltage time converter VDTC and the charge pump CP and the output voltage VOUT, used for separating the main and secondary nodes of the entire circuit, reducing the oscillation of the output voltage VOUT, and ensuring that the entire circuit remains stable within the load current range;

[0011] The undershoot improvement circuit is connected with the output voltage VOUT and the main power tube gate, used for detecting the sharp change of the output voltage VOUT and generating the third control pulse signal VN as a fast response loop improvement for large load steps after exceeding the threshold range.

[0012] The adaptive power transistor is connected after the output of the first gain stage composed of the voltage time converter VDTC and the charge pump CP, used for adaptively controlling the switch according to the load current condition, and providing a stable output voltage in a wide current load range.

[0013] According to a second aspect of the embodiments of the present disclosure, the present disclosure provides an LDO regulating method based on an adaptive power transistor, comprising:

[0014] The voltage difference time converter VDTC compares the output voltage VOUT with the reference voltage VREF, and generates the first control pulse signal UP or the second control pulse signal DN according to the comparison result;

[0015] The charge pump CP generates the pull-up or pull-down current according to the first control pulse signal UP or the second control pulse signal DN, and adjusts the power transistor gate voltage V01;

[0016] The Miller compensation capacitor separates the main and secondary nodes of the whole circuit, reduces the oscillation of the output voltage VOUT, and ensures that the whole circuit remains stable in the load current range;

[0017] The undershoot improvement circuit detects the sharp change of the output voltage VOUT and generates the third control pulse signal VN as a fast response loop improvement for large load steps after exceeding the threshold range.

[0018] The adaptive power transistor adaptively controls the switch according to the load current condition, and provides a stable output voltage in a wide current load range.

[0019] The technical scheme provided by the embodiments of the present disclosure can include the following beneficial effects: the LDO regulating circuit and method based on the adaptive power transistor are provided, stable voltage is ensured in a low power supply voltage and a wide load current range, and fast transient response of the circuit is realized in a wide load step.

[0020] It should be understood that the above general description and the following detailed description are only exemplary and explanatory, and cannot limit the present disclosure. BRIEF DESCRIPTION OF DRAWINGS

[0021] In order to make one or more embodiments or the prior art of the technical solutions in the specification clearer, the drawings needed in the embodiment or prior art description will be briefly introduced below. Obviously, the drawings in the following description are only some embodiments described in the specification, and other drawings can be obtained by those skilled in the art without creative labor.

[0022] Figure 1 is a schematic diagram of an adaptive power transistor-based LDO regulating circuit according to an embodiment of the present application;

[0023] Figure 2 is a schematic diagram of a detailed LDO regulating circuit according to an embodiment of the present application;

[0024] Figure 3 is a schematic diagram of an undershoot improvement circuit according to an embodiment of the present application;

[0025] Figure 4 is a flowchart of an adaptive power transistor-based LDO regulating method according to an embodiment of the present application. DETAILED DESCRIPTION

[0026] In order to make one or more embodiments or the prior art of the technical solutions in the specification clearer, the drawings needed in the embodiment or prior art description will be briefly introduced below. Obviously, the drawings in the following description are only some embodiments described in the specification, and other drawings can be obtained by those skilled in the art without creative labor.

[0027] Apparatus embodiment

[0028] According to an embodiment of the present application, an adaptive power transistor-based LDO regulating circuit is provided, Figure 1 is a schematic diagram of an adaptive power transistor-based LDO regulating circuit according to an embodiment of the present application, as Figure 1 shown, the adaptive power transistor-based LDO regulating circuit according to an embodiment of the present application specifically comprises:

[0029] The voltage difference time converter VDTC 10 is connected with the charge pump CP 12, and is used to compare the output voltage VOUT with the reference voltage VREF, and generate a first control pulse signal UP or a second control pulse signal DN according to the comparison result;

[0030] The voltage difference time converter VDTC 10 specifically comprises a dynamic amplifier, a first slope inverter and a pulse generator, wherein the dynamic amplifier is connected at the output of the output voltage VOUT and the reference voltage VREF, the output of the dynamic amplifier is connected to the first slope inverter, and the output of the first slope inverter is connected to the pulse generator.

[0031] The dynamic amplifier compares the output voltage VOUT with the reference voltage VREF, and generates VTP and VTN according to the comparison result under the action of clock, the first slope inverter controls the switch according to the value of VTP and VTN, and the first control pulse signal UP or the second control pulse signal DN is obtained through the pulse generator to adjust the V01 voltage size.

[0032] If the reference voltage VREF is less than the output voltage VOUT, the first control pulse signal UP is generated to pull down the gate voltage V01 of the power transistor; if the reference voltage VREF is greater than the output voltage VOUT, the second control pulse signal DN is generated to pull up the V01 voltage to adjust the subsequent circuit; if the reference voltage VREF is equal to the output voltage VOUT, no control signal is generated to maintain the stable state.

[0033] The charge pump CP 12 is connected with the auxiliary power transistor in the adaptive power transistor 18 and the non-negative gain stage, and is used to generate pull-up or pull-down current according to the first control pulse signal UP or the second control pulse signal DN to adjust the gate voltage V01 of the power transistor;

[0034] The Miller compensation capacitor 14 is connected between the output of the first gain stage composed of the voltage time converter VDTC 10 and the charge pump CP 12 and the output voltage VOUT, and is used to separate the main and secondary nodes of the entire circuit, reduce the oscillation of the output voltage VOUT, and ensure that the entire circuit remains stable within the range of load current;

[0035] The undershoot improvement circuit 16 is connected with the output voltage VOUT and the gate of the main power transistor, and is used to detect the sharp change of the output voltage VOUT and generate the third control pulse signal VN as a fast feedback loop to improve the large load step after exceeding the threshold range.

[0036] The undershoot improvement circuit 16 comprises a high-pass filter, a second slope inverter and a buffer, wherein the high-pass filter is connected with the output voltage VOUT, the output of the high-pass filter is connected to the second slope inverter, and the second slope inverter is connected to the buffer.

[0037] The high-pass filter detects the dramatic change of the output voltage VOUT, and if the change exceeds the threshold of the second slope inverter, a third control pulse signal VN is generated, which is adjusted by a buffer and reaches the transistor MN, and the transistor MN turns on the gate voltage VG of the pull-down main power transistor MP2, thereby improving the transient response of the low-dropout linear regulator under large load steps.

[0038] The adaptive power transistor 18 is connected to the output of the first gain stage composed of the voltage-time converter VDTC 10 and the charge pump CP 12, and is used to adaptively control the switch according to the load current condition, thereby providing a stable output voltage in a wide current load range.

[0039] The adaptive power transistor 18 includes a sub-power transistor MP1, a non-negative gain stage, and a main power transistor MP2, wherein the sub-power transistor MP1 and the non-negative gain stage are connected to the power transistor gate voltage V01, and the main power transistor MP2 is connected to the output of the sub-power transistor MP1.

[0040] The main power transistor MP2 is adaptively turned on or off according to the load current condition, thereby ensuring a wide range of load capacity of the circuit, and only the sub-power transistor MP1 is turned on in light load, the non-negative gain stage is turned on in heavy load, and the main and sub-power transistors work simultaneously to adjust the output voltage VOUT.

[0041] In summary, the above technical solution of the embodiment of the present application proposes an LDO regulating circuit based on an adaptive power transistor, in which the voltage difference-time converter VDTC replaces the error amplifier, the working range of the input power voltage is increased, and the input-output voltage difference is reduced; the undershoot improvement circuit greatly reduces the undershoot voltage and reduces the voltage recovery time; the adaptive power transistor enables the circuit to work in a wide load current range, thereby improving the load capacity.

[0042] The above technical solution of the embodiment of the present application will be described in detail below with reference to the accompanying drawings.

[0043] Figure 2 is a schematic diagram of the detailed LDO regulating circuit of the embodiment of the present application, as Figure 2 shown, the detailed LDO regulating circuit according to the embodiment of the present application specifically includes:

[0044] The voltage difference-time converter VDTC is connected to the charge pump CP, and is used to compare the output voltage VOUT with the reference voltage VREF, and generate a first control pulse signal UP or a second control pulse signal DN according to the comparison result.

[0045] The voltage difference time converter VDTC comprises a dynamic amplifier, a first tilt inverter and a pulse generator, wherein the dynamic amplifier is connected at the output of the output voltage VOUT and the reference voltage VREF, the output of the dynamic amplifier is connected to the first tilt inverter, and the output of the first tilt inverter is connected to the pulse generator.

[0046] The charge pump CP is connected to the auxiliary power transistor and the non-negative gain stage in the adaptive power transistor, and is used to generate a pull-up or pull-down current according to the first control pulse signal UP or the second control pulse signal DN, so as to adjust the power transistor gate voltage V01.

[0047] The Miller compensation capacitor is connected between the output of the first gain stage composed of the voltage time converter VDTC and the charge pump CP and the output voltage VOUT, and is used to separate the main and secondary nodes of the entire circuit, reduce the oscillation of the output voltage VOUT, and ensure that the entire circuit remains stable within the load current range.

[0048] The undershoot improvement circuit is connected to the output voltage VOUT and the gate of the main power transistor, and is used to detect the sharp change of the output voltage VOUT and generate a third control pulse signal VN as a fast feedback loop to improve the large load step after exceeding the threshold range.

[0049] The undershoot improvement circuit comprises a high-pass filter, a second tilt inverter and a buffer, wherein the high-pass filter is connected to the output voltage VOUT, the output of the high-pass filter is connected to the second tilt inverter, and the second tilt inverter is connected to the buffer.

[0050] The adaptive power transistor is connected after the output of the first gain stage composed of the voltage time converter VDTC and the charge pump CP, and is used to adaptively control the switch according to the load current condition, so as to provide a stable output voltage within a wide current load range.

[0051] The adaptive power transistor comprises an auxiliary power transistor MP1, a non-negative gain stage and a main power transistor MP2, wherein the auxiliary power transistor MP1 and the non-negative gain stage are connected to the power transistor gate voltage V01, and the output of the main power transistor MP2 is connected to the auxiliary power transistor MP1.

[0052] The working mode of the detailed LDO regulating circuit is as follows: the dynamic amplifier in the voltage difference time converter VDTC compares the output voltage VOUT with the reference voltage VREF, and generates VTP and VTN according to the comparison result under the action of the clock; the first tilt inverter controls the switch according to the values of VTP and VTN, and obtains the first control pulse signal UP or the second control pulse signal DN through the pulse generator to adjust the voltage size of V01; the main power transistor MP2 is adaptively turned on or turned off according to the load current condition, so as to ensure the wide range of load capacity of the circuit; only the auxiliary power transistor MP1 is turned on when the load is light; the non-negative gain stage is turned on when the load is heavy; the main and auxiliary power transistors work simultaneously to adjust the output voltage VOUT; the undershoot improvement circuit detects the change of the output voltage VOUT, and when the load current increases sharply, the pulse VN is generated to pull down the gate voltage VN of the main power transistor MP2, so as to improve the transient response of the low dropout linear regulator under the large load step.

[0053] In the embodiment of the present application, the voltage difference time converter VDTC adopts a differential input stage, only the pole created by integrating the output current of the charge pump CP, and no additional poles are generated inside the circuit, so that no additional frequency compensation method is needed.

[0054] In the embodiment of the present application, the adaptive power transistor judges the transistor state according to the size of the load current. Under the light load condition, the non-negative gain stage works in the transistor region and the main power transistor MP2 is turned off, at this time, the LDO can be regarded as a two-stage structure, and under the heavy load condition, the main power transistor MP2 is turned on and the LDO is converted into a three-stage structure.

[0055] Figure 3 is the schematic diagram of the undershoot improvement circuit of the embodiment of the present application, as shown in Figure 3 The undershoot improvement circuit according to the embodiment of the present application specifically comprises:

[0056] The undershoot improvement circuit comprises a high-pass filter, a second tilt inverter and a buffer, wherein the high-pass filter is connected with the output voltage VOUT, the high-pass filter output is connected with the second tilt inverter, and the second tilt inverter is connected with the buffer.

[0057] The high-pass filter detects the sharp change of the output voltage VOUT, and if the change exceeds the threshold value of the second tilt inverter, the third control pulse signal VN is generated, which is adjusted through the buffer to reach the transistor MN, and the transistor MN turns on the gate voltage VG of the main power transistor MP2 to improve the transient response of the low dropout linear regulator under the large load step.

[0058] The method embodiment according to the embodiment of the present application provides an LDO regulating method based on an adaptive power transistor, Figure 4is a schematic diagram of the adaptive power transistor-based LDO regulating method of the embodiment of the present application, as Figure 4 As shown, the adaptive power transistor-based LDO regulating method according to the embodiment of the present application specifically comprises:

[0059] In step S410, the output voltage VOUT is compared with the reference voltage VREF by the voltage difference time converter VDTC, and a first control pulse signal UP or a second control pulse signal DN is generated according to the comparison result.

[0060] The dynamic amplifier compares the output voltage VOUT with the reference voltage VREF, and generates VTP and VTN according to the comparison result under the action of the clock, the first tilting inverter controls the switch according to the values of VTP and VTN, and the first control pulse signal UP or the second control pulse signal DN is obtained through the pulse generator to adjust the V01 voltage size.

[0061] If the reference voltage VREF is less than the output voltage VOUT, the first control pulse signal UP is generated to pull down the gate voltage V01 of the power transistor; if the reference voltage VREF is greater than the output voltage VOUT, the second control pulse signal DN is generated to pull up the V01 voltage to adjust the subsequent circuit; and if the reference voltage VREF is equal to the output voltage VOUT, no control signal is generated to maintain the stable state.

[0062] In step S420, the pull-up or pull-down current is generated by the charge pump CP according to the first control pulse signal UP or the second control pulse signal DN to adjust the gate voltage V01 of the power transistor.

[0063] In step S430, the main and secondary nodes of the entire circuit are separated by the Miller compensation capacitor to reduce the oscillation of the output voltage VOUT and ensure that the entire circuit remains stable within the load current range.

[0064] In step S440, the undershoot is used to improve the detection of the dramatic change of the output voltage VOUT and generate a third control pulse signal VN after exceeding the threshold range, which is used as a fast response loop to improve the large load step.

[0065] The dramatic change of the output voltage VOUT is detected by the high-pass filter, and if the second tilting inverter threshold is exceeded, the third control pulse signal VN will be generated, which is adjusted through the buffer to reach the transistor MN. The transistor MN will be turned on to pull down the gate voltage VG of the main power transistor MP2, thereby improving the transient response of the low-dropout linear regulator under a large load step.

[0066] In step S450, the adaptive power transistor controls the switch according to the load current condition to provide a stable output voltage within a wide current load range.

[0067] By the main power transistor MP2, the circuit is ensured to have a wide range of load capacity, and only the auxiliary power transistor MP1 is turned on when the load current is light, the non-negative gain stage is turned on when the load current is heavy, and the main and auxiliary power transistors work simultaneously to adjust the output voltage VOUT.

[0068] To sum up, the technical scheme of the embodiment of the present application proposes an LDO adjusting method based on an adaptive power transistor, the working range of the input power voltage is increased and the input-output voltage difference is reduced by using a voltage difference time converter VDTC instead of an error amplifier; the undershoot voltage is greatly reduced and the voltage recovery time is reduced by using undershoot improvement circuit; the circuit can work in a wide range of load current by using the adaptive power transistor, and the load capacity is improved.

[0069] Finally, it should be noted that: the above embodiments are only used to illustrate the technical solutions of the present application, and not to limit them; although the present application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that: it can still modify the technical solutions recorded in the foregoing embodiments, or make equivalent replacement for part or all of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A low-dropout linear regulator (LDO) regulation circuit based on an adaptive power transistor, characterized in that, include: A voltage difference time converter (VDTC), connected to a charge pump (CP), is used to compare the output voltage VOUT with a reference voltage VREF, and generate a first control pulse signal UP or a second control pulse signal DN based on the comparison result; the voltage difference time converter (VDTC) specifically includes: The system includes a dynamic amplifier, a first tilt inverter, and a pulse generator, wherein the dynamic amplifier is connected to the output of the output voltage VOUT and the reference voltage VREF, the output of the dynamic amplifier is connected to the first tilt inverter, and the output of the first tilt inverter is connected to the pulse generator. The dynamic amplifier compares the output voltage VOUT with the reference voltage VREF, and generates VTP and VTN based on the comparison result under the action of a clock. The first tilt inverter controls the switch according to the values ​​of VTP and VTN, and obtains the first control pulse signal UP or the second control pulse signal DN through the pulse generator to adjust the magnitude of V01 voltage. The charge pump CP is connected to the sub-power transistor and non-negative gain stage in the adaptive power transistor. It is used to generate pull-up or pull-down current according to the first control pulse signal UP or the second control pulse signal DN to adjust the gate voltage V01 of the power transistor. The Miller compensation capacitor is connected across the output of the first gain stage, which consists of the voltage-time converter VDTC and the charge pump CP, and the output voltage VOUT. It is used to separate the primary and secondary nodes of the entire circuit, reduce the oscillation of the output voltage VOUT, and ensure that the entire circuit remains stable within the load current range. The undershoot improvement circuit is connected to the output voltage VOUT and the gate of the main power transistor. It is used to detect drastic changes in the output voltage VOUT and generate a third control pulse signal VN after the voltage exceeds the threshold range. This serves as a fast response loop to improve the load step. An adaptive power transistor, connected after the output of the first gain stage consisting of a voltage-time converter (VDTC) and a charge pump (CP), is used to adaptively control the switch according to load current conditions, providing a stable output voltage over the current load range.

2. The low-dropout linear regulator (LDO) regulation circuit based on adaptive power transistors according to claim 1, characterized in that, The dynamic amplifier is specifically used for: If the reference voltage VREF is less than the output voltage VOUT, a first control pulse signal UP is generated to pull down the gate voltage V01 of the power transistor; if the reference voltage VREF is greater than the output voltage VOUT, a second control pulse signal DN is generated to pull up V01 to adjust the voltage of the subsequent stage circuit; if the reference voltage VREF is equal to the output voltage VOUT, no control signal is generated to maintain a stable state.

3. The low-dropout linear regulator (LDO) regulation circuit based on adaptive power transistors according to claim 1, characterized in that, The undershoot improvement circuit specifically includes: The system includes a high-pass filter, a second tilt inverter, and a buffer, wherein the high-pass filter is connected to the output voltage VOUT, the output of the high-pass filter is connected to the second tilt inverter, and the second tilt inverter is connected to the buffer. The high-pass filter detects drastic changes in the output voltage VOUT. If the change exceeds the threshold of the second tilt inverter, a third control pulse signal VN will be generated. This signal is adjusted by the buffer and then reaches the transistor MN. The transistor MN will turn on and pull down the gate voltage VG of the main power transistor MP2, thereby improving the transient response of the low-dropout linear regulator under load step.

4. The low-dropout linear regulator (LDO) regulation circuit based on adaptive power transistors according to claim 1, characterized in that, The adaptive power transistor specifically includes: The system comprises a secondary power transistor MP1, a non-negative gain stage, and a main power transistor MP2, wherein the secondary power transistor MP1 and the non-negative gain stage are connected to the gate voltage V01 of the power transistor, and the output of the main power transistor MP2 is connected to the secondary power transistor MP1. The main power transistor MP2 adaptively turns on or off according to the load current condition to ensure the circuit's load-carrying capacity. Under light load, only the secondary power transistor MP1 turns on, while under heavy load, the non-negative gain stage turns on. The main and secondary power transistors work simultaneously to adjust the output voltage VOUT.

5. A method for regulating an LDO based on an adaptive power transistor, characterized in that, The low-dropout linear regulator (LDO) regulation circuit based on an adaptive power transistor, as described in any one of claims 1 to 4, comprises: The output voltage VOUT is compared with the reference voltage VREF by a voltage difference time converter VDTC, and a first control pulse signal UP or a second control pulse signal DN is generated based on the comparison result; specifically including: The dynamic amplifier compares the output voltage VOUT with the reference voltage VREF, and generates VTP and VTN based on the comparison result under the action of the clock. The first tilt inverter controls the switch according to the values ​​of VTP and VTN, and obtains the first control pulse signal UP or the second control pulse signal DN through the pulse generator to adjust the magnitude of V01 voltage. The charge pump CP generates pull-up or pull-down current according to the first control pulse signal UP or the second control pulse signal DN, thereby adjusting the gate voltage V01 of the power transistor. By separating the primary and secondary nodes of the entire circuit using Miller compensation capacitors, the oscillation of the output voltage VOUT is reduced, ensuring that the entire circuit remains stable within the load current range. The undershoot improvement circuit detects drastic changes in the output voltage VOUT and generates a third control pulse signal VN when the voltage exceeds the threshold range, serving as a fast-response loop to improve load step. By adaptively controlling the switch according to the load current conditions using an adaptive power transistor, a stable output voltage is provided within the current load range.

6. The LDO regulation method based on adaptive power transistors according to claim 5, characterized in that, The dynamic amplifier compares the output voltage VOUT with the reference voltage VREF, specifically including: If the reference voltage VREF is less than the output voltage VOUT, a first control pulse signal UP is generated to pull down the gate voltage V01 of the power transistor; if the reference voltage VREF is greater than the output voltage VOUT, a second control pulse signal DN is generated to pull up V01 to adjust the voltage of the subsequent stage circuit; if the reference voltage VREF is equal to the output voltage VOUT, no control signal is generated to maintain a stable state.

7. The LDO regulation method based on adaptive power transistors according to claim 5, characterized in that, The step of detecting drastic changes in the output voltage VOUT through the undershoot improvement circuit and generating a third control pulse signal VN after the voltage exceeds a threshold range specifically includes: The high-pass filter detects drastic changes in the output voltage VOUT. If the change exceeds the threshold of the second tilt inverter, a third control pulse signal VN is generated. This signal is adjusted by the buffer and reaches the transistor MN. The transistor MN will then conduct and pull down the gate voltage VG of the main power transistor MP2, thereby improving the transient response of the low dropout linear regulator under load step.

8. The LDO regulation method based on adaptive power transistors according to claim 5, characterized in that, The adaptive power transistor adaptively controls the switch according to the load current condition, specifically including: The main power transistor MP2 adaptively turns on or off according to the load current condition to ensure the circuit's load-carrying capacity. Under light load, only the secondary power transistor MP1 is turned on, while under heavy load, the non-negative gain stage is turned on. The main and secondary power transistors work simultaneously to adjust the output voltage VOUT.

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