Array substrate

Abstract

This application provides an array substrate, which includes a gate, a compensation electrode, an array substrate-side common electrode, and a source electrode. By disposing the source electrode portion and the compensation portion of the source electrode on opposite sides of the storage capacitor portion and connecting them to the storage capacitor portion, the area occupied by the source electrode can be reduced, thereby increasing the aperture ratio of the array substrate.

Description

Technical Field

[0001] This application relates to the field of display technology, and more particularly to an array substrate. Background Technology

[0002] Liquid crystal displays (LCDs) are currently the most widely used type of display. Compared to traditional cathode ray tube (CRT) displays, LCDs offer advantages such as thinner design, lower power consumption, and lower voltage operation. The display area of ​​an LCD consists of multiple pixel areas. Each pixel area is defined by two gate lines and two data lines, and contains thin-film transistors (TFTs) and pixel electrodes that serve as switching components.

[0003] like Figure 1 As shown, the array substrate of the liquid crystal display panel is provided with a gate 11, a source 12, a drain 13, and a pixel electrode 14. The source 12 and drain 13 are disposed on different film layers from the gate 11. The overlapping part of the source 12 and the gate 11 will generate parasitic capacitance (i.e., gate-source capacitance), which will affect the magnitude of the feed voltage. During the fabrication of the array substrate, due to process deviations, the source 12 may shift to the left or right. When the source 12 shifts to the right, the overlapping area of ​​the source 12 and the gate 11 will increase, and the parasitic capacitance of the source 12 and the gate 11 will also increase, resulting in an increase in the feed voltage. At this time, an AC voltage component will appear in the liquid crystal display panel, which can easily cause screen flicker and image retention problems.

[0004] like Figure 2 As shown, to solve the problem of parasitic capacitance changes between the gate 11 and the source 12 due to process deviations, a long arm 120 and a compensation part 121 are added at the source 12. The compensation part 121 and the source part 122 are respectively connected to the long arm 120. A compensation electrode 110 connected to the gate 11 is added at the gate 11, and the compensation part 121 overlaps with the compensation electrode 110. This ensures that when the source 12 is offset, the parasitic capacitance between the source 12 and the gate 11 remains unchanged. However, the added long arm 120 will compress the area of ​​the pixel electrode 14 in the vertical direction, which reduces the aperture ratio of the array substrate and thus leads to a decrease in the transmittance of the display panel.

[0005] In summary, existing array substrates suffer from reduced aperture ratio due to efforts to mitigate gate-source capacitance variations. Therefore, it is necessary to provide an array substrate that addresses this deficiency. Summary of the Invention

[0006] This application provides an array substrate that can improve the aperture ratio of the array substrate while achieving gate-source capacitance compensation.

[0007] This application provides an array substrate, including a gate, a compensation electrode, an array substrate-side common electrode, and a source electrode. The compensation electrode is disposed on one side of the gate and connected to the gate. The source electrode is disposed on a different layer from the gate electrode and the compensation electrode.

[0008] The source electrode includes a storage capacitor portion, a source electrode portion, and a compensation portion. The source electrode portion and the compensation portion are disposed on opposite sides of the storage capacitor portion and connected to the storage capacitor portion. A portion of the source electrode portion overlaps with the gate electrode, and a portion of the compensation portion overlaps with the compensation electrode. The source electrode and the array substrate-side common electrode are disposed in different layers. In the extending direction of the source electrode portion, the portion where the storage capacitor portion intersects with the source electrode portion also at least partially overlaps with the array substrate-side common electrode. In the extending direction of the compensation portion, the portion where the storage capacitor portion intersects with the compensation portion also at least partially overlaps with the array substrate-side common electrode.

[0009] According to one embodiment of this application, the array substrate includes a gate line and a pixel electrode. The gate and the compensation electrode are disposed on the same side of the gate line and connected to the gate line. The pixel electrode is disposed on a different layer from the source electrode and is in contact with the storage capacitor through a contact hole.

[0010] The contact hole is disposed between the gate and the compensation portion, and in a direction perpendicular to the extension direction of the source portion or the compensation portion, the minimum distance between the contact hole and the gate line is less than or equal to the width of the gate.

[0011] According to one embodiment of this application, in a direction perpendicular to the extending direction of the source portion or the compensation portion, the distance between the storage capacitor portion and the gate line is less than or equal to the distance between the source portion and the gate line, and the distance between the storage capacitor portion and the gate line is less than or equal to the distance between the compensation portion and the gate line.

[0012] According to one embodiment of this application, the extension direction of the source electrode is parallel to the extension direction of the compensation portion, and the extension direction of the source electrode is opposite to the extension direction of the compensation portion.

[0013] According to one embodiment of this application, in a direction perpendicular to the extending direction of the source portion or the compensation portion, a portion of the width of the source portion is equal to the width of the compensation portion.

[0014] According to one embodiment of this application, in the extending direction of the source portion or the compensation portion, the source portion and the compensation portion at least partially overlap or are offset.

[0015] According to one embodiment of this application, in the extending direction of the source portion or the compensation portion, the edge of one of the storage capacitor portion and the array substrate side common electrode extends beyond the same side edge of the other.

[0016] In a direction perpendicular to the extending direction of the source portion or the compensation portion, the edge of one of the storage capacitor portion and the array substrate side common electrode extends beyond the edge of the other on the same side.

[0017] According to one embodiment of this application, in the extending direction of the source portion or the compensation portion, the distance between the edge of the storage capacitor portion and the edge of the common electrode on the array substrate side is between 3 micrometers and 5 micrometers, and the distance between the gate and the storage capacitor portion is greater than or equal to 4.3 micrometers.

[0018] According to one embodiment of this application, in a direction perpendicular to the extending direction of the source portion or the compensation portion, the distance between the edge of the storage capacitor portion and the edge on the same side of the common electrode on the array substrate side is between 3 micrometers and 5 micrometers, and the width of the source portion is between 7 micrometers and 10 micrometers.

[0019] According to one embodiment of this application, the width of the source portion is between 7 micrometers and 10 micrometers in a direction perpendicular to the extending direction of the source portion or the compensation portion.

[0020] According to one embodiment of this application, the array substrate further includes a drain electrode, and in the extending direction of the source portion or the compensation portion, the distance between the drain electrode and the edge of the gate near the storage capacitor portion is greater than or equal to 7 micrometers.

[0021] The beneficial effects of the embodiments of this application are as follows: The embodiments of this application provide an array substrate, which includes a gate, a compensation electrode, and an array substrate-side common electrode. The compensation electrode is disposed on one side of the gate and connected to the gate. The array substrate also includes a source electrode, which is disposed on a different layer from the gate electrode and the compensation electrode. The source electrode includes a storage capacitor portion, a source portion, and a compensation portion. A portion of the source portion overlaps with the gate electrode, and a portion of the compensation portion overlaps with the compensation electrode. This ensures that the parasitic capacitance between the gate electrode and the source electrode remains unchanged. By disposing the source portion and the compensation portion on opposite sides of the storage capacitor portion and connecting the source portion and the compensation portion using the storage capacitor portion, the area occupied by the source electrode can be reduced, thereby increasing the aperture ratio of the array substrate. Attached Figure Description

[0022] To more clearly illustrate the technical solutions in the embodiments or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0023] Figure 1 This is a schematic diagram of the structure of the first pixel region in the related technology;

[0024] Figure 2 This is a schematic diagram of the structure of the second type of pixel region in the related technology;

[0025] Figure 3 This is a schematic diagram of the structure of a first type of pixel region provided in an embodiment of this application;

[0026] Figure 4 This is a partial film layer diagram of the first type of pixel region provided in the embodiments of this application;

[0027] Figure 5 This is a schematic diagram of the structure of the second type of pixel region provided in the embodiments of this application;

[0028] Figure 6 This is a schematic diagram of the structure of the third type of pixel region provided in the embodiments of this application;

[0029] Figure 7 This is a schematic diagram of the structure of the fourth type of pixel region provided in the embodiments of this application;

[0030] Figure 8 This is a schematic diagram of the structure of the fifth type of pixel region provided in the embodiments of this application;

[0031] Figure 9 This is a schematic diagram of the structure of the display panel provided in an embodiment of this application. Detailed Implementation

[0032] The following descriptions of the embodiments are based on the accompanying illustrations and are used to illustrate specific embodiments in which this application can be implemented. Directional terms used in this application, such as [up], [down], [front], [back], [left], [right], [inner], [outer], [side], etc., are only for reference to the accompanying drawings. Therefore, the directional terms used are for illustrative and understanding purposes and not for limiting the application. In the figures, structurally similar units are represented by the same reference numerals.

[0033] The present application will be further described below with reference to the accompanying drawings and specific embodiments.

[0034] This application provides an array substrate and a display panel that can improve the aperture ratio of the array substrate and the display panel while achieving gate-source capacitance compensation.

[0035] This application provides an array substrate with multiple pixel regions. Each pixel region is a region defined by two gate lines GL and two data lines DL. Thin film transistors and pixel electrodes, which serve as switching components, are provided within the pixel region.

[0036] like Figure 3 As shown, the array substrate may include a compensation electrode 22, which is disposed on one side of the gate 21. The gate 21 is connected to the compensation electrode 22, that is, the gate 21 is electrically connected to the compensation electrode 22.

[0037] In this embodiment, the gate 21 and the compensation electrode 22 are spaced apart, there is a gap between the gate 21 and the compensation electrode 22, and the gate 21 and the compensation electrode 22 may be located in the same film structure.

[0038] In other embodiments, the gate 21 and the compensation electrode 22 can be located in different film structures, depending on the actual situation and specific requirements. As long as the gate 21 and the compensation electrode 22 are connected and there is a gap between the gate 21 and the compensation electrode 22 in a direction parallel to the plane where the gate 21 or the compensation electrode 22 is located, it is not a unique limitation here.

[0039] Furthermore, the array substrate may also include a source electrode 24, which is disposed in a different layer from the gate electrode 21 and the compensation electrode 22, that is, the gate electrode 21 and the compensation electrode 22 are both located in different film layer structures from the source electrode 24.

[0040] For example, the array substrate may include a substrate, a first metal layer, and a second metal layer. The first metal layer may be disposed between the substrate and the second metal layer. The first metal layer may also be referred to as a gate metal layer. The gate 21 and the compensation electrode 22 may be disposed on the first metal layer. The second metal layer may also be referred to as a source / drain electrode metal layer. The source electrode 24 may be disposed on the second metal layer.

[0041] Furthermore, the source electrode 24 includes a storage capacitor portion 240, a source electrode portion 241, and a compensation portion 242. The source electrode portion 241 and the compensation portion 242 are disposed on opposite sides of the storage capacitor portion 240 and connected to the storage capacitor portion 240. A portion of the source electrode portion 241 overlaps with the gate electrode 21, and a portion of the compensation portion 242 overlaps with the compensation electrode 22.

[0042] In this embodiment, the source portion 241 is disposed on the side of the storage capacitor portion 240 near the gate 21, and the compensation portion 242 is disposed on the side of the storage capacitor portion 240 near the compensation electrode 22.

[0043] It should be noted that by providing the compensation electrode 22 on one side of the gate 21, the compensation electrode 22 is connected to the gate 21, and the storage capacitor portion 240 is disposed between the source portion 241 and the compensation portion 242. The storage capacitor portion 240 extends toward the gate 21 to form the source portion 241, and a portion of the source portion 241 overlaps with the gate 21. The storage capacitor portion 240 extends toward the compensation electrode 22 to form the compensation portion 242, and a portion of the compensation portion 242 overlaps with the compensation electrode 22. In this structure, the parasitic capacitance between the source 24 and the gate 21 is equal to the capacitance between the source portion 241 and the gate 21 plus the capacitance between the compensation portion 242 and the compensation electrode 22.

[0044] When the source electrode 24 shifts to the right due to process variations, the overlap area between the source electrode 241 and the gate electrode 21 increases, and the capacitance between them also increases. Conversely, the overlap area between the compensation electrode 242 and the compensation electrode 22 decreases, and the capacitance between them also decreases. The change in capacitance between the source electrode 241 and the gate electrode 21 equals the change in capacitance between the compensation electrode 242 and the compensation electrode 22, thus keeping the parasitic capacitance between the source electrode 24 and the gate electrode 21 constant. Similarly, when the source electrode 24 shifts to the left due to process variations, the parasitic capacitance between the source electrode 24 and the gate electrode 21 remains unchanged. Therefore, the technical solution provided in this application can solve the problem of changes in gate-source capacitance caused by process variations.

[0045] Furthermore, the array substrate also includes an array substrate-side common electrode 23, which is disposed on the same layer as the gate 21 and has a gap between them. The array substrate-side common electrode 23 is disposed on a different layer from the source 24 and overlaps with the storage capacitor portion 240 of the source 24 to form a storage capacitor. The storage capacitor portion 240 can serve as the upper electrode of the storage capacitor, and the array substrate-side common electrode 23 can serve as the lower electrode of the storage capacitor.

[0046] Furthermore, in the extending direction of the source portion 241, the portion where the storage capacitor portion 240 intersects with the source portion 241 also at least partially overlaps with the array substrate-side common electrode 23; in the extending direction of the compensation portion 242, the portion where the storage capacitor portion 240 intersects with the compensation portion 242 also at least partially overlaps with the array substrate-side common electrode 23.

[0047] like Figure 3 As shown, both the source portion 241 and the compensation portion 242 are strip-shaped. The extending direction of the source portion 241 is parallel to the extending direction of the compensation portion 242, and both are parallel to the first direction X. The extending direction of the source portion 241 is opposite to the extending direction of the compensation portion 242. In the first direction X, the portion where the storage capacitor portion 240 intersects with the source portion 241 partially overlaps with the array substrate-side common electrode 23, and the portion where the storage capacitor portion 240 intersects with the compensation portion 242 also partially overlaps with the array substrate-side common electrode 23.

[0048] The portions where the storage capacitor portion 240 intersects with the source portion 241 and the portions where the storage capacitor portion 240 intersects with the compensation portion 242 can be considered as portions of the storage capacitor portion 240 located between the source portion 241 and the compensation portion 242, and connected to both the source portion 241 and the compensation portion 242 respectively. These portions partially overlap with the common electrode 23 on the array substrate side. Similarly, portions of the storage capacitor portion 240 that do not intersect with the source portion 241 and the compensation portion 242 can also at least partially overlap to jointly form a storage capacitor. In this structure, it can be considered that the source portion 241 and the compensation portion 242 are directly connected to the storage capacitor portion 240. It should be noted that, compared to... Figure 2 The related technologies shown, and the technical solutions provided in the embodiments of this application, can be cancelled. Figure 2 The long-arm design of the source electrode directly connects the source electrode portion 241 and the compensation portion 242 to the storage capacitor portion 240, which reduces the space occupied by the source electrode 24 in the second direction Y, thereby increasing the aperture ratio of the pixel region. In one embodiment, using the technical solution provided in this application, approximately 12 micrometers of space can be saved in the second direction Y.

[0049] like Figure 3 As shown, the array substrate also includes a gate line GL and a pixel electrode 26. The gate 21 and the compensation electrode 22 are disposed on the same side of the gate line GL. The compensation electrode 22 is connected to the gate 21 through the gate line GL. In this structure, the space of the pixel electrode can be avoided by adding the compensation electrode 22, thereby ensuring the aperture ratio of the pixel area.

[0050] The pixel electrode 26 is disposed on a different layer from the source electrode 24 and is in contact with the storage capacitor portion 240 through a contact hole OH. The pixel electrode 26 may be disposed on the side of the source electrode 24 that is away from the substrate.

[0051] It should be noted that Figure 3In other accompanying figures, the pixel electrode 26 is referred to only as a blocky area. Figure 3 The shapes and sizes of the pixel electrodes 26 shown in the other accompanying drawings are not the shapes and sizes of the pixel electrodes 26 as described in the actual application.

[0052] Furthermore, the contact hole OH is disposed between the gate 21 and the compensation electrode 22. In a direction perpendicular to the extending direction of the source portion 241 or the compensation portion 242, the minimum distance a4 between the contact hole OH and the gate line GL is less than or equal to the width a5 of the gate 21. In this structure, by creating a contact hole OH in the area between the gate 21 and the compensation electrode 22 to connect the pixel electrode 26 and the source 24, not only can the distance between the contact hole OH and the gate line GL be reduced, and the space occupied by the contact hole OH be decreased, but the area of ​​the pixel electrode 26 can also be increased, thereby improving the aperture ratio of the pixel area and thus increasing the transmittance of the array substrate.

[0053] In one embodiment, such as Figure 3 As shown, the contact hole OG is disposed between the gate 21 and the compensation electrode 22. In a direction perpendicular to the extending direction of the source portion 241 or the compensation portion 242, the minimum distance a4 between the contact hole OH and the gate line GL is less than the width a5 of the gate 21. In some other embodiments, the minimum distance a4 between the contact hole OH and the gate line GL may also be equal to the width a5 of the gate 21.

[0054] Furthermore, the array substrate also includes a drain 25 and an active layer (not shown in the figure). The active layer is disposed on a different layer from the gate 21. The active layer and the gate 21 are at least partially overlapped. The drain 25 is disposed on a different layer from the gate 21. The drain 25 may be disposed on the same layer as the source 24 and is connected to the active layer respectively.

[0055] In this embodiment, the active layer may be disposed on the side of the gate 21 opposite to the substrate, and the source 24 and the drain 25 may be disposed on the side of the active layer opposite to the gate 21. In other embodiments, the stacking order of the gate 21, the active layer, the source 24, and the drain 25 may also be modified appropriately, and is not limited here.

[0056] Furthermore, in this embodiment, the pixel electrode in the array substrate has a 4-domain structure. In other embodiments, the technical solution provided in this application is also applicable to pixel electrodes with an 8-domain structure, and is not the only one described here.

[0057] Furthermore, the array substrate also includes a data line DL, the gate line GL is disposed on the same layer as the gate 21, the data line DL is disposed on the same layer as the source 24, the gate line GL extends along a first direction X, and the data line DL extends along a second direction Y, wherein the first direction X and the second direction Y intersect.

[0058] In this embodiment, the first direction X and the second direction Y can be perpendicular. In other embodiments, depending on the actual situation and specific needs, the first direction X and the second direction Y can be set at other angles, which is not limited here.

[0059] In this embodiment of the application, the drain 25 is connected to the data line DL, that is, the drain 25 is electrically connected to the data line DL.

[0060] Furthermore, such as Figure 3 As shown, both the source electrode portion 241 and the compensation portion 242 are strip-shaped. The extension direction of the source electrode portion 241 is parallel to the extension direction of the compensation portion 242, and both are parallel to the first direction X. The extension direction of the source electrode portion 241 is opposite to the extension direction of the compensation portion 242. With this structure, the structure of the source electrode 24 can be simplified, it is easy to manufacture, and it will not increase the manufacturing difficulty of the array substrate.

[0061] Furthermore, in a direction perpendicular to the extending direction of the source portion or the compensation portion, the width of a portion of the source portion is equal to the width of the compensation portion.

[0062] like Figure 3 As shown, in the second direction Y, the widths of the source portion 241 and the compensation portion 242 are equal. With this structure, even if the source 24 shifts due to process deviations, the area change of the overlapping portion of the source portion 241 and the gate 21 is equal to the area change of the overlapping portion of the compensation portion 242 and the compensation electrode 22, thereby ensuring that the parasitic capacitance between the source 24 and the gate 21 remains constant.

[0063] Furthermore, the distance a7 between the storage capacitor section 240 and the gate line GL is less than or equal to the distance a8 between the source section 241 and the gate line GL, and the distance a7 between the storage capacitor section 240 and the gate line GL is less than or equal to the distance a6 between the compensation section 242 and the gate line GL.

[0064] In one embodiment, such as Figure 4As shown, the distance a7 between the storage capacitor portion 240 and the gate line GL is equal to the distance a8 between the source portion 241 and the gate line GL, and the distance a7 between the storage capacitor portion 240 and the gate line GL is equal to the distance a6 between the compensation portion 242 and the gate line GL. That is, the edge of the storage capacitor portion 240 near the gate line GL is flush with the edge of the source portion 241 near the gate line GL, and the edge of the compensation portion 242 near the gate line GL. In the first direction X, the source portion 241 and the compensation portion 242 completely overlap, meaning the source portion 241 is located on the extension line of the compensation portion 242 along the first direction X. This structure reduces the space occupied by the source electrode 24, which is beneficial for increasing the area of ​​the pixel electrode and improving the aperture ratio of the pixel region.

[0065] In one embodiment, such as Figure 5 As shown, in the second direction Y, the distance a7 between the storage capacitor 240 and the gate line GL is less than the distance a8 between the source 241 and the gate line GL, and the distance a7 between the storage capacitor 240 and the gate line GL is less than the distance a6 between the compensation part 242 and the gate line GL. In the first direction X, the source part 241 and the compensation part 242 partially overlap, but this is not a unique limitation.

[0066] In one embodiment, the source portion 241 and the compensation portion 242 can also be completely offset in the first direction X, that is, the source portion 241 is arranged to avoid the extension line of the compensation portion 242. With this structure, the area of ​​the source 24 can be increased, thereby reducing the contact resistance of the source 24, reducing energy loss, and improving the performance of the thin-film transistor.

[0067] Furthermore, in the extending direction of the source portion 241 or the compensation portion 242, the edge of one of the storage capacitor portion 240 and the array substrate side common electrode 23 extends beyond the same side edge of the other; in a direction perpendicular to the extending direction of the source portion 241 or the compensation portion 242, the edge of one of the storage capacitor portion 240 and the array substrate side common electrode 23 extends beyond the same side edge of the other.

[0068] In one embodiment, such as Figure 3As shown, in the first direction X, the left edge of the array substrate-side common electrode 23 extends beyond the left edge of the storage capacitor portion 240, and the right edge of the array substrate-side common electrode 23 extends beyond the right edge of the storage capacitor portion 240; in the second direction Y, the upper edge of the storage capacitor portion 240 extends beyond the upper edge of the array substrate-side common electrode 23, and the lower edge of the storage capacitor portion 240 extends beyond the lower edge of the array substrate-side common electrode 23. With this structure, the accuracy of the source electrode 24 alignment can be ensured, and the offset of the source electrode 24 can be reduced, thereby improving the situation where the parasitic capacitance between the source electrode 24 and the gate electrode 21 changes.

[0069] Furthermore, in the extending direction of the source portion or the compensation portion, the distance between the edge of the storage capacitor portion and the same-side edge of the array substrate side common electrode is between 3 micrometers and 5 micrometers.

[0070] like Figure 3 As shown, in the first direction X, the left edge of the array substrate-side common electrode 23 extends beyond the left edge of the storage capacitor portion 240, and the distance x between the left edge of the array substrate-side common electrode 23 and the left edge of the storage capacitor portion 240 is between 3 micrometers and 5 micrometers. Similarly, the right edge of the array substrate-side common electrode 23 extends beyond the right edge of the storage capacitor portion 240, and the distance x between the right edge of the array substrate-side common electrode 23 and the right edge of the storage capacitor portion 240 is between 3 micrometers and 5 micrometers. In practical applications, the value of x can be, but is not limited to, 3, 3.5, 4, 4.5, or 5, as long as it is between 3 and 5.

[0071] In the second direction Y, the upper edge of the storage capacitor portion 240 extends beyond the upper edge of the array substrate-side common electrode 23, and the distance y between the upper edge of the storage capacitor portion 240 and the upper edge of the array substrate-side common electrode 23 is between 3 micrometers and 5 micrometers; the upper edge of the storage capacitor portion 240 extends beyond the lower edge of the array substrate-side common electrode 23, and the distance y between the upper edge of the storage capacitor portion 240 and the lower edge of the array substrate-side common electrode 23 is between 3 micrometers and 5 micrometers. Specifically, the value of y can be, but is not limited to, 3, 3.5, 4, 4.5, or 5, as long as it is between 3 and 5.

[0072] Furthermore, in a direction perpendicular to the extending direction of the source portion or the compensation portion, the width of the source portion is between 7 micrometers and 10 micrometers.

[0073] like Figure 4As shown, in the second direction Y, the width a1 of the source portion 241 is between 7 micrometers and 10 micrometers. Specifically, the value of a1 can be, but is not limited to, 7, 8, 9, or 10, as long as it is between 7 and 10.

[0074] Furthermore, the distance between the drain and the edge of the gate near the storage capacitor portion is greater than or equal to 7 micrometers.

[0075] like Figure 4 As shown, in the first direction X, the distance a2 between the drain 25 and the edge of the gate 21 near the storage capacitor portion 240 is greater than or equal to 7 micrometers. Specifically, the value of a2 can be, but is not limited to, 7, 7.5, 8, 8.5, or 9, as long as it is greater than or equal to 7.

[0076] Furthermore, the distance between the gate and the storage capacitor is greater than or equal to 4.3 micrometers.

[0077] like Figure 4 As shown, in the first direction X, the distance a3 between the gate 21 and the storage capacitor section 240 is greater than or equal to 4.3 micrometers. Specifically, the value of a3 can be, but is not limited to, 4.3, 4.5, 4.8, 5, or 6, etc., as long as it is greater than or equal to 4.3.

[0078] In this structure, by reducing the width a1 of the source portion 241 and increasing the distance a2 between the drain portion 25 and the edge of the gate 21 near the storage capacitor portion 240, and the distance a3 between the storage capacitor portion 240 and the gate 21, the electron transport path is extended and the electron transport capability is weakened. This prevents electrons from being transported to the storage capacitor through the path of the source portion 241, the gate 21 and the storage capacitor portion 240, which would cause a decrease in storage capacitance, a decrease in pixel holding voltage, leakage, and smudge-like defects.

[0079] In one embodiment, such as Figure 6As shown, the periphery of the array substrate-side common electrode 23 can extend beyond the periphery of the storage capacitor portion 240. That is, the storage capacitor portion 240 is recessed from the periphery of the array substrate-side common electrode 23. The left and right edges, as well as the top and bottom edges of the array substrate-side common electrode 23, extend beyond the same-side edge of the storage capacitor portion 240, and the extension distance should be between 3 micrometers and 5 micrometers. In the first direction X, the portion where the storage capacitor portion 240 intersects with the source portion 241 can completely overlap with the array substrate-side common electrode 23, and the portion where the storage capacitor portion 240 intersects with the compensation portion 242 can also completely overlap with the array substrate-side common electrode 23. With this structure, the accuracy of the source electrode 24 alignment can also be ensured, reducing the offset of the source electrode 24, thereby improving the situation where the parasitic capacitance between the source electrode 24 and the gate 21 changes.

[0080] In one embodiment, such as Figure 7 As shown, in the first direction X, the left edge of the storage capacitor portion 240 extends beyond the left edge of the array substrate-side common electrode 23, and the right edge of the storage capacitor portion 240 extends beyond the right edge of the array substrate-side common electrode 23; in the second direction Y, the upper edge of the array substrate-side common electrode 23 extends beyond the upper edge of the storage capacitor portion 240, and the lower edge of the array substrate-side common electrode 23 extends beyond the lower edge of the storage capacitor portion 240, with the extension distance being between 3 micrometers and 5 micrometers. With this structure, the accuracy of the source electrode 24 alignment can also be ensured, reducing the offset of the source electrode 24, thereby improving the situation where the parasitic capacitance between the source electrode 24 and the gate 21 changes.

[0081] In one embodiment, such as Figure 8 As shown, the peripheral edges of the storage capacitor portion 240 can extend beyond the peripheral edges of the array substrate-side common electrode 23. That is, the storage capacitor portion 240 is wider than the periphery of the array substrate-side common electrode 23. The left and right edges, as well as the top and bottom edges of the storage capacitor portion 240, all extend beyond the same-side edges of the array substrate-side common electrode 23, and the extension distance should be between 3 micrometers and 5 micrometers. With this structure, the accuracy of the source electrode 24 alignment can also be ensured, reducing the offset of the source electrode 24, thereby improving the situation where the parasitic capacitance between the source electrode 24 and the gate 21 changes. It should be noted that since the array substrate-side common electrode 23 is covered by the storage capacitor portion 240, therefore... Figure 8 The array substrate-side common electrode 23 is not shown in the figure.

[0082] In practical applications, depending on the actual situation and specific requirements, the combination of the array substrate side common electrode 23 and the storage capacitor section 240 in the first direction X and the second direction Y can be adjusted to be either outward or inward, and no single limitation is made here.

[0083] Based on the array substrate provided in the above embodiments of this application, embodiments of this application also provide a display panel, such as... Figure 9 As shown, the display panel 10 includes a counter substrate 100 and an array substrate 200 as described above, wherein the counter substrate 100 and the array substrate 200 are disposed opposite to each other. The display panel may further include a liquid crystal layer disposed between the counter substrate 100 and the array substrate 200.

[0084] Based on the display panel provided in the above embodiments of this application, this application also provides a display device, which may include a backlight module and a display panel as described above, wherein the backlight module is disposed on one side of the display panel.

[0085] The beneficial effects of the embodiments of this application are as follows: The embodiments of this application provide an array substrate and a display panel. The array substrate includes a gate, a compensation electrode, and a common electrode on the array substrate side. The compensation electrode is disposed on one side of the gate and connected to the gate. The array substrate also includes a source electrode. The source electrode and the gate electrode are disposed on different layers, and the source electrode and the compensation electrode are disposed on different layers. The source electrode includes a storage capacitor portion, a source electrode portion, and a compensation portion. A portion of the source electrode portion overlaps with the gate electrode, and a portion of the compensation portion overlaps with the compensation electrode. This ensures that the parasitic capacitance between the gate electrode and the source electrode remains unchanged. By disposing the source electrode portion and the compensation portion on opposite sides of the storage capacitor portion and connecting the source electrode portion and the compensation portion using the storage capacitor portion, the area occupied by the source electrode can be reduced, thereby improving the aperture ratio of the array substrate.

[0086] In summary, although the present application discloses the preferred embodiments as described above, the above preferred embodiments are not intended to limit the present application. Those skilled in the art can make various modifications and refinements without departing from the spirit and scope of the present application. Therefore, the scope of protection of the present application is based on the scope defined by the claims.

Claims

1. An array substrate, characterized in that, It includes a gate, a compensation electrode, an array substrate-side common electrode, and a source electrode. The compensation electrode is disposed on one side of the gate and connected to the gate. The source electrode is disposed on a different layer from the gate electrode and the compensation electrode is disposed on a different layer. The source electrode includes a storage capacitor portion, a source electrode portion, and a compensation portion. The source electrode portion and the compensation portion are disposed on opposite sides of the storage capacitor portion and connected to the storage capacitor portion. A portion of the source electrode portion overlaps with the gate electrode, and a portion of the compensation portion overlaps with the compensation electrode. The source electrode and the array substrate-side common electrode are disposed in different layers. In the extending direction of the source electrode portion, the portion where the storage capacitor portion intersects with the source electrode portion also at least partially overlaps with the array substrate-side common electrode. In the extending direction of the compensation portion, the portion where the storage capacitor portion intersects with the compensation portion also at least partially overlaps with the array substrate-side common electrode.

2. The array substrate as described in claim 1, characterized in that, The array substrate includes a gate line and a pixel electrode. The gate and the compensation electrode are disposed on the same side of the gate line and connected to the gate line. The pixel electrode is disposed on a different layer from the source electrode and is in contact with the storage capacitor through a contact hole. The contact hole is disposed between the gate and the compensation electrode, and in a direction perpendicular to the extension direction of the source portion or the compensation portion, the minimum distance between the contact hole and the gate line is less than or equal to the width of the gate.

3. The array substrate as described in claim 2, characterized in that, In a direction perpendicular to the extending direction of the source portion or the compensation portion, the distance between the storage capacitor portion and the gate line is less than or equal to the distance between the source portion and the gate line, and the distance between the storage capacitor portion and the gate line is less than or equal to the distance between the compensation portion and the gate line.

4. The array substrate as described in claim 1, characterized in that, The extension direction of the source electrode is parallel to the extension direction of the compensation part, and the extension direction of the source electrode is opposite to the extension direction of the compensation part.

5. The array substrate as described in claim 4, characterized in that, In a direction perpendicular to the extending direction of the source portion or the compensation portion, the width of a portion of the source portion is equal to the width of the compensation portion.

6. The array substrate as described in claim 4, characterized in that, In the extending direction of the source portion or the compensation portion, the source portion and the compensation portion at least partially overlap or are offset.

7. The array substrate as described in claim 4, characterized in that, In the extending direction of the source portion or the compensation portion, the edge of one of the storage capacitor portion and the array substrate side common electrode extends beyond the same side edge of the other. In a direction perpendicular to the extending direction of the source portion or the compensation portion, the edge of one of the storage capacitor portion and the array substrate side common electrode extends beyond the edge of the other on the same side.

8. The array substrate as described in claim 7, characterized in that, In the extending direction of the source portion or the compensation portion, the distance between the edge of the storage capacitor portion and the edge of the common electrode on the array substrate side is between 3 micrometers and 5 micrometers, and the distance between the gate and the storage capacitor portion is greater than or equal to 4.3 micrometers.

9. The array substrate as claimed in claim 7, characterized in that, In a direction perpendicular to the extending direction of the source portion or the compensation portion, the distance between the edge of the storage capacitor portion and the edge on the same side of the common electrode on the array substrate side is between 3 micrometers and 5 micrometers, and the width of the source portion is between 7 micrometers and 10 micrometers.

10. The array substrate as claimed in claim 1, characterized in that, The array substrate further includes a drain electrode, and in the extending direction of the source portion or the compensation portion, the distance between the drain electrode and the edge of the gate near the storage capacitor portion is greater than or equal to 7 micrometers.

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