Processor scheduling methods, devices, electronic equipment, and storage media

Abstract

This application discloses a processor scheduling method, apparatus, electronic device, and storage medium. The processor scheduling method is applied to an electronic device. The processor of the electronic device includes a first processor core and a second processor core, which share a common power domain. The processing power of the first processor core is higher than that of the second processor core. The processor scheduling method includes: if the first processor core meets the conditions corresponding to an idle state and the second processor core is in an operating state, obtaining the current operating frequency of the first processor core as a first frequency; obtaining the operating frequency of the second processor core as a second frequency; if the voltage corresponding to the first frequency is greater than the voltage corresponding to the second frequency, adjusting the operating frequency of the first processor core to a third frequency, wherein the voltage corresponding to the third frequency is less than the voltage corresponding to the second frequency. This method can reduce the power consumption of the electronic device.

Description

Technical Field

[0001] This application relates to the field of electronic equipment technology, and more specifically, to a processor scheduling method, apparatus, electronic equipment, and storage medium. Background Technology

[0002] With the rapid advancement of technology and living standards, electronic devices are becoming increasingly widespread. Furthermore, people's performance demands on these devices are also rising, leading to the emergence of devices equipped with multi-core processors. However, while increasing the configuration capabilities of electronic devices, it also results in greater power consumption. Summary of the Invention

[0003] In view of the above problems, this application proposes a processor scheduling method, apparatus, electronic device and storage medium.

[0004] In a first aspect, embodiments of this application provide a processor scheduling method applied to an electronic device. The processor of the electronic device includes a first processor core and a second processor core, the first processor core and the second processor core sharing a power domain, the processing power of the first processor core being higher than that of the second processor core. The method includes: if the first processor core meets the conditions corresponding to an idle state and the second processor core is in a working state, obtaining the current operating frequency of the first processor core as a first frequency; obtaining the operating frequency of the second processor core as a second frequency; if the voltage corresponding to the first frequency is greater than the voltage corresponding to the second frequency, adjusting the operating frequency of the first processor core to a third frequency, wherein the voltage corresponding to the third frequency is less than the voltage corresponding to the second frequency.

[0005] Secondly, embodiments of this application provide a processor scheduling device applied to an electronic device. The processor of the electronic device includes a first processor core and a second processor core, which share a common power domain. The processing power of the first processor core is higher than that of the second processor core. The device includes a first frequency acquisition module, a second frequency acquisition module, and a frequency adjustment module. The first frequency acquisition module is used to acquire the current operating frequency of the first processor core as a first frequency if the first processor core meets the conditions corresponding to an idle state and the second processor core is in a working state. The second frequency acquisition module is used to acquire the operating frequency of the second processor core as a second frequency. The frequency adjustment module is used to adjust the operating frequency of the first processor core to a third frequency if the voltage corresponding to the first frequency is greater than the voltage corresponding to the second frequency, wherein the voltage corresponding to the third frequency is less than the voltage corresponding to the second frequency.

[0006] Thirdly, embodiments of this application provide an electronic device, including: one or more processors, the processors including a first processor core and a second processor core; a memory; one or more application programs, wherein the one or more application programs are stored in the memory and configured to be executed by the one or more processors, and the one or more application programs are configured to execute the processor scheduling method provided in the first aspect above.

[0007] Fourthly, embodiments of this application provide a computer-readable storage medium storing program code, which can be invoked by a processor to execute the processor scheduling method provided in the first aspect above.

[0008] The solution provided in this application includes an electronic device processor comprising a first processor core and a second processor core sharing a common power domain. The processing power of the first processor core is higher than that of the second processor core. When the first processor core meets the conditions corresponding to an idle state, and the second processor core is in an active state, the current operating frequency of the first processor core is obtained as a first frequency, and the operating frequency of the second processor core is obtained as a second frequency. If the voltage corresponding to the first frequency is greater than the voltage corresponding to the second frequency, the operating frequency of the first processor core is adjusted to a third frequency, wherein the voltage corresponding to the third frequency is less than the voltage corresponding to the second frequency. Therefore, when the first and second processor cores share a common power domain, when the first processor core enters an idle state, it can be powered at the voltage corresponding to the operating frequency of the second processor core in an active state. Furthermore, since the voltage corresponding to the operating frequency of the second processor core is relatively lower, the power consumption of the electronic device can be reduced. Attached Figure Description

[0009] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0010] Figure 1 A schematic diagram of a system architecture provided in an embodiment of this application is shown.

[0011] Figure 2 A flowchart of a processor scheduling method according to an embodiment of this application is shown.

[0012] Figure 3 A flowchart of a processor scheduling method according to another embodiment of this application is shown.

[0013] Figure 4 A flowchart of a processor scheduling method according to yet another embodiment of this application is shown.

[0014] Figure 5 A flowchart of a processor scheduling method according to another embodiment of this application is shown.

[0015] Figure 6 A flowchart of a processor scheduling method according to another embodiment of this application is shown.

[0016] Figure 7 A block diagram of a processor scheduling apparatus according to an embodiment of this application is shown.

[0017] Figure 8 This is a block diagram of an electronic device for executing a processor scheduling method according to an embodiment of this application.

[0018] Figure 9 This is a storage unit in this application embodiment for storing or carrying program code that implements the processor scheduling method according to this application embodiment. Detailed Implementation

[0019] To enable those skilled in the art to better understand the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings.

[0020] With the rapid development of mobile internet technology, electronic devices (such as smartphones and tablets) have permeated every aspect of life. Furthermore, users' demands for the performance of electronic devices are increasing, leading to the emergence of multi-core processors. A multi-core processor refers to a processor that includes multiple processor cores. However, while adopting a multi-core architecture, it also increases the power consumption of electronic devices, thus leading to the development of the BIG-LITTLE processor architecture. The BIG-LITTLE processor architecture allocates the appropriate number of processor cores to the appropriate tasks, thereby reducing the power consumption of electronic devices.

[0021] Furthermore, since different processor cores require a separate power supply module for power supply and voltage control, some manufacturers, for cost reasons, group different processor cores into the same power domain. For processor cores within the same power domain, a single independent power supply and module can be used for unified power supply and voltage control, thereby saving on the number of power supply modules and thus reducing costs. Specifically, for processor architectures employing super-large cores, large cores, and small cores, the super-large cores and large cores share a single power domain.

[0022] In related technologies, processor cores with different processing capabilities are allocated to the same power domain. In particular, for processor architectures that use super-large cores, large cores, and small cores, the super-large cores and large cores share a single power domain.

[0023] After extensive research, the inventors discovered that in certain scenarios, processor cores with relatively high processing power enter an idle state at a higher frequency. Since the more powerful and less powerful processor cores share the same power domain, if the less powerful core is active and operating at a low frequency, the voltage corresponding to that low frequency is lower than the voltage corresponding to the high frequency chosen by the more powerful core. Consequently, a relatively higher voltage is used for power supply, but the more powerful core is idle and not processing tasks, leading to increased power consumption. For example, in scenarios where the super-large core and the large core share a power domain, during web page loading, the processor load is heavy, so the super-large core will be activated, and its operating frequency will be high. When the load is not heavy during loading, the super-large core will enter an idle state (at which time the super-large core frequency is still high), and the remaining tasks will be executed by the small core or the large core. After the super-large core enters an idle state at a high frequency, since the current load is not heavy, the large core will also be triggered by the scheduler to adjust its frequency and try to enter a low frequency point. If the voltage corresponding to the low frequency point selected by the large core is lower than the voltage corresponding to the high frequency of the super-large core, the high voltage corresponding to the high frequency of the super-large core will be maintained during hardware voting, thus increasing power consumption.

[0024] To address the aforementioned problems, the inventors have proposed a processor scheduling method, apparatus, electronic device, and storage medium according to embodiments of this application. This allows for the following scenario: when the first processor core and the second processor core share a single power domain, the second processor core, which is in an idle state, can be powered at the voltage corresponding to its operating frequency. Furthermore, since the voltage corresponding to the operating frequency of the second processor core is relatively low, the power consumption of the electronic device can be reduced. The specific processor scheduling method will be described in detail in subsequent embodiments.

[0025] The system architecture of the electronic device to which the processor scheduling method provided in the embodiments of this application is applied will be described below.

[0026] Please see Figure 1 Electronic devices may include Figure 1 The system architecture 10 shown may include an operating system 20, a processor 110, and multiple power domains (such as...). Figure 1 The first power domain 141 and the second power domain 142 are shown. Processor 110 may include multiple processor cores, for example, Figure 1 The first processor core 111, the second processor core 112, the third processor core 113, and the fourth processor core 114 are shown.

[0027] In some implementations, the multiple processor cores of processor 110 can be divided into multiple power domains based on the physical hardware architecture, with each power domain including at least two processor cores. This reduces the number of power modules and lowers costs. For example, Figure 1 In the system architecture shown, the first processor core 111 and the second processor core 112 can be assigned to the first power domain 141, and the third processor core 113 and the fourth processor core 114 can be assigned to the second power domain 142.

[0028] In this context, a power domain refers to an area that allows for unified power supply and voltage control. Within the same power domain, independent power modules can be used to power and control the voltage of the processor cores. System architecture 10 may include one or more power domains ( Figure 1 (Only two are shown in the image). Of course, for processor cores located in the same power domain, the devices associated with the processor core can also be powered and have their voltage controlled by that power domain. The devices associated with the processor core can be caches, memory controllers, etc., and are not limited here.

[0029] Scheduler 11 may be a computer program running in operating system 200 for task scheduling. Operating system 200 can interact with front-end application 12, which can generate one or more processing tasks (such as...). Figure 1 The processing tasks shown are 1 to n (where n is a positive integer). Scheduler 11 can schedule the processing tasks generated by front-end application 12 to one or more processor cores in processor 110 so that the processor cores can execute the tasks. Scheduler 11 can allocate processing tasks according to the processing tasks generated by front-end application 12 and the actual load of each processor core, thereby reducing the power consumption of electronic devices.

[0030] Optionally, the scheduler 11 can run on any active processor core. Of course, the scheduler 11 can also determine the processor core to run on based on the load of the active processor core, and then migrate to that processor core to run, thereby ensuring load balancing among processor cores; alternatively, a dedicated processor core or other hardware (e.g., application-specific integrated circuit, programmable logic device, etc.) can be set up to run the scheduler 11 to improve the running speed of the scheduler 11.

[0031] In this embodiment, processor cores located in the same power domain may include processor cores with different processing capabilities. In subsequent embodiments, the first processor core 111 and the second processor core 112 share a power domain, and the processing capabilities of the first processor core 111 and the second processor core 112 are different. For example, the processor 110 may include four 2.04GHz AMD A55 processor cores, three 2.54GHz AMD A77 processor cores, and one 3.13GHz AMD A77 processor core. The 3.13GHz AMD A77 processor core can be used as a super-large core, the 2.54GHz AMD A77 processor core can be used as a large core, and the 2.04GHz AMD A55 processor core can be used as a small core. The processing capabilities of the super-large core, the large core, and the small core decrease sequentially. Furthermore, the super-large core shares a power domain with all the large cores.

[0032] It should be noted that, Figure 1 The system architecture 10 shown is an example including one processor 300. In practical applications, it can include multiple processors. It should be understood that... Figure 1 The system architecture shown is merely illustrative; the system architecture 10 of the electronic device may also include more or fewer devices or software modules, for example, Figure 1 The system architecture 10 shown may include more processors or processor cores, etc., which are not limited here.

[0033] The embodiments of the processor scheduling method provided in this application will be described in detail below with reference to the accompanying drawings.

[0034] Please see Figure 2 , Figure 2 This document illustrates a flowchart of a processor scheduling method according to an embodiment of this application. In a specific embodiment, the processor scheduling method is applied to the aforementioned electronic device. The specific flow of this embodiment will be described below using an electronic device as an example. It is understood that the electronic device used in this embodiment can be a smartphone, tablet computer, smartwatch, smart glasses, laptop computer, etc., and is not limited thereto. The following will focus on... Figure 2 The process shown is described in detail, and the processor scheduling method may specifically include the following steps:

[0035] Step S110: If the first processor core meets the conditions corresponding to the idle state and the second processor core is in the working state, obtain the current working frequency of the first processor core as the first frequency.

[0036] In this embodiment, when a power domain includes processor cores with different processing capabilities, if a processor core with relatively stronger processing capabilities enters an idle state at a higher frequency, and the voltage corresponding to the operating frequency of a processor core with relatively weaker processing capabilities is lower than the voltage corresponding to the operating frequency of the processor core with relatively stronger processing capabilities, then the power domain will supply power at the voltage corresponding to the operating frequency of the processor core with relatively stronger processing capabilities, thereby increasing the power consumption of the electronic device. Therefore, when a power domain in an electronic device includes a first processor core and a second processor core, and the processing capability of the first processor core is relatively higher than that of the second processor core, it can be determined whether the first processor core meets the conditions corresponding to the idle state to determine whether the aforementioned increase in power consumption will occur. Furthermore, when the first processor core meets the conditions corresponding to the idle state, and the second processor core is in an operating state, the operating frequencies of both can be obtained to determine whether the aforementioned increase in power consumption is met. Specifically, the operating frequency of the first processor core can be obtained and used as the first frequency. Processing capability refers to the processing speed of a processor core when it achieves the same processing effect for the same processing task; that is, when the first processor core and the second processor core process the same task, the processing speed of the first processor core is higher than that of the second processor core. In addition, a more powerful processor core can handle more complex processing tasks. In other words, between the first processor core and the second processor core, the first processor core can handle more complex processing tasks.

[0037] In some implementations, if it is determined that the first processor core is in an idle state and the second processor core is in an active state, the operating frequencies of the first and second processor cores can be obtained to determine whether the increased power consumption situation described above applies. Optionally, the scheduler can monitor the status of the processor cores in real time. If the first processor core is in an idle state while the second processor core is in an active state, the increased power consumption situation described above may occur. Therefore, the subsequent step of obtaining the operating frequencies of both cores can be performed.

[0038] In other embodiments, the operating frequencies of the first and second processor cores can be obtained when the first processor core is about to enter an idle state and the second processor core is in an active state, to determine whether the increased power consumption situation described above applies. Optionally, since the operating state of the processor cores is scheduled by the scheduler—that is, the scheduler determines the processor cores that need to work and controls the operating frequency of the processor cores based on the generated processing tasks—it is possible to determine when the scheduler determines that the first processor core is about to enter an idle state and the second processor core is in an active state.

[0039] In some implementations, a correspondence between processor cores and power domains can be stored. That is, processor cores in an electronic device are divided into the same power domain. Based on this correspondence, it can be determined that the first processor core and the second processor core are in the same power domain, and then the process of the processor scheduling method provided in the embodiments of this application can be executed.

[0040] In some implementations, the first processor core enters an idle state when the scheduler determines that the current load is below a first load threshold. This allows the powerful but power-intensive first processor core to hibernate, thereby reducing the power consumption of the electronic device. In this case, the scheduler may keep the second processor core active because there may still be processing tasks requiring the second processor core. For example, the first processor core can be a super-large core as described above, and the second processor core can be a large core as described above, both sharing a power domain. In high-load application scenarios, the scheduler will activate the super-large core and adjust it to a higher operating frequency. When exiting the application scenario, due to lower load, the scheduler will control the super-large core to enter an idle state.

[0041] Step S120: Obtain the operating frequency of the second processor core as the second frequency.

[0042] In this embodiment, the operating frequency of the second processor core can also be obtained as the second frequency. Optionally, the operating frequency of the second processor core can be obtained from the frequency management module of the scheduler. Of course, when obtaining the operating frequency of the first processor core, the operating frequency of the first processor core is also obtained from the same frequency management module. Naturally, the method of obtaining the operating frequencies of the first and second processor cores is not limited.

[0043] It should be noted that the order in which the operating frequency of the first processor core is obtained and the operating frequency of the second processor core are obtained is not limited. It can be that if the first processor core meets the conditions corresponding to the idle state and the second processor core is in the working state, the operating frequency of the first processor core is obtained first as the first frequency, and then the operating frequency of the second processor core is obtained as the second frequency; it can also be that the operating frequency of the second processor core is obtained first as the second frequency, and then the operating frequency of the first processor core is obtained as the first frequency; or it can be that the operating frequency of the first processor core is obtained as the first frequency and the operating frequency of the second processor core is obtained as the second frequency simultaneously.

[0044] Step S130: If the voltage corresponding to the first frequency is greater than the voltage corresponding to the second frequency, adjust the operating frequency of the first processor core to a third frequency, wherein the voltage corresponding to the third frequency is less than the voltage corresponding to the second frequency.

[0045] In this embodiment, after obtaining the first frequency and the second frequency, the voltage corresponding to the first frequency of the first processor core and the voltage corresponding to the second frequency of the second processor core can be obtained. The voltage corresponding to the first frequency and the voltage corresponding to the second frequency are compared. Based on the comparison result, it is determined whether the voltage corresponding to the first frequency is greater than the voltage corresponding to the second frequency. If the voltage corresponding to the first frequency is greater than the voltage corresponding to the second frequency, the power domains corresponding to both will use a relatively higher voltage, i.e., the voltage corresponding to the frequency of the first processor core, for power supply. At this time, the first processor core meets the conditions corresponding to the idle state and does not need to work, which will lead to increased power consumption. Therefore, the operating frequency of the first processor core can be adjusted to a third frequency so that the voltage corresponding to the operating frequency of the first processor core is less than the voltage corresponding to the operating frequency of the second processor core. This will cause the power supply voltage of the power domain to be the power supply voltage corresponding to the second frequency, reducing the power supply voltage relative to before, thereby reducing the power consumption of the electronic device, and the first processor core meets the conditions corresponding to the idle state without affecting the normal operation of the electronic device. Conversely, if the voltage corresponding to the first frequency is not greater than the voltage corresponding to the second frequency, the operating frequency adjustment can be omitted.

[0046] In some implementations, when adjusting the operating frequency of the first processor core, since the required voltage and operating frequency are usually positively correlated, the scheduler can reduce the operating frequency of the first processor core so that the voltage corresponding to the reduced third frequency is not greater than the voltage corresponding to the second frequency of the second processor core. Optionally, the operating frequency of the first processor core can be adjusted to the lowest frequency point, i.e., the aforementioned third frequency is this lowest frequency point.

[0047] In one possible implementation, after the scheduler determines the third frequency that the first processor core needs to be adjusted to, it can send a frequency adjustment request to the hardware frequency conversion module via Cpufreq to adjust the operating frequency to the third frequency. Accordingly, the hardware frequency conversion module adjusts the operating frequency of the first processor core to the third frequency based on this request. Here, Cpufreq is a driver for Dynamic Voltage and Frequency Regulating (DVFS), which the scheduler can use to adjust the operating frequency of the processor core.

[0048] In some implementations, due to the different configurations of different processor cores, the correspondence between different operating frequencies and required voltages also differs. Therefore, the correspondence between the voltage and operating frequency of the first processor core and the voltage and operating frequency of the second processor core can be stored. Then, based on the stored correspondence, the voltage corresponding to the first frequency of the first processor core and the voltage corresponding to the second frequency of the second processor core can be obtained.

[0049] It should be noted that in this embodiment, the number of first and second processor cores in the power domain shared by the first and second processor cores is not limited. That is, it can be understood that the power domain includes two types of processor cores. When there are multiple first processor cores and a single second processor core, for example, when the power domain includes multiple large cores and one small core, the above process is executed when all first processor cores meet the conditions corresponding to the idle state and the second processor core is in the working state. When there is a single first processor core and multiple second processor cores, for example, when the power domain includes one super-large core and multiple large cores, the working frequency of the first processor core is adjusted to a third frequency when the voltage corresponding to the first frequency is greater than the voltage corresponding to the working frequency of each working second processor core. When there are multiple first and second processor cores, the above process needs to be executed when all first processor cores meet the conditions corresponding to the idle state and the second processor core is in the working state, and the working frequency of the first processor core is adjusted to a third frequency when the voltage corresponding to the working frequency of any one first processor core is greater than the voltage corresponding to the working frequency of all working second processor cores.

[0050] Optionally, the processor scheduling method provided in this application embodiment can be executed by a scheduler, which can run on any processor core that is in operation, or on a specially configured hardware device.

[0051] The processor scheduling method provided in this application embodiment can enable the first processor core and the second processor core to share a single power domain, thereby reducing the number of power supply modules and lowering costs. Furthermore, when the first processor core, which has relatively stronger processing power, enters an idle state, it can be powered at the voltage corresponding to the operating frequency of the second processor core, which is in operation. Since the voltage corresponding to the operating frequency of the second processor core is relatively low, the power consumption of the electronic device can be reduced.

[0052] Please see Figure 3 , Figure 3 A flowchart illustrating a processor scheduling method according to another embodiment of this application is shown. This processor scheduling method is applied to the aforementioned electronic device, and will be discussed below. Figure 3 The process shown is described in detail, and the processor scheduling method may specifically include the following steps:

[0053] Step S210: If the first processor core is in a working state, obtain the probability that the first processor core will enter an idle state from the working state as the first probability.

[0054] In this embodiment, the operating frequencies of the first processor core and the second processor core can be acquired when the first processor core is in an active state and about to enter an idle state, and when the second processor core is in an active state, to determine whether the operating frequencies of the two cores satisfy the aforementioned power consumption increase condition. Specifically, when the processor cores are in an active state, the probability of the first processor core entering an idle state can be acquired as a first probability. The probability of the first processor core entering an idle state represents the likelihood that the first processor core is currently in an idle state; the higher the probability, the more likely it is to enter an idle state.

[0055] In some implementations, obtaining the probability that the first processor core enters an idle state from a working state as a first probability may include: obtaining the processor's task queue; and determining the probability that the first processor core enters an idle state from a working state based on the processing tasks corresponding to the first processor core in the task queue, wherein the probability is negatively correlated with the number of processing tasks. Understandably, the more processing tasks corresponding to the first processor core, the more tasks it currently needs to process, and therefore the lower the probability of it entering an idle state; conversely, the more processing tasks corresponding to the first processor core, the higher the probability of it entering an idle state. Therefore, the number of processing tasks corresponding to the first processor core in the task queue can be obtained to determine the probability. Optionally, the probability can be set to 100% when the number of processing tasks for the first processor core is 0.

[0056] In other implementations, the processor load can also be obtained to determine the aforementioned probability. This load can be obtained through a per-entity loadtracking (PELT) module in the device. Optionally, the processor load can be described using processor utilization; for example, the value used to describe the processor load can be the utilization value of the processor cores.

[0057] In one possible implementation, when the processor of the electronic device includes a super-large core, a large core, and a small core, the super-large core is the aforementioned first processor core, and the large core is the aforementioned second processor core. In this case, the super-large core is typically activated when the processor load is high, i.e., when there are many tasks to process, in order to optimize the power consumption of the electronic device. Therefore, in this case, the processor load can be obtained to determine the probability of the first processor core entering an idle state based on the processor load.

[0058] Optionally, it can be determined whether the processor load is less than a second load threshold, which is the basis for determining whether the first processor core should be adjusted to an idle state. If the processor load is less than the second load threshold, the above probability can be determined as 100%; otherwise, the above probability can be determined as 0%.

[0059] Optionally, it can be determined whether the processor load is less than a second load threshold, which serves as the basis for determining whether the first processor core will be adjusted to an idle state. If the processor load is less than the second load threshold, the probability can be set to 100%. If the processor load is not less than the second load threshold, it can be further determined whether the processor load is less than a third load threshold, which is greater than the second load threshold and serves as the basis for determining whether it will enter an idle state. If it is less than the third load threshold, the processor load trend can be obtained based on the load data within a preset time period before the current moment. When the trend is decreasing, the probability is determined based on the magnitude of the decrease. Of course, the probability determined when the processor load is not less than the second load threshold should be less than 100%. In addition, the determined probability is positively correlated with the magnitude of the decrease, for example, proportionally. If the processor load is not less than the third load threshold, it means that there is no possibility of adjusting to an idle state, so the probability is set to 0.

[0060] Of course, the specific method for obtaining the probability of the first processor core transitioning from the working state to the idle state is not limited.

[0061] Step S220: If the first probability is greater than the first preset probability, and the second processor core is in working state, obtain the current working frequency of the first processor core as the first frequency.

[0062] In this embodiment, after obtaining the first probability, it can be compared with a first preset probability. The first preset probability serves as the basis for determining whether the first processor core should transition from a working state to an idle state. Based on the comparison result, if the first probability is greater than the first preset probability, it indicates that the first processor core will transition from a working state to an idle state. Therefore, the acquisition process can be executed to adjust the operating frequency of the first processor core to reduce power consumption when the aforementioned power consumption increase condition is met. Conversely, if the first probability is not greater than the first preset probability, the subsequent process can be skipped. The specific value of the first preset probability is not limited; for example, it can be 90%, 95%, etc.

[0063] Step S230: Obtain the operating frequency of the second processor core as the second frequency.

[0064] Step S240: If the voltage corresponding to the first frequency is greater than the voltage corresponding to the second frequency, adjust the operating frequency of the first processor core to a third frequency, wherein the voltage corresponding to the third frequency is less than the voltage corresponding to the second frequency.

[0065] In the embodiments of this application, steps S230 and S240 can be referred to the contents of other embodiments, and will not be repeated here.

[0066] Step S250: Based on the voltage corresponding to the third frequency and the voltage corresponding to the second frequency, determine that the supply voltage corresponding to the power domain is the voltage corresponding to the second frequency.

[0067] In this embodiment, after adjusting the operating frequency of the first processor core to a third frequency, the voltage corresponding to the third frequency is made lower than the voltage corresponding to the second frequency. At this point, the power supply voltage corresponding to the power domain can be determined as the voltage corresponding to the second frequency based on the voltage corresponding to the third frequency and the voltage corresponding to the second frequency. In other words, the relatively higher voltage, i.e., the voltage of the second frequency, is determined from the voltage corresponding to the third frequency and the voltage corresponding to the second frequency as the power supply voltage.

[0068] Step S260: Adjust the power supply voltage of the power domain to the voltage corresponding to the second frequency.

[0069] In this embodiment, after determining that the power supply voltage of the power domain is the voltage corresponding to the second frequency, the power supply voltage of the power domain can be adjusted to the voltage corresponding to the second frequency. This avoids the power domain still using a relatively high voltage when the first processor core enters the idle state from a relatively high voltage frequency, thus avoiding an increase in power consumption.

[0070] It should be noted that steps S250 and S260 can also be used in other embodiments. That is, after adjusting the operating frequency of the first processor core to the third frequency in other embodiments, the process of steps S250 and S260 can also be executed.

[0071] The processor scheduling method provided in this application involves obtaining a first probability that the first processor core will transition from an active state to an idle state when the first processor core is in an active state. If the first probability is greater than a first preset probability, and the second processor core is in an active state, the method obtains the current operating frequency of the first processor core as a first frequency and the operating frequency of the second processor core as a second frequency. If the voltage corresponding to the first frequency is greater than the voltage corresponding to the second frequency, the operating frequency of the first processor core is adjusted to a third frequency, where the voltage corresponding to the third frequency is less than the voltage corresponding to the second frequency. This allows the first and second processor cores to share a single power domain, enabling them to be powered at the voltage corresponding to the operating frequency of the second processor core when the first processor core is about to enter an idle state. Furthermore, since the voltage corresponding to the operating frequency of the second processor core is relatively small, the power consumption of the electronic device can be reduced.

[0072] Please see Figure 4 , Figure 4 A flowchart illustrating a processor scheduling method according to another embodiment of this application is shown. This processor scheduling method is applied to the aforementioned electronic device, and will be discussed below. Figure 4 The process shown is described in detail, and the processor scheduling method may specifically include the following steps:

[0073] Step S310: If the first processor core enters an idle state and the second processor core is in a working state, obtain the current working frequency of the first processor core as the first frequency.

[0074] Unlike the previous embodiment, in this embodiment, the operating frequencies of the first processor core can be obtained after it enters an idle state from a working state, and when the second processor core is in a working state, in order to determine whether the operating frequencies of the two processor cores meet the above-mentioned increased power consumption condition.

[0075] In some implementations, since the working state of the processor cores is scheduled by the scheduler, that is, the scheduler determines the processor cores that need to work based on the generated processing tasks and controls the working frequency of the processor cores, it can determine that the first processor core has entered an idle state when the scheduler controls the first processor core to enter an idle state, and the scheduler can also obtain the situation that the second processor core is in a working state.

[0076] Step S320: Obtain the operating frequency of the second processor core as the second frequency.

[0077] Step S330: If the voltage corresponding to the first frequency is greater than the voltage corresponding to the second frequency, adjust the operating frequency of the first processor core to a third frequency, wherein the voltage corresponding to the third frequency is less than the voltage corresponding to the second frequency.

[0078] In the embodiments of this application, steps S320 and S330 can be referred to the contents of other embodiments, and will not be repeated here.

[0079] The processor scheduling method provided in this application embodiment can enable the first processor core and the second processor core to share a power domain. When the first processor core enters an idle state, it can be powered at the voltage corresponding to the operating frequency of the second processor core, which is in operation. Furthermore, since the voltage corresponding to the operating frequency of the second processor core is relatively small, the power consumption of the electronic device can be reduced.

[0080] Please see Figure 5 , Figure 5 A flowchart illustrating a processor scheduling method according to another embodiment of this application is shown. This processor scheduling method is applied to the aforementioned electronic device, and will be discussed below. Figure 5 The process shown is described in detail, and the processor scheduling method may specifically include the following steps:

[0081] Step S410: If the first processor core meets the conditions corresponding to the idle state and the second processor core is in the working state, obtain the current working frequency of the first processor core as the first frequency.

[0082] Step S420: Obtain the operating frequency of the second processor core as the second frequency.

[0083] Step S430: If the voltage corresponding to the first frequency is greater than the voltage corresponding to the second frequency, adjust the operating frequency of the first processor core to a third frequency, wherein the voltage corresponding to the third frequency is less than the voltage corresponding to the second frequency.

[0084] In the embodiments of this application, steps S410 to S430 can be referred to the content of the foregoing embodiments, and will not be repeated here.

[0085] Step S440: If the first processor core meets the conditions corresponding to the working state, adjust the working frequency of the first processor core to the first frequency.

[0086] In this embodiment, if the first processor core meets the conditions corresponding to the idle state, the second processor core is in the working state, and the voltage corresponding to the operating frequency of the first processor core is greater than the voltage corresponding to the operating frequency of the second processor core, after reducing the operating frequency of the first processor core to a third frequency, the operating frequency of the first processor core can be adjusted back to the previous first frequency if the conditions corresponding to the working state are met. It is understood that the first processor core may require a higher operating frequency when it enters the working state after exiting the idle state; therefore, it can be adjusted back to the previous first frequency to ensure that the first processor core can smoothly execute processing tasks, thereby guaranteeing performance. For example, when the first processor core is the aforementioned super-large core, it typically needs to handle relatively complex processing tasks during operation, and will use a higher operating frequency to ensure processing performance. Therefore, when the super-large core enters an idle state at a higher frequency, it will need to operate at a higher frequency again when it exits the idle state. Alternatively, the first frequency of the first processor core may be its normal operating frequency, so it can be adjusted back to its previous first frequency after exiting the idle state. Furthermore, the first processor core may have entered an idle state because the processing task was suddenly shut down, and after a period of time, it needs to continue processing the previous task. Therefore, after exiting the idle state, it can be adjusted back to its previous first frequency to ensure the normal processing of the task.

[0087] In some implementations, after determining that the voltage corresponding to the first frequency is greater than the voltage corresponding to the second frequency, and adjusting the operating frequency of the first processor core to the third frequency, the correspondence between the first processor core and the first frequency can be stored. Therefore, when the first processor core meets the conditions corresponding to its operating state, the operating frequency of the first processor core can be adjusted back to the previous first frequency based on the stored correspondence.

[0088] In some implementations, when the first processor core is about to enter the working state from an idle state, its operating frequency can be adjusted to a first frequency. This allows the first processor core to be pre-adjusted back to the first frequency, ensuring that it operates at the first frequency after entering the working state and can then process tasks. Specifically, the probability of the first processor core entering the working state from an idle state can be obtained as a second probability; if the second probability is greater than a second preset probability, the operating frequency of the first processor core is adjusted to the first frequency.

[0089] In this embodiment, the probability of the first processor core entering the working state from the idle state represents the likelihood that the first processor core is currently in the working state. The higher the probability, the more likely it is to enter the working state.

[0090] As one implementation, the processor load can be obtained to determine the aforementioned probability. This load can be obtained through a per-entity load tracking (PELT) module in the device. Optionally, the processor load can be described using processor utilization; for example, the value used to describe the processor load can be the utilization value of a processor core. Since the first processor core is a relatively powerful processor core, it is more likely to enter a working state when the processor load is high. Therefore, the aforementioned probability can be determined based on the processor load, and this probability is positively correlated with the processor load.

[0091] In other embodiments, when the first processor core enters the working state, its operating frequency can be adjusted to a first frequency to ensure that the first processor core can be understood to operate at the first frequency after entering the working state, thereby processing the processing tasks. Optionally, since the working state of the processor core is scheduled by the scheduler, that is, the scheduler determines the processor core that needs to work and controls the operating frequency of the processor core based on the generated processing tasks, it can be determined that the first processor core will enter the working state when the scheduler controls the first processor core to enter the working state.

[0092] It should be noted that step S440 in this embodiment can also be applied to other embodiments. That is, after adjusting the operating frequency of the first processor core to the third frequency, the operating frequency of the first processor core can be adjusted to the first frequency if the first processor core meets the conditions corresponding to the working state.

[0093] The processor scheduling method provided in this application embodiment can enable the first processor core and the second processor core to share a single power domain, thereby reducing the number of power supply modules and lowering costs. Furthermore, when the first processor core, which has relatively stronger processing power, enters an idle state, it can be powered at the voltage corresponding to the operating frequency of the second processor core, which is in the working state. Since the voltage corresponding to the operating frequency of the second processor core is relatively low, the power consumption of the electronic device can be reduced. Additionally, when the first processor core exits the idle state and enters the working state, its operating frequency is increased to a first frequency, thereby ensuring processing performance.

[0094] Please see Figure 6 , Figure 6 A flowchart illustrating a processor scheduling method according to another embodiment of this application is shown. This processor scheduling method is applied to the aforementioned electronic device, and will be discussed below. Figure 6The process shown is described in detail, and the processor scheduling method may specifically include the following steps:

[0095] Step S510: If the first processor core meets the conditions corresponding to the idle state and the second processor core is in the working state, obtain the current working frequency of the first processor core as the first frequency.

[0096] In this embodiment, step S510 can be referred to the content of the foregoing embodiments, and will not be repeated here.

[0097] Step S520: When the current load of the second processor core is lower than the preset load, adjust the operating frequency of the second processor to the second frequency.

[0098] In this embodiment, for a power domain including a first processor core and a second processor core, where the processing power of the first processor core is higher than that of the second processor core, if the first processor core is in an idle state, the second processor core may also reduce its operating frequency due to the reduced load on the current processor. Therefore, the scheduler can obtain the current load of the second processor core to determine whether the current load is lower than a preset load. If the current load is lower than the preset load, the operating frequency of the second processor core can be adjusted to a second frequency, thereby making the operating state of the processor core correspond to the load of the processor core.

[0099] Step S530: Obtain the operating frequency of the second processor core as the second frequency.

[0100] Step S540: If the voltage corresponding to the first frequency is greater than the voltage corresponding to the second frequency, adjust the operating frequency of the first processor core to a third frequency, wherein the voltage corresponding to the third frequency is less than the voltage corresponding to the second frequency.

[0101] In the embodiments of this application, steps S530 and S540 can be referred to the content of the foregoing embodiments, and will not be repeated here.

[0102] In some scenarios, the first processor core can be the aforementioned super-large core, and the second processor core can be the aforementioned large core. This allows the super-large core to enter an idle state from a higher frequency, while the large core adjusts to a lower frequency. At this time, the voltage corresponding to the operating frequency of the super-large core is greater than the voltage corresponding to the operating frequency of the large core. Adjusting the operating frequency of the super-large core enables subsequent power supply to be based on the voltage corresponding to the operating frequency of the large core, thereby reducing power consumption.

[0103] In some embodiments, the electronic device may also include other power domains. For example, the power domains corresponding to the aforementioned first processor core and second processor core are the first power domains. The electronic device may also include a second power domain, a third power domain, etc.; the processor may also include other processor cores, such as a third processor core, a fourth processor core, etc. Other processor cores can be allocated to other power domains. For example, the third and fourth processor cores can share the second power domain. If the voltage corresponding to the first frequency is greater than the voltage corresponding to the second frequency, it can also be determined whether the load corresponding to the second processor core is less than the fourth load threshold. If the load corresponding to the second processor core is not less than (greater than or equal to) the fourth load threshold, it means that the second processor core currently has many processing tasks. Therefore, the second processor core can continue to process tasks at the second frequency, thereby adjusting the operating frequency of the first processor core to the third frequency, thereby reducing power consumption. If the load corresponding to the second processor core is less than the fourth load threshold, it means that the second processor core currently has few processing tasks. In this case, the processing tasks of the second processor core can be migrated to processor cores in other power domains, such as the third processor core in the second power domain. This allows both the first and second processor cores to enter an idle state. At this time, even if the power domains corresponding to the first and second processor cores are powered by a higher voltage, since the first and second processor cores are in an idle state, it will not result in a large power consumption and makes the task allocation more reasonable.

[0104] The processor scheduling method provided in this application embodiment can enable the first processor core and the second processor core to share a single power domain, thereby reducing the number of power supply modules and lowering costs. Furthermore, when the first processor core, which has relatively stronger processing power, enters an idle state, and the operating frequency of the second processor core is adjusted, power can be supplied at the voltage corresponding to the operating frequency of the second processor core in its active state. Since the voltage corresponding to the operating frequency of the second processor core is relatively small, the power consumption of the electronic device can be reduced.

[0105] Please see Figure 7This document illustrates a structural block diagram of a processor scheduling device 400 according to an embodiment of this application. The processor scheduling device 400 applies the aforementioned electronic device and is used in an electronic device whose processor includes a first processor core and a second processor core. The first processor core and the second processor core share a common power domain. The processing power of the first processor core is higher than that of the second processor core. The processor scheduling device 400 includes: a first frequency acquisition module 410, a second frequency acquisition module 420, and a frequency adjustment module 430. Specifically, the first frequency acquisition module 410 acquires the current operating frequency of the first processor core as a first frequency if the first processor core meets the conditions corresponding to an idle state and the second processor core is in a working state; the second frequency acquisition module 420 acquires the operating frequency of the second processor core as a second frequency; and the frequency adjustment module 430 adjusts the operating frequency of the first processor core to a third frequency if the voltage corresponding to the first frequency is greater than the voltage corresponding to the second frequency, wherein the voltage corresponding to the third frequency is less than the voltage corresponding to the second frequency.

[0106] In some implementations, the first frequency acquisition module 410 may be used to: if the first processor core is in a working state, acquire the probability that the first processor core will enter an idle state from the working state as a first probability; if the first probability is greater than a first preset probability and the second processor core is in a working state, acquire the current working frequency of the first processor core as a first frequency.

[0107] In one possible implementation, the first frequency acquisition module 410 acquires the probability of the first processor core entering an idle state from a working state as a first probability, which may include: acquiring the task queue of the processor; and determining the probability of the first processor core entering an idle state from a working state as a first probability based on the processing tasks corresponding to the first processor core in the task queue, wherein the probability is negatively correlated with the number of processing tasks.

[0108] In some implementations, the first frequency acquisition module 410 can be used to: if the first processor core enters an idle state and the second processor core is in a working state, acquire the current working frequency of the first processor core as the first frequency.

[0109] In some embodiments, the frequency adjustment module 430 can also be used to adjust the operating frequency of the first processor core to the first frequency if the voltage corresponding to the first frequency is greater than the voltage corresponding to the second frequency after adjusting the operating frequency of the first processor core to the third frequency, and if the first processor core meets the conditions corresponding to the operating state.

[0110] In one possible implementation, the frequency adjustment module 430 can also be used to: obtain the probability that the first processor core enters the working state from the idle state as a second probability; if the second probability is greater than the second preset probability, adjust the working frequency of the first processor core to the first frequency.

[0111] In one possible implementation, the frequency adjustment module 430 can also be used to: adjust the operating frequency of the first processor core to the first frequency if the first processor core enters the working state from the idle state.

[0112] In one possible implementation, the processor scheduling device 400 may further include a frequency storage module. The frequency storage module may be used to store the correspondence between the first processor core and the first frequency after adjusting the operating frequency of the first processor core to a third frequency if the voltage corresponding to the first frequency is greater than the voltage corresponding to the second frequency. The frequency adjustment module 430 may be used to adjust the operating frequency of the first processor core to the first frequency based on the correspondence if the first processor core meets the conditions corresponding to its operating state.

[0113] In some embodiments, the frequency adjustment module 430 may also be used to adjust the operating frequency of the second processor to the second frequency when the current load of the second processor core is lower than a preset load before obtaining the operating frequency of the second processor core as the second frequency.

[0114] In some embodiments, the processor scheduling device 400 may further include a power supply determination module and a voltage adjustment module. The power supply determination module is used to determine, based on the voltage corresponding to the third frequency and the voltage corresponding to the second frequency, the supply voltage corresponding to the power domain as the voltage corresponding to the second frequency after adjusting the operating frequency of the first processor core to a third frequency if the voltage corresponding to the first frequency is greater than the voltage corresponding to the second frequency; the voltage adjustment module is used to adjust the supply voltage of the power domain to the voltage corresponding to the second frequency.

[0115] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the specific working process of the above-described device and module can be referred to the corresponding process in the foregoing method embodiments, and will not be repeated here.

[0116] In the several embodiments provided in this application, the coupling between modules can be electrical, mechanical, or other forms of coupling.

[0117] Furthermore, the functional modules in the various embodiments of this application can be integrated into one processing module, or each module can exist physically separately, or two or more modules can be integrated into one module. The integrated modules described above can be implemented in hardware or as software functional modules.

[0118] In summary, the solution provided in this application includes a processor in an electronic device comprising a first processor core and a second processor core sharing a common power domain. The processing power of the first processor core is higher than that of the second processor core. When the first processor core meets the conditions corresponding to its idle state, and the second processor core is in an active state, the operating frequency of the first processor core is obtained as a first frequency, and the operating frequency of the second processor core is obtained as a second frequency. If the voltage corresponding to the first frequency is greater than the voltage corresponding to the second frequency, the operating frequency of the first processor core is adjusted to a third frequency, wherein the voltage corresponding to the third frequency is less than the voltage corresponding to the second frequency. Therefore, when the first and second processor cores share a common power domain, when the first processor core enters an idle state, it can be powered at the voltage corresponding to the operating frequency of the second processor core in an active state. Furthermore, since the voltage corresponding to the operating frequency of the second processor core is relatively lower, the power consumption of the electronic device can be reduced.

[0119] Please refer to Figure 8 This document illustrates a structural block diagram of an electronic device according to an embodiment of this application. The electronic device 100 can be a smartphone, tablet computer, smartwatch, smart glasses, laptop computer, or other electronic device capable of running applications. The electronic device 100 in this application may include one or more of the following components: a processor 110, a memory 120, and one or more applications, wherein the one or more applications can be stored in the memory 120 and configured to be executed by one or more processors 110, and the one or more applications are configured to perform the methods described in the foregoing method embodiments.

[0120] Processor 110 may include multiple processor cores. Processor 110 connects to various parts within the electronic device 100 using various interfaces and lines, and performs various functions and processes data of the electronic device 100 by running or executing instructions, programs, code sets, or instruction sets stored in memory 120, and by calling data stored in memory 120. The multiple processor cores may include at least a first processor core and a second processor core, which share a common power domain. The processing power of the first processor core is higher than that of the second processor core.

[0121] Optionally, the processor 110 can be implemented using at least one hardware form selected from Digital Signal Processing (DSP), Field-Programmable Gate Array (FPGA), and Programmable Logic Array (PLA). The processor 110 can integrate one or a combination of several of the following: Central Processing Unit (CPU), Graphics Processing Unit (GPU), and modem. The CPU primarily handles the operating system, user interface, and applications; the GPU is responsible for rendering and drawing the displayed content; and the modem handles wireless communication. It is understood that the modem may also not be integrated into the processor 110 and can be implemented using a separate communication chip.

[0122] The memory 120 may include random access memory (RAM) or read-only memory (ROM). The memory 120 can be used to store instructions, programs, code, code sets, or instruction sets. The memory 120 may include a program storage area and a data storage area. The program storage area may store instructions for implementing an operating system, instructions for implementing at least one function (such as touch functionality, sound playback functionality, image playback functionality, etc.), and instructions for implementing the various method embodiments described below. The data storage area may also store data created by the electronic device 100 during use (such as phonebook data, audio and video data, chat log data, etc.).

[0123] Please refer to Figure 9 This diagram illustrates a structural block diagram of a computer-readable storage medium provided in an embodiment of this application. The computer-readable medium 800 stores program code that can be called by a processor to execute the methods described in the above method embodiments.

[0124] The computer-readable storage medium 800 may be an electronic memory such as flash memory, EEPROM (Electrically Erasable Programmable Read-Only Memory), EPROM, hard disk, or ROM. Optionally, the computer-readable storage medium 800 includes a non-transitory computer-readable storage medium. The computer-readable storage medium 800 has storage space for program code 810 that performs any of the method steps described above. This program code can be read from or written to one or more computer program products. The program code 810 may be compressed, for example, in a suitable form.

[0125] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application.

Claims

1. A method of scheduling a processor, the method comprising: The method is applied to an electronic device, a processor of the electronic device includes a first processor core and a second processor core, the first processor core and the second processor core share a power supply domain, the processing capability of the first processor core is higher than that of the second processor core, and the method comprises the following steps: If the first processor core meets the condition corresponding to the idle state and the second processor core is in the working state, the working frequency of the first processor core is obtained as the first frequency; The working frequency of the second processor core is obtained as the second frequency; If the voltage corresponding to the first frequency is greater than the voltage corresponding to the second frequency, the working frequency of the first processor core is adjusted to the third frequency, wherein the voltage corresponding to the third frequency is less than the voltage corresponding to the second frequency; Based on the voltage corresponding to the third frequency and the voltage corresponding to the second frequency, the power supply voltage corresponding to the power supply domain is determined as the voltage corresponding to the second frequency; The power supply voltage of the power supply domain is adjusted to the voltage corresponding to the second frequency.

2. The method of claim 1, wherein, The method further comprises the following steps: If the first processor core is in the working state, the probability that the first processor core enters the idle state from the working state is obtained as the first probability; If the first probability is greater than the first preset probability and the second processor core is in the working state, the working frequency of the first processor core is obtained as the first frequency.

3. The method of claim 2, wherein, The method further comprises the following steps: The task queue of the processor is obtained; Based on the processing task corresponding to the first processor core in the task queue, the probability that the first processor core enters the idle state from the working state is determined as the first probability, and the probability is negatively correlated with the number of the processing task.

4. The method of claim 1, wherein, The method further comprises the following steps: If the first processor core enters the idle state and the second processor core is in the working state, the working frequency of the first processor core is obtained as the first frequency.

5. The method of claim 1, wherein, The method further comprises the following steps: If the first processor core meets the condition corresponding to the working state, the working frequency of the first processor core is adjusted to the first frequency.

6. The method of claim 5, wherein, The method further comprises the following steps: The probability that the first processor core enters the working state from the idle state is obtained as the second probability; If the second probability is greater than the second preset probability, the working frequency of the first processor core is adjusted to the first frequency.

7. The method of claim 5, wherein, The method further includes: If the first processor core enters the working state from the idle state, adjusting the working frequency of the first processor core to the first frequency.

8. The method of claim 5, wherein, The method further includes: storing the correspondence between the first processor core and the first frequency; The method further includes: If the first processor core meets the condition corresponding to the working state, adjusting the working frequency of the first processor core to the first frequency based on the correspondence.

9. The method according to any one of claims 1 to 8, characterized in that, The method further includes: If the current load of the second processor core is lower than the preset load, adjusting the working frequency of the second processor to the second frequency.

10. A scheduling apparatus of a processor, the apparatus comprising: The electronic device includes a processor including a first processor core and a second processor core, and the first processor core and the second processor core share a power supply domain, the processing capability of the first processor core is higher than that of the second processor core, and the apparatus includes a first frequency acquisition module, a second frequency acquisition module, a frequency adjustment module, a voltage determination module, and a voltage adjustment module. The first frequency acquisition module is configured to, if the first processor core meets the condition corresponding to the idle state and the second processor core is in the working state, acquire the working frequency of the first processor core as the first frequency. The second frequency acquisition module is configured to acquire the working frequency of the second processor core as the second frequency. The frequency adjustment module is configured to, if the voltage corresponding to the first frequency is greater than the voltage corresponding to the second frequency, adjust the working frequency of the first processor core to a third frequency, where the voltage corresponding to the third frequency is less than the voltage corresponding to the second frequency. The voltage determination module is configured to determine, based on the voltage corresponding to the third frequency and the voltage corresponding to the second frequency, that the supply voltage corresponding to the power supply domain is the voltage corresponding to the second frequency. The voltage adjustment module is configured to adjust the supply voltage of the power supply domain to the voltage corresponding to the second frequency.

11. An electronic device, comprising: The apparatus includes: one or more processors including a first processor core and a second processor core; a memory; one or more application programs stored in the memory and configured to be executed by the one or more processors, the one or more programs being configured to perform the method of any one of claims 1-9.

12. A computer readable storage medium, characterized in that, The computer-readable storage medium stores program code that can be invoked by a processor to perform the method of any one of claims 1-9.

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