Adjustable data protection scheme using artificial intelligence

Abstract

Devices and methods can involve implementing an adjustable data protection scheme using artificial intelligence. Implementing an adjustable data protection scheme can include receiving failure data for a plurality of memory devices and receiving an indication of a failure of a stripe of the plurality of memory devices based on the failure data. Based on the failure data and the indication of the failure of the stripe of the plurality of memory devices, a data protection scheme adjustment for the memory devices can be generated. The data protection scheme adjustment can be received from an AI accelerator and can be implemented by a plurality of memory devices.

Description

Technical Field

[0001] This disclosure generally relates to electronic storage systems and apparatuses, and more specifically, to devices and methods associated with implementing adjustable data protection schemes using artificial intelligence (AI). Background Technology

[0002] Memory devices are typically provided as internal semiconductor integrated circuit devices in computers or other electronic devices. Many different types of memory exist, including volatile and non-volatile memory. Volatile memory may require power to maintain its data and includes random access memory (RAM), dynamic random access memory (DRAM), and synchronous dynamic random access memory (SDRAM), among others. Non-volatile memory provides permanent data by retaining the stored data when no power is supplied and can include NAND flash memory, NOR flash memory, read-only memory (ROM), electrically erasable programmable ROM (EEPROM), erasable programmable ROM (EPROM), and resistive variable memory, such as phase-change random access memory (PCRAM), resistive random access memory (RRAM), and magnetoresistive random access memory (MRAM), among others.

[0003] Memory is also used as a volatile and non-volatile data storage device for a wide range of electronic applications. These include, but are not limited to, personal computers, portable memory sticks, digital cameras, cellular phones, portable music players such as MP3 players, movie players, and other electronic devices. Memory cells can be arranged in arrays, where arrays are used in memory devices. Various data protection schemes can be used to ensure the integrity of data within memory. Summary of the Invention

[0004] In one aspect, this disclosure provides an apparatus comprising: a plurality of memory devices implementing a data protection scheme; an artificial intelligence (AI) accelerator coupled to the plurality of memory devices; wherein the AI ​​accelerator is configured to: receive fault data of the plurality of memory devices; receive indications of faults in stripes of the plurality of memory devices based on the fault data; and generate an adjustment to the data protection scheme for the plurality of memory devices based on the fault data and the indications of faults in stripes of the plurality of memory devices; wherein the plurality of memory devices are configured to: receive the data protection scheme adjustment from the AI ​​accelerator; and implement the data protection scheme adjustment.

[0005] In another aspect, this disclosure further provides a method comprising: receiving temperature data of a memory device coupled to an artificial intelligence (AI) accelerator, the memory device implementing a data protection scheme during operation of the memory device; receiving an indication of a stripe fault in the memory device; generating an adjustment of the data protection scheme for the memory device at the AI ​​accelerator based on the temperature data and the indication of the stripe fault in the memory device; and implementing the data protection scheme adjustment at the memory device.

[0006] In another aspect, this disclosure further provides an apparatus comprising: a memory device implementing a data protection scheme; an artificial intelligence (AI) accelerator coupled to the memory device; wherein the AI ​​accelerator is configured to: receive the raw bit error rate (RBER) of the memory device during operation of the memory device; receive data corresponding to pass or fail conditions of the memory device; and, based on the RBER and the data, generate adjustments to the data protection scheme for the memory device to extend the lifetime of the memory device; wherein the memory device is configured to implement the data protection scheme adjustments.

[0007] In another aspect, this disclosure further provides a system comprising: an AI accelerator implemented in a cloud system; a plurality of memory devices implementing a data protection scheme; wherein the AI ​​accelerator is configured to: receive manufacturing data and test data; receive status data describing the state of the plurality of memory devices; receive a fuse identifier (ID) corresponding to at least one of the plurality of memory devices; generate a data protection scheme adjustment for a memory cell corresponding to the fuse ID in response to the receipt of the manufacturing data, test data, and status data; and wherein the plurality of memory devices are configured to implement a data protection scheme adjustment for a memory cell corresponding to the fuse ID. Attached Figure Description

[0008] Figure 1 This is a block diagram of a device in the form of a computing system that includes a memory subsystem, according to several embodiments of the present disclosure.

[0009] Figure 2 A block diagram illustrating RAIN adjustments performed via a cloud system according to several embodiments of the present disclosure.

[0010] Figure 3 A block diagram illustrating a memory subsystem for implementing RAIN adjustment based on erase latency and programming latency, according to several embodiments of the present disclosure.

[0011] Figure 4 A block diagram illustrating a memory subsystem for implementing RAIN adjustment based on temperature data, according to several embodiments of the present disclosure.

[0012] Figure 5A block diagram illustrating a memory subsystem for implementing RAIN adjustment based on the raw bit error rate, according to several embodiments of the present disclosure.

[0013] Figure 6 Example flowcharts illustrating methods for implementing a data protection scheme according to several embodiments of the present disclosure.

[0014] Figure 7 This describes an example machine of a computer system in which a set of instructions for causing the machine to perform the various methods discussed herein can be executed. Detailed Implementation

[0015] This disclosure includes apparatus and methods related to implementing adjustable data protection schemes using artificial intelligence (AI). In various embodiments, the protection scheme includes a redundant NAND redundancy array (RAIN) data protection scheme. RAIN utilizes a parity check protection scheme to protect data stored by a memory device. For example, the RAIN scheme may utilize parity check elements to recover data from the memory device.

[0016] Typically, RAIN is designed for the lifetime of a memory system and may degrade its performance. RAIN can be optimized to not impair memory system performance. However, optimizing RAIN to avoid performance degradation may reduce the lifetime of the memory system. RAIN can be designed for a specific failure rate. For defects not included in a specific failure rate, the RAIN scheme may not recover data stored by the memory system.

[0017] This disclosure addresses the above and other shortcomings. For certain use cases where RAIN usage is unnecessary and / or can be weakened, RAIN performance can be relaxed. Where necessary, RAIN performance can be activated and / or enhanced. RAIN may be required when block and / or word lines have high defect rates or when end-of-life conditions are present. In several embodiments, the operation of the memory system's RAIN can be based on AI. For example, memory system utilization and / or RAIN usage can be analyzed to generate adjustments to the RAIN scheme. Additionally, historical usage data can be used to adjust RAIN settings throughout the memory system's lifetime.

[0018] For example, an Artificial Neural Network (ANN) can be used to analyze the use of RAIN and / or memory systems. As used herein, AI refers to the ability of a machine to improve itself through “learning,” for example, by storing patterns and / or instances that can be used for later action. Machine learning refers to the ability of a device to learn from data provided as instances. Machine learning can be a subset of AI. As used herein, an ANN can provide learning by forming probabilistic weighted associations between inputs and outputs. Probabilistic weighted associations can be provided by including multiple nodes in the ANN. Nodes, along with weights, biases, and activation functions, can be used to generate the ANN’s output based on the inputs to the ANN. An ANN can utilize several inputs to generate RAIN adjustment recommendations. Inputs may include, for example, fault data corresponding to the faults of stripes of multiple memory devices in a memory subsystem. The output may be an adjustment to a data protection scheme that can be a RAIN scheme.

[0019] The figures in this document follow a numbering convention, where the first one or more numbers correspond to the figure number, and the remaining numbers identify elements or components within the figure. Similar elements or components between different figures can be identified by using similar numbers. For example, 114 could represent... Figure 1 Component "14" in the text, and similar components in Figure 3 The value in the middle can be represented as 314. Similar elements within the diagram can be represented using hyphens and additional numbers or letters. See, for example... Figure 1 The elements 103-1, ..., 103-N are shown in the figures. It should be understood that elements shown in various embodiments herein may be added, interchanged, and / or removed to provide several additional embodiments of this disclosure. Furthermore, it should be understood that the scale and relative dimensions of the elements provided in the figures are intended to illustrate certain embodiments of the invention and should not be construed as limiting.

[0020] Figure 1 This is a block diagram of a device in the form of a computing system 100, including a memory subsystem 115, according to several embodiments of the present disclosure. As used herein, the memory system 115, the AI ​​accelerator 114, and the memory devices 103-1 to 103-N and / or the host 102 may also be individually considered as a “device”, for example.

[0021] The memory subsystem 115 may include media, such as volatile memory devices and / or non-volatile memory devices (e.g., memory devices 103-1 to 103-N). Memory devices 103-1 to 103-N may be referred to as memory device 103.

[0022] The memory subsystem 115 may be a storage device, a memory module, or a combination of a storage device and a memory module. Examples of storage devices include solid-state drives (SSDs), such as NAND flash drives, Universal Serial Bus (USB) flash drives, embedded multimedia controller (eMMC) drives, universal flash memory (UFS) drives, secure digital cards (SD cards), and hard disk drives (HDDs). Examples of memory modules include dual in-line memory modules (DIMMs), small outline DIMMs (SO-DIMMs), and various types of non-volatile dual in-line memory modules (NVDIMMs).

[0023] The computing system 100 may be a desktop computer, a laptop computer, a web server, a mobile device, a vehicle (e.g., a car, an airplane, a drone, a train or other means of transport), an Internet of Things (IoT) enabled device, an embedded computer (e.g., a computer contained in a vehicle, industrial equipment or a networked commercially available device), or such a computing device containing memory and processing means (e.g., a processor).

[0024] The computing system 100 may include a host system 102 coupled to one or more memory subsystems 115. In some embodiments, the host system 102 is coupled to different types of memory subsystems 115. Figure 1 This describes an example of a host system 102 coupled to a memory subsystem 115. As used herein, “coupled to” or “coupled with” generally refers to a connection between components, which can be an indirect or direct communication connection (e.g., without an intermediate component), whether wired or wireless, and includes connections such as electrical, optical, and magnetic connections.

[0025] Host system 102 may include a processor chipset and a software stack executed by the processor chipset. The processor chipset may include one or more cores, one or more caches, a memory controller (e.g., an NVDIMM controller), and a storage protocol controller (e.g., a PCIe controller, a SATA controller). Host system 102 uses memory subsystem 115, for example, to write data to memory subsystem 115 and to read data from memory subsystem 115.

[0026] Host system 102 can be coupled to memory subsystem 115 via a physical host interface. Examples of physical host interfaces include, but are not limited to, Serial Advanced Technology Attachment (SATA) interfaces, Peripheral Component Interconnect High Speed ​​(PCIe) interfaces, Universal Serial Bus (USB) interfaces, Fibre Channel, Serial Attached SCSI (SAS), Small Computer System Interface (SCSI), Dual Data Rate (DDR) memory bus, Dual In-line Memory Module (DIMM) interfaces (e.g., DIMM sockets supporting Dual Data Rate (DDR)), Open NAND Flash Interface (ONFI), Dual Data Rate (DDR), Low Power Dual Data Rate (LPDDR), or any other interface. The physical host interface can be used to transmit data between host system 102 and memory subsystem 115. When memory subsystem 115 is coupled to host system 102 via a PCIe interface, host system 102 can further utilize an NVM Fast (NVMe) interface to access components (e.g., memory device 103). The physical host interface provides an interface for transmitting control, address, data and other signals between the memory subsystem 115 and the host system 102. Figure 1 The memory subsystem 115 is described as an example. Generally, the host system 102 can access multiple memory subsystems via the same communication connection, multiple separate communication connections, and / or a combination of communication connections.

[0027] Memory device 103 may comprise any combination of different types of non-volatile memory devices and / or volatile memory devices. Volatile memory devices may be, but are not limited to, random access memory (RAM), such as dynamic random access memory (DRAM) and synchronous dynamic random access memory (SDRAM).

[0028] Some examples of non-volatile memory devices (e.g., memory device 103) include NAND flash memory and in-place write memory, such as three-dimensional crosspoint (“3D crosspoint”) memory devices, which are crosspoint arrays of non-volatile memory cells. The crosspoint array of non-volatile memory can perform bit storage based on changes in bulk resistance in conjunction with a stackable cross-grid data access array. Furthermore, compared to many flash-based memories, crosspoint non-volatile memory can perform in-place write operations, where non-volatile memory cells can be programmed without pre-erasing them. NAND flash memory includes, for example, two-dimensional NAND (2D NAND) and three-dimensional NAND (3D NAND).

[0029] Each of the memory devices 103 may include one or more arrays of memory cells. One type of memory cell, such as a single-level cell (SLC), may store one bit per cell. Other types of memory cells, such as multi-level cells (MLC), three-level cells (TLC), four-level cells (QLC), and five-level cells (PLC), may store multiple bits per cell. In some embodiments, each of the memory devices 103 may include one or more arrays of memory cells, such as SLC, MLC, TLC, QLC, PLC, or any combination thereof. In some embodiments, a particular memory device may include an SLC portion of memory cells, as well as an MLC portion, a TLC portion, a QLC portion, or a PLC portion. The memory cells of the memory device 103 may be grouped into pages, which may refer to logical cells of the memory device used for storing data. In the case of some types of memory (e.g., NAND), pages may be grouped to form blocks.

[0030] While non-volatile memory devices, such as 3D cross-point non-volatile memory cell arrays and NAND-type memories (e.g., 2D NAND, 3D NAND), are described, memory device 103 may be based on any other type of non-volatile memory, such as read-only memory (ROM), phase-change memory (PCM), select memory, other chalcogenide-based memories, ferroelectric transistor random access memory (FeTRAM), ferroelectric random access memory (FeRAM), magnetic random access memory (MRAM), spin-transfer torque (STT)-MRAM, conductive bridged RAM (CBRAM), resistive random access memory (RRAM), oxide-based RRAM (OxRAM), NOR flash memory, and electrically erasable programmable read-only memory (EEPROM).

[0031] The memory subsystem controller 116 (or, for simplicity, controller 116) can communicate with the memory device 103 to perform operations, such as reading data, writing data, erasing data, and other such operations at the memory device 103. The memory subsystem controller 116 may include hardware, such as one or more integrated circuits and / or discrete components, buffer memories, or combinations thereof. The hardware may include a digital circuit system with dedicated (i.e., hard-decoded) logic to perform the operations described herein. The memory subsystem controller 116 may be a microcontroller, a dedicated logic circuit system (e.g., a field-programmable gate array (FPGA), an application-specific integrated circuit (ASIC), etc.), or other suitable processor.

[0032] The memory subsystem controller 116 may include a processing means, such as a processor 117 configured to execute instructions stored in local memory 118. In the illustrated example, the local memory 118 of the memory subsystem controller 116 includes embedded memory configured to store instructions for performing various processes, operations, logic flows, and routines that control the operation of the memory subsystem 115, including handling communication between the memory subsystem 115 and the host system 102.

[0033] In some embodiments, local memory 118 may include memory registers that store memory pointers, retrieved data, etc. For example, local memory 118 may also include read-only memory (ROM) for storing microcode. Although in Figure 1 The instance memory subsystem 115 has been described as including a memory subsystem controller 116, but in another embodiment of this disclosure, the memory subsystem 115 does not include a memory subsystem controller 116, but instead may rely on external control (e.g., provided by an external host or by a processor or controller separate from the memory subsystem).

[0034] Generally, the memory subsystem controller 116 can receive commands or operations from the host system 102 and can translate these commands or operations into instructions or appropriate commands to perform the desired access to the memory device 103. The memory subsystem controller 116 may be responsible for other operations, such as wear leveling, garbage collection, error detection and error correction code (ECC) operations, encryption, caching, and address translation between logical addresses (e.g., logical block addresses, namespaces) and physical addresses (e.g., physical block addresses) associated with the memory device 103. The memory subsystem controller 116 may further include a host interface circuitry for communicating with the host system 102 via a physical host interface. The host interface circuitry can translate commands received from the host system into instructions for accessing the memory device 103 and translate responses associated with the memory device 103 into information for the host system 102.

[0035] The memory subsystem 115 may also include additional circuitry or components not described. In some embodiments, the memory subsystem 115 may include a cache or buffer (e.g., DRAM) and an address circuitry (e.g., a row decoder and a column decoder) that can receive and decode addresses from the memory subsystem controller 116 to access the memory device 103.

[0036] In some embodiments, memory device 103 includes a local media controller that operates in conjunction with memory subsystem controller 116 to perform operations on one or more memory cells of memory device 103. An external controller (e.g., memory subsystem controller 116) may externally manage memory device 103 (e.g., perform media management operations on the memory device). In some embodiments, memory device 103 is a managed memory device, which is a native memory device combined with a local controller for media management within the same memory device package. An example of a managed memory device is a managed NAND (MNAND) device.

[0037] A memory subsystem controller 116 is coupled to an AI accelerator 114. The AI ​​accelerator 114 may include hardware and / or firmware. For example, the AI ​​accelerator 114 may include various circuit systems (e.g., hardware), such as one or more processing devices (e.g., microprocessors), such as a graphics processing unit (GPU), an application-specific integrated circuit (ASIC), or a field-programmable gate array (FPGA). The processor of the AI ​​accelerator 114 may perform low-precision arithmetic operations. For example, the AI ​​accelerator 114 may be implemented using phase-change memory. The processor of the AI ​​accelerator 114 may be a memory cell of a memory array. For example, a memory cell may be used to perform matrix multiplication. Memory cells may be configured to perform operations by controlling the resistance of the memory cell. Memory cells may be used to perform operations in parallel. In various instances, the AI ​​accelerator 114 may implement a processor separate from the memory cells of the memory array.

[0038] For example, AI accelerator 114 may be a deep learning accelerator (DLA). The AI ​​accelerator may be implemented at the edge of memory system 115. For example, AI accelerator 114 may be implemented external to memory device 103. AI accelerator 114 may be coupled to the output path of an I / O circuitry system that couples memory device 103 to memory subsystem 115. For example, AI accelerator 114 may include a feedback circuitry system.

[0039] AI accelerator 114 may also be coupled to memory subsystem controller 116. Memory subsystem controller 116 may control AI accelerator 114. For example, memory subsystem controller 116 may provide data to AI accelerator 114 and may receive output from AI accelerator. Inputs to AI accelerator 114 may be provided as inputs to an ANN hosted by AI accelerator 114. Memory subsystem controller 116 may also cause the outputs of AI accelerator 114 and / or ANN to be provided to memory device 103 and / or host system 102.

[0040] The memory subsystem controller 116 may also include a data protection scheme circuitry 119. For example, the data protection scheme circuitry 119 may be a circuitry that manages the RAIN scheme. The data protection scheme circuitry 119 may be configured to manage the output of the AI ​​accelerator 114 to adjust the data protection scheme of the memory device 103. The data protection scheme circuitry 119 may also be configured to provide input to the AI ​​accelerator 114. For example, the data protection scheme circuitry 119 may provide temperature data, erase delay data, programming delay data, and / or RBER data to the AI ​​accelerator 114, as well as other data that may be provided to the AI ​​accelerator 114. The data protection scheme circuitry 119 may also be configured to perform additional processing on the output of the AI ​​accelerator 114 as needed.

[0041] Memory device 103 may implement a data protection scheme. Data protection scheme circuitry 119 manages the implementation of the data protection scheme through memory device 103. The data protection scheme (e.g., RAIN) may include striping (e.g., segmentation) information, such that different portions of the information are stored on different memory devices (e.g., memory device 103). The portions of segmented data stored on more than one device are collectively referred to as stripes. Alternatively, the data protection scheme may also include mirroring, which may involve storing double copies of data on more than one device. As an example, written data may be striped across N-1 of N memory devices, where error information may be stored in the Nth memory device. Error information (e.g., parity data) may be calculated by data protection scheme circuitry 119 and written to the Nth memory device (e.g., parity element). Data protection scheme circuitry 119 may employ flexible stripe lengths and flexible ratios of parity elements to storage elements. Data protection scheme circuitry 119 may be configured to write and / or read data across memory device 103 in stripes. For example, the memory subsystem controller 116 may be configured to read data stripes from a plurality of physical pages of the memory device 103, each of the plurality of physical pages of the memory device storing a plurality of corresponding codewords. The memory subsystem controller 116 may be configured to combine more than one payload portion of a plurality of corresponding codewords from one of the plurality of physical pages of the memory device 103 to form a logical page of data. The logical page of data may then be transferred to the host system 102 (e.g., as several partitions).

[0042] Computing system 100 can be coupled to a cloud system via network 195. The cloud system may contain an AI network 112, such as an ANN. Host system 102 can couple computing system 100 to network 195. Although the examples described herein are given in the context of the RAIN scheme, the examples can also be applied to different data protection schemes.

[0043] Figure 2 This diagram illustrates RAIN adjustments performed via a cloud system 220 according to several embodiments of the present disclosure. The cloud system 220 includes an AI network 212 and a memory subsystem 215. The cloud system 220 is coupled to a memory device storing a data pool 223 and / or manufacturing and testing data 222. As used herein, the data pool 223 is a collection of examples of data.

[0044] For example, AI network 212 can be an ANN and can be hosted by an AI accelerator on cloud system 220. AI network 212 can be accessed via, for example, from... Figure 1 Network 195 receives input from memory subsystem 215. Memory subsystem 215, which provides the input, may be a NAND memory subsystem. Memory subsystem 215 may include... Figure 1 The controller shown is the memory subsystem controller 116.

[0045] Input received by AI network 212 may include data (e.g., fault data) describing whether a stripe, block, and / or word line of memory subsystem 215 experiences a fault or not. For example, the data may describe whether a stripe, block, and / or word line of the memory device of memory subsystem 215 experiences a fault or not. For example, a previous RAIN adjustment performed by memory subsystem 215 may have a target specific stripe, block, and / or word line representing a specific die of memory subsystem 215. The data received by AI network 212 may describe whether a specific stripe, block, and / or word line continues to experience faults due to a previous RAIN adjustment, or whether a specific block and / or word line no longer experiences faults due to a previous RAIN adjustment. As described herein, faults experienced by memory subsystem 215 include data loss experienced by memory subsystem 215. Data loss may occur during reading from and / or writing to memory subsystem 215.

[0046] Data describing the faults or lack thereof experienced by a specific stripe, block, and / or word line may include an identifier for the die of the memory subsystem 215. The die of the memory subsystem 215 may be identified using a fuse ID. A fuse ID is an identifier that identifies a specific fuse and / or die of the memory subsystem 215. For example, a fuse ID can be used to identify a die of a memory device, a stripe of a memory device, a block of a memory device, and / or a word line of a memory device.

[0047] The input received by AI network 212 may also include faults that cannot be corrected using RAIN adjustment. Faults that cannot be corrected using RAIN adjustment may include the type of fault. The type of fault may include erase faults, programming faults, and / or read faults. The input describing faults that cannot be corrected using RAIN adjustment may also include fault data. Fault data may include programming delay data, read delay data, erase delay data, and / or raw bit error rate (RBER), as well as other possible data that can be used to describe the fault. The input describing the fault may further include data corresponding to stripes, blocks, and / or word lines of memory subsystem 215 and / or fuse IDs identifying the stripes, blocks, and / or word lines of memory devices in memory subsystem 215. The input describing the fault may also include a count of bits that cannot be recovered using RAIN adjustment.

[0048] AI network 212 can utilize inputs to generate RAIN adjustments. For certain use cases where RAIN is not required, RAIN adjustments can relax RAIN performance. In cases where RAIN is required, RAIN adjustments can also enhance RAIN performance. RAIN may be needed if defective stripes, blocks, and / or word lines are present. The degree of defect in stripes, blocks, and / or word lines can be identified in various ways. For example, memory subsystem 215 can identify the degree of defect in stripes, blocks, and / or word lines as a failure in decoding data stored in the memory array of memory subsystem 215. Memory subsystem 215 can determine whether previously implemented RAIN adjustments successfully addressed the failures experienced by stripes, blocks, and / or word lines. Faults that were not resolved by implementing RAIN adjustments can be identified, and said identification can be provided as input to AI network 212. Figures 3 to 5 It enables the monitoring of various attributes of the memory subsystem 215 that can be used to identify faults in the memory subsystem 215 and to generate RAIN adjustments.

[0049] AI network 212 can provide RAIN adjustment to memory subsystem 215. Memory subsystem 215 can implement RAIN adjustment. RAIN adjustment may include adjusting the ratio of parity elements to storage elements. For example, the ratio of parity elements to storage elements may be changed from 1:7 (e.g., one parity element for every seven storage elements) to 1:5 (e.g., one parity element for every five storage elements). As used herein, storage elements may include elements of memory subsystem 215 for storing codewords.

[0050] RAIN adjustment may include avoiding the use of stripes, blocks, and / or word lines of the memory device or initializing the use of stripes, blocks, and / or word lines of the memory device. RAIN adjustment may also include adjusting the level of memory cells for specific stripes, blocks, and / or word lines. For example, memory cells in a specific block may be configured to act as MLCs, where the memory cells were previously configured to act as SLCs. Memory cells in a specific block may also be configured to act as SLCs, where the memory cells were previously configured to act as MLCs.

[0051] AI network 212 can also provide summary reports to a memory device, which can store the summary reports as a data pool 223 (e.g., a pool of data) of unsupported faults. The summary reports can identify faults that have not been adjusted by AI network 212. For example, the summary reports can identify faults that cannot be corrected by RAIN and are therefore described as unsupported faults.

[0052] Data pool 223 may store data on unsupported faults, such as those provided by summary reports. This unsupported fault data may be provided to a memory device used to store manufacturing and / or testing data 222. The unsupported fault data may be used in manufacturing and / or testing to identify design changes to the memory subsystem 215 that can overcome previous unsupported faults.

[0053] Manufacturing and / or testing data 222 may also include real-time manufacturing inline data and testing data available to the AI ​​network 212. The real-time manufacturing inline data and testing data may include inline data containing parameter measurements from the memory subsystem 215 and test trends used to assess defect rates on stripes, blocks, and / or word lines. The AI ​​network 212 may utilize the real-time manufacturing inline data and testing data to generate RAIN adjustments for faults that the AI ​​network 212 has not previously experienced. If the AI ​​network 212 receives data corresponding to a fault experienced by the memory subsystem 215, the AI ​​network 212 may or may not experience the fault.

[0054] Figure 3 This diagram illustrates a memory subsystem 315 for implementing RAIN adjustment based on erase latency and programming latency, according to several embodiments of the present disclosure. The memory subsystem 315 includes an AI network 314 and a memory device 303. The memory subsystem 315 may be coupled to a cloud system 321 via an interface of a computing system. The cloud system 321 may include an AI network, such as an ANN configured as a pool of data.

[0055] Compared to systems implemented in the cloud Figure 2AI networks 212 and 314 can be implemented in memory subsystem 315. AI network 314 can receive data from memory device 303. For example, AI network 314 can receive erase latency data (TBERS) and programming latency data (TPROG) from memory device 303.

[0056] The erase delay data may include the duration for performing an erase operation on the memory device 303. The programming delay data may include the duration for performing a programming operation on the memory device 303. Erasure delay data and programming delay data may be received from the memory device 303. In various examples, faults experienced by the memory device 303 or faults expected to be experienced by the memory device 303 can be identified by analyzing the erase delay data and / or the programming delay data.

[0057] AI network 314 can also receive feedback on stripes, blocks, and / or word lines that have triggered enhanced RAIN coverage in the event of their failure. Memory device 303 can monitor stripes, blocks, and / or word lines to determine if they have failed. Failures in stripes, blocks, and / or word lines can indicate to memory device 303 that enhanced RAIN coverage is needed. For example, RAIN coverage can be enhanced by changing the ratio of parity elements to memory elements. In various instances, memory device 303 can also provide cycle counts corresponding to erase latency data, programming latency data, memory device 303, and / or failures experienced by stripes, blocks, and / or word lines. RAIN adjustments can also be generated based on the cycle counts.

[0058] AI network 314 can generate RAIN adjustments based on feedback, erase latency data, and / or programming latency data from stripes, blocks, and / or word lines. In various examples, the erase latency and / or programming latency provided via erase latency data and programming latency data can constitute a signature corresponding to a fault experienced by the stripes, blocks, and / or word lines of memory device 303. For example, the signature provided by memory device 303 can be compared with previously experienced signatures that can be stored in a table. Previously experienced signatures may include a series of fault latency for erase and programming operations. The signature may also be referred to as a fault signature. The fault signature can be associated with RAIN adjustments that enhance coverage. Signatures received from memory device 303 (e.g., erase and programming times) can be compared with signatures stored by AI network 314 to generate RAIN adjustments. RAIN adjustments can be provided to memory device 303.

[0059] In various instances, feedback on stripes, blocks, and / or word lines can be utilized by AI network 314 to determine whether additional RAIN adjustments are needed. For example, AI network 314 may generate additional RAIN adjustments based on cycle counts and / or raw bit error rates (RBER) experienced after RAIN adjustments have been implemented by memory device 303. For instance, if a particular stripe, block, and / or word line of memory device 303 continues to experience faults as described by erase delay data, programming delay data, cycle counts, and / or RBER, AI network 314 may generate additional RAIN adjustments. Similarly, even if no fault is associated with the stripe, block, and / or word line, additional stripes, blocks, and / or word lines with signatures similar to a previous signature identified as a fault signature may have RAIN adjustments implemented on them because the probability of an impending fault is high.

[0060] AI network 314 can also provide data to cloud system 321, wherein the data describes signatures visible to AI network 314 and data regarding RAIN adjustments implemented to correct faults. Cloud system 321 can utilize the data received from AI network 314 to perform further optimizations. Cloud system 321 can provide suggestions for signatures not yet encountered by AI network 314 to provide better guidance.

[0061] Figure 4 A block diagram illustrating a memory subsystem 415 for implementing RAIN adjustment based on temperature data, according to several embodiments of the present disclosure. The memory subsystem 415 includes an AI network 414 and a memory device 403.

[0062] The memory device 403 may provide temperature data to the AI ​​network 414. The temperature data may include temperature readings from the memory device 403 during operation of the memory device 403. The memory device 403 may also provide feedback on faults experienced by stripes, blocks, and / or word lines or the absence of faults experienced by stripes, blocks, and / or word lines, wherein the stripes, blocks, and / or word lines are programmed with enhanced RAIN coverage during cross-temperature use.

[0063] AI network 414 can utilize temperature data and feedback to generate RAIN adjustments. Visible temperature changes on memory device 403 can be monitored. In response to the monitored temperature changes, AI network 414 can trigger changes to RAIN coverage if necessary. In many cases, the temperature changes can be correlated with faults experienced by memory device 403 or future faults that memory device 403 may experience without additional RAIN coverage.

[0064] In various examples, memory device 403 may provide RBER. AI network 414 may monitor RBER to determine whether it increases during temperature changes to generate a cross-temperature limit. AI network 414 may generate RAIN adjustment based on the cross-temperature limit. The cross-temperature limit may be a threshold that can be used to determine whether to implement RAIN adjustment and / or what type of RAIN adjustment to implement.

[0065] In various instances, a rain adjustment can be implemented to prevent (e.g., tolerate) failure of the memory device 403. The rain adjustment can be performed before the memory device 403 experiences a failure. For example, the rain adjustment can be performed at a first temperature of the memory device 403, even if failure is not expected before a second temperature is reached. The difference between the second temperature and the first temperature can be a tolerance to prevent the memory device 403 from experiencing a failure.

[0066] Figure 5 This illustration shows a block diagram of a memory subsystem 515 for implementing RAIN adjustment based on RBER, according to several embodiments of the present disclosure. The memory subsystem 515 may include components directly or via, for example... Figure 1 The controller shown is coupled to the AI ​​network 514 of the memory device 503.

[0067] Memory device 503 may provide RBER to AI network 514. RBER may be a reading from memory device 503 or the controller of memory device 503 and / or the controller of memory subsystem 515. RBER may be a reading generated during operation or use of memory device 503. Memory device 503 may also provide feedback on stripes, blocks, and / or word lines of memory device 503. Feedback may be provided to AI network 514. Feedback may provide data about stripes, blocks, and / or word lines programmed with enhanced RAIN coverage due to high lifespan. Feedback may also describe the tolerance between fault conditions and pass conditions of memory device 503. Pass conditions describe the ability to decode data read from memory device 503.

[0068] AI network 514 can receive RBER and feedback. AI network 514 can monitor RBER to determine if RBER is increasing. It can monitor the increase in RBERT visible during the cycle to measure the average tolerance of the fault limit. RAIN adjustment calculation can maintain the tolerance from the fault level to extend the lifetime of memory device 503 or a portion of memory device 503 (e.g., stripes, blocks, and / or word lines).

[0069] In various instances, RBER can serve as an indicator of the cycles experienced by memory device 503. As memory device 503 ages, it is expected to have a larger RBER. Therefore, RAIN coverage can be strengthened as memory device 503 ages to reduce RBER and associated failure conditions of memory device 503.

[0070] In various instances, memory device 503 may provide the number of cycles of memory device 503, blocks of memory device 503, and / or word lines of memory device 503. AI network 514 may generate RAIN adjustments based on the number of cycles and / or RBER.

[0071] Figure 6 This illustration provides example flowcharts of a method 670 for implementing a data protection scheme according to several embodiments of the present disclosure. Method 670 can be executed by processing logic, which may include hardware (e.g., processing device, circuit system, dedicated logic, programmable logic, microcode, device hardware, integrated circuit, etc.), software (e.g., instructions that run or execute on the processing device), or a combination thereof. In some embodiments, by Figure 1 The control circuit system (e.g., controller) 105 executes method 670. Although shown in a specific sequence or order, the order of processes may be modified unless otherwise specified. Therefore, the illustrated embodiments should be understood as examples only, and the illustrated processes may be executed in different orders, and some processes may be executed in parallel. In addition, one or more processes may be omitted in various embodiments. Therefore, not all processes are required in every embodiment. Other process flows are possible.

[0072] At box 671, temperature data from a memory device coupled to the artificial intelligence (AI) accelerator can be received. At box 672, the memory device can implement a data protection scheme during operation. The AI ​​accelerator and the memory device can be located within the memory subsystem.

[0073] At box 673, an indication of a stripe fault in the memory device can be received. For example, the memory device can provide the indication to the controller of the memory subsystem. The memory subsystem can relay the indication to the AI ​​accelerator. At box 674, and based on temperature data and the indication of a stripe fault in the memory device, a data protection scheme adjustment for the memory device can be generated at the AI ​​accelerator. The AI ​​accelerator can provide the data protection scheme adjustment to the memory device. At box 675, the memory device can implement the data protection scheme adjustment.

[0074] The AI ​​accelerator can determine whether the temperature data indicates a temperature greater than a threshold temperature for the memory device. A temperature greater than the threshold may indicate the need for adjustments to data protection schemes to avoid or mitigate memory device failure.

[0075] It can receive multiple RBERs experienced by the memory device when generating previous temperature data. The AI ​​accelerator can generate a threshold temperature based on the multiple RBERs and previous temperature data.

[0076] It can also receive different indications that the memory device is fault-free. Based on temperature data and these different indications, the AI ​​accelerator can generate different data protection scheme adjustments for the memory device. These adjustments can strengthen the data protection scheme coverage in the memory device, while different adjustments can weaken the data protection scheme coverage.

[0077] In various instances, multiple memory devices can implement data protection schemes. An AI accelerator coupled to multiple memory devices can receive fault data from these devices. The AI ​​accelerator can also receive indications of faults in stripes of the multiple memory devices based on the fault data. For example, the fault data can cause the multiple memory devices to indicate that a fault has occurred or is about to occur in a stripe of the memory device. Based on the fault data and the indications of faults in the stripes of the multiple memory devices, adjustments to the data protection scheme for the multiple memory devices can be generated. The multiple memory devices can receive and implement these data protection scheme adjustments from the AI ​​accelerator.

[0078] In various examples, the AI ​​accelerator can receive indications of faults in blocks of multiple memory devices and indications of faults in word lines of the memory devices. The AI ​​accelerator can also receive indications of faults in stripes of multiple memory devices. Multiple memory devices configured to implement data protection scheme adjustments are further configured to adjust the ratio of parity elements to memory elements, to avoid utilizing blocks of multiple memory devices, and / or to adjust the number of storable bits in each of the multiple memory cells. Adjusting the number of storable bits in each of the multiple memory cells may include adjusting the memory cell from single-level cell (SLC) to multi-level cell (MLC) or from MLC to single-level cell (SLC). Data protection scheme adjustments can be selected by comparing fault data with multiple signatures including fault data using a table. For example, data protection scheme adjustments can be selected by comparing erase delay data and programming delay data with multiple signatures including erase delay data and programming delay data pairs using a table. In various instances, the signature includes erase delay data and programming delay data. The signature may also include erase delay data or programming delay data. The signature may further include fault data.

[0079] The AI ​​accelerator can generate additional data protection scheme adjustments for multiple blocks of the memory device based on the cycle count of multiple blocks and the RBER of multiple blocks of the memory device. Multiple blocks can have erase and programming latencies similar to those corresponding to erase latency and programming latency for faulty data.

[0080] The AI ​​accelerator can further provide data corresponding to the fault data to the cloud system to add it to the fault pool. The AI ​​accelerator can receive additional data protection scheme adjustments corresponding to the fault pool from the cloud system. The AI ​​accelerator can also generate data protection scheme adjustments for multiple memory devices that have not yet experienced faults by selecting data protection scheme adjustments from the additional data protection scheme adjustments. Fault data may include latency data, read latency data, erase latency data, and raw bit error rate (RBER).

[0081] Devices implementing AI data protection schemes can receive the RBER (Recovery Bit Rate) of the memory device at the AI ​​accelerator during the operation of the memory device. They can also receive data corresponding to the pass or fail conditions of the memory device. Based on the RBER and the data, adjustments to the data protection scheme for the memory device can be generated to extend its lifespan. These adjustments can then be implemented on the memory device.

[0082] Data corresponding to pass or fail conditions of stripes, blocks, and / or word lines of the memory device can be received by the AI ​​accelerator. The AI ​​accelerator can also generate data protection scheme adjustments for stripes, blocks, and / or word lines of the memory device. The AI ​​accelerator can also utilize data and RBER to generate an average tolerance for fail conditions. The AI ​​accelerator can also generate data protection scheme adjustments based on the average tolerance and fail conditions.

[0083] The system implementing the protection scheme may include an AI accelerator implemented in a cloud system and multiple memory devices implementing the data protection scheme. The AI ​​accelerator may be configured to receive manufacturing data and test data, receive status data describing the state of the multiple memory devices, and receive a fuse ID corresponding to at least one of the multiple memory devices. In response to the receipt of manufacturing data, test data, and status data, adjustments to the data protection scheme for the memory cell corresponding to the fuse ID may be generated. The multiple memory devices may be configured to implement adjustments to the data protection scheme for the memory cell corresponding to the fuse ID.

[0084] The AI ​​accelerator can generate a summary report for faults in stripes of multiple memory devices described in the status data that have not been adjusted by a data protection scheme. The summary report may include status data for inclusion in a pool of unsupported faults. This pool of unsupported faults can be used for manufacturing and testing NAND memory devices. The data protection scheme may be a standalone Redundant Array of Independent NAND (RAIN) scheme.

[0085] Figure 7 This describes an example machine of a computer system 790 within which a set of instructions for causing the machine to perform the various methods discussed herein can be executed. In various embodiments, the computer system 790 may correspond to a system that includes, is coupled to, or utilizes a memory subsystem (e.g., ...). Figure 1 The memory subsystem 115) or can be used to execute the controller (e.g., Figure 1 The system operating the controller circuit system 116) (e.g., Figure 1 (Computing system 100). In alternative embodiments, the machine may be connected (e.g., networked) to other machines in a LAN, intranet, extranet, and / or the Internet. The machine may operate as a peer machine in a peer-to-peer (or distributed) network environment or as a server or client machine in a cloud computing infrastructure or environment, or within the capacity of a server or client machine in a client-server network environment.

[0086] The machine may be a personal computer (PC), tablet PC, set-top box (STB), personal digital assistant (PDA), cellular telephone, network appliance, server, network router, switch, or bridge, or any machine capable of executing (sequentially or otherwise) a set of instructions specifying actions to be taken by said machine. Furthermore, while a single machine is described, the term "machine" should also be considered to include any set of machines that individually or collectively execute a set of instructions (or multiple sets of instructions) to perform any one or more of the methods discussed herein.

[0087] The example computer system 790 includes a processing device 791, a main memory 793 (e.g., read-only memory (ROM), flash memory, dynamic random access memory (DRAM), such as synchronous DRAM (SDRAM) or Rambus DRAM (RDRAM), etc.), a static memory 797 (e.g., flash memory, static random access memory (SRAM), etc.), and a data storage system 798, which communicate with each other via a bus 796.

[0088] Processing device 791 represents one or more general-purpose processing devices, such as microprocessors, central processing units, etc. More specifically, the processing device may be a Complex Instruction Set Computing (CISC) microprocessor, a Reduced Instruction Set Computing (RISC) microprocessor, a Very Long Instruction Word (VLIW) microprocessor, or a processor implementing other instruction sets, or a processor implementing a combination of instruction sets. Processing device 791 may also be one or more special-purpose processing devices, such as application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), digital signal processors (DSPs), network processors, etc. Processing device 791 is configured to execute instructions 792 for performing the operations and steps discussed herein. Computer system 790 may further include a network interface device 794 communicating via network 795.

[0089] The data storage system 798 may include a machine-readable storage medium 799 (also referred to as a computer-readable medium) on which one or more instruction sets 792 or software embodying any one or more methods or functions described herein are stored. The instructions 792 may also reside wholly or at least partially in main memory 793 and / or processing device 791 during execution by computer system 790, which also constitute machine-readable storage media.

[0090] In one embodiment, instruction 792 includes implementation corresponding to Figure 1 The machine-readable storage medium 799 is shown as a single medium in the exemplary embodiment, but the term "machine-readable storage medium" should be considered to include a single medium or multiple media storing one or more sets of instructions. The term "machine-readable storage medium" should also be considered to include any medium capable of storing or encoding a set of instructions executable by a machine and causing the machine to perform any one or more of the methods of this disclosure. Therefore, the term "machine-readable storage medium" should be considered to include, but is not limited to, solid-state memory, optical media, and magnetic media.

[0091] As used herein, “several things” can refer to one or more of such things. For example, “several memory devices” can refer to one or more memory devices. “Multiple things” means two or more. Additionally, designations such as “N” as used herein, especially with respect to reference numerals in the figures, indicate that several specific features so specified may be included together with several embodiments of this disclosure.

[0092] The figures in this document follow a numbering convention, where the first one or more numbers correspond to the figure number, and the remaining numbers identify elements or components in the figure. Similar elements or components between different figures can be identified by using similar numbers. It should be understood that elements shown in the various embodiments herein may be added, interchanged, and / or removed to provide several additional embodiments of this disclosure. Furthermore, the scale and relative proportions of the elements provided in the figures are intended to illustrate various embodiments of this disclosure and are not intended to be limiting.

[0093] While specific embodiments have been illustrated and described herein, those skilled in the art will understand that arrangements calculated to achieve the same results may replace the specific embodiments shown. This disclosure is intended to cover adaptations or variations of various embodiments of this disclosure. It should be understood that the above description is illustrative rather than restrictive. Combinations of the above embodiments and other embodiments not specifically described herein will be apparent to those skilled in the art upon review of the above description. The scope of the various embodiments of this disclosure includes other applications using the above structures and methods. Therefore, the scope of the various embodiments of this disclosure should be determined by reference to the full scope of the appended claims and the equivalents granted by such claims.

[0094] In the foregoing detailed description, various features have been grouped together in a single embodiment for the purpose of simplification. This approach of the present disclosure should not be construed as reflecting an intention that the disclosed embodiments of the present disclosure must use more features than are expressly stated in each claim. Rather, as reflected in the appended claims, the subject matter of the invention lies in less than all the features of a single disclosed embodiment. Therefore, the appended claims are hereby incorporated into the detailed description, wherein each claim is, in itself, a separate embodiment.

Claims

1. An apparatus comprising: Multiple memory devices, each implementing a data protection scheme; An artificial intelligence (AI) accelerator coupled to the plurality of memory devices; The AI ​​accelerator is configured to: Receive fault data from the plurality of memory devices; Based on the fault data, an indication of a fault in the stripe of the plurality of memory devices is received; as well as Based on the fault data and the indication of the fault in the stripe of the plurality of memory devices, an adjustment of the data protection scheme for the plurality of memory devices is generated; The plurality of memory devices are configured to: Receive the data protection scheme adjustment from the AI ​​accelerator; as well as Implement the aforementioned data protection scheme adjustments; and Additional data protection scheme adjustments for the multiple blocks of the multiple memory devices are generated based on the cycle counts of the multiple blocks of the multiple memory devices and based on the raw bit error rates of the multiple blocks of the multiple memory devices. The plurality of blocks have erase delays and programming delays similar to those corresponding to the erase delay and programming delay corresponding to the fault data.

2. The device of claim 1, wherein the AI ​​accelerator is further configured to receive indications of faults in blocks of the plurality of memory devices.

3. The device of claim 1, wherein the AI ​​accelerator is further configured to receive an indication of a fault in the word lines of the plurality of memory devices.

4. The device of claim 1, wherein the plurality of memory devices configured to implement the data protection scheme adjustment are further configured to adjust the ratio of parity check elements to memory elements.

5. The device of claim 1, wherein the plurality of memory devices configured to implement the data protection scheme adjustment are further configured to avoid using blocks of the plurality of memory devices.

6. The device of claim 1, wherein the plurality of memory devices configured to implement the data protection scheme adjustment are further configured to adjust the number of bits that each of the plurality of memory cells can store.

7. The apparatus of claim 6, wherein the plurality of memory devices are configured to adjust the number of bits that each of the plurality of memory cells can store from a single-level cell (SLC) to a multi-level cell (MLC).

8. The device of claim 6, wherein the plurality of memory devices are configured to adjust the level of the plurality of memory cells from a multilevel cell (MLC) to a single-level cell (SLC).

9. The device of claim 1, wherein the AI ​​accelerator is further configured to utilize an artificial neural network (ANN) to generate the data protection scheme adjustment.

10. The device of claim 1, wherein the AI ​​accelerator configured to generate the data protection scheme adjustment is further configured to select the data protection scheme adjustment by comparing the fault data with a plurality of signatures including the fault data using a table.

11. The device of claim 1, wherein the AI ​​accelerator is further configured to: The data corresponding to the fault data is provided to the cloud system to be added to the fault pool; as well as Receive additional data protection scheme adjustments from the cloud system corresponding to the fault in the pool; The data protection scheme adjustment is generated for faults that the plurality of memory devices have not yet experienced by selecting a data protection scheme adjustment from the additional data protection scheme adjustment.

12. The device according to claim 1, wherein the fault data includes delay data, read delay data, erase delay data, and raw bit error rate (RBER).

13. A method comprising: Receive the raw bit error rate (RBER) experienced by the time memory device before generating temperature data; The memory device receives temperature data coupled to the artificial intelligence (AI) accelerator, and the memory device implements a data protection scheme during operation of the memory device. A threshold temperature is generated at the AI ​​accelerator based on the multiple RBERs and previous temperature data; Receive an indication of a stripe failure in the memory device; At the AI ​​accelerator, determine whether the temperature data indicates that the temperature corresponding to the temperature data is greater than the threshold temperature of the memory device; Based on the indication that the temperature data is greater than the threshold temperature and the fault of the stripe of the memory device, an adjustment of the data protection scheme for the memory device is generated at the AI ​​accelerator; as well as The data protection scheme adjustment is implemented at the memory device.

14. The method of claim 13, further comprising: Receive different indications that the memory device is not faulty; as well as Based on the temperature data and the different indications of no faults in the memory device, different data protection scheme adjustments for the memory device are generated at the AI ​​accelerator.

15. The method of claim 14, wherein the data protection scheme adjustment strengthens the data protection scheme coverage in the memory device, and the different data protection scheme adjustments weaken the independent NAND redundant array RAIN coverage in the memory device.

16. An apparatus comprising: Memory devices that implement data protection schemes; An artificial intelligence (AI) accelerator coupled to the memory device; The AI ​​accelerator is configured to: The raw bit error rate (RBER) received from the memory device and during operation of the memory device; Receive data corresponding to the pass or fault conditions of the memory device; as well as Based on the RBER and the data, adjustments are made to the data protection scheme for the memory device to extend the lifespan of the memory device; The memory device is configured to implement the data protection scheme adjustment; Additional data protection scheme adjustments for the multiple blocks of the memory device are generated based on the cycle count of the multiple blocks of the memory device and based on the original bit error rate of the multiple blocks of the memory device. The plurality of blocks have erase delays and programming delays similar to those corresponding to the erase delay and programming delay corresponding to the fault data.

17. The device of claim 16, wherein the AI ​​accelerator is configured to receive the data corresponding to a pass or fail condition of a block or word line of the memory device.

18. The device of claim 16, wherein the AI ​​accelerator is configured to generate the data protection scheme adjustment for blocks or word lines of the memory device.

19. The device of claim 16, wherein the AI ​​accelerator is further configured to: Using the data corresponding to the pass or fail condition of the memory device and the RBER, an average tolerance for the failure condition is generated; and The data protection scheme is adjusted based on the average tolerance and the fault conditions.

20. A system comprising: AI accelerators are implemented in cloud systems; Multiple memory devices, each implementing a data protection scheme; The AI ​​accelerator is configured to: Receive manufacturing and testing data; Receive status data describing the status of the plurality of memory devices; Receive a fuse identifier ID corresponding to at least one of the plurality of memory devices; In response to the receipt of the manufacturing data, the test data, and the status data, an adjustment to the data protection scheme for the memory cell corresponding to the fuse ID is generated; as well as The plurality of memory devices are configured to implement the data protection scheme adjustment for the memory cell corresponding to the fuse ID.

21. The system of claim 20, wherein the AI ​​accelerator is further configured to generate a summary report for faults in stripes of the plurality of memory devices that are not adjusted by the data protection scheme as described in the status data.

22. The system of claim 21, wherein the AI ​​accelerator is further configured to provide the summary report containing the status data for inclusion in a pool of unsupported faults.

23. The system of claim 22, wherein the pool of unsupported faults is used for manufacturing and testing NAND memory devices.

24. The system of claim 20, wherein the data protection scheme is a redundant NAND array RAIN.

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