Method and system for calculating equivalent performance parameters of wiring area of ​​integrated circuit products

Abstract

This invention provides a method and system for calculating the equivalent performance parameters of routing areas in integrated circuit products. It involves preprocessing the design file data of the integrated circuit product, exporting the circuit diagram of each routing area, and determining the partitioning scheme based on the design characteristics of the circuit diagram. A mesoscopic finite element model of each partition is established based on its external geometric contour. Periodic boundary conditions and loads are added to the mesoscopic model of each partition, and a finite element solver is called to solve the response of the mesoscopic model. The equivalent performance parameters of the partition are calculated based on the solution results. A geometric model of the integrated circuit product is then established and partitioned. The aforementioned equivalent performance parameters are assigned to each partition of the geometric model of the routing area used for macroscopic finite element simulation. This invention can quickly, accurately, and in batches calculate the anisotropic equivalent performance parameters of each partition within each routing area according to the actual routing design corresponding to each partition in each routing layer, and has good applicability.

Description

Technical Field

[0001] The invention belongs to the technical field of integrated circuit design, and relates to a method and system for calculating equivalent performance parameters of a wiring area of ​​an integrated circuit product. Background Art

[0002] The statements in this section merely provide background information related to the present invention and do not necessarily constitute prior art.

[0003] At present, with the increasing development of the electronic information industry and the progress of integrated circuit design, manufacturing, and packaging, in order to meet the increasing functional and performance requirements of integrated circuit products, the entire integrated circuit industry is moving towards heterogeneous integration, complex structure, and miniaturization. Along with the above development characteristics, the reliability of integrated circuit products in the manufacturing and service process has become increasingly critical; if traditional experimental testing methods are used to conduct detailed research on its preparation and service process, the time and economic costs will increase dramatically. Therefore, in recent years, many people have carried out finite element simulation research on the manufacturing and service process of integrated circuit products, and how to improve the accuracy of simulation analysis in the finite element modeling process is crucial.

[0004] Taking the printed circuit board (PCB) as an example, the wiring design of different wiring layers inside it will inevitably lead to the non-uniform and asymmetric distribution of copper and resin in space. At the same time, since the characteristic size of the copper wire in the wiring layer is three to four orders of magnitude different from the overall size of the PCB, if the wiring layer is directly refined according to the actual morphology of the copper wire-resin, the calculation amount of the subsequent simulation analysis will be very large, and it is almost impossible to simulate and analyze it at the current level of computer computing power. This cross-scale feature is also common in the wiring area of ​​other integrated circuit products (such as the metallization layer used for component connection in the back-end process of chip manufacturing, the wiring layer in the chip packaging substrate, the rewiring layer in the chip three-dimensional packaging technology, and the silicon through-hole structure). This makes the application of finite element simulation methods to study the manufacturing and service process of integrated circuit products always have the problems of cumbersome and complex modeling process, insufficient simulation accuracy, and difficult computing power to support.

[0005] Therefore, in the modeling process of the wiring area, the modeling method that is widely recognized and adopted is the partition equivalent modeling method, that is, the wiring area of ​​the integrated circuit product is divided into multiple areas according to certain rules, and then the equivalent performance parameters corresponding to each partition are calculated and assigned to the corresponding partition, and then applied to the finite element simulation analysis of the preparation or service process of the overall integrated circuit product.

[0006] As a result, the accuracy of the calculation of the equivalent performance parameters of each partition directly affects the finite element simulation accuracy of the overall integrated circuit product. In existing research, the calculation of the equivalent performance parameters of the partitions uses an approximate calculation method: that is, based on the characteristic parameters such as the copper content of the partition, an empirical equation is used to calculate the equivalent performance parameters of each partition. This calculation method of the equivalent performance parameters rarely considers the material performance differences caused by complex characteristics such as the complex distribution and orientation of copper wires in the partitions of the wiring area, the distribution and size of holes, etc., and it is impossible to obtain accurate equivalent performance parameters for each partition, which in turn leads to the simulation analysis of integrated circuit products being unable to fully consider the complex response of these detailed characteristics of the wiring area to external loads, making the finite element simulation accuracy in this area low, and the guiding value for the design and manufacturing of integrated circuit products is insufficient. Summary of the invention

[0007] In order to solve the above problems, the present invention proposes a method and system for calculating equivalent performance parameters of wiring areas of integrated circuit products. The present invention can quickly, accurately and batch calculate the anisotropic equivalent performance parameters of each partition in each wiring area according to the actual wiring design corresponding to each partition in each wiring layer, thereby realizing higher-precision simulation research of integrated circuit products under general computer hardware conditions, and providing more valuable guidance for the design and manufacture of integrated circuit products.

[0008] According to some embodiments, the present invention adopts the following technical solutions:

[0009] A method for calculating equivalent performance parameters of a wiring area of ​​an integrated circuit product comprises the following steps:

[0010] Obtaining and processing circuit diagrams of various wiring areas of integrated circuit products;

[0011] Comprehensively consider the minimum feature size of the wiring area, the overall size of the integrated circuit product, and the computing power of the available computing resources, determine the partitioning scheme, and partition the corresponding wiring area according to the partitioning scheme;

[0012] Establishing a mesoscopic finite element model of each partition for calculating equivalent performance parameters;

[0013] Each microscopic finite element model is regarded as a unit cell, and according to the equivalent performance parameters to be solved, corresponding periodic boundary conditions are applied to solve and obtain the corresponding equivalent performance parameters;

[0014] Summarize all the equivalent performance parameters required for each partition;

[0015] According to the geometric outline of the integrated circuit product, a geometric model of the integrated circuit product for macroscopic finite element simulation is established, a geometric model of the wiring area is obtained accordingly, and the geometric model is partitioned according to the partitioning scheme;

[0016] The equivalent performance parameters of each partition obtained by solving the problem are correspondingly assigned to each partition of the geometric model, so as to obtain the equivalent performance parameters required by the macroscopic finite element model of the wiring area and establish the macroscopic finite element model of the wiring area.

[0017] As an optional implementation, the specific process of processing the circuit diagram of each wiring area of ​​the integrated circuit product includes: exporting the circuit diagram of each wiring area as a bitmap format image file, and performing image processing on the bitmap format image file, so as to represent different wiring materials of the wiring area with different colors.

[0018] As an optional implementation, the specific process of determining the partitioning scheme by comprehensively considering the minimum feature size of the wiring area, the overall size of the integrated circuit product, and the computing power of the available computing resources includes:

[0019] For an integrated circuit product with an X-direction size of L and a Y-direction size of W, the corresponding wiring layer is divided into i equal parts in the X-direction and j equal parts in the Y-direction, and a total of Q (Q = i × j) matrix-type rectangular partitions of equal size are obtained, and the size of each rectangular partition in the X-direction is u (u = L / i) and the size in the Y-direction is v (v = W / j), and the processed image is divided into the same matrix-type rectangular partition images of equal size, and each rectangular partition image of equal size corresponds to a partition, and each rectangular partition image has N columns of pixels distributed in the X-direction and M rows of pixels distributed in the Y-direction. Among them, if the values ​​of i and j are larger, the accuracy of the equivalent performance parameters calculated will be higher, but the calculation efficiency will be lower; therefore, the values ​​of i and j need to comprehensively consider the minimum feature size of the wiring area, the overall size of the integrated circuit product, and the computing power of the available computing resources, and be determined according to the target accuracy and target period of the equivalent performance parameter solution.

[0020] As an optional implementation, the mesoscopic finite element model is an actual mesoscopic geometric model, that is, an actual geometric model that reflects the specific geometric features of each partition of the wiring area and is established according to the actual circuit structure of each partition of the wiring area;

[0021] Or it can be a heterogeneous unit microscopic model, that is, according to the geometric outline of the partition of the wiring area, a regular hexahedral geometric model is established, and after the finite elements are divided, the material category on the corresponding wiring diagram is mapped according to the location of the element.

[0022] As an optional implementation, the process of establishing the heterogeneous unit microscopic finite element model includes:

[0023] Correspondingly, a hexahedral geometric model is established, whose in-plane X-direction dimension is consistent with the X-direction dimension of the rectangular partition image, whose Y-direction dimension is consistent with the Y-direction dimension of the rectangular partition image, and whose thickness-direction dimension is the actual wiring layer thickness. According to the pixel density of the rectangular partition image, the model is divided into N columns of finite elements in the X-direction of the plane and into M rows of finite elements in the Y-direction. Reasonable unit division is performed in the thickness direction according to the actual thickness. Based on the assumption of consistency of material distribution in the thickness direction of the wiring layer, each group of units with the same X and Y coordinates along the thickness direction is merged into one set.

[0024] The obtained rectangular partition image corresponding to the partition of the equivalent performance parameter to be solved is converted into an array of M rows × N columns according to its pixel value, and the items of the array correspond to the pixels of the rectangular partition image in row and column positions one by one;

[0025] According to the row (Y coordinate) and column (X coordinate) positions corresponding to each set, the pixel values ​​of the corresponding row (Y coordinate) and column (X coordinate) positions are retrieved one by one from the obtained array, and different material properties are assigned to the corresponding pixel value sets.

[0026] As an optional embodiment, the equivalent performance parameters include but are not limited to thermal, chemical and mechanical performance parameters.

[0027] As an optional implementation, a finite element solver is used to obtain corresponding equivalent performance parameters.

[0028] A system for calculating equivalent performance parameters of wiring areas of integrated circuit products, comprising:

[0029] A pre-processing module is configured to obtain and process the circuit diagram of each wiring area of ​​the integrated circuit product;

[0030] A partitioning module is configured to comprehensively consider the minimum feature size of the wiring area, the overall size of the integrated circuit product, and the computing power of the available computing resources, determine a partitioning scheme, and partition the corresponding wiring area according to the partitioning scheme;

[0031] A mesoscopic finite element model building module is configured to build a mesoscopic finite element model of each partition for calculating equivalent performance parameters;

[0032] The equivalent performance parameter calculation module is configured to regard each microscopic finite element model as a unit cell, and according to the equivalent performance parameter to be solved, apply corresponding periodic boundary conditions, and use the finite element solver to solve and obtain the corresponding equivalent performance parameter;

[0033] An equivalent performance parameter summary module is configured to summarize all equivalent performance parameters required by each partition;

[0034] A macro-geometric model building module is configured to build a geometric model of the integrated circuit product for macro-finite element simulation according to the geometric outline of the integrated circuit product, obtain a geometric model of the wiring area accordingly, and partition the geometric model according to the partitioning scheme;

[0035] The macro finite element model building module is configured to assign the equivalent performance parameters of each partition obtained by solving to each partition of the geometric model accordingly, obtain the equivalent performance parameters required by the macro finite element model of the wiring area, and build the macro finite element model of the wiring area.

[0036] A computer-readable storage medium stores a plurality of instructions, wherein the instructions are suitable for being loaded by a processor of a terminal device and executing the steps in the method.

[0037] A terminal device includes a processor and a computer-readable storage medium, wherein the processor is used to implement various instructions; and the computer-readable storage medium is used to store multiple instructions, wherein the instructions are suitable for being loaded by the processor and executing the steps in the described method.

[0038] Compared with the prior art, the present invention has the following beneficial effects:

[0039] (1) The equivalent performance calculation method of the wiring area of ​​an integrated circuit product based on the microscopic model proposed in the present invention is applicable to integrated circuit products of any size and any category;

[0040] (2) The calculation method proposed in the present invention can reflect the influence of the design characteristics of each partition of the wiring area on its equivalent performance parameters, thereby effectively improving the accuracy and reliability of the application of the finite element method to study integrated circuit products;

[0041] (3) The present invention is still feasible when applied to large-scale and complex integrated circuit products by applying a batch script tool, thereby making the finite element simulation of large-scale and complex integrated circuit products more efficient and reliable. BRIEF DESCRIPTION OF THE DRAWINGS

[0042] The accompanying drawings in the specification, which constitute a part of the present invention, are used to provide a further understanding of the present invention. The exemplary embodiments of the present invention and their descriptions are used to explain the present invention and do not constitute improper limitations on the present invention.

[0043] Figure 1 It is a schematic diagram of the process of the present invention;

[0044] Figure 2 is a wiring layer circuit diagram after binarization processing in an embodiment of the present invention;

[0045] Figure 3 is a heterogeneous unit model of the first six partitions of the first row of an embodiment of the present invention;

[0046] Among them, the dark color is copper and the light color is resin. DETAILED DESCRIPTION

[0047] The present invention will be further described below in conjunction with the accompanying drawings and embodiments.

[0048] It should be noted that the following detailed descriptions are all illustrative and intended to provide further explanation of the present invention. Unless otherwise specified, all technical and scientific terms used herein have the same meanings as those commonly understood by those skilled in the art to which the present invention belongs.

[0049] It should be noted that the terms used herein are only for describing specific embodiments and are not intended to limit exemplary embodiments according to the present invention. As used herein, unless the context clearly indicates otherwise, the singular form is also intended to include the plural form. In addition, it should be understood that when the terms "comprising" and / or "including" are used in this specification, it indicates the presence of features, steps, operations, devices, components and / or combinations thereof.

[0050] like Figure 1 As shown, a method for calculating equivalent performance parameters of the wiring area of ​​an integrated circuit product is provided. For an integrated circuit product, the design file data is first preprocessed to derive the circuit diagram of each wiring area, and the partitioning scheme is determined according to the design features of the circuit diagram. A microscopic finite element model of each partition is established according to the external geometric contour of the partition. Then, periodic boundary conditions and loads are added to the microscopic model of each partition, and a finite element solver is called to solve the response of the microscopic model and the equivalent performance parameters of the partition are calculated according to the solution results; finally, the calculation results are summarized into an equivalent performance parameter database of the partition. On the other hand, according to the external contour of the wiring layer of the integrated circuit product, a geometric model of the integrated circuit product for macroscopic finite element simulation is established and a geometric model of the wiring area is obtained; the partition is performed according to the determined partitioning scheme, and then the equivalent performance parameter database of the established partition is retrieved and correspondingly assigned to each partition of the geometric model of the wiring area for macroscopic finite element simulation.

[0051] Specifically, the following steps are included:

[0052] (1) Preprocess the design file data of integrated circuit products and analyze their geometric outlines and circuit diagrams of each wiring area;

[0053] (2) Exporting the circuit diagram of each wiring area into a bitmap format image file, with different colors representing different wiring materials in the wiring area; for example, for a printed circuit board, the copper material in the wiring area is represented by black, and the resin material is represented by white;

[0054] (3) determining a suitable partitioning scheme and performing partitioning according to the relative ratio of the minimum feature size of the wiring area to the overall size of the integrated circuit product and the computing power of available computing resources;

[0055] (4) according to the partitioning scheme determined in step (3), a mesoscopic finite element model for equivalent performance parameter calculation is established for the partition for which the equivalent performance parameter is to be solved;

[0056] (5) treating the microscopic finite element model established in step (4) as a unit cell, and applying corresponding periodic boundary conditions according to the equivalent performance parameters to be solved;

[0057] (6) Submit the solution to the finite element solver to obtain the corresponding equivalent performance parameters;

[0058] (7) Repeat steps (5) and (6) until each required equivalent performance parameter of the partition is obtained and summarized into an equivalent performance parameter table;

[0059] (8) Repeat steps (4) to (7) until the required equivalent performance parameters of each partition are obtained and summarized into an equivalent performance parameter database for future use;

[0060] (9) establishing a geometric model of the integrated circuit product for macroscopic finite element simulation based on the geometric profile of the integrated circuit product analyzed in step (1), obtaining a geometric model of the wiring area accordingly, and partitioning the geometric model of the wiring area in the macroscopic finite element model based on the partitioning scheme of the wiring area determined in step (3);

[0061] (10) The equivalent performance parameters of each partition obtained in step (8) are correspondingly assigned to each partition of the wiring area for macroscopic finite element simulation established in step (9), so as to obtain the equivalent performance parameters required by the macroscopic finite element model of the wiring area and establish the macroscopic finite element model of the wiring area.

[0062] In some embodiments, the bitmap format file described in step (2) should have a resolution that allows all wiring features to be clearly discernible;

[0063] In some embodiments, the microscopic finite element model established in step (4) can be an actual microscopic geometric model, that is, an actual geometric model that reflects the specific geometric characteristics of each partition of the wiring area based on the actual circuit structure; or it can be a heterogeneous unit model, that is, a regular hexahedral geometric model is established based on the geometric contours of the partitions of the wiring area, and after dividing the finite units, the material categories on the corresponding wiring diagram are mapped according to the locations of the units; the material categories include but are not limited to copper materials, resin materials and silicon materials; the mapping of material categories on the wiring diagram based on the locations of the units can be batch processed through scripts, so that the present invention is still feasible when applied to large-scale, complex integrated circuit products.

[0064] In some embodiments, the equivalent performance parameters to be solved in step (5) include but are not limited to thermal, chemical, and mechanical performance parameters.

[0065] In some embodiments, applying periodic boundary conditions to the finite element model in step (5) can be batch processed by scripts, so that the present invention is still feasible when applied to large-scale, complex integrated circuit products.

[0066] In some embodiments, the solver described in step (6) may be a general solver or a dedicated solver.

[0067] In some embodiments, the steps (5) and (6) described in step (7) are repeated until each required equivalent performance parameter of the partition is obtained and summarized into an equivalent performance parameter table. Batch processing can be performed through a script, so that the present invention is still feasible when applied to large-scale, complex integrated circuit products.

[0068] In some embodiments, steps (4) to (7) are repeated as described in step (8) until the required equivalent performance parameters of each partition are obtained, which are summarized into an equivalent performance parameter database and can be batch processed through scripts, so that the present invention is still feasible when applied to large-scale, complex integrated circuit products.

[0069] In some embodiments, the step (10) of assigning the equivalent performance parameters of each partition obtained in the step (8) to each partition of the wiring area for macroscopic finite element simulation established in the step (9) can be batch processed by a script, so that the present invention is still feasible when applied to large-scale, complex integrated circuit products.

[0070] Two typical embodiments are used as examples for description below.

[0071] Example 1: PCB partition equivalent performance calculation applied to the pressing manufacturing stage (before drilling)

[0072] This embodiment takes a small multi-layer PCB (94mm long, 61mm wide, 1mm thick) as an example, with the help of general finite element software and batch processing scripts developed based on Python language, and applies the micro-finite element model to realize the batch calculation and summary statistics of the equivalent mechanical performance parameters and equivalent thermal expansion coefficient of the PCB wiring layer partitions. This embodiment focuses on the solution accuracy of the equivalent performance parameters under the premise of acceptable solution efficiency. In addition, at the stage studied in this embodiment, the PCB has not been drilled, so only the influence of two materials, copper and resin, is considered. With the long side of 94mm as the X direction, the short side of 61mm as the Y direction, and the thickness direction as the Z direction, the specific implementation process is as follows:

[0073] (1) Output the circuit diagram of each wiring layer of the PCB from the PCB design software as a picture file in the portable network graphic (PNG) format; in order to ensure that the thinnest copper line is clearly visible, the resolution of the output picture file is 37 pixels / mm based on the minimum copper line width of the PCB;

[0074] (2) Binarize the output bitmap, uniformly process the copper distribution area as black (pixel value is 0), and the resin distribution area as white (pixel value is 1), as shown in the following figure: Figure 2 As shown;

[0075] (3) According to the relative ratio of the minimum copper wire width of the PCB to the overall size of the PCB, under the computing power of the available computing resources, in order to obtain higher calculation accuracy under the premise of acceptable calculation efficiency of equivalent performance parameters, the partitioning scheme is determined as follows: each wiring layer is divided into 94 columns in the X direction and 61 rows in the Y direction, resulting in a total of 5734 equal-sized partitions, each of which is a square with a side length of 1 mm; accordingly, the binary image obtained in step (2) is divided into 5734 (=61×94) equal-sized square images, each of which corresponds to a partition, and each image includes 1369 (=37×37) pixels;

[0076] (4) According to the partitioning scheme determined in step (3), a microscopic finite element model for equivalent performance calculation is established for the partition whose equivalent performance parameters are to be solved:

[0077] (4.1) A hexahedral geometric model with dimensions of 1 mm in the X and Y directions and the actual wiring layer thickness (35 μm) in the Z direction is established in a general finite element software. According to the pixel density of the partition image, the model is divided into 1369 (=37×37) finite elements in the X and Y directions and 4 layers of finite elements in the Z direction. Based on the assumption of consistency of material distribution in the thickness direction of the wiring layer, each group of 4 elements with the same X and Y coordinates along the thickness direction are merged into one set.

[0078] (4.2) Convert the square binary image corresponding to the partition of the equivalent performance parameter to be solved obtained in step (3) into a two-dimensional array of 37 rows × 37 columns according to its pixel values, and the items of the array correspond to the pixels of the square binary image in terms of row (Y coordinate) and column (X coordinate) positions one by one;

[0079] (4.3) According to the row (Y coordinate) and column (X coordinate) position corresponding to each set in step (4.1), the pixel values ​​of the corresponding row (Y coordinate) and column (X coordinate) position are retrieved one by one from the array obtained in step (4.2), and the set corresponding to the pixel value of 1 is assigned to the resin material, and the set corresponding to the pixel value of 0 is assigned to the copper material, such as Figure 3 As shown;

[0080] (5) applying corresponding periodic boundary conditions according to the equivalent performance parameters to be solved;

[0081] (6) Submit the general finite element solver to obtain the corresponding equivalent performance parameters;

[0082] (7) Repeat steps (5) and (6) until each required equivalent performance parameter of the partition is obtained and summarized into an equivalent performance parameter table, as shown in Table 1;

[0083] Table 1 Equivalent performance parameters calculated for a certain partition

[0084]

[0085] (8) Repeat steps (4) to (7) until equivalent performance parameters of all partitions are obtained and summarized into an equivalent performance parameter database;

[0086] (9) Establishing a geometric model of the PCB for macroscopic finite element simulation and obtaining a geometric model of the wiring layer, whose thickness dimension is consistent with the thickness dimension of the actual wiring layer, and partitioning the geometric model of the wiring layer into 1 mm × 1 mm partitions in the in-plane direction according to the partitioning scheme in step (3);

[0087] (10) The equivalent performance parameters of each partition obtained in step (8) are correspondingly assigned to each partition of the wiring area for macroscopic finite element simulation established in step (9), so as to obtain the equivalent performance parameters required by the macroscopic finite element model of the wiring area and establish the macroscopic finite element model of the wiring area.

[0088] Example 2: PCB equivalent performance calculation for reflow soldering and service stage

[0089] This embodiment takes a small multi-layer PCB (94mm long, 61mm wide, 1mm thick) as an example, with the help of general finite element software and batch scripts developed in Python language, and applies the micro-finite element model to realize the batch calculation and summary statistics of the equivalent mechanical performance parameters and equivalent thermal expansion coefficient of the wiring layer partitions in the reflow soldering and service stages after the PCB drilling process. This embodiment focuses on the solution efficiency of the equivalent performance parameters under the premise of acceptable solution accuracy. In addition, since the process stage under study needs to consider the influence of the holes in the PCB, the implementation method is slightly different from Example 1. With the long side of 94mm as the X direction, the short side of 61mm as the Y direction, and the thickness direction as the Z direction, the specific implementation process is as follows:

[0090] (1) Output the circuit diagram of each wiring layer of the PCB from the PCB design software as a .png image file; in order to ensure that the thinnest copper line is clearly visible, the resolution of the output image file is 37 pixels / mm based on the minimum copper line width of the PCB;

[0091] (2) grayscale the output bitmap, uniformly process the copper distribution area to black (pixel value is 0), the hole distribution area to gray (pixel value is 128), and the resin distribution area to white (pixel value is 255);

[0092] (3) According to the relative ratio of the minimum copper wire width of the PCB to the overall size of the PCB, under the computing power of the available computing resources, in order to obtain higher computing efficiency under the premise of acceptable equivalent performance parameter calculation accuracy, the partitioning scheme is determined as follows: each wiring layer is divided into 47 columns in the X direction and 30 rows in the Y direction, then the size of each partition is 2 mm in the X direction and 2.033 mm in the Y direction, and there are a total of 1410 (=47×30) equal-sized rectangular partitions; accordingly, the grayscale image obtained in step (2) is divided into 1410 equal-sized rectangular images, each image corresponds to a partition, and each image has 74 columns of pixels distributed in the X direction and 75 rows of pixels distributed in the Y direction;

[0093] (4) According to the partitioning scheme determined in step (3), a microscopic finite element model for equivalent performance calculation is established for the partition whose equivalent performance parameters are to be solved:

[0094] (4.1) A hexahedral geometric model with an in-plane dimension of 2 mm in the X direction, 2.033 mm in the Y direction, and the actual wiring layer thickness (35 μm) in the Z direction is established in a general finite element software. According to the pixel density of the partition image, the model is divided into 74 columns of finite elements in the X direction, 75 rows of finite elements in the Y direction, and 4 layers of finite elements in the Z direction. Based on the assumption of the consistency of material distribution in the thickness direction of the wiring layer, each group of elements along the thickness direction is merged into one set;

[0095] (4.2) Convert the rectangular partition image corresponding to the partition of the equivalent performance parameter to be solved obtained in step (3) into a two-dimensional array of 75 rows × 74 columns according to its pixel values, and the items of the array correspond to the pixels of the rectangular partition image in terms of row (Y coordinate) and column (X coordinate) positions one by one;

[0096] (4.3) According to the row (Y coordinate) and column (X coordinate) position corresponding to each set in step (4.1), the pixel values ​​of the corresponding row (Y coordinate) and column (X coordinate) position are retrieved one by one from the array obtained in step (4.2), and the set corresponding to the pixel value of 0 is assigned to the copper material, the set corresponding to the pixel value of 128 is assigned to the hole material, and the set corresponding to the pixel value of 255 is assigned to the resin material;

[0097] (5) applying corresponding periodic boundary conditions according to the equivalent performance parameters to be solved;

[0098] (6) Submit the general finite element solver to obtain the corresponding equivalent performance parameters;

[0099] (7) Repeat steps (5) and (6) until each required equivalent performance parameter of the partition is obtained and summarized into an equivalent performance parameter table;

[0100] (8) Repeat steps (4) to (7) until equivalent performance parameters of all partitions are obtained and summarized into an equivalent performance parameter database;

[0101] (9) Establishing a geometric model of the PCB for macroscopic finite element simulation and obtaining a geometric model of the wiring layer, whose thickness is consistent with the thickness of the actual wiring layer. According to the partitioning scheme in step (3), the geometric model of the wiring layer is equally divided into 47 columns in the X direction and 30 rows in the Y direction. The size of each partition is 2 mm in the X direction and 2.033 mm in the Y direction, and a total of 1410 (=47×30) rectangular partitions of equal size are obtained;

[0102] (10) The equivalent performance parameters of each partition obtained in step (8) are correspondingly assigned to each partition of the wiring area for macroscopic finite element simulation established in step (9), so as to obtain the equivalent performance parameters required by the macroscopic finite element model of the wiring area and establish the macroscopic finite element model of the wiring area.

[0103] The present invention also provides the following product embodiments:

[0104] A system for calculating equivalent performance parameters of wiring areas of integrated circuit products, comprising:

[0105] A pre-processing module is configured to obtain and process the circuit diagram of each wiring area of ​​the integrated circuit product;

[0106] A partitioning module is configured to comprehensively consider the minimum feature size of the wiring area, the overall size of the integrated circuit product, and the computing power of the available computing resources, determine a partitioning scheme, and partition the corresponding wiring area according to the partitioning scheme;

[0107] A mesoscopic finite element model building module is configured to build a mesoscopic finite element model of each partition for calculating equivalent performance parameters;

[0108] The equivalent performance parameter calculation module is configured to regard each microscopic finite element model as a unit cell, and according to the equivalent performance parameter to be solved, apply corresponding periodic boundary conditions, and use the finite element solver to solve and obtain the corresponding equivalent performance parameter;

[0109] An equivalent performance parameter summary module is configured to summarize all equivalent performance parameters required by each partition;

[0110] A macro-geometric model building module is configured to build a geometric model of the integrated circuit product for macro-finite element simulation according to the geometric outline of the integrated circuit product, obtain a geometric model of the wiring area accordingly, and partition the geometric model according to the partitioning scheme;

[0111] The macro finite element model building module is configured to assign the equivalent performance parameters of each partition obtained by solving to each partition of the geometric model accordingly, obtain the equivalent performance parameters required by the macro finite element model of the wiring area, and build the macro finite element model of the wiring area.

[0112] A computer-readable storage medium stores a plurality of instructions, wherein the instructions are suitable for being loaded by a processor of a terminal device and executing the steps in the above method.

[0113] A terminal device includes a processor and a computer-readable storage medium, wherein the processor is used to implement various instructions; the computer-readable storage medium is used to store multiple instructions, wherein the instructions are suitable for being loaded by the processor and executing the steps in the above method.

[0114] Those skilled in the art will appreciate that embodiments of the present invention may be provided as methods, systems, or computer program products. Therefore, the present invention may take the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware. Moreover, the present invention may take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage) containing computer-usable program code.

[0115] The present invention is described with reference to flowcharts and / or block diagrams of methods, devices (systems), and computer program products according to embodiments of the present invention. It should be understood that each process and / or block in the flowchart and / or block diagram, as well as the combination of processes and / or blocks in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to produce a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0116] These computer program instructions may also be stored in a computer-readable memory capable of directing a computer or other programmable data processing device to operate in a specific manner, so that the instructions stored in the computer-readable memory produce an article of manufacture comprising an instruction device, which implements the process Figure 1 A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.

[0117] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operating steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing instructions for implementing the process. Figure 1 A process or multiple processes and / or boxes Figure 1 The steps for the functions specified in one or more boxes.

[0118] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. For those skilled in the art, the present invention may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.

[0119] Although the above describes the specific implementation mode of the present invention in conjunction with the accompanying drawings, it is not intended to limit the scope of protection of the present invention. Those skilled in the art should understand that various modifications or variations that can be made by those skilled in the art on the basis of the technical solution of the present invention without creative work are still within the scope of protection of the present invention.

Claims

1. A method for calculating equivalent performance parameters of an integrated circuit product wiring area, characterized in that: The following steps are involved: Obtaining and processing circuit diagrams of various wiring areas of integrated circuit products; Comprehensively consider the minimum feature size of the wiring area, the overall size of the integrated circuit product, and the computing power of the available computing resources, determine the partitioning scheme, and partition the corresponding wiring area according to the partitioning scheme; Establishing a mesoscopic finite element model of each partition for calculating equivalent performance parameters; Each microscopic finite element model is regarded as a unit cell, and according to the equivalent performance parameters to be solved, corresponding periodic boundary conditions are applied to solve and obtain the corresponding equivalent performance parameters; Summarize all the equivalent performance parameters required for each partition; According to the geometric outline of the integrated circuit product, a geometric model of the integrated circuit product for macroscopic finite element simulation is established, a geometric model of the wiring area is obtained accordingly, and the geometric model is partitioned according to the partitioning scheme; The equivalent performance parameters of each partition obtained by solving the problem are correspondingly assigned to each partition of the geometric model, so as to obtain the equivalent performance parameters required by the macroscopic finite element model of the wiring area and establish the macroscopic finite element model of the wiring area.

2. A method for calculating equivalent performance parameters of an integrated circuit product wiring area as claimed in claim 1, characterized in that: The specific process of processing the circuit diagram of each wiring area of ​​the integrated circuit product includes: exporting the circuit diagram of each wiring area into a bitmap format image file, and performing image processing on the bitmap format image file, so as to represent different wiring materials of the wiring area with different colors.

3. The method for calculating equivalent performance parameters of wiring area of ​​an integrated circuit product as claimed in claim 1, characterized in that: Taking into account the minimum feature size of the wiring area, the overall size of the integrated circuit product, and the computing power of the available computing resources, the specific process of determining the partitioning scheme includes: For an integrated circuit product with an X-direction size of L and a Y-direction size of W, the corresponding wiring layer is equally divided into i parts in the X-direction and j parts in the Y-direction, and a total of Q matrix-type rectangular partitions of equal size are obtained, Q=i×j, and the size of each rectangular partition in the X-direction is u and the size in the Y-direction is v, u=L / i, v=W / j, and accordingly the processed image is divided into the same matrix-type rectangular partition images of equal size, each rectangular partition image of equal size corresponds to a partition, and each rectangular partition image has N columns of pixels distributed in the X-direction and M rows of pixels distributed in the Y-direction; The values ​​of i and j need to take into account the minimum feature size of the wiring area, the overall size of the integrated circuit product, and the computing power of the available computing resources, and are determined based on the target accuracy and target period of the equivalent performance parameter solution.

4. The method for calculating equivalent performance parameters of an integrated circuit product wiring area according to claim 1, characterized in that: The mesoscopic finite element model is an actual mesoscopic geometric model, that is, an actual geometric model that reflects the specific geometric features of each partition of the wiring area and is established according to the actual circuit structure of each partition of the wiring area; Or it can be a heterogeneous unit microscopic model, that is, according to the geometric outline of the partition of the wiring area, a regular hexahedral geometric model is established, and after the finite elements are divided, the material category on the corresponding wiring diagram is mapped according to the location of the element.

5. A method for calculating equivalent performance parameters of wiring areas of integrated circuit products as claimed in claim 4, characterized in that: When the mesoscopic finite element model is a heterogeneous unit mesoscopic model, the process of establishing the heterogeneous unit mesoscopic finite element model includes: Correspondingly, a hexahedral geometric model is established, whose in-plane X-direction dimension is consistent with the X-direction dimension of the rectangular partition image, whose Y-direction dimension is consistent with the Y-direction dimension of the rectangular partition image, and whose thickness-direction dimension is the actual wiring layer thickness. According to the pixel density of the rectangular partition image, the model is divided into N columns of finite elements in the X-direction of the plane and into M rows of finite elements in the Y-direction. Reasonable unit division is performed in the thickness direction according to the actual thickness. Based on the assumption of consistency of material distribution in the thickness direction of the wiring layer, each group of units with the same X and Y coordinates along the thickness direction is merged into one set. The obtained rectangular partition image corresponding to the partition of the equivalent performance parameter to be solved is converted into an array of M rows × N columns according to its pixel value, and the items of the array correspond to the pixels of the rectangular partition image in row and column positions one by one; According to the row corresponding to each set, Y Coordinates, columns, X Coordinate position, retrieve the corresponding rows one by one from the obtained array, that is, Y Coordinates, columns, X The pixel value at the coordinate position, and the corresponding pixel value set are assigned different material properties.

6. The method for calculating equivalent performance parameters of a wiring area of ​​an integrated circuit product as claimed in claim 1, characterized in that: The equivalent performance parameters include thermal, chemical and mechanical performance parameters.

7. A method for calculating equivalent performance parameters of an integrated circuit product wiring area as claimed in claim 1, characterized in that: The corresponding equivalent performance parameters are obtained by using the finite element solver.

8. A system for calculating equivalent performance parameters of wiring areas of integrated circuit products, characterized in that: include: A pre-processing module is configured to obtain and process the circuit diagram of each wiring area of ​​the integrated circuit product; A partitioning module is configured to comprehensively consider the minimum feature size of the wiring area, the overall size of the integrated circuit product, and the computing power of the available computing resources, determine a partitioning scheme, and partition the corresponding wiring area according to the partitioning scheme; A mesoscopic finite element model building module is configured to build a mesoscopic finite element model of each partition for calculating equivalent performance parameters; The equivalent performance parameter calculation module is configured to regard each microscopic finite element model as a unit cell, and according to the equivalent performance parameter to be solved, apply corresponding periodic boundary conditions, and use the finite element solver to solve and obtain the corresponding equivalent performance parameter; An equivalent performance parameter summary module is configured to summarize all equivalent performance parameters required by each partition; A macro-geometric model building module is configured to build a geometric model of the integrated circuit product for macro-finite element simulation according to the geometric outline of the integrated circuit product, obtain a geometric model of the wiring area accordingly, and partition the geometric model according to the partitioning scheme; The macro finite element model building module is configured to assign the equivalent performance parameters of each partition obtained by solving to each partition of the geometric model accordingly, obtain the equivalent performance parameters required by the macro finite element model of the wiring area, and build the macro finite element model of the wiring area.

9. A computer-readable storage medium, characterized in that: A plurality of instructions are stored therein, and the instructions are suitable for being loaded by a processor of a terminal device and executing the steps in the method as claimed in any one of claims 1 to 7.

10. A terminal device, characterized in that: The method comprises a processor and a computer-readable storage medium, wherein the processor is used to implement various instructions; and the computer-readable storage medium is used to store a plurality of instructions, wherein the instructions are suitable for being loaded by the processor and executing the steps in the method as claimed in any one of claims 1 to 7.

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