Series-Stacked Phase DC-DC Converter with Stable Operation

Abstract

A series-stacked phase DC-DC converter with stable operation is disclosed. A power converter circuit is also disclosed. In one aspect, the power converter circuit includes: a first top buck converter circuit coupled in parallel to a second top buck converter circuit at a first connection node and a second connection node; and a bottom buck converter circuit coupled in series to each of the first and second top buck converter circuits at the second connection node; a power input terminal coupled to the first and second top buck converter circuits; and a power output terminal coupled to the bottom buck converter circuit and the first connection node.

Description

[0001] Cross-reference to related applications

[0002] This application claims priority to U.S. Provisional Patent Application No. 63 / 236,116, filed August 23, 2021, entitled “Serial Stacked Phase DC-DC Converter with Stable Operation,” which is incorporated herein by reference in its entirety for all purposes. Technical Field

[0003] The described embodiments generally relate to power converters, and more specifically, embodiments of the invention relate to series-stacked DC-DC power converter circuits. Background Technology

[0004] Today, consumers have access to a wide variety of electronic devices. Many of these devices feature integrated circuits powered by regulated low-voltage DC power supplies. These low-voltage supplies are typically generated by dedicated power converter circuits that use a higher voltage input from a battery or other power source. In some applications, the dedicated power converter circuit can be one of the largest power dissipation components in an electronic device, and sometimes it consumes more space than the integrated circuit that powers it. As electronic devices become more complex and compact, there is a growing need for more efficient power converter circuits. Summary of the Invention

[0005] In some embodiments, a circuit is disclosed. The circuit includes: a first top buck converter circuit coupled in parallel to a second top buck converter circuit at a first connection node and a second connection node; and a bottom buck converter circuit coupled in series to each of the first and second top buck converter circuits at a second connection node; a power input terminal coupled to the first and second top buck converter circuits; and a power output terminal coupled to the bottom buck converter circuit and the first connection node.

[0006] In some embodiments, the first top buck converter circuit includes a first high-side switch coupled to a first low-side switch at a first switching node.

[0007] In some embodiments, the first top buck converter circuit includes a first flying capacitor coupled to the first switching node.

[0008] In some embodiments, the second top buck converter circuit includes a second high-side switch coupled to the second low-side switch at the second switching node.

[0009] In some embodiments, the power input terminal is coupled to first and second high-side switches.

[0010] In some embodiments, the second top buck converter circuit includes a second flying capacitor coupled to the second switching node.

[0011] In some embodiments, a first flying capacitor is coupled to a first inductor via a first switch, and a second flying capacitor is coupled to the first inductor via a second switch.

[0012] In some embodiments, the bottom buck converter circuit includes a third high-side switch coupled to a third low-side switch at a third switching node.

[0013] In some embodiments, the third switching node is coupled to the second inductor.

[0014] In some embodiments, the power output terminal is coupled to a third switching node via a second inductor and to a first connection node via a first inductor.

[0015] In some embodiments, a circuit is disclosed. The circuit includes: a first top buck converter circuit coupled to an input terminal; a second top buck converter circuit coupled to the input terminal, the first top buck converter circuit being coupled to the second top buck converter circuit at first and second connection nodes; a bottom buck converter circuit coupled to the first and second top buck converter circuits at a second connection node; and an output terminal coupled to the bottom buck converter circuit and the first connection node.

[0016] In some embodiments, the first top buck converter circuit includes a first high-side switch coupled to a first low-side switch at a first switching node.

[0017] In some embodiments, the first top buck converter circuit includes a first flying capacitor coupled to the first switching node.

[0018] In some embodiments, the second top buck converter circuit includes a second high-side switch coupled to the second low-side switch at the second switching node.

[0019] In some embodiments, the input terminal is coupled to first and second high-side switches.

[0020] In some embodiments, the second top buck converter circuit includes a second flying capacitor coupled to the second switching node.

[0021] In some embodiments, a first flying capacitor is coupled to a first inductor via a first switch, and a second flying capacitor is coupled to the first inductor via a second switch.

[0022] In some embodiments, the bottom buck converter circuit includes a third high-side switch coupled to a third low-side switch at a third switching node.

[0023] In some embodiments, the third switching node is coupled to the second inductor.

[0024] In some embodiments, the first and second top buck converter circuits and the bottom buck converter circuit are arranged to generate an output voltage at the output terminal that is lower than the input voltage at the input terminal. Attached Figure Description

[0025] Figure 1 This invention describes a series-stacked phase DC-DC power converter circuit according to an embodiment of the present disclosure.

[0026] Figure 2A This describes an embodiment of the present disclosure operating at a 50% duty cycle. Figure 1 The switching sequence and timing diagram of the circuit; and

[0027] Figure 2B This describes the operation with maximum duty cycle according to embodiments of the present disclosure. Figure 1 The switching sequence and timing diagram of the circuit. Detailed Implementation

[0028] The circuits and related techniques disclosed herein generally relate to power converters. More specifically, the circuits, apparatus, and related techniques disclosed herein relate to series-stacked phase DC-DC power converters. In some embodiments, charge transfer between the storage elements of the top phase and the storage elements of the bottom phase of a series-stacked phase DC-DC converter can be eliminated. Removing the charge transfer between the storage elements can eliminate positive feedback loops that may exist in the series-stacked phase DC-DC converter. By eliminating positive feedback loops, embodiments of this disclosure can prevent operational interruptions of the series-stacked phase DC-DC converter and provide continuous and stable operation of the converter.

[0029] In various embodiments, positive feedback loops can be eliminated and the converter can be stably operated, while allowing the converter to achieve a 100% duty cycle during its operation. Furthermore, embodiments of this disclosure can eliminate charge transfer between the top-phase and bottom-phase storage elements of the converter without using devices with higher rated voltages, thereby reducing system costs. Additionally, embodiments of this disclosure can prevent operational interruptions of series-stacked phase DC-DC power converters without affecting the efficiency of the power converter. Various inventive embodiments, including methods, processes, systems, apparatuses, etc., are described herein.

[0030] Several illustrative embodiments will now be described with reference to the accompanying drawings, which form part of this invention. The following description is merely illustrative and is not intended to limit the scope, applicability, or configuration of this disclosure. In fact, the following description of the embodiments will provide an enlightening description for those skilled in the art to implement one or more embodiments. It should be understood that various changes can be made to the function and configuration of elements without departing from the spirit and scope of this disclosure. In the following description, specific details are set forth for purposes of explanation in order to provide a thorough understanding of particular inventive embodiments. However, it will be apparent that various embodiments can be practiced without these specific details. The drawings and descriptions are not intended to be limiting. The terms “example” or “exemplary” are used herein to mean “serving as an example, illustration, or representation.” Any embodiment or design described herein as “exemplary” or “example” is not necessarily to be construed as preferred or superior to other embodiments or designs.

[0031] Figure 1 This describes a series-stacked phase DC-DC power converter circuit 100 according to an embodiment of the present disclosure. For example... Figure 1 As shown, circuit 100 may include the two top buck converter stages shown in segments 101 (top phase-A) and 103 (top phase-B). Circuit 100 may further include the bottom buck converter stage shown in segment 105 (bottom phase). The top or bottom phase buck converter stage may also be referred to as a top or bottom buck converter circuit. The high-side and low-side switches of the buck converter in top phase-A 101 are replicated in top phase-B 103. Top phase-A 101 and top phase-B 103 may be coupled to input terminal 111 and connection node 107 to form a parallel configuration. In addition, top phase-A 101 and top phase-B 103 may be coupled together at a first connection node 109. Input terminal 111 may be arranged to receive input voltage V. in Top phase-A 101 and top phase-B 103 can be connected in series to bottom phase 105 (with voltage V) at connection node 107. M Top phase-A 101 may be a buck converter stage that may include switches 102 and 104 connected in series, and top phase-B 103 may be a buck converter stage that may include switches 118 and 120 connected in series. Bottom phase 105 may be a buck converter that includes switches 106 and 108 connected in series. Circuit 100 may include flying capacitors 122 and 124. Flycap 122 may be coupled to switch node 141 and flycap 124 may be coupled to switch node 143. Circuit 100 may be connected between input terminal 111 and ground 115. Circuit 100 may include a stage with an output voltage V. outOutput terminal 154. Output terminal 154 can be coupled to load capacitor 130 and load 132. In some embodiments, V out The value can be less than V in The value. Circuit 100 may further include an inductor 128 coupled between the first connection node 109 and the output terminal 154. Circuit 100 may also include an inductor 126 connected between the switching node 145 and the output terminal 154.

[0032] Circuit 100 may further include a first clock generator 134 that generates a first clock Φ1 138, a second clock generator 136 that generates a second clock Φ2 140, and a third clock generator Φ 1A The third clock generator 142 of 146 and the generator of the fourth clock Φ 1B The fourth clock generator 144 of 148. In some embodiments, the third clock Φ 1A 146 and the fourth clock Φ 1B 148 can be generated from the first clock Φ1 138. Top phase-A 101 may further include switches 110 and 112. Switches 110 and 112 may be coupled to flycap 122. Switch 112 can be used to connect flycap 122 to ground, while switch 110 can be used to connect flycap 122 to inductor 128. Top phase-B may further include switches 114 and 116. Switches 114 and 116 may be coupled to flycap 124. Switch 116 can be used to connect flycap 124 to ground, while switch 114 can be used to connect flycap 124 to inductor 128. Switch 102 may be controlled by a third clock 146, while switches 104, 112, and 114 may be controlled by a clock 149 that is the inverse of the third clock 146. Switch 106 can be controlled by a second clock 140, while switch 108 can be controlled by a clock 151 that is the inverted version of the second clock 140. Switch 118 can be controlled by a fourth clock 148, while switches 110, 120, and 116 can be controlled by a clock 153 that is the inverted version of the fourth clock 148. In circuit 100, top phase-A 101 and top phase-B 103 can operate alternately to charge flycaps 122 and 124. Flycaps 122 and 124 provide a continuous power supply to bottom phase 105. In this way, connection node 107 can operate without the use of a charging capacitor, because either flycap 122 or 124 is continuously connected at connection node 107, thereby providing a supply voltage for the operation of bottom phase 105. Therefore, positive feedback loops are avoided, and operational interruptions of the series-stacked phase DC-DC power converter are prevented. Furthermore, circuit 100 can operate without positive feedback and without using devices with relatively high rated voltages, thereby reducing system costs.

[0033] Now also refer to Figure 1 and Figure 2A This illustrates an embodiment of the switching sequence of circuit 100 and timing diagram 200A. Timing diagram 200A illustrates the 50% duty cycle operation of circuit 100. In the first time period, referring to the top phase -A 101, when the third clock 146 is high, switch 102 can be controlled to turn on and charge flycap 122. Switches 104 and 112 can be controlled to turn off because they are controlled by the inversion of the third clock 146. Switch 110 can be controlled to turn on during this time period because switch 110 is controlled by the inversion of the fourth clock 148, which is high during this time period. Therefore, a switching sequence from V can be formed. in To flycap 122 to inductor 128 to V out The current path is such that flycap 122 is charged during this period. Similarly, referring to the top phase -B 103, when the fourth clock 148 is high, switch 118 can be controlled to turn on and charge flycap 124. Switches 120 and 116 can be turned off because they are controlled by clock 153 (the inverted version of the fourth clock 148). Switch 114 can be controlled to turn on during this period because it is controlled by the inverted version of the third clock 146, which is high during this period. Therefore, a current path from V... in To flycap 124 to inductor 128 to V out The current path. During this period, the flycap 124 is charged.

[0034] During the second time cycle, when the third clock 146 is low and its inverse is high, switches 104, 110, 112, 114, 116, and 120 can be controlled to turn on. Therefore, flycaps 122 and 124 are connected in parallel at node V. M Between and ground. This makes the connection to node V... M The capacitance is maximized. Furthermore, since switches 110 and 112 are connected in parallel to switches 114 and 116, the impedance of inductor 128 to ground is minimized. Additionally, since switches 104 and 120 appear in parallel configuration with node V in the flycap... M Therefore, the connection between flycap 122 and 124 and node V is established. M The effective resistance between them is minimized, and the effective resistance between flycaps 122 and 124 and ground 115 is also minimized due to the parallel configuration of switches 112 and 116. In this way, these switches can be optimized to be relatively small so that the converter can operate at peak efficiency.

[0035] Now also refer to Figure 1 and Figure 2B This illustrates an embodiment of the switching sequence of circuit 100 and timing diagram 200B. Timing diagram 200B illustrates the maximum duty cycle operation of circuit 100. In the maximum duty cycle operation mode, the first clock 138 operates at its maximum duty cycle, while the second clock 140 also operates at its maximum duty cycle. Circuit 100 can operate normally under these conditions, and its operation is uninterrupted. In some embodiments, during the charging cycle of inductor 128, two switches (102 and 110, or 118 and 114) may be present in series with inductor 128. A slight increase in the effective resistance in series with inductor 128 may slightly reduce the maximum efficiency of the converter; however, this is compensated for by the smaller losses of low-side operation of the top phase.

[0036] Those skilled in the art will understand that alternative methods exist for the switches in control circuit 100 to phase the switches in a way that achieves simpler overall loop control. In alternative switching schemes, instead of turning on all switches 104, 112, 110, 114, 116, and 120 together as previously described, active and inactive phases can be designed, wherein switch 110 is turned on when top phase-A is active, and switch 114 is turned on when top phase-B is active. In this switching scheme, inductor 128 can release its current via switches 110 and 112 or via switches 114 and 116. In this way, conditions such as zero inductor current can be monitored and detected relatively easily. In this scheme, flycap 122 and flycap 124 can be alternately used as flying capacitors and for node V. M The capacitors can operate, and may or may not have a short overlap period. In another example of a switching scheme, under light load conditions, flycap 122 and flycap 124 can operate in parallel to minimize power loss. In yet another example of a switching scheme, the terminals of either flycap 122 or 124 can be tri-state, which can be used to reduce noise and / or reduce capacitor-capacitor charge sharing losses. Those skilled in the art will further understand that alternative methods of switching in control circuit 100 can be used to optimize light load efficiency, or minimize area, and / or minimize electromagnetic interference (EMI).

[0037] Although this document describes and illustrates systems and methods for removing charge transfer across flying capacitors in a series-stacked phase DC-DC converter with regard to a particular configuration of a series-stacked DC-DC power converter circuit, embodiments of this disclosure are suitable for use with other configurations of power converters. For example, DC-DC power converter circuits may employ embodiments of this disclosure to eliminate positive feedback loops and operate more efficiently.

[0038] In some embodiments, the described switch may be formed in silicon or any other semiconductor material. In various embodiments, the described switch may be a transistor. In some embodiments, the described switch may be a metal-oxide-semiconductor field-effect transistor (MOSFET). In various embodiments, the disclosed MOSFETs may be formed on a single die well. In some embodiments, the disclosed series-stacked phase DC-DC converter may be monolithically integrated onto a single die. In various embodiments, top phase-A, top phase-B, and bottom phase may be formed on separate individual dies. In some embodiments, top phase-A, top phase-B, and bottom phase, and any combination thereof, may be formed in groups on separate dies; for example, top phase-A and top phase-B may be formed on a single die and bottom phase may be formed on another die, or top phase-A and bottom phase may be formed on a single die and top phase-B may be formed on another die. In various embodiments, the top phase-A, top phase-B, and bottom phase may be integrated into a single electronic package, such as, but not limited to, a quad flat no-lead (QFN) package, a dual flat no-lead (DFN) package, or a ball grid array (BGA) package. In some embodiments, the top phase-A, top phase-B, and bottom phase may be packaged separately into an electronic package. In various embodiments, controller circuitry and / or control logic circuitry may be integrated with the disclosed series-stacked phase DC-DC converter into a single die.

[0039] In the foregoing description, embodiments of this disclosure have been described with reference to numerous specific details that may vary with different implementations. Therefore, the description and drawings should be considered illustrative rather than restrictive. The unique and exclusive reference to the scope of this disclosure, and what the applicant intends to be the scope of this disclosure, is the literal and equivalent scope of the set of claims published in this application, including any subsequent amendments, in the specific form of such claims. Specific details of particular embodiments may be combined in any suitable manner without departing from the spirit and scope of the embodiments of this disclosure.

[0040] Additionally, spatially relative terms such as “bottom” or “top” may be used to describe the relationship of an element and / or feature to another element and / or feature, as illustrated in the diagrams. It will be understood that, in addition to the orientations depicted in the diagrams, the spatially relative terms are intended to cover different orientations of the device in use and / or operation. For example, if the device in the diagrams is flipped, then an element described as the “bottom” surface may be oriented “on” other elements or features. The device may be oriented in other ways (e.g., rotated 90 degrees or in other orientations) and the spatially relative descriptors used herein shall be interpreted accordingly.

[0041] As used herein, the terms “and,” “or,” and “one / or” can have a variety of meanings, which are expected to depend at least in part on the context in which such terms are used. Generally, if “or” is used to relate a list (such as A, B, or C), it implies A, B, and C, used here in an inclusive sense, and A, B, or C, used here in an exclusive sense. Additionally, the term “one or more” as used herein can be used to describe any feature, structure, or property in the singular, or to describe a combination of features, structures, or properties. However, it should be noted that this is merely an illustrative example, and the subject matter claimed is not limited to this example. Furthermore, if the term “at least one of” is used to relate a list (such as A, B, or C), it can be interpreted as referring to any combination of A, B, and / or C, such as A, B, C, AB, AC, BC, AA, AAB, ABC, AABBCCC, etc.

[0042] Throughout this specification, references to “an example,” “an instance,” “some instances,” or “exemplary embodiments” mean that a particular feature, structure, or characteristic described with respect to a feature and / or instance may be included in at least one feature and / or instance of the claimed subject matter. Therefore, the appearance of the phrases “in an example,” “an instance,” “in some instances,” “in some embodiments,” or other similar phrases throughout this specification does not necessarily refer to the same feature, instance, and / or limitation. Furthermore, a particular feature, structure, or characteristic may be combined in one or more instances and / or features.

[0043] In the preceding detailed description, numerous specific details have been set forth to provide a thorough understanding of the claimed subject matter. However, those skilled in the art will understand that the claimed subject matter can be practiced without these specific details. In other instances, methods and apparatus known to those of ordinary skill in the art have not been described in detail to avoid obscuring the claimed subject matter. Therefore, it is intended that the claimed subject matter be limited to the specific instances disclosed, but rather that it may also include all aspects falling within the scope of the appended claims and their equivalents.

Claims

1. A circuit comprising: A first top buck converter circuit is coupled in parallel to a second top buck converter circuit at a first connection node and a second connection node. Bottom buck converter circuit, which is coupled in series at the second connection node to each of the first top buck converter circuit and the second top buck converter circuit; A power input terminal, coupled to the first top-down buck converter circuit and the second top-down buck converter circuit, wherein the power input terminal is not directly connected to the first connection node; and A power output terminal is coupled to the bottom buck converter circuit and the first connection node, wherein the power output terminal is coupled to the first connection node only through a first inductor.

2. The circuit of claim 1, wherein the first top buck converter circuit includes a first high-side switch coupled to a first low-side switch at a first switching node.

3. The circuit of claim 2, wherein the first top buck converter circuit includes a first flying capacitor coupled to the first switching node.

4. The circuit of claim 3, wherein the second top buck converter circuit includes a second high-side switch coupled to the second low-side switch at the second switching node.

5. The circuit of claim 4, wherein the power input terminal is coupled to the first high-side switch and the second high-side switch.

6. The circuit of claim 4, wherein the second top buck converter circuit includes a second flying capacitor coupled to the second switching node.

7. The circuit of claim 6, wherein the first flying capacitor is coupled to the first inductor via a first switch, and the second flying capacitor is coupled to the first inductor via a second switch.

8. The circuit of claim 7, wherein the bottom buck converter circuit includes a third high-side switch coupled to a third low-side switch at a third switching node.

9. The circuit of claim 8, wherein the third switching node is coupled to the second inductor.

10. The circuit of claim 9, wherein the power output terminal is coupled to the third switching node via the second inductor and to the first connection node via the first inductor.

11. A circuit comprising: The first top buck converter circuit is coupled to the input terminal; A second top buck converter circuit is coupled to the input terminal, and the first top buck converter circuit is coupled to the second top buck converter circuit at a first connection node and a second connection node, wherein the input terminal is not directly connected to the first connection node. The bottom buck converter circuit is coupled to the first top buck converter circuit and the second top buck converter circuit at the second connection node; and An output terminal is coupled to the bottom buck converter circuit and the first connection node, wherein the output terminal is coupled to the first connection node only through a first inductor.

12. The circuit of claim 11, wherein the first top buck converter circuit includes a first high-side switch coupled to a first low-side switch at a first switching node.

13. The circuit of claim 12, wherein the first top buck converter circuit includes a first flying capacitor coupled to the first switching node.

14. The circuit of claim 13, wherein the second top buck converter circuit includes a second high-side switch coupled to the second low-side switch at the second switching node.

15. The circuit of claim 14, wherein the input terminal is coupled to the first high-side switch and the second high-side switch.

16. The circuit of claim 14, wherein the second top buck converter circuit includes a second flying capacitor coupled to the second switching node.

17. The circuit of claim 16, wherein the first flying capacitor is coupled to the first inductor via a first switch, and the second flying capacitor is coupled to the first inductor via a second switch.

18. The circuit of claim 17, wherein the bottom buck converter circuit includes a third high-side switch coupled to a third low-side switch at a third switching node.

19. The circuit of claim 18, wherein the third switching node is coupled to the second inductor.

20. The circuit of claim 11, wherein the first top buck converter circuit, the second top buck converter circuit, and the bottom buck converter circuit are arranged to generate an output voltage at the output terminal that is lower than the input voltage at the input terminal.

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