Memory cell structure and method of forming the same

Abstract

A memory cell structure and a method for forming the same, the method comprising: using a first sidewall and a second sidewall as masks, etching a transition floating gate layer until the substrate surface is exposed to form two mutually independent memory gate structures on the substrate and an opening between the two memory structures, each memory gate structure including a floating gate, a control gate dielectric layer located on the floating gate, and a control gate located on the control gate dielectric layer, the floating gate including a first region and a second region located on the first region, the first region including opposing first and second sidewalls, the first sidewalls facing adjacent memory gate structures, the second sidewalls protruding a first dimension relative to the control gate sidewalls, the first sidewalls protruding a second dimension relative to the control gate sidewalls, the second dimension being larger than the first dimension; forming an erase gate within the opening to improve the erase efficiency of the formed memory cell structure.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing technology, and in particular to a memory cell structure and its formation method. Background Technology

[0002] Flash memory, as an electrically programmable and erasable non-volatile storage device, is widely used in System-on-Chip (SoC). Structurally, flash memory devices can be mainly divided into stacked-gate structures and split-gate structures. Traditional stacked-gate flash memory structures suffer from reliability issues such as programming / erasing interference, over-erasing, charge retention characteristics, and write / erase durability. Split-gate flash memory structures, using a two-transistor cell structure, can effectively avoid the reliability problems of stacked-gate flash memory.

[0003] The split-gate flash memory structure includes an erase gate, a control gate, and a floating gate. The control gate is located above the floating gate and is isolated by a dielectric layer. The erase gate is located between two pairs of control gates and the floating gate, serving as a common erase gate. Two word lines are located on either side of the two pairs of control gates and the floating gate, each isolated by a dielectric layer. The oxide layer between the erase gate and the floating gate is a tunneling dielectric layer. The floating gate extends partially beneath the erase gate, forming an overlapping wrap-around structure. This unique structure improves erasing capability and efficiency. Due to its high reliability, excellent manufacturing process compatibility, low startup voltage, and prevention of over-erasure, the split-gate flash memory structure is widely used in embedded flash memory.

[0004] However, the erasure capability and efficiency of existing split-gate flash memory structures need further improvement. Summary of the Invention

[0005] The technical problem solved by this invention is to provide a storage cell structure and a method for forming the same, so as to improve the performance of the formed storage cell structure.

[0006] To solve the above-mentioned technical problems, the present invention provides a memory cell structure, comprising: a substrate; two mutually discrete memory gate structures located on the substrate, the two memory structures having an opening between them, each memory gate structure including a floating gate, a control gate dielectric layer located on the floating gate, and a control gate located on the control gate dielectric layer, the floating gate including a first region and a second region located on the first region, the first region including opposing first sidewalls and second sidewalls, the first sidewalls facing the adjacent memory gate structure, the second sidewalls protruding a first dimension relative to the control gate sidewalls, the first sidewalls protruding a second dimension relative to the control gate sidewalls, the second dimension being larger than the first dimension; an erase gate located within the opening; word lines located on both sides of the memory gate structure and the erase gate respectively; a first sidewall located between the second region, the control gate, the control gate dielectric layer sidewall, and the erase gate sidewall, the surface of the first sidewall being perpendicular to the first sidewall of the first region; and a second sidewall located between the second region, the control gate, the control gate dielectric layer sidewall, and the word line sidewall, the surface of the second sidewall being perpendicular to the second sidewall of the first region.

[0007] Optionally, the ratio of the second dimension to the dimension of the first region along the normal direction of the substrate ranges from 1.2:1 to 2:1.

[0008] Optionally, the second sidewall is also located between the second region, the control gate sidewall, and the erase gate sidewall; the first sidewall includes a second sidewall located between the second region, the control gate sidewall, and the erase gate sidewall, and a third sidewall located on the surface of the second sidewall between the second region, the control gate sidewall, and the erase gate sidewall.

[0009] Optionally, the substrate has a source region and a drain region; the source region is located in the substrate below the erase gate, and the drain region is located in the substrate on the side of the word line away from the control gate structure.

[0010] Optionally, the control gate dielectric layer includes a first dielectric layer, a second dielectric layer located on the surface of the first dielectric layer, and a third dielectric layer located on the surface of the second dielectric layer; the material of the first dielectric layer includes silicon oxide; the material of the second dielectric layer includes silicon nitride; and the material of the third dielectric layer includes silicon oxide.

[0011] Accordingly, the technical solution of the present invention also provides a method for forming a memory cell structure, comprising: providing a substrate; forming a floating gate material layer, a control gate dielectric material layer on the floating gate material layer, and a control gate material layer on the control gate dielectric material layer on the surface of the substrate; etching the control gate material layer, the control gate dielectric material layer, and the floating gate material layer to form a transition floating gate layer, two transition memory structures on the transition floating gate layer, and initial openings in the two transition memory structures, each of the transition memory structures including a second region of the floating gate, a control gate dielectric layer on the second region, and a control gate on the control gate dielectric layer, the transition memory structure having a third sidewall exposed by the sidewall of the initial opening, and a fourth sidewall opposite to the third sidewall; forming a first sidewall on the surface of the third sidewall; forming a second sidewall on the surface of the fourth sidewall, wherein the first sidewall has a larger dimension along the normal direction of the first sidewall. The dimensions of the second sidewall along the normal direction of the second sidewall; using the first sidewall and the second sidewall as masks, the transition floating gate layer is etched until the substrate surface is exposed to form two mutually independent memory gate structures on the substrate and an opening between the two memory structures. Each memory gate structure includes a floating gate, a control gate dielectric layer located on the floating gate, and a control gate located on the control gate dielectric layer. The floating gate includes a first region and a second region located on the first region. The second region is formed by the transition floating gate layer. The first region includes opposing first and second sidewalls. The first sidewall faces the adjacent memory gate structure. The second sidewall protrudes a first dimension relative to the control gate sidewall, and the first sidewall protrudes a second dimension relative to the control gate sidewall. The second dimension is larger than the first dimension. An erase gate is formed within the opening. Word lines are formed on both sides of the memory gate structure and the erase gate.

[0012] Optionally, the second sidewall is formed first, followed by the first sidewall, with the second sidewall also located on the third sidewall. The first sidewall includes a second sidewall located on the third sidewall and a third sidewall located on the surface of the second sidewall on the third sidewall. The method for forming the first sidewall includes: after forming the second sidewall, forming a first sidewall material layer on the surface of the transition floating gate layer, the top surface of the transition storage structure, and the sidewall surface; etching back the first sidewall material layer until the surface of the transition floating gate layer and the top surface of the transition storage structure are exposed, forming the third sidewall on the sidewall surface of the transition storage structure; and removing the third sidewall from the fourth sidewall surface.

[0013] Optionally, the method for removing the third sidewall from the surface of the fourth sidewall includes: forming a second mask layer on the surface of the substrate, the second mask layer exposing the top surface of the third sidewall of the fourth sidewall; and etching the third sidewall of the fourth sidewall using the second mask layer as a mask.

[0014] Optionally, the method for forming the second sidewall includes: after forming the initial opening, forming a second sidewall material layer on the surface of the transition grid layer, the top surface of the transition storage structure, and the sidewall surface; and etching back the second sidewall material layer until the surface of the transition grid layer and the top surface of the transition storage structure are exposed.

[0015] Optionally, before forming the second sidewall material layer and after forming the initial opening, a dielectric material layer is formed on the surface of the transition floating gate layer, the top of the transition storage structure, and the sidewall surface; the dielectric material layer is etched to form a fourth sidewall.

[0016] Optionally, after forming the third sidewall and before forming the first sidewall, the method further includes: implanting ions into the substrate on both sides of the transition storage gate structure to form a critical voltage layer in the substrate.

[0017] Optionally, the process parameters of the ion implantation process include: doping ions including P-type ions, energy range of 30 keV to 90 keV, and implantation dose range of 1E12 atom / cm. 2 Up to 3E14atom / cm 2 .

[0018] Optionally, before forming the floating gate material layer, a floating gate oxide material layer is also formed on the substrate surface.

[0019] Compared with the prior art, the technical solution of the embodiments of the present invention has the following beneficial effects:

[0020] In a method for forming a memory cell structure provided by the present invention, the floating gate includes a first region and a second region located on the first region. The first region includes a first sidewall and a second sidewall facing each other. The first sidewall faces the adjacent memory gate structure. The second sidewall protrudes by a first dimension relative to the control gate sidewall, and the first sidewall protrudes by a second dimension relative to the control gate sidewall. The second dimension is larger than the first dimension, which increases the portion of the floating gate that penetrates into the erase gate. The increased coupling area between the floating gate and the erase gate facilitates the tunneling of electrons in the floating gate into the erase gate, thereby improving the erasure efficiency of the formed memory cell structure.

[0021] Furthermore, ions are implanted into the substrate on both sides of the transition storage gate structure to form a critical voltage layer in the substrate. The storage cell structure is also a MOS device. The critical voltage layer is disposed between the source and drain of the device. The threshold voltage of the device can be adjusted by the critical voltage layer to control the turn-on or turn-off of the formed device.

[0022] In a memory cell structure provided by the present invention, the floating gate includes a first region and a second region located on the first region. The first region includes a first sidewall and a second sidewall facing each other. The first sidewall faces the adjacent memory gate structure. The second sidewall protrudes by a first dimension relative to the control gate sidewall, and the first sidewall protrudes by a second dimension relative to the control gate sidewall. The second dimension is larger than the first dimension, which increases the portion of the floating gate that penetrates into the erase gate. The increased coupling area between the floating gate and the erase gate facilitates the tunneling of electrons in the floating gate into the erase gate, thereby improving the erasure efficiency of the formed memory cell structure. Attached Figure Description

[0023] Figures 1 to 4 This is a schematic diagram illustrating the formation process of a storage cell structure.

[0024] Figures 5 to 13 This is a schematic diagram of the steps in the method for forming a storage cell structure according to an embodiment of the present invention. Detailed Implementation

[0025] It should be noted that the terms "surface" and "on" in this specification are used to describe the relative spatial position and are not limited to whether there is direct contact.

[0026] As described in the background section, the erasure capability and efficiency of existing split-gate flash memory structures need further improvement. A memory cell structure will now be described and analyzed in conjunction with this study.

[0027] Figures 1 to 4 This is a schematic diagram of the formation process of a storage unit structure.

[0028] Please refer to Figure 1 A substrate 101 is provided; a floating gate oxide material layer 102 is formed on the substrate 101; a floating gate material layer 103 is formed on the surface of the floating gate oxide material layer 102; a plurality of control gate structures are formed on a portion of the surface of the floating gate material layer 103, each control gate structure including two mutually independent control gates, each control gate including a dielectric layer 104, a control gate layer 105 located on the dielectric layer 104, and a hard mask layer 106 located on the control gate layer 105, each control gate structure including a first sidewall adjacent to the other control gate and a second sidewall opposite to the first sidewall.

[0029] Please refer to Figure 2 A first sidewall 107 is formed on each control gate sidewall; after the first sidewall 107 is formed, a second sidewall 108 is formed on the first sidewall of the control gate, and the second sidewall 108 is located between the first sidewall and the first sidewall 107.

[0030] Please refer to Figure 3Using the first sidewall 107, the second sidewall 108, and the control gate as a mask, the floating gate material layer 103 is etched until the floating gate oxide material layer 102 is exposed, forming a floating gate layer 109; a third sidewall 110 is formed on the sidewall of the floating gate layer 109.

[0031] Please refer to Figure 4 An erase gate 111 is formed on the surface of the substrate 101 between adjacent control gate layers 105 in each of the control gate structures; word lines 112 are formed on the surface of the substrate 101 on both sides of the control gate structure and the erase gate 111.

[0032] The above method is used to form a discrete gate flash memory structure. In each of the control gate structures, the sidewall of the floating gate layer 109 adjacent to another floating gate layer 109 is formed using a first sidewall 107 and a second sidewall 108 as a mask, and has a longer floating gate cantilever relative to the other side of the floating gate layer 109. The floating gate cantilever refers to the portion of the floating gate layer 109 that protrudes relative to the control gate layer 105 in a direction parallel to the surface of the substrate 100. Figure 3 As shown, the height 'a' of the floating gate cantilever along the direction normal to the surface of the substrate 100 is 350 angstroms, and the length 'b' of the floating gate cantilever along the direction parallel to the surface of the substrate 100 is 260 angstroms. In the formed split-gate flash memory structure, during the erase operation, the larger the length-to-height ratio of the floating gate cantilever, i.e., the more the floating gate cantilever extends into the erase gate 111, the more conducive it is for electrons in the floating gate layer 109 to tunnel through the floating gate cantilever into the erase gate, resulting in higher erase efficiency.

[0033] The length of the floating gate cantilever formed by the above method depends on the thickness of the first sidewall 107 and the second sidewall 108, and the height of the floating gate cantilever depends on the size of the normal of the floating gate layer 109 on the surface of the substrate 100. The improvement of the floating gate cantilever structure is limited, which is not conducive to improving the erasure capability and efficiency of the formed discrete gate flash memory structure.

[0034] To address the aforementioned issues, the present invention provides a method for forming a memory cell structure in which the floating gate includes a first region and a second region located on the first region. The first region includes opposing first and second sidewalls. The first sidewall faces an adjacent memory gate structure. The second sidewall protrudes a first dimension relative to the control gate sidewall, and the first sidewall protrudes a second dimension relative to the control gate sidewall. The second dimension is larger than the first dimension, thereby increasing the portion of the floating gate that penetrates into the erase gate. The increased coupling area between the floating gate and the erase gate facilitates electron tunneling in the floating gate into the erase gate, thereby improving the erasure efficiency of the formed memory cell structure.

[0035] To make the above-mentioned objectives, features and beneficial effects of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0036] Figures 5 to 13 This is a schematic diagram of the steps in the method for forming a storage cell structure according to an embodiment of the present invention.

[0037] Please refer to Figure 5 Substrate 200 is provided.

[0038] In this embodiment, the substrate 200 is made of silicon. In other embodiments, the substrate is made of silicon carbide, silicon germanium, a multi-element semiconductor material composed of group III-V elements, silicon-on-insulator (SOI), or germanium-on-insulator (GOI). The multi-element semiconductor material composed of group III-V elements includes InP, GaAs, GaP, InAs, InSb, InGaAs, or InGaAsP.

[0039] Subsequently, two mutually independent memory gate structures and an opening between the two memory structures are formed on the substrate. Each memory gate structure includes a floating gate and a control gate located on the floating gate. The floating gate includes a first region and a second region located on the first region. The first region includes opposing first and second sidewalls. The first sidewall faces the adjacent memory gate structure. The second sidewall protrudes a first dimension relative to the control gate sidewall, and the first sidewall protrudes a second dimension relative to the control gate sidewall. The second dimension is larger than the first dimension. For the method of forming the memory gate structure and the opening, please refer to [reference needed]. Figures 5 to 11 .

[0040] Please continue to refer to this. Figure 5 A floating gate material layer 201, a control gate dielectric material layer 205 on the floating gate material layer 201, and a control gate material layer 202 on the floating gate material layer 201 are formed on the surface of the substrate 200.

[0041] The floating gate material layer 201 is used to form the floating gate in the future; the control gate material layer 202 is used to form the control gate in the future; and the control gate dielectric material layer 205 is used to form the control gate dielectric layer in the future.

[0042] In this embodiment, before forming the floating gate material layer 201, a floating gate oxide material layer 204 is also formed on the surface of the substrate 200.

[0043] In this embodiment, the control gate dielectric material layer 205 includes a first dielectric material layer (not shown in the figure), a second dielectric material layer (not shown in the figure) located on the surface of the first dielectric material layer, and a third dielectric material layer (not shown in the figure) located on the surface of the second dielectric material layer; the material of the first dielectric material layer includes silicon oxide; the material of the second dielectric material layer includes silicon nitride; and the material of the third dielectric material layer includes silicon oxide.

[0044] Please refer to Figure 6 The control gate material layer 202, the control gate dielectric material layer 205, and the floating gate material layer 201 are etched to form a transition floating gate layer 300, two transition memory structures on the transition floating gate layer 300, and an initial opening 207 in the two transition memory structures. Each of the transition memory structures includes a second region II of the floating gate, a control gate dielectric layer 210 on the second region II, and a control gate 206 on the control gate dielectric layer 210. The transition memory structure has a third sidewall 208 exposed by the sidewall of the initial opening 207, and a fourth sidewall 209 opposite to the third sidewall 208.

[0045] In this embodiment, the method of etching the control gate material layer 202, the control gate dielectric material layer 205, and the floating gate material layer 201 further includes: forming a first mask layer 203 on a portion of the surface of the control gate material layer 202, and using the first mask layer 203 as a mask to etch the control gate material layer 202, the control gate dielectric material layer 205, and the floating gate material layer 201.

[0046] In this embodiment, the method for forming the first mask layer 203 includes: forming a first mask material layer (not shown in the figure) on a portion of the surface of the control gate material layer 202; forming a patterned photoresist layer (not shown in the figure) on a portion of the surface of the first mask material layer; and etching the first mask layer using the photoresist layer as a mask to form the first mask layer 203.

[0047] The transition floating gate layer 300 is used to subsequently form the first region of the floating gate.

[0048] Subsequently, a first sidewall is formed on the surface of the third sidewall 208; a second sidewall is formed on the surface of the fourth sidewall 209, wherein the dimension of the first sidewall along the normal direction of the first sidewall is greater than the dimension of the second sidewall along the normal direction of the second sidewall.

[0049] In this embodiment, the second sidewall is formed first, followed by the first sidewall. The second sidewall is also located on the third sidewall 208. The first sidewall includes the second sidewall located on the third sidewall 208 and a third sidewall located on the surface of the second sidewall of the third sidewall 208. Specifically, the method for forming the first sidewall and the second sidewall is described in [reference needed]. Figures 7 to 10 For more specific details on the method for forming the second sidewall, please refer to [reference needed]. Figure 7 .

[0050] Please refer to Figure 7 After forming the initial opening 207, a second sidewall material layer (not shown in the figure) is formed on the surface of the transition floating gate layer 300, the top surface of the transition storage structure, and the sidewall surface; the second sidewall material layer is etched back until the surface of the transition floating gate layer 300 and the top surface of the transition storage structure are exposed.

[0051] Specifically, the second sidewall material layer is also located on the surface of the first mask layer 203; the second sidewall material layer is etched back until the surface of the transition floating gate layer 300 and the top surface of the first mask layer 203 are exposed to form the second sidewall 211.

[0052] In this embodiment, before forming the second sidewall material layer and after forming the initial opening 207, a dielectric material layer 212 is formed on the surface of the transition floating gate layer 300, the top surface of the transition storage structure, and the sidewall surface. More specifically, the dielectric material layer 212 is also located on the surface of the first mask layer 203; the second sidewall material layer is etched back until the dielectric material layer 212 on the surface of the transition floating gate layer 300 and the top surface of the transition storage structure is exposed to form the second sidewall 211.

[0053] The material of the second sidewall material layer includes a dielectric material, which includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbon oxynitride, and silicon carbonitride. In this embodiment, the material of the second sidewall material layer is silicon nitride.

[0054] The medium material layer 212 is used to form the fourth sidewall.

[0055] Please refer to Figure 8 After forming the second sidewall 211, a first sidewall material layer (not shown in the figure) is formed on the surface of the transition floating gate layer 300, the top surface of the transition storage structure, and the sidewall surface; the first sidewall material layer is etched back until the surface of the transition floating gate layer 300 and the top surface of the transition storage structure are exposed, and the third sidewall 213 is formed on the sidewall surface of the transition storage structure.

[0056] Specifically, the first sidewall material layer is also located on the surface of the first mask layer 203. More specifically, the first sidewall material layer is also located on the surface of the dielectric material layer 212.

[0057] Specifically, the first sidewall material layer is etched back until the transition memory structure sidewall surface and the top surface of the first mask layer 203 are exposed. More specifically, the first sidewall material layer is etched back until the dielectric material layer 212 on the transition floating gate layer 300 and the dielectric material layer 212 on top of the first mask layer 203 are exposed. The material of the first sidewall material layer includes a dielectric material, which includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, and silicon carbonitride. In this embodiment, the material of the first sidewall material layer is silicon oxide.

[0058] The second sidewall 211 located on the third sidewall 208 and the third sidewall 213 located on the surface of the second sidewall 211 of the third sidewall 208 are used to subsequently form the first sidewall.

[0059] Please refer to Figure 9 After the third sidewall 213 is formed and before the first sidewall is formed, the method further includes: implanting ions into the substrate 200 on both sides of the transition storage gate structure to form a critical voltage layer 214 in the substrate 200.

[0060] In this embodiment, the method for forming the critical voltage layer 214 further includes: forming a third mask layer (not shown in the figure) on the surface of the substrate 200, the top surface of the transition storage structure and the opening 207, the third mask layer exposing the substrate 200 on both sides of the transition storage gate structure; using the third mask layer as a mask, implanting ions into the substrate 200 to form the adjacent voltage layer 214.

[0061] Specifically, the third mask layer exposes the transition floating gate layers 300 on both sides of the transition memory gate structure. More specifically, the third mask layer exposes the surface of the dielectric material layer 212 on the transition floating gate layers 300 on both sides of the transition memory gate structure.

[0062] The dielectric material layer 212 helps to improve the uniformity of ion implantation and enhance the performance of the critical voltage layer 214.

[0063] The process parameters for the ion implantation process include: doping ions including P-type ions, energy range of 30 keV to 90 keV, and implantation dose range of 1 E12 atom / cm². 2 Up to 3E14atom / cm 2 .

[0064] The memory cell structure is also a MOS device. The critical voltage layer is set between the source and drain of the device. The threshold voltage of the device can be adjusted by the critical voltage layer to control the opening or closing of the formed device.

[0065] Please refer to Figure 10 Remove the third sidewall 213 from the surface of the fourth sidewall 209.

[0066] In this embodiment, the method for removing the third sidewall 213 from the surface of the fourth sidewall 209 includes: forming a second mask layer (not shown in the figure) on the surface of the substrate 200, the second mask layer exposing the top surface of the third sidewall 213 of the fourth sidewall 209; and etching the third sidewall 213 of the fourth sidewall 209 using the second mask layer as a mask.

[0067] The first sidewall 215 includes a second sidewall 211 located on the third sidewall 208 and a third sidewall 213 located on the surface of the second sidewall 211. Subsequently, the first sidewall 215 is used as a mask to form the first region of the floating gate. The first sidewall 215 can be formed using multiple sidewall processes to increase the size of the subsequent first region sidewall protruding relative to the control gate sidewall.

[0068] In this embodiment, the dielectric material layer 212 is etched to form a fourth sidewall 216.

[0069] Please refer to Figure 11 Using the first sidewall 215 and the second sidewall 211 as masks, the transition floating gate layer 300 is etched until the surface of the substrate 200 is exposed to form two mutually independent memory gate structures on the substrate 200 and an opening 217 between the two memory structures. Each memory gate structure includes a floating gate, a control gate dielectric layer 210 located on the floating gate, and a control gate 206 located on the control gate dielectric layer 210. The floating gate includes a first region I and a second region II located on the first region I. The second region II is formed by the transition floating gate layer 300. The first region I includes a first sidewall a and a second sidewall b facing the adjacent memory gate structure. The second sidewall b protrudes a first dimension m relative to the control gate sidewall. The first sidewall a protrudes a second dimension n relative to the control gate sidewall. The second dimension n is greater than the first dimension m.

[0070] The second dimension n is greater than the first dimension m. Therefore, the resulting memory cell structure increases the portion of the floating gate that penetrates into the erase gate. The increased coupling area between the floating gate and the erase gate facilitates the tunneling of electrons in the floating gate into the erase gate, thereby improving the erasure efficiency of the resulting memory cell structure.

[0071] The ratio of the second dimension n to the dimension of the first region I along the normal direction of the substrate ranges from 1.2:1 to 2:1. Specifically, in this embodiment, the dimension of the first region I along the normal direction of the substrate 200 ranges from 150 angstroms to 300 angstroms; the second dimension n, i.e., the length of the first sidewall a relative to the protruding portion of the control gate 206 sidewall, ranges from 280 angstroms to 360 angstroms.

[0072] Please refer to Figure 12 This forms the erasure gate 218 within the opening 217.

[0073] In this embodiment, before forming the erase gate 218, a source region 219 is also formed in the substrate at the bottom of the opening 217.

[0074] In this embodiment, the method for forming the source region 219 includes: forming a fourth mask layer on the surface of the substrate 200, the fourth mask layer being located on the top and sidewalls of the storage gate structure, and the fourth mask layer exposing the bottom surface of the opening 217; using the fourth mask layer as a mask, implanting doped ions at the bottom of the opening 217 to form the source region 219; and removing the fourth mask layer.

[0075] In this embodiment, the method for forming the erase gate 218 includes: forming an erase gate material layer on the opening 217, the surface of the storage structure, and the surface of the substrate 200; forming a fifth mask layer on the surface of the erase gate material layer, the fifth mask layer exposing the erase gate material layer on the surface of the opening 217; and etching the erase gate material layer using the fifth mask layer as a mask until the top surface of the storage structure and the surface of the substrate 200 are exposed.

[0076] In this embodiment, after the source region 219 is formed, an erase gate material layer (not shown in the figure) is formed inside the opening 217 and on the surface of the fourth mask layer, and the erase gate material layer is etched back until the fourth mask layer is exposed.

[0077] In other embodiments, the methods for forming the erase gate 218 and the source region 219 are not limited thereto. In another embodiment, the source region may also be pre-formed in the substrate, and then two mutually discrete memory gate structures and an opening between the two memory structures are formed on the substrate, the opening exposing the source region.

[0078] Please refer to Figure 13 This forms the word lines 220 on both sides of the storage gate structure and the erase gate 218.

[0079] In this embodiment, after the word line 220 is formed, a drain region 221 is also formed in the storage gate structure, the erase gate 218 and the substrate 200 on both sides of the word line 220.

[0080] In this embodiment, the method for forming the drain region 221 includes: forming a sixth mask layer on the surface of the substrate 200, the surface of the storage gate structure, the erase gate 218 and the word line 220, the sixth mask layer exposing the substrate 200 on both sides of the storage gate structure, the erase gate 218 and the word line 220; and implanting doped ions into the substrate 200 to form the drain region 221.

[0081] Accordingly, one embodiment of the present invention also provides a storage cell structure formed using the above method. Please refer to [the documentation / reference]. Figure 13 It includes: a substrate 200; two discrete memory gate structures located on the substrate 200, the two memory structures having an opening 217 between them (e.g., ...). Figure 11 As shown), each memory gate structure includes a floating gate, a control gate dielectric layer on the floating gate, and a control gate 206 on the control gate dielectric layer. The floating gate includes a first region I and a second region II on the first region I. The first region I includes opposing first sidewalls a and b. The first sidewall a faces the adjacent memory gate structure. The second sidewall b protrudes by a first dimension m relative to the sidewall of the control gate 206. The first sidewall a protrudes by a second dimension n relative to the sidewall of the control gate 206. The second dimension n is greater than the first dimension m. Erasure is located within the opening 217. Gate 217; word lines 220 located on both sides of the storage gate structure and the erase gate 217 respectively; a first sidewall 215 located between the second region II, the control gate 206, the sidewall of the control gate dielectric layer 210 and the sidewall of the erase gate 217, the surface of the sidewall of the first sidewall 215 sharing a vertical plane with the first sidewall 215 of the first region I; a second sidewall 211 located between the control gate 206, the sidewall of the control gate dielectric layer 210 and the sidewall of the word line 220, the surface of the sidewall of the second sidewall 211 sharing a vertical plane with the second sidewall b of the first region I.

[0082] The memory cell structure increases the portion of the floating gate that extends into the erase gate, and the increased coupling area between the floating gate and the erase gate facilitates the tunneling of electrons in the floating gate into the erase gate, thereby improving the erasure efficiency of the formed memory cell structure.

[0083] The ratio of the second dimension n to the dimension of the first region I along the normal direction of the substrate ranges from 1.2:1 to 2:1. Specifically, in this embodiment, the dimension of the first region I along the normal direction of the substrate 200 ranges from 150 angstroms to 300 angstroms; the length of the first sidewall a relative to the protruding portion of the sidewall of the control gate 206 ranges from 280 angstroms to 360 angstroms.

[0084] In this embodiment, the second sidewall 211 is also located between the second region II, the sidewall of the control gate 206, and the sidewall of the erase gate 218; the first sidewall 215 includes the second sidewall 211 located between the second region II, the sidewall of the control gate 206, and the sidewall of the erase gate 218, and a third sidewall 213 (e.g., ...) located on the surface of the second sidewall 211 between the second region II, the sidewall of the control gate 206, and the sidewall of the erase gate 218. Figure 9 (As shown).

[0085] The substrate 200 has a source region 219 and a drain region 221; the source region 219 is located in the substrate 200 below the erase gate 218, and the drain region 221 is located in the substrate 200 on both sides of the memory gate structure, the erase gate 218 and the word line 220.

[0086] The control gate dielectric layer 210 includes a first dielectric layer (not shown in the figure), a second dielectric layer (not shown in the figure) located on the surface of the first dielectric layer, and a third dielectric layer (not shown in the figure) located on the surface of the second dielectric layer; the material of the first dielectric layer includes silicon oxide; the material of the second dielectric layer includes silicon nitride; and the material of the third dielectric layer includes silicon oxide.

[0087] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A storage cell structure, characterized in that, include: Substrate; Two independent memory gate structures are located on the substrate, with an opening between them. Each memory gate structure includes a floating gate, a control gate dielectric layer on the floating gate, and a control gate on the control gate dielectric layer. The floating gate includes a first region and a second region on the first region. The first region includes opposing first and second sidewalls. The first sidewall faces the adjacent memory gate structure. The second sidewall protrudes a first dimension relative to the control gate sidewall, and the first sidewall protrudes a second dimension relative to the control gate sidewall. The second dimension is larger than the first dimension. The erasure grid is located within the opening; Word lines located on both sides of the storage gate structure and the erase gate, respectively; A first sidewall located between the second region, the control gate, the control gate dielectric layer sidewall, and the erase gate sidewall, wherein the surface of the first sidewall is perpendicular to the first sidewall of the first region; A second sidewall located between the second region, the control gate, the control gate dielectric layer sidewall, and the word line sidewall, wherein the surface of the second sidewall is perpendicular to the second sidewall of the first region; The source region and drain region are located within the substrate, the source region being located within the substrate below the erase gate, and the drain region being located within the substrate on the side of the word line away from the control gate structure; The critical voltage layer is located within the substrate of the memory gate structure on the side near the drain region and between the source region and the drain region.

2. The storage cell structure as described in claim 1, characterized in that, The ratio of the second dimension to the dimension of the first region along the normal direction of the substrate ranges from 1.2:1 to 2:

1.

3. The storage cell structure as described in claim 1, characterized in that, The second sidewall is also located between the second region, the control gate sidewall, and the erase gate sidewall; the first sidewall includes a second sidewall located between the second region, the control gate sidewall, and the erase gate sidewall, and a third sidewall located on the surface of the second sidewall between the second region, the control gate sidewall, and the erase gate sidewall.

4. The storage cell structure as described in claim 1, characterized in that, The control gate dielectric layer includes a first dielectric layer, a second dielectric layer located on the surface of the first dielectric layer, and a third dielectric layer located on the surface of the second dielectric layer; the material of the first dielectric layer includes silicon oxide; the material of the second dielectric layer includes silicon nitride; and the material of the third dielectric layer includes silicon oxide.

5. A method for forming a storage cell structure, characterized in that, include: Provide substrate; A floating gate material layer, a control gate dielectric material layer on the floating gate material layer, and a control gate material layer on the control gate dielectric material layer are formed on the surface of the substrate. The control gate material layer, the control gate dielectric material layer, and the floating gate material layer are etched to form a transition floating gate layer, two transition memory structures on the transition floating gate layer, and initial openings in the two transition memory structures. Each transition memory structure includes a second region of the floating gate, a control gate dielectric layer on the second region, and a control gate on the control gate dielectric layer. The transition memory structure has a third sidewall exposed by the sidewall of the initial opening, and a fourth sidewall opposite to the third sidewall. A second sidewall is formed on the surfaces of the third and fourth sidewalls; A third sidewall is formed on the surface of the second sidewall of the transition storage structure; After the third sidewall is formed, ions are implanted into the substrate on both sides of the two transition storage structures and the initial opening to form a critical voltage layer in the substrate. After the critical voltage layer is formed, the third sidewall on the fourth sidewall surface is removed to form a first sidewall on the third sidewall surface. The first sidewall includes a second sidewall located on the third sidewall and a third sidewall located on the surface of the second sidewall of the third sidewall. The dimension of the first sidewall along the normal direction of the first sidewall is greater than the dimension of the second sidewall along the normal direction of the second sidewall. Using the first and second sidewalls as masks, the transition floating gate layer is etched until the substrate surface is exposed to form two mutually independent memory gate structures on the substrate and an opening between the two memory gate structures. Each memory gate structure includes a floating gate, a control gate dielectric layer located on the floating gate, and a control gate located on the control gate dielectric layer. The floating gate includes a first region and a second region located on the first region. The first region is formed by the transition floating gate layer. The first region includes opposing first and second sidewalls. The first sidewall faces the adjacent memory gate structure. The second sidewall protrudes a first dimension relative to the control gate sidewall. The first sidewall protrudes a second dimension relative to the control gate sidewall. The second dimension is larger than the first dimension. A source region is formed within the substrate at the bottom of the opening; After the drain area is formed, an erasure gate is formed within the opening; Forming the memory gate structure and word lines on both sides of the erase gate; A drain region is formed in the substrate on both sides of the storage gate structure, the erase gate, and the word line, such that the critical voltage layer is located between the source region and the drain region.

6. The method for forming a memory cell structure as described in claim 5, characterized in that, The method for forming the first sidewall includes: after forming the second sidewall, forming a first sidewall material layer on the surface of the transition grid layer, the top surface of the transition storage structure, and the sidewall surface; etching back the first sidewall material layer until the surface of the transition grid layer and the top surface of the transition storage structure are exposed, and forming the third sidewall on the sidewall surface of the transition storage structure.

7. The method for forming a memory cell structure as described in claim 6, characterized in that, The method for removing the third sidewall from the surface of the fourth sidewall includes: forming a second mask layer on the surface of the substrate, the second mask layer exposing the top surface of the third sidewall of the fourth sidewall; and etching the third sidewall of the fourth sidewall using the second mask layer as a mask.

8. The method for forming a memory cell structure as described in claim 7, characterized in that, The method for forming the second sidewall includes: after forming the initial opening, forming a second sidewall material layer on the surface of the transition grid layer, the top surface of the transition storage structure, and the sidewall surface; and etching back the second sidewall material layer until the surface of the transition grid layer and the top surface of the transition storage structure are exposed.

9. The method for forming a memory cell structure as described in claim 8, characterized in that, Before forming the second sidewall material layer, and after forming the initial opening, a dielectric material layer is formed on the surface of the transition floating grid layer, the top of the transition storage structure, and the sidewall surface. The dielectric material layer is etched to form a fourth sidewall.

10. The method for forming a memory cell structure as described in claim 5, characterized in that, The process parameters for the ion implantation process include: doping ions including P-type ions, energy range of 30 keV to 90 keV, and implantation dose range of 1E12 atom / cm. 2 Up to 3E14 atom / cm 2 .

11. The method for forming a memory cell structure as described in claim 5, characterized in that, Before forming the floating gate material layer, a floating gate oxide material layer is also formed on the surface of the substrate.

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