A pilot evaluation method for multi-chip integration on silicon substrates

Abstract

The present invention relates to a pilot evaluation method for multi-chip integration on a silicon substrate, comprising: a. setting a test system and an adapter; b. providing a window (10) on a PCB (7); using conductive glue to bond the edge of a silicon substrate (1) without an electrical connection portion to the edge of the window on the PCB; using bonding wires (3) to bond a test PAD point (2) on the silicon substrate to a PAD point (4) on the PCB; connecting the PAD point on the PCB to a pin header pad (6) via PCB wiring (5); and soldering a straight-insert pin header to the pin header pad; c. inserting the soldered straight-insert pin header into the adapter, running the test system software, and automatically judging whether the circuit test data is qualified according to a set threshold. The present invention can monitor the process of multi-chip integration on a silicon substrate during the development process, and can perform overall test evaluation after each chip is assembled, effectively locating the failure position, and avoiding failure analysis after all chips are subsequently installed.

Description

Technical field:

[0002] The invention belongs to the technical field of semiconductor testing, and in particular relates to a pilot evaluation method for multi-chip integration on a silicon substrate. Background technology:

[0004] Printed circuit boards (PCBs) have long served as the substrate for modular circuits, an essential component for the integrated configuration of components. However, over time, most modular circuits are trending towards miniaturization, with a major trend towards replacing packaged circuits with chips for modular integration. As a substrate, PCBs, due to material limitations, are a bottleneck to miniaturization. Furthermore, material inconsistencies with chips create significant stress during assembly, a significant challenge. Furthermore, modular circuits are increasingly becoming lightweight, and PCBs, as a significant component of their weight, are constrained by their inherent performance, making further reduction difficult. In this context, silicon wafers have emerged as a new substrate for modular circuits.

[0005] The manufacturing process of silicon wafers is similar to that of semiconductor chips and has the same function as PCB boards. During the manufacturing process, they can leave PAD points for chip welding or assembly, just like PCB boards. They can also run wiring inside to complete the electrical connection between components. In addition, silicon wafers can also be stacked and assembled through TSV through-holes, taking miniaturization a step further.

[0006] Multi-chip integration on silicon substrates has become a major trend, but testing during the assembly process has become a major challenge. A search of existing patents revealed that the Chinese invention patent, "A Method for Testing Electrical Connectivity of Double-Sided Substrates" (patent number: CN202011376754.9), proposes a method for testing electrical connections during silicon substrate fabrication. However, it does not address how to test electrical connections during multi-chip assembly. Summary of the invention:

[0008] The present invention designs a pilot evaluation method for multi-chip integration on a silicon substrate, which can effectively test and evaluate the electrical connection status during the multi-chip assembly process.

[0009] Technical solutions and measures adopted by the present invention to solve its technical problems

[0010] A pilot evaluation method for multi-chip integration on a silicon substrate, characterized by comprising:

[0011] a. Set up the test system and adapter. The test system includes a voltage / current unit, a differential voltmeter unit, a precision AC source unit, and a high-precision acquisition unit. The adapter includes a locking fixture and a system power interface. The voltage / current unit, differential voltmeter unit, precision AC source unit, high-precision acquisition unit, and locking fixture are electrically connected to the system power interface.

[0012] The units, locking fixtures, and system power supply interfaces used in the test system and adapter are all prior art;

[0013] b. There is a window on the PCB board. Use conductive glue to bond the edge of the silicon substrate without electrical connections to the edge of the window on the PCB board. Use bonding wire to bond the test PAD points on the silicon substrate to the PAD points on the PCB board. The PAD points on the PCB board are connected to the pin header pads through the PCB board wiring. The pin header pads are soldered to the pin headers;

[0014] c. Insert the soldered straight-plug pin header into the locking fixture on the adapter and run the test system software. The voltage / current unit, differential voltmeter, and precision AC source unit of the test system apply the required voltage / current to the silicon substrate under test. The test data is collected by the high-precision acquisition unit and the final test results are obtained after calculation. The test data is displayed on the computer host / display, and the circuit test data is automatically judged to be qualified according to the set threshold.

[0015] As needed, a peripheral processing circuit connected to the system power interface may be further provided in the adapter.

[0016] Advantageous Effects of the Invention

[0017] Through the present invention, the process of multi-chip integration on a silicon substrate during the development process can be monitored, the status of the module can be effectively controlled, and an overall test and evaluation can be performed after each chip is assembled, effectively locating the failure position, avoiding the inability to perform failure analysis after all subsequent installations. At the same time, by evaluating the module status in real time, the assembly of subsequent chips after failure can be avoided, greatly reducing the development cost. Description of the drawings:

[0019] Figure 1 This is a schematic diagram of silicon substrate assembly on a custom PCB board;

[0020] Figure 2 It is a structural schematic diagram of the present invention. Specific implementation method:

[0022] like Figure 1 As shown, the structure after assembling the silicon substrate on the customized PCB board includes a silicon substrate 1, a PAD point 2 for testing on the silicon substrate, a bonding wire 3, a PAD point 4 on the PCB board, a PCB board wiring 5, a pin pad 6, and a customized PCB board 7.

[0023] Conductive adhesive is used to bond the edge 1a of the silicon substrate 1, which does not have electrical connections, to the edge of a custom PCB board 7, where a window 10 is located. This allows for subsequent cutting and removal of the silicon substrate, ensuring that subsequent chip integration can continue after bonding to the PCB. Bonding wire 3 is used to connect the test pad 2 on the silicon substrate to the pad 4 on the PCB. The pad 4 on the PCB is then connected to the pin header pad 6 via PCB wiring 5, allowing for subsequent soldering of the in-line pin header 14, which is then inserted into the adapter's socket for direct testing on the test system.

[0024] like Figure 2 As shown, the present invention mainly provides a pilot evaluation method for multi-chip integration on a silicon substrate, including a test system which is an analog test system, including a voltage / current unit, a differential voltmeter unit, a precision AC source unit, and a high-precision acquisition unit 5; an adapter is designed for connecting the test system, including a locking fixture 7, a system power interface 8, and, if necessary, a peripheral processing circuit 9;

[0025] The specific implementation process is as follows: During the actual test, the edge of the silicon substrate 1 to be tested is bonded to the PCB window 10 using conductive adhesive 11. The size of the silicon substrate 1 to be tested is slightly larger than the size of the PCB window 10. The test PAD point on the silicon substrate is bonded to the PAD point on the PCB board using bonding wire 3. The straight-plug pin header 14 is soldered and inserted into the locking clamp on the adapter. The test system software is run, and the voltage / current unit, differential voltmeter, and precision AC source unit of the test system apply the required voltage / current to the silicon substrate to be tested. The test data is collected by the high-precision acquisition unit, and the final test results are obtained after calculation. The test data is displayed on the computer host / display, and the circuit test data is automatically judged to be qualified based on the set threshold.

Claims

1. A pilot evaluation method for multi-chip integration on a silicon substrate, characterized in that include: a. Set up the test system and adapter. The test system includes a voltage / current unit, a differential voltmeter unit, a precision AC source unit, and a high-precision acquisition unit. An adapter, including a locking fixture, a system power interface (8); a voltage / current unit, a differential voltmeter unit, a precision AC source unit, a high-precision acquisition unit, and a locking fixture electrically connected to the system power interface (8); b. A window (10) is provided on the PCB board (7), and the edge of the silicon substrate (1) without the electrical connection portion is bonded to the edge of the PCB board window (10) using conductive glue, and the test PAD point (2) on the silicon substrate is bonded to the PAD point (4) on the PCB board using bonding wire (3), and the PAD point (4) on the PCB board is connected to the pin pad (6) through the PCB board wiring (5), and the pin pad (6) is welded to the straight-insert pin (14); c. Insert the soldered straight-insert pin header (14) into the locking fixture on the adapter, run the test system software, and use the voltage / current unit, differential voltmeter, and precision AC source unit of the test system to apply the required voltage / current to the silicon substrate to be tested. The test data is collected by the high-precision acquisition unit, and the final test results are obtained after calculation. The test data is displayed on the computer host / display, and the circuit test data is automatically judged to be qualified according to the set threshold.

2. A pilot evaluation method for multi-chip integration on a silicon substrate according to claim 1, characterized in that include: The adapter is also provided with a peripheral processing circuit connected to the system power interface (8).

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