Decoder driving circuit and method thereof, word line decoding circuit, and semiconductor memory

Abstract

The embodiment of the present application provides a decoding drive circuit and its method, a word line decoding circuit, and a semiconductor memory. The decoding drive circuit includes at least one decoding drive unit, and the decoding drive unit includes a first-stage drive circuit and a second-stage drive circuit. Among them, the first-stage drive circuit is used to receive an enable control signal, a decoding input signal, and a drive control signal, and generate a first drive signal and a second drive signal according to the enable control signal, the drive control signal, and the decoding input signal. The second-stage drive circuit is used to generate a target word line drive signal according to the first drive signal and the second drive signal. In this way, the embodiment of the present application provides a new decoding drive circuit. The decoding drive circuit amplifies the decoding input signal in two stages according to the drive control signal, which can not only improve the circuit efficiency, save the circuit area, but also improve the performance of the DRAM.

Description

Technical Field

[0001] The present application relates to the technical field of integrated circuits, and in particular to a decoding driving circuit and method thereof, a word line decoding circuit and a semiconductor memory. Background Art

[0002] Dynamic Random Access Memory (DRAM) is a semiconductor memory device commonly used in computers. It consists of many repeated storage cells. Different storage cells need to be selected through word lines and bit lines. However, the circuit design of the current DRAM related word lines is unreasonable, resulting in the need to improve the performance of DRAM. Summary of the invention

[0003] The present application provides a decoding driving circuit and method thereof, a word line decoding circuit and a semiconductor memory, which can improve efficiency and save area.

[0004] The technical solution of this application is implemented as follows:

[0005] In a first aspect, an embodiment of the present application provides a decoding driving circuit, the decoding driving circuit comprising at least one decoding driving unit, the decoding driving unit comprising a first-stage driving circuit and a second-stage driving circuit; wherein:

[0006] The first stage driving circuit is used to receive an enable control signal, a decoded input signal and a driving control signal, and generate a first driving signal and a second driving signal according to the enable control signal, the driving control signal and the decoded input signal;

[0007] The second-stage driving circuit is used to generate a target word line driving signal according to the first driving signal and the second driving signal.

[0008] In a second aspect, an embodiment of the present application provides a decoding driving method, which is applied to a decoding driving circuit, wherein the decoding driving circuit includes at least one decoding driving unit, and the decoding driving unit includes a first-level driving circuit and a second-level driving circuit; the method includes:

[0009] Receiving an enable control signal, a decoded input signal and a drive control signal through a first-stage drive circuit, and generating a first drive signal and a second drive signal according to the enable control signal, the drive control signal and the decoded input signal;

[0010] The first driving signal and the second driving signal are received by the second-stage driving circuit, and a target word line driving signal is generated according to the first driving signal and the second driving signal.

[0011] In a third aspect, an embodiment of the present application provides a word line decoding circuit, which includes a word line driving circuit, an inverted main word line driving circuit, and a local decoding driving circuit; wherein, the word line driving circuit at least includes the decoding driving circuit as in the first aspect.

[0012] In a fourth aspect, an embodiment of the present application provides a semiconductor memory, which includes the word line decoding circuit as in the third aspect.

[0013] An embodiment of the present application provides a decoding driving circuit and its method, a word line decoding circuit, and a semiconductor memory. The decoding driving circuit includes at least one decoding driving unit, and the decoding driving unit includes a first-stage driving circuit and a second-stage driving circuit; wherein, the first-stage driving circuit is configured to receive an enable control signal, a decoding input signal, and a driving control signal, and generate a first driving signal and a second driving signal according to the enable control signal, the driving control signal, and the decoding input signal; the second-stage driving circuit is configured to generate a target word line driving signal according to the first driving signal and the second driving signal. In this way, an embodiment of the present application provides a new decoding driving circuit, which amplifies the decoding input signal in two stages according to the driving control signal, not only improving the circuit efficiency, saving the circuit area, but also improving the driving performance. Description of the Drawings

[0014] Figure 1 It is a schematic diagram of a partial structure of a DRAM provided by an embodiment of the present application;

[0015] Figure 2 It is a schematic diagram of the structure of a storage unit provided by an embodiment of the present application;

[0016] Figure 3 It is a schematic diagram of the structure of a local word line driving unit provided by an embodiment of the present application;

[0017] Figure 4 It is a schematic diagram of the structure of a group of local word line driving units provided by an embodiment of the present application;

[0018] Figure 5 It is a schematic diagram of a partial structure of another DRAM provided by an embodiment of the present application;

[0019] Figure 6 It is a schematic diagram of a partial structure of yet another DRAM provided by an embodiment of the present application;

[0020] Figure 7 It is a schematic diagram of the structure of a WLDV decoding driving unit provided by the related art;

[0021] Figure 8 It is a schematic diagram of the structure of a WLRst decoding driving unit provided by an embodiment of the present application;

[0022] Figure 9 Schematic diagram of the structure of a bMWL decoding and driving unit provided by an embodiment of the present application;

[0023] Figure 10 Schematic diagram of the structure of a decoding and driving circuit provided by an embodiment of the present application;

[0024] Figure 11 Schematic diagram of the structure of another decoding and driving circuit provided by an embodiment of the present application;

[0025] Figure 12 Schematic diagram of the specific structure of a decoding and driving circuit provided by an embodiment of the present application;

[0026] Figure 13 Schematic diagram of the specific structure of another decoding and driving circuit provided by an embodiment of the present application;

[0027] Figure 14 Schematic diagram of the flow of a decoding and driving method provided by an embodiment of the present application;

[0028] Figure 15A Schematic diagram of the process of short - circuit defect detection provided by an embodiment of the present application;

[0029] Figure 15B Schematic diagram of the process of another short - circuit defect detection provided by an embodiment of the present application;

[0030] Figure 16A Schematic diagram of the process of yet another short - circuit defect detection provided by an embodiment of the present application;

[0031] Figure 16B Schematic diagram of the process of still another short - circuit defect detection provided by an embodiment of the present application;

[0032] Figure 17 Schematic diagram of the structure of a word - line decoding circuit provided by an embodiment of the present application;

[0033] Figure 18 Schematic diagram of the structure of a semiconductor memory provided by an embodiment of the present application. Specific implementation manners

[0034] Next, the technical solutions in the embodiments of the present application will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present application. It can be understood that the specific embodiments described herein are only used to explain the relevant application, rather than limiting the application. Additionally, it should be noted that for the sake of description, only parts related to the relevant application are shown in the drawings.

[0035] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the technical field to which this application belongs. The terms used herein are for the purpose of describing embodiments of this application only and are not intended to limit this application.

[0036] In the following description, reference is made to "some embodiments", which describe a subset of all possible embodiments. However, it can be understood that "some embodiments" can be the same subset or different subsets of all possible embodiments and can be combined with each other without conflict.

[0037] It should be noted that the terms "first / second / third" involved in the embodiments of this application are only used to distinguish similar objects and do not represent a specific order for the objects. It can be understood that "first / second / third" can be interchanged in a specific order or sequence when allowed, so that the embodiments of this application described here can be implemented in an order other than that illustrated or described here.

[0038] Dynamic random access memory DRAM is a commonly used semiconductor storage device in a computer, which consists of many repeated storage units. Different storage units need to be selected via word lines and bit lines. However, the current DRAM still has defects in the circuit design of related word lines.

[0039] See Figure 1 , which shows a partial structural schematic diagram of a DRAM provided by an embodiment of this application. As Figure 1 shown, the core of the DRAM is a storage cell array (or called Array array, Array Mat), a sense amplifier (Sense Amplifier, SA) array, a row decoder and control circuit (XDEC), a column decoder and control circuit (YDEC), a drive circuit (or called SSA&Write Driver circuit), and a data input / output conversion circuit, etc.; among them, a DRAM can include multiple storage cell arrays and multiple sense amplifier arrays. Generally, the sense amplifier array can be further divided into a sense amplifier odd array and a sense amplifier even array.

[0040] The storage cell array is composed of a large number of storage cells (or called Cell). A single storage cell can be uniquely selected through word lines (Word Line, BL) and bit lines. Specifically, a word line signal is given by the row decoder and control circuit to determine the target word line, and a bit line signal (or called CSL signal) is given by the column decoder and control circuit to determine the target bit line, so as to select the target storage cell in the memory array. In addition, in the above process, the sense amplifier array plays a role in signal amplification, and the drive circuit plays a role in signal driving.

[0041] The structures of memory cells include various types. Taking the memory cell with a 1T1C structure as an example, refer to Figure 2 , which shows a schematic structural diagram of a memory cell provided by an embodiment of the present application. As Figure 2 shown, the memory cell includes a transistor and a capacitor, and the gate of the transistor is connected to the word line, and the drain of the transistor is connected to the bit line.

[0042] In particular, for each word line, there corresponds a local word line driver unit (Local WL Driver, LWD). Refer to Figure 3 , which shows a schematic structural diagram of a local word line driver unit provided by an embodiment of the present application. As Figure 3 shown, each local word line driver unit is used to receive the target word line driving signal (which can be represented by the WLDV signal), the inverted main word line driving signal (which can be represented by the bMWL signal), and the local decoding driving signal (which can be represented by the WLRst signal) output by the decoding driving circuit, and output a word line signal (which can be represented by the WL signal) to select the target word line. According to the relevant industry technical standards, refer to Figure 4 , which shows a schematic structural diagram of a group of local word line driver units provided by an embodiment of the present application. As Figure 4 shown, generally 4 local driver units (LWD) are taken as a group, that is, local driver unit × 4. Here, WLDV <n>The WLDV signal is used to represent different decoding values. Other signals are similar, and n is a natural number.

[0043] See Figure 5 , which shows a partial structural schematic diagram of another DRAM provided by an embodiment of the present application. As Figure 5 shown, the memory cell array includes 1024 word lines and 1024 local drive units (LWD units). Each LWD unit is correspondingly connected to a word line, and these LWD units are placed on both sides of the memory cell array. For example, the local drive units of odd word lines (i.e., WLo) can be placed on the left, and the local drive units of even word lines (i.e., WLe) can be placed on the right.

[0044] The number of word lines in memories of different specifications can be different. According to industry convention, generally 1024 word lines form a memory cell array (Array Mat). Specifically, for an Array Mat, the relationship between the row decoding and control circuit and the memory array unit is described. See Figure 6 , which shows a partial structural schematic diagram of yet another DRAM provided by an embodiment of the present application. As Figure 6 shown, the row decoding and control circuit (XDEC) includes a WLDV decoding and driving unit, a WLRst decoding and driving unit, and a bMWL decoding and driving unit, which are respectively used to output WLDV signals, WLRst signals, and bMWL signals, so that the local drive unit can select the target word line according to the above three signals. According to industry convention, the decoding values of the WLDV signal include 0 to 7, the decoding values of the WLRst signal include 0 to 7, and the decoding values of the bMWL signal include 0 to 127. Specifically, WLDV<0, 2, 4, 6> and bMWL<0 to 127> enter the LWD units on the right side of the memory cell array to drive 512 even word lines; WLDV<1, 3, 5, 7> and bMWL<0 to 127> enter the LWD units on the left side of the array sub-unit to drive 512 odd word lines.

[0045] For the WLDV decoding and driving unit, see Figure 7 , which shows a structural schematic diagram of a WLDV decoding and driving unit provided by the related art. As Figure 7 shown, the inputs of the WLDV decoding and driving unit are the decoding input signal and the driving control signal (which can be represented by the WLDVEn signal). One Section has 8 groups of WLDV decoding and driving units, which respectively correspond to WLDV<7:0>.

[0046] For the WLRst decoding and driving unit, see Figure 8 , which shows a structural schematic diagram of a WLRst decoding and driving unit provided by an embodiment of the present application. As Figure 8 As shown, the inputs of the WLRst decoding and driving unit are the decoding input signal and the WLRstEn signal. An Array Mat has a total of 8 groups of WLRst decoding and driving units, corresponding to WLRst<7:0> respectively.

[0047] For the bMWL decoding and driving unit, refer to Figure 9 , which shows a schematic structural diagram of a bMWL decoding and driving unit provided in an embodiment of the present application. As Figure 9 shown, the inputs of the bMWL decoding and driving unit are the decoding input A signal, the decoding input B signal, the decoding input C signal, and the bMWLEn signal. An Array Mat has a total of 128 groups of bMWL decoding and driving units, corresponding to bMWL<127:0> respectively.

[0048] In the above background art, regarding the specific sources and functions of each signal, reference can be made to the prior art. This part of the content has no relation to the technical solution of the embodiment of the present application and will not be elaborated here.

[0049] As can be seen from the above, in the related art, 8 groups of WLDV decoding and driving units with the same structure are required to implement WLDV signals with different decoding values, resulting in a large circuit area and low circuit transfer efficiency, which affects the performance of the DRAM.

[0050] Based on this, an embodiment of the present application provides a decoding and driving circuit. The decoding and driving circuit includes at least one decoding and driving unit, and the decoding and driving unit includes a first-stage driving circuit and a second-stage driving circuit; wherein, the first-stage driving circuit is used to receive an enable control signal, a decoding input signal, and a driving control signal, and generate a first driving signal and a second driving signal according to the enable control signal, the driving control signal, and the decoding input signal; the second-stage driving circuit is used to generate a target word line driving signal according to the first driving signal and the second driving signal. In this way, based on the new decoding and driving circuit provided by the embodiment of the present application, not only can the circuit efficiency be improved, but also the circuit area can be saved, and at the same time, the performance of the DRAM can be improved.

[0051] The following will describe each embodiment of the present application in detail with reference to the accompanying drawings.

[0052] In an embodiment of the present application, refer to Figure 10 , which shows a schematic structural diagram of a decoding and driving circuit 10 provided in an embodiment of the present application. As Figure 10 shown, the decoding and driving circuit 10 includes at least one decoding and driving unit 110, and the decoding and driving unit 110 includes a first-stage driving circuit 111 and a second-stage driving circuit 112:

[0053] The first - stage driving circuit 111 is configured to receive an enable control signal, a decoding input signal, and a driving control signal, and generate a first driving signal and a second driving signal according to the enable control signal, the driving control signal, and the decoding input signal;

[0054] The second - stage driving circuit 112 is connected to two output terminals of the first - stage driving circuit 111, and is configured to generate a target word - line driving signal according to the first driving signal and the second driving signal.

[0055] It should be noted that the decoding and driving circuit 10 provided in the embodiments of the present application is applied to various signal - driving scenarios, and those skilled in the art can flexibly apply it. For the convenience of description, hereinafter, the target word - line driving signal (i.e., the aforementioned WLDV signal) is taken as an example for explanation, but this does not constitute a limitation to the embodiments of the present application.

[0056] According to the foregoing content, there are 8 different decoding values for the WLDV signal, namely WLDV<7:0>. Therefore, the decoding and driving circuit 10 includes at least one decoding and driving unit 110 corresponding to different decoding values. Specifically, each decoding and driving unit 110 includes a first - stage driving circuit 111 and a second - stage driving circuit 112. During operation, the first - stage driving circuit 111 is configured to receive a decoding input signal and a driving control signal, so as to generate a first driving signal and a second driving signal; then, the second - stage driving circuit 112 receives the first driving signal and the second driving signal, and outputs the final target word - line driving signal (i.e., the WLDV signal).

[0057] Further, in some embodiments, refer to Figure 11 , which shows a schematic structural diagram of another decoding and driving circuit 10 provided in the embodiments of the present application. As Figure 11 shown, the second - stage driving circuit 112 may include a first switching transistor 201 and a second switching transistor 201;

[0058] The second - stage driving circuit 112 is specifically configured to control the operating state of the first switching transistor 201 according to the first driving signal, control the operating state of the second switching transistor 202 according to the second driving signal; and generate a target word - line driving signal according to the operating state of the first switching transistor 201 and the operating state of the second switching transistor 202.

[0059] It should be noted that the second - stage driving circuit 112 is composed of two switching transistors. The operating state of the first switching transistor 201 is controlled by the first driving signal, the operating state of the second switching transistor 202 is controlled by the second driving signal, and the operating states of the first switching transistor 201 and the second switching transistor 202 determine the level state of the target word - line driving signal.

[0060] It should also be noted that in some embodiments, the second-stage driving circuit 112 is specifically configured to control the target word line driving signal to be in the first level state when the first switching transistor 201 is in the on state and the second switching transistor 202 is in the off state; or

[0061] the second-stage driving circuit 112 is specifically configured to control the target word line driving signal to be in the second level state when the first switching transistor 201 is in the off state and the second switching transistor 202 is in the on state; or

[0062] the second-stage driving circuit 112 is specifically configured to control the target word line driving signal to be in the third level state when the first switching transistor 201 is in the off state and the second switching transistor 202 is in the off state.

[0063] It should be noted that the driving principle of the second-stage driving circuit 112 is as follows:

[0064] Case 1: If the first switching transistor 201 is in the on state and the second switching transistor 202 is in the off state, the target word line driving signal is in the first level state;

[0065] Case 2: If the first switching transistor 201 is in the off state and the second switching transistor 202 is in the on state, the target word line driving signal is in the second level state;

[0066] Case 3: If the first switching transistor 201 is in the off state and the second switching transistor 202 is in the off state, the target word line driving signal is in the third level state.

[0067] Exemplarily, the first level state is a high level state, the second level state is a low level state, and the third level state is a Floating state.

[0068] Furthermore, in some embodiments, as Figure 11 shown, the first end of the first switching transistor 201 is connected to an output terminal of the first-stage driving circuit 112 for receiving the first driving signal; the first end of the second switching transistor 202 is connected to another output terminal of the first-stage driving circuit 112 for receiving the second driving signal;

[0069] the second end of the first switching transistor 201 is connected to the first power supply terminal, and the second end of the second switching transistor 202 is connected to the ground terminal;

[0070] the third end of the first switching transistor 201 is connected to the third end of the second switching transistor 202 for outputting the target word line driving signal.

[0071] It should be noted that since the second end of the first switching transistor 201 is connected to the first power supply terminal, when the second switching transistor is turned on, the target word line driving signal will be pulled up to a relatively high level, that is, in the high-level state; conversely, when the second end of the second switching transistor 201 is grounded, when the second switching transistor is turned on, the target word line driving signal will be pulled down to a relatively low level, that is, in the low-level state. When both the first switching transistor 201 and the second switching transistor 202 are turned off, the target word line driving signal will be in the Floating state, depending on the specific occurrence scenario.

[0072] In this embodiment, the switching transistors are all metal-oxide-semiconductor field-effect transistors (MOSFETs, simply referred to as MOS). In particular, Figure 11 in, the circuit symbols of the first switching transistor 201 and the second switching transistor 202 are different, indicating that they are different types of devices. The first switching transistor 201 can be a P-type channel MOSFET (PMOS), and the second switching transistor 202 can be an N-type channel MOSFET (NMOS). In the subsequent description of the embodiments of the present application, for the MOSFET, the first end indicates the gate, the second end indicates the source, and the third end indicates the drain. Therefore, for the PMOS, the upper right pin is the second end, and the lower right pin is the third end; for the NMOS, the upper right pin is the third end, and the lower right pin is the second end.

[0073] Of course, due to the diversity of circuit devices, for the first switching transistor 201 and the second switching transistor 202, they can be completely implemented by other circuit devices or a combination of circuit devices. The embodiments of the present application only provide a feasible related solution, but this solution does not constitute a limiting condition.

[0074] Further, in some embodiments, the decoding and driving circuit 10 further includes an enable control circuit 120, and the output end of the enable control circuit 120 is connected to the input end of the first-stage driving circuit 111; wherein,

[0075] The enable control circuit 120 is configured to output an enable control signal according to the driving control signal.

[0076] It should be noted that as Figure 11 As shown, the decoding and driving circuit further includes an enable control circuit 120, and the enable control circuit 120 assists the first-stage driving circuit 111 to complete the first-stage driving. Specifically, the driving control signal is respectively input into the enable control circuit 120 and the first-stage driving circuit 111. The enable control circuit 120 first outputs an enable control signal according to the driving control signal. Then, the first-stage driving circuit 111 jointly drives and controls the decoding input signal according to the enable control signal and the driving control signal, so as to obtain a first driving signal and a second driving signal. Finally, the second-stage driving circuit 112 outputs a target word line driving signal according to the first driving signal and the second driving signal.

[0077] In some embodiments, the driving control signal includes a first driving control signal (which can be represented by the WLDVEn signal) and a second driving control signal (which can be represented by the WLDVEnN signal), and the level states of the first driving control signal and the second driving control signal are opposite. The first-stage driving circuit 111 includes a first control circuit and a second driving circuit. At this time,

[0078] The first control circuit is used to drive and control the decoding input signal according to the first driving control signal and the enable control signal to generate a first driving signal;

[0079] The second control circuit is used to drive and control the decoding input signal according to the first driving control signal, the second driving control signal and the enable control signal to generate a second driving signal.

[0080] In a specific embodiment, as Figure 11 shown, the enable control circuit includes a third switching transistor 203, and the first control circuit includes a fourth switching transistor 204, a fifth switching transistor 205 and a sixth switching transistor 206; wherein,

[0081] The first ends of the third switching transistor 203 and the fourth switching transistor 204 are connected to receive the first driving control signal; the first ends of the fifth switching transistor 205 and the sixth switching transistor 206 are connected to receive the decoding input signal; the third ends of the fourth switching transistor 204, the fifth switching transistor 205 and the sixth switching transistor 206 are all connected to an output end of the first-stage driving circuit 111 for outputting a first driving signal; a connection is made between the third end of the third switching transistor 203 and the second end of the sixth switching transistor 206, and the second end of the third switching transistor 203 is connected to the ground end; the second end of the fourth switching transistor 204 is connected to the second power supply end, and the second end of the fifth switching transistor 205 is connected to the third power supply end.

[0082] In another specific embodiment, as Figure 11 As shown, the enable control circuit further includes a seventh switching transistor 207 and an eighth switching transistor 208, and the second control circuit includes a ninth switching transistor 209, a tenth switching transistor 210, an eleventh switching transistor 211, and a twelfth switching transistor 212; wherein,

[0083] The first end of the seventh switching transistor 207 and the first end of the twelfth switching transistor 212 receive a first drive control signal; the first end of the eighth switching transistor 218 and the first end of the ninth switching transistor 209 receive a second drive control signal; the first end of the tenth switching transistor 210 and the first end of the eleventh switching transistor 211 receive a decoded input signal; the third ends of the ninth switching transistor 209, the tenth switching transistor 210, the eleventh switching transistor 211, and the twelfth switching transistor 212 are all connected to another output end of the second-stage drive circuit 112 for outputting a second drive signal; a connection is made between the third end of the eighth switching transistor 208, the second end of the tenth switching transistor 210, and the second end of the twelfth switching transistor 212, a connection is made between the third end of the seventh switching transistor 207 and the second end of the eleventh switching transistor 211, the second end of the seventh switching transistor 207 is connected to the ground terminal, the second end of the eighth switching transistor 208 is connected to the fourth power supply terminal, and the second end of the ninth switching transistor 209 is connected to the ground terminal.

[0084] Here, the first power supply terminal, the second power supply terminal, the third power supply terminal, and the fourth power supply terminal all refer to power supply terminals capable of outputting a stable voltage; wherein, the power supplies connected to the first power supply terminal, the second power supply terminal, the third power supply terminal, and the fourth power supply terminal may be the same or different; it is specifically determined according to actual application requirements, and the embodiments of the present application do not make specific limitations.

[0085] As Figure 11 shown, the control enable signal is a broad concept and includes the outputs of the third switching transistor 203, the seventh switching transistor 207, and the eighth switching transistor 208.

[0086] Further, in some embodiments, in an Array Mat of a semiconductor memory, the first power supply terminal may include a first type of first power supply terminal and a second type of first power supply terminal, and the decoded drive unit may be a first type of decoded drive unit or a second type of decoded drive unit; wherein,

[0087] The first type of decoded drive units share the first type of first power supply terminal, the second type of decoded drive units share the second type of first power supply terminal, and the word lines corresponding to the first type of decoded drive units and the word lines corresponding to the second type of decoded drive units are distributed in an odd-even alternating pattern.

[0088] It should be noted that the decoding and driving unit can be divided into a first type of decoding and driving unit or a second type of decoding and driving unit. The first type of decoding and driving unit is used to drive odd word lines, and the second type of decoding and driving unit is used to drive even word lines. In other words, the decoding and driving unit of a decoding and driving circuit can be a first type of decoding and driving unit or a second type of decoding and driving unit.

[0089] Correspondingly, the first power supply terminal can include a first type of first power supply terminal and a second type of first power supply terminal. All the first type of decoding and driving units share the first type of first power supply terminal, and all the second type of decoding and driving units share the second type of first power supply terminal. In this way, not only the number of power supply terminals is saved, but also the first type of first power supply terminal / second type of first power supply terminal can be used for fault location (see the subsequent description).

[0090] Exemplarily, the specific connection manner of the first type of first power supply terminal and the second type of first power supply terminal is as follows: The first type of first power supply terminal is connected to the second terminal of the first switching tube in the first type of decoding and driving unit to supply power to the first type of decoding and driving unit; the second type of first power supply terminal is connected to the second terminal of the first switching tube in the second type of decoding and driving unit to supply power to the second type of decoding and driving unit.

[0091] In addition, for the first type of first power supply terminal and the second type of first power supply terminal, the power supplies connected to the first type of first power supply terminal and the second type of first power supply terminal can be the same or different; it is specifically determined according to actual application requirements, and the embodiments of the present application do not make specific limitations either.

[0092] In this way, the first type of decoding and driving unit is used to receive a decoding input signal and a driving control signal, and generate a target word line driving signal corresponding to the first type of word line; the second type of decoding and driving unit is used to receive a decoding input signal and a driving control signal, and generate a target word line driving signal corresponding to the second type of word line.

[0093] It should be understood that the first type of word line and the second type of word line are distributed alternately in odd and even numbers. For example, the first type of word line is an odd word line and the second type of word line is an even word line; or the first type of word line is an even word line and the second type of word line is an odd word line.

[0094] Furthermore, in some embodiments, when the number of the first type of decoding and driving units and the number of the second type of decoding and driving units are both two or more, in a decoding and driving circuit 10, every two first type of decoding and driving units share an enable control circuit 120, or every two second type of decoding and driving units share an enable control circuit 120.

[0095] It should be noted that for the decoding and driving circuit 10, every two decoding and driving units therein can share the enable control circuit 120. It should be understood that since the sharing of the first power supply terminal already exists as described above, the decoding and driving units sharing the enable control circuit 120 are preferably also connected to the same first power supply terminal.

[0096] That is to say, the decoding and driving circuit 10 can include one enable control circuit 120 and two first - type decoding and driving units; or the decoding and driving circuit 10 can include one enable control circuit 120 and two second - type decoding and driving units. In addition, in a decoding and driving circuit 10, different decoding and driving units receive different decoding input signals, so as to be able to output different target word line signals. For an Array Mat in a semiconductor memory, multiple sets of decoding and driving circuits 10 can be set according to actual application requirements.

[0097] In addition, it is also possible to control every four decoding and driving units to share the enable control circuit. Therefore, in some embodiments, when the number of both the first - type decoding and driving units and the second - type decoding and driving units is four or more, in a decoding and driving circuit 10, every four first - type decoding and driving units share one enable control circuit 120, or every four second - type decoding and driving units share one enable control circuit 120.

[0098] That is to say, the decoding and driving circuit 10 can include one enable control circuit 120 and four first - type decoding and driving units; or the decoding and driving circuit 10 can include one enable control circuit 120 and four second - type decoding and driving units. Similarly, for an Array Mat in a semiconductor memory, multiple sets of the above - mentioned decoding and driving circuits 10 can be set according to actual application requirements.

[0099] Taking the case where there are 8 different decoding values (WLDV<7:0>) for the target word line decoding signal as an example, the circuit sharing will be explained in detail below.

[0100] In one case, refer to Figure 12 , which shows a schematic structural diagram of a decoding and driving circuit provided by an embodiment of the present application. It should be understood that there are two sets of the dotted - box circuits in the actual circuit structure in Figure 12 , that is, the first - type decoding and driving units × 2, or the second - type decoding and driving units × 2.

[0101] As shown in Figure 12 As shown in the figure, in an Array Mat of a semiconductor memory for the WLDV signal, there are four sets of decoding and driving circuits. The input signals of each set of decoding and driving circuits are the WLDVEn signal (equivalent to the first driving control signal), the decoding input signal, and the WLDVEnN signal (equivalent to the second driving control signal); among them,

[0102] For the first set of decoding and driving circuits, it includes an enable control circuit and two first - type decoding and driving units, which are used to output WLDV<4,0>;

[0103] For the third set of decoding and driving circuits, it includes an enable control circuit and two first - type decoding and driving units, which are used to output WLDV<6,2>, and the two first - type decoding and driving units in the first set of decoding and driving circuits and the two first - type decoding and driving units in the third set of decoding and driving circuits share the first - type first power supply terminal (PWLDV0);

[0104] For the second set of decoding and driving circuits, it includes an enable control circuit and two second - type decoding and driving units, which are used to output WLDV<5,1>;

[0105] For the fourth set of decoding and driving circuits, it includes an enable control circuit and two second - type decoding and driving units, which are used to output WLDV<7,3>, and the two second - type decoding and driving units in the second set of decoding and driving circuits and the two second - type decoding and driving units in the fourth set of decoding and driving circuits share the second - type first power supply terminal (PWLDV1).

[0106] In another case, refer to Figure 13 , which shows a schematic structural diagram of another decoding and driving circuit provided by an embodiment of the present application. It should be understood that in Figure 13 , there are four sets of the circuit in the dashed - line box in the actual circuit structure, that is, the first - type decoding and driving units × 4, or the second - type decoding and driving units × 4.

[0107] As Figure 13 shown, for the WLDV signal, in an Array Mat of a semiconductor memory, there are two sets of decoding and driving circuits. The input signals of each set of decoding and driving circuits are the WLDVEn signal (equivalent to the first driving control signal), the decoding input signal, and the WLDVEnN signal (equivalent to the second driving control signal); among them,

[0108] For the first set of decoding and driving circuits, it includes an enable control circuit and four first - type decoding and driving units, which are used to output WLDV<0,2,4,6>, and the four first - type decoding and driving units in the first set of decoding and driving circuits share the first - type first power supply terminal;

[0109] For the second set of decoding and driving circuits, it includes an enable control circuit and four second - type decoding and driving units, which are used to output WLDV<1, 3, 5, 7>, and the four second - type decoding and driving units in the second set of decoding and driving circuits share the second - type first power supply terminal.

[0110] It should be understood that different sharing forms will bring trade - offs in performance, and design needs to be carried out according to the actual application environment and test requirements.

[0111] In the embodiments of the present application, a new decoding and driving circuit is provided for the WLDV signal. For example Figure 12 Or Figure 13 The circuit structure shown. The decoding and driving circuit 10 includes at least one decoding and driving unit 110, and each decoding and driving unit 110 includes two - stage driving circuits. The first - stage amplifying circuit 111 amplifies the decoding input signal according to the enable control signal and the driving control signal to obtain the first driving signal and the second driving signal. The second - stage amplifying circuit 111 generates the target word - line driving signal according to the first driving signal and the second driving signal. In addition, the enable control circuit 120 and the power supply terminal are shared by different decoding and driving units, thereby improving the circuit efficiency, saving the circuit area, and finally improving the performance of the DRAM.

[0112] It should also be noted that for Figures 11 to 13 , the types of the first switching transistor 201, the second switching transistor 202, the third switching transistor 203, the fourth switching transistor 204, the fifth switching transistor 205, the sixth switching transistor 206, the seventh switching transistor 207, the eighth switching transistor 208, the ninth switching transistor 209, the tenth switching transistor 210, the eleventh switching transistor 211 and the twelfth switching transistor 212 are field - effect MOS transistors; the first end of the field - effect MOS transistor is the gate terminal, the second end of the field - effect MOS transistor is the source terminal, and the third end of the field - effect MOS transistor is the drain terminal.

[0113] Furthermore, the first switching transistor 201, the third switching transistor 203, the fourth switching transistor 204, the sixth switching transistor 206, the seventh switching transistor 207, the eleventh switching transistor 211 are PMOS, while the second switching transistor 202, the fifth switching transistor 205, the tenth switching transistor 210, the eighth switching transistor 208, the twelfth switching transistor 212 are all NMOS.

[0114] In summary, as Figures 10 to 13 shown, the embodiments of the present application provide a new decoding and driving circuit that can output the WLDV signal. For an Array Mat in a semiconductor memory, a total of eight groups of decoding and driving units 110 are required to output WLDV<7:0>.

[0115] In each WLDV decoding and driving unit, the first switching transistor 201 / second switching transistor 202 form the driving unit of the final stage of the basic WLDV signal; the third switching transistor 203 / fourth switching transistor 204 / fifth switching transistor 205 / sixth switching transistor 206 form the control and pre-stage driving of the first switching transistor 201;

[0116] The seventh switching transistor 207 / eighth switching transistor 208 / ninth switching transistor 209 / tenth switching transistor 210 / eleventh switching transistor 211 / twelfth switching transistor 212 form the control and pre-stage driving of the second switching transistor 202;

[0117] In particular, the third switching transistor 203 / seventh switching transistor 207 / eighth switching transistor 208 (equivalent to using a control circuit) are shared by every 2 WLDV decoding and driving units / every 4 WLDV decoding and driving units, thereby saving area and improving circuit efficiency.

[0118] The power supply terminals of the first switching transistors 201 of different WLDV decoding and driving units are also divided into 2 groups, and every 4 WLDV decoding and driving units share them, that is, WLDV<0, 2, 4, 6> share one group; WLDV<1, 3, 5, 7> share one group, which respectively correspond to the odd and even word lines in the memory cell array. In this way, through the separate control of the odd and even word lines, the states of adjacent word lines can be respectively controlled during testing to analyze the leakage path (see the following content).

[0119] In addition, the inputs of the decoding and driving unit include WLDVEn0 / WLDVEnN0 (equivalent to driving control signals) and decoding input signals, and these three signals can control the state combinations of the first switching transistor 201 / second switching transistor 202: (1) the first switching transistor 201 is turned on / the second switching transistor 202 is turned off; (2) the first switching transistor 201 is turned off / the second switching transistor 202 is turned on; (3) the first switching transistor 201 is turned off / the second switching transistor 202 is turned off, thereby controlling the level state of the target word line driving signal.

[0120] In particular, for Figure 12 , in the actual application process, during normal operation, WLDVEnN0 = WLDVEnN1 = WLDVEnN2 = WLDVEnN3 = 0, LDVEn0 = WLDVEn1 = WLDVEn2 = WLDVEn3 = (assumed to be WLDVEn), then the states of WLDV<7:0> are simply controlled by the 8-bit decoding input and the WLDVEn signal.

[0121] The embodiment of the present application provides a decoding and driving circuit. The decoding and driving circuit includes at least one decoding and driving unit, and the decoding and driving unit includes a first-stage driving circuit and a second-stage driving circuit. Among them, the first-stage driving circuit is used to receive an enable control signal, a decoding input signal, and a driving control signal, and generate a first driving signal and a second driving signal according to the enable control signal, the driving control signal, and the decoding input signal. The second-stage driving circuit is used to generate a target word line driving signal according to the first driving signal and the second driving signal. In this way, the embodiment of the present application provides a new decoding and driving circuit. The decoding and driving circuit amplifies the decoding input signal in two stages according to the driving control signal, which can not only improve the circuit efficiency, save the circuit area, but also improve the driving performance.

[0122] In another embodiment of the present application, refer to Figure 14 , which shows a schematic flow chart of a decoding and driving method provided by the embodiment of the present application. As Figure 14 shown, the method may include:

[0123] S301: Receive an enable control signal, a decoding input signal, and a driving control signal through the first-stage driving circuit, and generate a first driving signal and a second driving signal according to the enable control signal, the driving control signal, and the decoding input signal.

[0124] S302: Receive the first driving signal and the second driving signal through the second-stage driving circuit, and generate a target word line driving signal according to the first driving signal and the second driving signal.

[0125] It should be noted that the decoding and driving method provided by the embodiment of the present application is applied to the aforementioned decoding and driving circuit, and the decoding and driving circuit includes at least one decoding and driving unit, and the decoding and driving unit includes a first-stage driving circuit and a second-stage driving circuit.

[0126] Therefore, receive an enable control signal, a decoding input signal, and a driving control signal through the first-stage driving circuit, and perform driving control on the decoding input signal according to the enable control signal and the driving control signal to generate a first driving signal and a second driving signal. Then, the second-stage driving circuit performs driving control according to the first driving signal and the second driving signal, and finally generates a target word line driving signal.

[0127] It should also be noted that the decoding and driving circuit further includes an enable control circuit, and the output end of the enable control circuit is connected to the input end of the first-stage driving circuit. Therefore, in some embodiments, the method may further include:

[0128] Generate an enable control signal according to the driving control signal through the enable control circuit.

[0129] It should be noted that the foregoing drive control signals are respectively input into the enable control circuit and the first-stage drive circuit. The enable control circuit first performs enable control processing according to the drive control signals to obtain an enable control signal, and then the first-stage drive circuit performs drive control on the decoded input signal according to the drive control signals and the enable control signal to obtain a first drive signal and a second drive signal.

[0130] Specifically, the drive control signals include a first drive control signal and a second drive control signal, and the first-stage drive circuit includes a first control circuit and a second control circuit. Therefore, in some embodiments, the step of receiving the enable control signal, the decoded input signal, and the drive control signals by the first-stage drive circuit and generating the first drive signal and the second drive signal according to the enable control signal and the drive control signals may include:

[0131] Receiving the first drive control signal, the enable control signal, and the decoded input signal by the first control circuit, and performing drive control on the decoded input signal according to the first drive control signal and the enable control signal to generate a first drive signal;

[0132] Receiving the first drive control signal, the second drive control signal, the enable control signal, and the decoded input signal by the second control circuit, and performing drive control on the decoded input signal according to the first drive control signal, the second drive control signal, and the enable control signal to generate a second drive signal;

[0133] Here, the level states of the first drive control signal and the second drive control signal are different.

[0134] It should also be noted that the second-stage drive circuit includes a first switching transistor and a second switching transistor. Therefore, in some embodiments, the step of generating a target word line drive signal according to the first drive signal and the second drive signal may include:

[0135] Controlling the working state of the first switching transistor according to the first drive signal;

[0136] Controlling the working state of the second switching transistor according to the second drive signal;

[0137] Generating a target word line drive signal according to the working state of the first switching transistor and the working state of the second switching transistor.

[0138] It should be noted that the first drive signal can control the first switching transistor to be in an on or off state, and the second drive signal can control the second switching transistor to be in an on or off state. According to the states of the first switching transistor and the second switching transistor, the level state of the target word line drive signal is different.

[0139] In a specific embodiment, generating a target word line driving signal according to the working states of the first switching tube and the second switching tube may include:

[0140] When the first switching tube is in the on state and the second switching tube is in the off state, controlling the target word line driving signal to be in a first level state; or,

[0141] When the first switching tube is in the off state and the second switching tube is in the on state, controlling the target word line driving signal to be in a second level state; or,

[0142] When the first switching tube is in the off state and the second switching tube is in the off state, controlling the target word line driving signal to be in a third level state.

[0143] It should be noted that if the first switching tube is on and the second switching tube is off, the target word line driving signal is in the first level state; if the first switching tube is off and the second switching tube is on, the target word line driving signal is in the second level state, and if the first switching tube is off and the second switching tube is off, the target word line driving signal is in the third level state. Here, the first level state is a high level state, the second level state is a low level state, and the third level state is a floating state.

[0144] Furthermore, the target word line driving signal can be a WLDV signal. According to the relevant background technology content described above ( Figures 1 to 9 ) it can be known that the WLDV signal, the WLRst signal, and the bMWL signal are jointly used to determine the WL signal, and the WL signal is used to select the word line, that is, the WL signal can control the level state of the word line. In other words, the level state of the target word line includes a high level state, a low level state, and a floating state, and there is an associated relationship between the level state of the target word line and the target word line driving signal.

[0145] Furthermore, in some embodiments, the decoding and driving unit includes at least one first type of decoding and driving unit or at least one second type of decoding and driving unit; wherein,

[0146] At least one first type of decoding and driving unit shares a first type of first power supply terminal, at least one second type of decoding and driving unit shares a second type of first power supply terminal, and the word lines corresponding to the first type of decoding and driving unit and the word lines corresponding to the second type of decoding and driving unit are distributed in an odd-even alternating pattern.

[0147] It should be noted that according to the foregoing content, the decoding and driving circuit includes at least one decoding and driving unit, and these decoding and driving units are respectively used to determine different target word line decoding signals, such as WLDV<7:0>, and WLDV<7:0> can cooperate with bMWL<127:0> to select different word lines.

[0148] On this basis, the decoding and driving unit can be a first-type decoding and driving unit or a second-type decoding and driving unit, and the word lines corresponding to the first-type decoding and driving units and the word lines corresponding to the second-type decoding and driving units are distributed alternately in odd and even numbers. Here, the first-type decoding and driving units share a first power supply terminal of the first type, and the second-type decoding and driving units share a first power supply terminal of the second type.

[0149] In other words, the first-type decoding and driving units of all odd word lines share one first power supply terminal, and the first-type decoding and driving units of all even word lines share another first power supply terminal, so that different power controls can be performed on adjacent word lines. Due to such a circuit structure, the embodiments of the present application also provide a method for detecting word line defects, which is specifically described below.

[0150] In some embodiments, the target word line includes a first word line and a word line to be detected, and the first word line and the word line to be detected are adjacent; the method may further include:

[0151] Turn on the first word line so that the first word line is in a high level state;

[0152] Control the word line to be detected to change from a low level state to a Floating state;

[0153] If it is detected that the data stored in the word line to be detected changes, it is determined that there is a short circuit defect between the word line to be detected and the first word line.

[0154] It should be noted that in the memory cell array, two adjacent word lines are taken and are respectively called the first word line and the word line to be detected. First, turn on the first word line, that is, the first word line is in a high level state; then, control the word line to be detected to change from a low level state to a Floating state. At this time, if there is a short circuit defect between the word line to be detected and the first word line, then the word line to be detected will be pulled high to a high level state by the first word line, and at this time, the data of the level state stored in the word line to be detected will change. In this way, the manufacturing defect between the word line to be detected and the first word line can be detected.

[0155] Here, the first word line and the word line to be detected can be any two adjacent word lines in the memory cell array.

[0156] See Figure 15A , which shows a schematic diagram of a process for detecting a short circuit defect provided by an embodiment of the present application. As Figure 15A shown, Wlo<1> / Wle<2> / Wlo<2> are physically adjacent in the memory cell array (as Figure 5 shown), taking Wlo<1> or Wlo<2> as the word line to be detected and Wle<2> as the first word line.

[0157] Specifically, these word lines can be written with different data patterns in sequence first, and then only turn on Wle<2> (for example, to 3.5V). Next, let Wlo<1> and Wlo<2> be in the Floating state starting from a low potential (for example, -0.3V); if there is a short circuit between Wlo<1> and Wle<2>, it will be pulled up, and the stored data will also change following Wle<2>. As Figure 15A shown, if there is a short circuit between Wlo<1> and Wle<2>, the level state of Wlo<1> is pulled up, and then the data stored in Wlo<1> will also change following Wle<2>. In this way, when the staff detects a change in the data stored in Wlo<1>, it can be confirmed that there is a manufacturing defect between Wlo<1> and Wle<2>.

[0158] As Figure 15B shown, Wle<1> / Wle<2> / Wle<3> are in a physically adjacent state within the local word line driving unit on the right side of the memory cell array (as Figure 5 shown). Taking Wle<1> or Wle<3> as the word line to be detected and Wle<2> as the first word line. Similarly, control Wle<2> to be in a high level state (for example, to 3.5V), control Wlo<1> and Wlo<2> to be in the Floating state starting from a low potential (for example, -0.3V). If the data stored in Wle<1> or Wle<3> changes, there is a manufacturing defect between the changed word line and Wle<2>.

[0159] Similarly, in some embodiments, the following method can also be used for fault detection:

[0160] Turn off the first word line so that the first word line is in a low level state;

[0161] Turn on the word line to be detected so that the word line to be detected is in a high level state, and control the word line to be detected to change from the high level state to the Floating state;

[0162] If it is detected that the data writing of the word line to be detected fails, it is determined that there is a short circuit defect between the word line to be detected and the first word line.

[0163] It should be noted that the embodiment of the present application also provides another fault detection method:

[0164] First, turn off the first word line, i.e., the first word line is in a low level state; then, turn on the word line to be detected and control the word line to be detected to change from a high level state to a Floating state. At this time, if there is no short circuit between the word line to be detected and the first word line, then the word line to be detected should remain in a high level state (on state), and data can be written to the word line to be detected. However, if there is a short circuit between the word line to be detected and the first word line, then the word line to be detected should be pulled down to a low level state (off state), and at this time, data cannot be written to the word line to be detected. In this way, manufacturing defects between the word line to be detected and the first word line can be detected.

[0165] See Figure 16A , which shows a schematic diagram of another short circuit defect detection process provided by an embodiment of the present application. As Figure 16A shown, take Wle<2> as the word line to be detected, and Wlo<1> and Wlo<2> as the first word lines. First, turn on Wle<2> (for example, to 3.5v) and control Wle<2> to change from a high level state to a Floating state. At this time, since neither Wlo<1> nor Wlo<2> is turned on, they are both in a low level state. If there is a short circuit between Wle<2> and Wlo<1> (it can also be between Wle<2> and Wlo<2>), then Wle<2> will be pulled down, that is, the on state of Wle<2> fails and data cannot be written to it. In this way, it can be determined whether there are manufacturing defects in Wle<2>.

[0166] As Figure 16B shown, take Wle<2> as the word line to be detected, and Wle<1> or Wle<3> as the first word line. Similarly, control Wle<2> to change from a high level state (for example, to 3.5v) to a Floating state, and Wle<1> or Wle<3> is in an off state. If data cannot be written to Wle<2>, then there are manufacturing defects in Wle<2>.

[0167] In summary, through the decoding and driving method provided by the embodiment of the present application, not only can the efficiency of decoding and driving be improved, the circuit area can be saved, but also whether there are manufacturing defects in adjacent word lines can be quickly detected.

[0168] An embodiment of the present application provides a decoding driving method, which is applied to a decoding driving circuit. The decoding driving circuit includes at least one decoding driving unit, and the decoding driving unit includes a first-stage driving circuit and a second-stage driving circuit. The first control circuit receives a first driving control signal, a signal, and a decoding input signal, and drives and controls the decoding input signal according to the first driving control signal and the enable control signal to generate a first driving signal. The second control circuit receives the first driving control signal, a second driving control signal, the enable control signal, and the decoding input signal, and drives and controls the decoding input signal according to the first driving control signal, the second driving control signal, and the enable control signal to generate a second driving signal. In this way, by providing a new decoding driving circuit, the decoding input signal is amplified in two stages according to the driving control signal, which can improve the circuit efficiency, save the circuit area, and can also quickly detect whether there are manufacturing defects in adjacent word lines, and finally improve the performance of the DRAM.

[0169] In another embodiment of the present application, refer to Figure 17 , which shows a schematic structural diagram of a word line decoding circuit 40 provided by an embodiment of the present application. As Figure 17 shown, the word line decoding circuit 40 includes a word line driving circuit 401 (for outputting a WLDV signal), an inverted main word line driving circuit 402 (for outputting a bMWL signal), and a local decoding driving circuit (for outputting a WLRst signal). Among them, the word line driving circuit 401 at least includes the aforementioned decoding driving circuit 10.

[0170] For the word line decoding circuit 40, since it includes the aforementioned decoding driving circuit 10, and the decoding driving circuit amplifies the decoding input signal in two stages according to the driving control signal, it can not only improve the circuit efficiency, but also save the circuit area, and also improve the driving performance.

[0171] In still another embodiment of the present application, refer to Figure 18 , which shows a schematic structural diagram of a semiconductor memory 50 provided by an embodiment of the present application. As Figure 18 shown, the semiconductor memory 50 includes the word line decoding circuit 40 of any one of the foregoing embodiments.

[0172] In some embodiments, the semiconductor memory 50 may be a DRAM.

[0173] In an embodiment of the present application, for the semiconductor memory 50, since it includes the word line decoding circuit 40 and amplifies the decoding input signal in two stages according to the driving control signal, it can not only improve the circuit efficiency, but also save the circuit area, and at the same time can also improve the performance of the DRAM.

[0174] In some embodiments, the semiconductor memory 50 is a DRAM, and the specifications of the DRAM conform to DDR4 or DDR5.

[0175] The above are only the preferred embodiments of the present application, and are not intended to limit the protection scope of the present application.

[0176] It should be noted that in the present application, the terms "include", "comprise" or any other variant thereof are intended to cover non-exclusive inclusion, such that a process, method, article or device comprising a series of elements includes not only those elements but also other elements not expressly listed, or also includes elements inherent to such process, method, article or device. Without further limitation, an element defined by the statement "comprising a..." does not exclude the presence of additional identical elements in the process, method, article or device comprising such element.

[0177] The serial numbers of the embodiments of the present application above are only for description and do not represent the superiority or inferiority of the embodiments.

[0178] The methods disclosed in several method embodiments provided by the present application can be arbitrarily combined without conflict to obtain new method embodiments.

[0179] The features disclosed in several product embodiments provided by the present application can be arbitrarily combined without conflict to obtain new product embodiments.

[0180] The features disclosed in several method or device embodiments provided by the present application can be arbitrarily combined without conflict to obtain new method embodiments or device embodiments.

[0181] The above are only the specific implementation manners of the present application, but the protection scope of the present application is not limited thereto. Any person skilled in the art within the technical scope disclosed by the present application can easily think of changes or substitutions, which should be covered by the protection scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.< / n>

Claims

1. A decoding driving circuit, characterized in that, the decoding driving circuit includes at least one decoding driving unit, and the decoding driving unit includes a first-stage driving circuit and a second-stage driving circuit; wherein, the first-stage driving circuit is configured to receive an enable control signal, a decoding input signal, and a driving control signal, and generate a first driving signal and a second driving signal according to the enable control signal, the driving control signal, and the decoding input signal; the second-stage driving circuit is configured to generate a target word line driving signal according to the first driving signal and the second driving signal; the second-stage driving circuit includes a first switching tube and a second switching tube; the second-stage driving circuit is specifically configured to control the working state of the first switching tube according to the first driving signal, control the working state of the second switching tube according to the second driving signal; and generate the target word line driving signal according to the working state of the first switching tube and the working state of the second switching tube; a first end of the first switching tube is connected to an output end of the first-stage driving circuit for receiving the first driving signal; a first end of the second switching tube is connected to the other output end of the first-stage driving circuit for receiving the second driving signal; a second end of the first switching tube is connected to a first power supply terminal, and a second end of the second switching tube is connected to a ground terminal; a third end of the first switching tube is connected to a third end of the second switching tube for outputting the target word line driving signal; the decoding driving circuit further includes an enable control circuit, and an output end of the enable control circuit is connected to an input end of the first-stage driving circuit; wherein, the enable control circuit is configured to generate the enable control signal according to the driving control signal; the driving control signal includes a first driving control signal and a second driving control signal, and the first-stage driving circuit includes a first control circuit and a second control circuit; wherein, the first control circuit is configured to perform driving control on the decoding input signal according to the first driving control signal and the enable control signal to generate the first driving signal; the second control circuit is configured to perform driving control on the decoding input signal according to the first driving control signal, the second driving control signal, and the enable control signal to generate the second driving signal; wherein, the level states of the first driving control signal and the second driving control signal are different.

2. The decoding driving circuit according to claim 1, characterized in that, the second-stage driving circuit is specifically configured to control the target word line driving signal to be in a first level state when the first switching tube is in an on state and the second switching tube is in an off state; or the second-stage driving circuit is specifically configured to control the target word line driving signal to be in a second level state when the first switching tube is in an off state and the second switching tube is in an on state; or The second - stage driving circuit is specifically configured to control the target word - line driving signal to be in a third - level state when the first switching transistor is in the off state and the second switching transistor is in the off state.

3. The decoding and driving circuit according to claim 2, wherein: The first - level state is a high - level state, the second - level state is a low - level state, and the third - level state is a floating state.

4. The decoding and driving circuit according to claim 1, wherein: The enabling control circuit includes a third switching transistor, and the first control circuit includes a fourth switching transistor, a fifth switching transistor, and a sixth switching transistor; wherein, The first ends of the third switching transistor and the fourth switching transistor receive the first driving control signal; the first ends of the fifth switching transistor and the sixth switching transistor receive the decoding input signal; The third ends of the fourth switching transistor, the fifth switching transistor, and the sixth switching transistor are all connected to an output terminal of the first - stage driving circuit for outputting the first driving signal. The third end of the third switching transistor is connected to the second end of the sixth switching transistor, and the second end of the third switching transistor is connected to the ground terminal; the second end of the fourth switching transistor is connected to the second power supply terminal, and the second end of the fifth switching transistor is connected to the third power supply terminal.

5. The decoding and driving circuit according to claim 4, wherein: The enabling control circuit further includes a seventh switching transistor and an eighth switching transistor, and the second control circuit includes a ninth switching transistor, a tenth switching transistor, an eleventh switching transistor, and a twelfth switching transistor; wherein, The first ends of the seventh switching transistor and the twelfth switching transistor receive the first driving control signal; the first ends of the eighth switching transistor and the ninth switching transistor receive the second driving control signal; the first ends of the tenth switching transistor and the eleventh switching transistor receive the decoding input signal; The third ends of the ninth switching transistor, the tenth switching transistor, the eleventh switching transistor, and the twelfth switching transistor are all connected to another output terminal of the second - stage driving circuit for outputting the second driving signal; The third end of the eighth switching transistor, the second end of the tenth switching transistor, and the second end of the twelfth switching transistor are connected; the third end of the seventh switching transistor and the second end of the eleventh switching transistor are connected; the second end of the seventh switching transistor is connected to the ground terminal, the second end of the eighth switching transistor is connected to the fourth power supply terminal, and the second end of the ninth switching transistor is connected to the ground terminal.

6. The decoding and driving circuit according to claim 5, wherein: The types of the first switching transistor, the second switching transistor, the third switching transistor, the fourth switching transistor, the fifth switching transistor, the sixth switching transistor, the seventh switching transistor, the eighth switching transistor, the ninth switching transistor, the tenth switching transistor, the eleventh switching transistor, and the twelfth switching transistor are MOS field - effect transistors; wherein, The first terminal of the field effect MOS transistor is the gate, the second terminal of the field effect MOS transistor is the source, and the third terminal of the field effect MOS transistor is the drain.

7. The decoding and driving circuit according to claim 6, wherein the types of the first switching transistor, the fourth switching transistor, the fifth switching transistor, the eighth switching transistor, the tenth switching transistor and the twelfth switching transistor are P-type channel field effect MOS transistors; the types of the first switching transistor, the third switching transistor, the sixth switching transistor, the seventh switching transistor, the ninth switching transistor and the eleventh switching transistor are N-type channel field effect MOS transistors.

8. A decoding and driving method, characterized in that it is applied to a decoding and driving circuit, and the decoding and driving circuit includes at least one decoding and driving unit, and the decoding and driving unit includes a first-stage driving circuit and a second-stage driving circuit; the method includes: receiving an enable control signal, a decoding input signal and a driving control signal through the first-stage driving circuit, and generating a first driving signal and a second driving signal according to the enable control signal, the driving control signal and the decoding input signal; receiving the first driving signal and the second driving signal through the second-stage driving circuit, and generating a target word line driving signal according to the first driving signal and the second driving signal; the decoding and driving circuit further includes an enable control circuit, and the method further includes: generating the enable control signal according to the driving control signal through the enable control circuit; the driving control signal includes a first driving control signal and a second driving control signal, and the first-stage driving circuit includes a first control circuit and a second control circuit; the step of receiving an enable control signal, a decoding input signal and a driving control signal through the first-stage driving circuit, and generating a first driving signal and a second driving signal according to the enable control signal, the driving control signal and the decoding input signal includes: receiving the first driving control signal, the enable control signal and the decoding input signal through the first control circuit, and performing driving control on the decoding input signal according to the first driving control signal and the enable control signal to generate the first driving signal; receiving the first driving control signal, the second driving control signal, the enable control signal and the decoding input signal through the second control circuit, and performing driving control on the decoding input signal according to the first driving control signal, the second driving control signal and the enable control signal to generate the second driving signal; wherein, the level states of the first driving control signal and the second driving control signal are different.

9. The decoding and driving method according to claim 8, wherein the second-stage driving circuit includes a first switching transistor and a second switching transistor, and the step of generating a target word line driving signal according to the first driving signal and the second driving signal includes: controlling the working state of the first switching transistor according to the first driving signal; controlling the working state of the second switching transistor according to the second driving signal; Generate the target word line driving signal according to the operating states of the first switching transistor and the second switching transistor.

10. The decoding and driving method according to claim 9, wherein: The generating of the target word line driving signal according to the operating states of the first switching transistor and the second switching transistor includes: When the first switching transistor is in an on state and the second switching transistor is in an off state, control the target word line driving signal to be in a first level state; or, When the first switching transistor is in an off state and the second switching transistor is in an on state, control the target word line driving signal to be in a second level state; or, When the first switching transistor is in an off state and the second switching transistor is in an off state, control the target word line driving signal to be in a third level state.

11. The decoding and driving method according to claim 10, wherein: The first level state is a high level state, the second level state is a low level state, and the third level state is a floating state.

12. The decoding and driving method according to claim 11, wherein: The level states of the target word line include a high level state, a low level state, and a floating state; wherein, there is an associated relationship between the level state of the target word line and the target word line driving signal.

13. A word line decoding circuit, wherein: The word line decoding circuit includes a word line driving circuit, an inverted main word line driving circuit, and a local decoding and driving circuit; wherein, the word line driving circuit at least includes the decoding and driving circuit according to any one of claims 1 to 7.

14. A semiconductor memory, wherein: The semiconductor memory includes the word line decoding circuit according to claim 13.

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