A method for improving the life of an sst-type nonvolatile memory

Abstract

The application provides a method for prolonging the service life of an SST type nonvolatile memory. The nonvolatile memory comprises a plurality of basic cell array structures, and the array structures are divided into a data area and a reference area. The method adds a reference area write operation in the erasing and writing operation steps of the SST type nonvolatile memory, so that the bit line currents of the data area and the reference area are attenuated at the same time, the ratio between the bit line current of the data area and the bit line current of the reference area is slowed down, the erasing and writing operation times of the data area are prolonged, the hardware process of the SST type nonvolatile memory does not need to be changed, the cost is saved, and the method is simple and easy to operate.

Description

Technical Field

[0001] This invention relates to the field of non-volatile storage devices, and more particularly to a method for improving the lifespan of SST-type non-volatile memory. Background Technology

[0002] With the rapid development of microelectronics technology, digital signals are widely used in various fields, such as military, communications, scientific experiments, and smart cards. Simultaneously, data storage systems have become increasingly important and occupy a crucial position in many applications. For modern data storage systems, the realization of high-speed, high-capacity storage technology has been extensively studied. However, while storage capacity and speed have improved, ensuring the lifespan of data storage has become a critical issue.

[0003] The most mainstream memory currently is non-volatile memory (FLASH). FLASH memory can be read and written; however, it must be erased before writing. When FLASH memory is subjected to frequent erase and write operations at the same address, bad cells will quickly appear, affecting the normal operation of the memory. Currently, the SST type FLASH memory on the market is developed and sold by Silicon Storage Technology, Inc. (SST). SST type FLASH memory generally consists of six parts: gate, source, drain, control gate, floating gate, and substrate. Figure 1The diagram shows the basic cell structure of a typical SST-type FLASH memory. The core structure of an SST-type FLASH memory cell is a floating gate. Charge is stored within the floating gate, which is the function of erasing the FLASH memory. Removing charge from the floating gate is the function of writing to the FLASH memory. The erasure function of a FLASH memory is a process of storing charge in the floating gate using a high voltage. During the erase operation, the FLASH memory cell is in an "on" state, and the word line of the FLASH memory array is pulled low to zero potential. After the erase operation is complete, charge is stored in the floating gate, causing the gate threshold voltage (VT) of the floating gate to go high. At this point, the FLASH memory state, from a circuit perspective, is a logic "1". The write operation of a FLASH memory refers to removing the charge stored in the floating gate, causing the gate threshold voltage (VT) of the floating gate in the FLASH memory cell to go low. At this point, the FLASH memory state, from a circuit perspective, is a logic "0". In a FLASH memory, the current of each basic cell is read by a designated sensitive amplifier circuit. During the read process, a fixed voltage is applied to the word line. When the gate threshold voltage (VT) of the floating gate in the basic cell of the FLASH memory decreases, the floating gate is turned on, and current is detected on the corresponding bit line, which is the logic "1". Similarly, when the gate threshold voltage (VT) of the floating gate in the basic cell of the FLASH memory increases, the floating gate is not turned on, the sensitive amplifier does not detect current, which is the logic "0".

[0004] During the erase and write operations of a FLASH memory, the bit line current of the basic cell is compared with the reference current (Iref). If the bit line current value is lower than the reference current value, the logic is determined to be "0"; if the bit line current value is higher than the reference current value, the logic is determined to be "1". The current values ​​read in the erase and write operation states must have a sufficient difference to make the read operation easily distinguishable. In addition, the erase and write capability of the basic cell of the FLASH memory will gradually decay over time. In practice, due to the reliability requirements of erase and write operations, it is generally necessary to perform more than 100,000 erase and write operations. This requires the FLASH memory to have a minimum difference between the bit line current value read in the erase and write operation states and the reference current value, so as to ensure that the original logic "1" or "0" state can still be accurately read after the FLASH memory state decays.

[0005] SST-type FLASH memory is an array structure composed of multiple basic units. This array structure is divided into a data area and a reference area, such as... Figure 2The diagram shows a typical array structure of a common SST-type FLASH memory. This array structure includes word lines, bit lines, a data area, and a reference area. In a specific embodiment of the present invention, columns 1 to 1024 of this array structure are the data area, and columns 1025 to 1028 are the reference area. In general, the typical steps for storing data in an SST-type FLASH memory are as follows: before storing data, an erase operation is performed on both the data area and the reference area. Then, the success of the data area erase is verified. Subsequently, after the erase operation is completed, a write operation is performed on the data area, while no data is written to the reference area. Finally, the correctness of the data written to the data area is verified, and the previous erase and write operations are repeated.

[0006] In typical SST-type FLASH memory data storage, after multiple erase and write operations in the data area, the floating gate, source, and drain in the basic cells of the FLASH memory gradually age, and the bit line current gradually decreases. However, since the reference area has not undergone any write operations, its bit line current hardly decreases. Therefore, the ratio of the bit line current in the data area to the bit line current in the reference area becomes increasingly lower, making it impossible to erase the data area. The FLASH memory is then considered damaged or malfunctioning. Therefore, there is an urgent need to provide a method to improve the lifespan of SST-type non-volatile memory to address the problem of high-frequency erase and write operations affecting its lifespan. Summary of the Invention

[0007] To address the shortcomings of the existing technology, the purpose of this invention is to improve the lifespan of SST-type non-volatile memory by adding a reference area write operation to the erase and write operations of the SST-type non-volatile memory, thereby increasing the number of erase and write operations on the data area of ​​the SST-type non-volatile memory and thus improving the lifespan of the SST-type non-volatile memory.

[0008] To achieve the above-mentioned technical objectives, the technical solution adopted by this invention is as follows:

[0009] A method for improving the lifespan of SST-type non-volatile memory, wherein the non-volatile memory includes several basic cell array structures, the array structures being divided into a data area and a reference area, and the specific steps of the method are as follows:

[0010] Step 1: Perform an erase operation on all basic cells of the non-volatile memory, that is, clear the charge in the floating gate of all basic cells;

[0011] Step 2: Verify whether the data area erasure operation was successful. This involves verifying the bit line current of the data area and comparing it with the reference current value of the reference area. If the bit line current value of the data area is greater than the reference current value of the reference area, the data area erasure operation is successful and is defined as "1"; otherwise, if the bit line current value of the data area is less than the reference current value of the reference area, the erasure operation fails and is defined as "0".

[0012] Step 3: Verify the correctness of the data area after erasure. This involves verifying the bit line current value of the data area and comparing it with the reference current value of the reference area. If the bit line current value of the data area is greater than the reference current value of the reference area, the data area is correct and is defined as "1"; otherwise, if the bit line current value of the data area is less than the reference current value of the reference area, the data area is incorrect and is defined as "0".

[0013] Step 4: Simultaneous write operation is performed on the data area and the reference area, i.e., charge is injected onto the floating gate; Step 5: Erase operation is performed on all basic cells of the non-volatile memory, i.e., the charge in the floating gate of all basic cells is cleared.

[0014] Step 6: Verify whether the data written to the data area is correct, that is, verify the bit line current value of the data area. Compare the bit line current value of the data area with the reference current value of the reference area. If the bit line current value of the data area is greater than the reference current value of the reference area, the data is written correctly and is defined as "1". Conversely, if the bit line current value of the data area is less than the reference current value of the reference area, the data is written incorrectly and is defined as "0".

[0015] Step 7: Perform the remaining erase and write operations in the order of Steps 1 to 6 above.

[0016] The present invention, by employing the method of adding a reference area write operation to the erase and write operations of the SST type non-volatile memory, achieves the following beneficial effects: the bit line currents of the data area and the reference area decay simultaneously, slowing down the decline in the ratio between the bit line currents of the data area and the reference area, thereby extending the number of erase and write operations of the data area. Furthermore, the hardware process of the SST type non-volatile memory does not require changes, thus saving costs, and the implementation method is simple and easy to operate.

[0017] The present invention will be further described below with reference to the accompanying drawings and specific embodiments. Attached Figure Description

[0018] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on the provided drawings without creative effort.

[0019] Figure 1 This is a basic unit structure diagram of a typical SST type FLASH memory.

[0020] Figure 2 This is a schematic diagram of the array structure of a commonly used SST type FLASH memory.

[0021] Figure 3 This is a schematic diagram illustrating the steps of a method for improving the lifespan of SST-type non-volatile memory, specifically implemented according to the present invention. Detailed Implementation

[0022] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0023] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0024] See Figure 3 The present invention provides a schematic diagram illustrating the steps of a method for improving the lifespan of an SST-type non-volatile memory. The non-volatile memory includes several basic cell array structures, each array structure being divided into a data area and a reference area. The specific steps of the method are as follows:

[0025] Step 1 S301: Perform an erase operation on all basic cells of the non-volatile memory, that is, clear the charge in the floating gate of all basic cells;

[0026] Step 2 S302: Verify whether the data area erasure operation was successful, that is, verify the bit line current of the data area. Compare the bit line current value of the data area with the reference current value of the reference area. If the bit line current value of the data area is greater than the reference current value of the reference area, the data area erasure operation is successful and is defined as "1"; otherwise, if the bit line current value of the data area is less than the reference current value of the reference area, the erasure operation fails and is defined as "0".

[0027] Step 3 S303: Verify whether the data in the data area is correct after erasure, that is, verify the bit line current value of the data area. Compare the bit line current value of the data area with the reference current value of the reference area. If the bit line current value of the data area is greater than the reference current value of the reference area, the data in the data area is correct and is defined as "1"; otherwise, if the bit line current value of the data area is less than the reference current value of the reference area, the data in the data area is incorrect and is defined as "0".

[0028] Step 4 S304: Simultaneous write operation is performed on the data area and the reference area, that is, charge is injected onto the floating gate;

[0029] Step 5 S305: Perform an erase operation on all basic cells of the non-volatile memory, that is, clear the charge in the floating gate of all basic cells;

[0030] Step 6 S306: Verify whether the data written to the data area is correct, that is, verify the bit line current value of the data area. Compare the bit line current value of the data area with the reference current value of the reference area. If the bit line current value of the data area is greater than the reference current value of the reference area, the data is written correctly and is defined as "1". Conversely, if the bit line current value of the data area is less than the reference current value of the reference area, the data is written incorrectly and is defined as "0".

[0031] Step 7 S307: Perform the remaining erase and write operations in the order of Steps 1 to 6 above.

[0032] The above provides a detailed description of a method for improving the lifespan of SST-type non-volatile memory provided by the present invention. Specific examples have been used to illustrate the principles and implementation methods of the present invention. The description of the above embodiments is only for the purpose of helping to understand the method and core ideas of the present invention. At the same time, for those skilled in the art, there will be changes in the specific implementation methods and application scope based on the ideas of the present invention. Therefore, the content of this specification should not be construed as a limitation of the present invention.

[0033] It should be noted that the various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. Similar or identical parts between embodiments can be referred to interchangeably. For the apparatus disclosed in the embodiments, since it corresponds to the method disclosed in the embodiments, the description is relatively simple; relevant parts can be referred to the method section.

[0034] It should also be noted that, in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that elements inherent to a process, method, article, or apparatus that comprises a list of elements, or elements inherent to such processes, methods, articles, or apparatus, are also included. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0035] The above description of the disclosed embodiments enables those skilled in the art to make or use the invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the invention. Therefore, the invention is not to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A method for improving the lifespan of an SST-type non-volatile memory, wherein the non-volatile memory comprises a plurality of basic cell array structures, the array structure being divided into a data area and a reference area, characterized in that, The specific steps of the method are as follows: Step 1: Perform an erase operation on all basic cells of the non-volatile memory, that is, clear the charge in the floating gate of all basic cells; Step 2: Verify whether the data area erasure operation was successful. This involves verifying the bit line current of the data area and comparing it with the reference current value of the reference area. If the bit line current value of the data area is greater than the reference current value of the reference area, the data area erasure operation is successful and is defined as "1"; otherwise, if the bit line current value of the data area is less than the reference current value of the reference area, the erasure operation fails and is defined as "0". Step 3: Verify the correctness of the data area after erasure. This involves verifying the bit line current value of the data area and comparing it with the reference current value of the reference area. If the bit line current value of the data area is greater than the reference current value of the reference area, the data area is correct and is defined as "1"; otherwise, if the bit line current value of the data area is less than the reference current value of the reference area, the data area is incorrect and is defined as "0". Step 4: Simultaneous write operations are performed on the data area and the reference area, i.e., charge is injected onto the floating gate; Step 5: Perform an erase operation on all basic cells of the non-volatile memory, that is, clear the charge in the floating gate of all basic cells; Step 6: Verify whether the data written to the data area is correct, that is, verify the bit line current value of the data area. Compare the bit line current value of the data area with the reference current value of the reference area. If the bit line current value of the data area is greater than the reference current value of the reference area, the data is written correctly and is defined as "1". Conversely, if the bit line current value of the data area is less than the reference current value of the reference area, the data is written incorrectly and is defined as "0". Step 7: Perform the remaining erase and write operations in the order of Steps 1 to 6 above.

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