Soft-error resistant sram
By employing a dual interlocking structure and layout-optimized SRAM memory cells, the problems of multi-node flipping and insufficient read stability are solved, achieving a highly reliable and fast write-resistant SRAM design resistant to soft errors.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- SHANGHAI HUAHONG GRACE SEMICON MFG CORP
- Filing Date
- 2022-11-30
- Publication Date
- 2026-05-29
AI Technical Summary
Existing SRAM memory cells suffer from problems such as multi-node flipping and insufficient read noise tolerance, especially with frequent read errors under low voltage. Furthermore, existing soft error protection designs are inadequate in terms of multi-node flipping and write speed.
The SRAM memory cell with a dual interlock structure includes MOS transistors and transmission transistors connected by common source and common drain. By increasing the distance between the inverting memory nodes through layout design, four interlocked memory nodes are formed, which enhances the resistance to multi-node flip-flops. Furthermore, the read static noise tolerance and write noise tolerance are improved by optimizing the layout settings.
It effectively resists single and multiple node flips, improves read and write stability, increases read static noise tolerance and write noise tolerance, has self-recovery capability, and features high reliability and fast write speed.
Smart Images
Figure CN115719609B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to a semiconductor integrated circuit, and more particularly to a static random access memory (SRAM) resistant to soft errors. Background Technology
[0002] Memory is an important component of modern electronic systems. Modern computers operate around memory, so hardening memory to resist soft errors is an important way to eliminate soft errors in electronic systems.
[0003] To date, there has been a great deal of research on hardening design for SRAM memory cells. Depending on the core hardening technology applied to the memory cell structure, it can be divided into redundancy hardening, layout hardening, and combined hardening.
[0004] Redundancy hardening is the most commonly used hardening technique in SRAM memory cell circuit-level hardening design. The method of hardening the circuit is to store two or more times the stored data and use this backup data to correct or block single-node flips that occur in the SRAM memory cell, thereby achieving the purpose of suppressing soft errors.
[0005] The Dual Interlocked Storage Cell (DICE) is a classic, widely used, redundant, and hardened storage cell structure. The circuit structure of a DICE storage cell is as follows: Figure 1 As shown.
[0006] The DICE memory cell includes four pairs of PMOS and NMOS transistors connected together by their drains: PMOS P0 and NMOS N0, PMOS P1 and NMOS N1, PMOS P2 and NMOS N2, and PMOS P3 and NMOS N3. Each drain connection forms a memory node, namely memory nodes S0, Q, QN, and S1. Each PMOS transistor P0-P3 and NMOS transistor N0-N3 is also connected to a corresponding memory node, and the connected memory node is out of phase with the memory node of the corresponding drain. Moreover, the gates of the same pair of PMOS and NMOS transistors are connected to different memory nodes. For example, the gate of PMOS transistor P0 is connected to memory node S1, and the gate of NMOS transistor N0 is connected to memory node Q. Memory nodes S1 and Q are in phase but are out of phase with memory node S0.
[0007] Figure 1 It also includes four transfer transistors, all of which are NMOS transistors, namely NMOS transistors N4, N5, N6 and N7. The source of each transfer transistor is connected to a memory node, the drain is connected to the corresponding bit line BL or BLB, and the gate is connected to the word line WL.
[0008] Figure 1 In this configuration, storage nodes Q and QN store opposite logical information, forming a latched data structure; similarly, storage nodes S0 and S1 form another pair of latched data structures. However, Q-QN and S0-S1 do not form a latch, thus isolating the two pairs of nodes storing the same data, S0-QN and Q-S1. Figure 1 Assuming the logical state of the internal nodes S0-Q-QN-S1 of the DICE storage unit is 0-1-0-1, changing the storage state of the DICE unit will result in a change of the interlocked node pairs. Figure 1 The circuit can resist the logical state change when a node in the DICE memory cell is flipped due to a single node flip.
[0009] Figure 1 The disadvantages or deficiencies of the circuit shown include:
[0010] The DICE (Digital Initialization, Interchangeable Memory) cell structure is initially designed to resist single-node flipping. However, with the continuous shrinking of process dimensions, a single soft error event no longer causes a single node within the cell to flip, but rather multiple nodes to flip simultaneously—a single-event multi-node flip (SIF). Unfortunately, DICE cells do not possess the capability to resist multi-node flips. Furthermore, DICE cells suffer from relatively low read noise tolerance, making them prone to read failures or errors under low voltage conditions.
[0011] In existing technologies, some and Figure 1 New memory cells with different structures to resist soft errors have been proposed, such as Quatro10T, we-Quatro12T, NS10T, PS10T, QUCCE10T, QUCCE12T, RHD12T, etc.
[0012] However, Quatro10T, we-Quatro12T, NS10T, and PS10T can only tolerate errors in some of their internal nodes.
[0013] The QUCCE10T and QUCCE12T have poor tolerance for soft errors in nodes with internal storage "0";
[0014] The RHD12T exhibits good resistance to soft errors, but its write speed is very slow.
[0015] Other soft-error resistant units, such as RSP14T, SIS10T and RHMD10T, have also been proposed. Figures 2A-2J The circuit structures of the 10 types of soft-error resistant memory cells described above are shown below. Detailed descriptions are not provided here; please refer to [reference needed]. Figures 2A-2J The circuit diagram is recorded.
[0016] The RSP14T is an improvement over the RHD12T, offering better resistance to soft errors, but it also results in a larger area and higher power consumption.
[0017] The SIS10T and RHMD10T have excessively high write and read speeds because they only have two transmission transistors. Summary of the Invention
[0018] The technical problem to be solved by the present invention is to provide a soft error resistant SRAM that can resist multi-node flips and improve read static noise margin (RSNM) and write noise margin (WNM).
[0019] To solve the above-mentioned technical problems, the SRAM storage cell of the soft-error resistant SRAM provided by the present invention has a dual interlocking structure, including:
[0020] A first NMOS transistor and a second NMOS transistor are connected in common source configuration. The drain of the first NMOS transistor is the first memory node, and the drain of the second NMOS transistor is the second memory node. The sources of both the first and second NMOS transistors are grounded. The gate of the first NMOS transistor is connected to the second memory node, and the gate of the second NMOS transistor is connected to the first memory node. The first memory node and the second memory node are inverted.
[0021] A first PMOS transistor and a second PMOS transistor are connected by a common source. The drain of the first PMOS transistor is the third storage node, and the drain of the second PMOS transistor is the fourth storage node. The sources of the first PMOS transistor and the second PMOS transistor are both grounded. The gate of the first PMOS transistor is connected to the fourth storage node, and the gate of the second PMOS transistor is connected to the third storage node. The third storage node and the fourth storage node are inversely related to each other.
[0022] The gate and source of the fifth MOS transistor with common drain connection are connected between the first memory node and the third memory node in phase, so that the first memory node and the third memory node form a source follower relationship.
[0023] The gate and source of the sixth MOS transistor with common drain connection are connected between the second and fourth memory nodes that are in phase, so that the second and fourth memory nodes form a source follower relationship.
[0024] The gate of the third MOS transistor is connected to the second memory node, and the source and drain of the third MOS transistor are connected between the first memory node and the third memory node. The third MOS transistor serves as a switch.
[0025] The gate of the fourth MOS transistor is connected to the first memory node, and the source and drain of the fourth MOS transistor are connected between the second memory node and the fourth memory node. The fourth MOS transistor serves as a switch.
[0026] A further improvement is that the SRAM storage cell further includes a first transmission transistor, a second transmission transistor, a third transmission transistor, and a fourth transmission transistor.
[0027] The first storage node is connected to the input end of the first transmission tube.
[0028] The second storage node is connected to the input of the second transmission tube.
[0029] The third storage node is connected to the input of the third transmission tube.
[0030] The fourth storage node is connected to the input of the fourth transmission tube.
[0031] A further improvement is that the first transmission tube, the second transmission tube, the third transmission tube, and the fourth transmission tube all have the same conductivity type.
[0032] A further improvement is that the gates of the first transmission transistor, the second transmission transistor, the third transmission transistor, and the fourth transmission transistor are all connected to word lines.
[0033] A further improvement is that the outputs of both the first and third transmission tubes are connected to the first bit line.
[0034] The output terminals of the second transmission tube and the fourth transmission tube are both connected to the second bit line, and the first bit line and the second bit line are opposite to each other.
[0035] The drain of the first transmission tube, the second transmission tube, the third transmission tube, and the fourth transmission tube are used as input terminals and the source is used as output terminals.
[0036] A further improvement is that the first transmission transistor, the second transmission transistor, the third transmission transistor, and the fourth transmission transistor are all PMOS transistors.
[0037] A further improvement is that the first transmission transistor, the second transmission transistor, the third transmission transistor, and the fourth transmission transistor are all NMOS transistors.
[0038] A further improvement is that both the fifth MOS transistor and the sixth MOS transistor are NMOS transistors.
[0039] A further improvement is that both the third MOS transistor and the fourth MOS transistor are NMOS transistors.
[0040] A further improvement is that, on the layout, the second NMOS transistor, the fourth MOS transistor, the fourth transmission transistor, the second transmission transistor, and the sixth MOS transistor are all formed in the first active region.
[0041] The first PMOS transistor is formed in the second active region.
[0042] The second PMOS transistor is formed in the third active region.
[0043] The first NMOS transistor, the third MOS transistor, the third transmission transistor, the first transmission transistor, and the fifth MOS transistor are all formed in the fourth active region.
[0044] Both the first active region and the fourth active region are N-type doped.
[0045] Both the second active region and the third active region are P-type doped.
[0046] A further improvement is that, on the layout, the polysilicon gate of the sixth MOS transistor extends from the first active region into the second active region and forms the polysilicon gate of the first PMOS transistor.
[0047] The polysilicon gate of the fifth MOS transistor extends from the fourth active region into the third active region and forms the polysilicon gate of the second PMOS transistor.
[0048] The polysilicon gate of the second NMOS transistor and the polysilicon gate of the fourth MOS transistor are parallel and connected together outside the first active region.
[0049] The polysilicon gate of the first NMOS transistor and the polysilicon gate of the third MOS transistor are parallel and connected together outside the fourth active region.
[0050] The source region of the fourth transmission transistor and the drain region of the fourth MOS transistor are shared.
[0051] The source region of the third transmission transistor and the drain region of the third MOS transistor are shared.
[0052] The source region of the second transmission transistor and the source region of the sixth MOS transistor are shared.
[0053] The source region of the first transmission transistor and the source region of the fifth MOS transistor are shared.
[0054] The drain region of the second NMOS transistor and the source region of the fourth MOS transistor are shared.
[0055] The drain region of the first NMOS transistor and the source region of the third MOS transistor are shared.
[0056] A further improvement is that the polysilicon gate of the sixth MOS transistor, the drain region of the second PMOS transistor, and the drain region of the fourth MOS transistor are all connected to the fourth memory node composed of the first metal layer through corresponding contact holes at the top.
[0057] A further improvement is that the polysilicon gate of the fifth MOS transistor, the drain region of the first PMOS transistor, and the drain region of the third MOS transistor are all connected to the third memory node composed of the first metal layer through corresponding contact holes at the top.
[0058] A further improvement is that the source regions of the fourth MOS transistor, the sixth MOS transistor, and the polysilicon gate of the first NMOS transistor are all connected to the second memory node composed of the second metal layer through corresponding top contact holes, the first metal layer, and the first layer vias, respectively.
[0059] A further improvement is that the source regions of the third MOS transistor, the fifth MOS transistor, and the polysilicon gate of the second NMOS transistor are all connected to the first memory node composed of the second metal layer through corresponding top contact holes, the first metal layer, and the first layer vias, respectively.
[0060] A further improvement is that the widths of the first active regions at the second NMOS transistor and the fourth MOS transistor are equal;
[0061] The width of the first active region at the second NMOS transistor is greater than the width of the first active region at the sixth MOS transistor, so that the driving capability of both the second NMOS transistor and the fourth MOS transistor is greater than the driving capability of the sixth MOS transistor.
[0062] The width of the first active region at the second NMOS transistor is greater than the width of the third active region, so that the driving capability of both the second NMOS transistor and the fourth MOS transistor is greater than the driving capability of the second PMOS transistor.
[0063] The widths of the fourth active regions at the first NMOS transistor and the third MOS transistor are equal.
[0064] The width of the fourth active region at the first NMOS transistor is greater than the width of the fourth active region at the fifth MOS transistor, so that the driving capability of both the first NMOS transistor and the third MOS transistor is greater than the driving capability of the fifth MOS transistor.
[0065] The width of the fourth active region at the first NMOS transistor is greater than the width of the second active region, so that the driving capability of the first NMOS transistor and the third MOS transistor is greater than the driving capability of the first PMOS transistor.
[0066] This invention has four interlocked storage nodes, which can resist not only the flipping of a single sensitive node, but also the flipping of multiple nodes, such as the flipping of the third and fourth storage nodes, i.e., Q-QN dual-node flipping; this invention can also improve rsnm and wnm.
[0067] This invention, through layout settings, can increase the distance between the first and fourth storage nodes (S0-QN) and between the second and third storage nodes (S1-Q), thereby avoiding charge sharing between node pairs S0-QN and S1-Q, and preventing single-particle multi-node flipping between these node pairs. Attached Figure Description
[0068] The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments:
[0069] Figure 1 This is a circuit diagram of an existing DICE memory cell;
[0070] Figures 2A-2J This is a circuit diagram of an existing SRAM memory cell that is resistant to soft errors;
[0071] Figure 3 This is a circuit diagram of the SRAM storage cell of the SRAM resistant to soft errors according to an embodiment of the present invention;
[0072] Figure 4 This is a layout of the SRAM storage cells of the SRAM resistant to soft errors according to an embodiment of the present invention;
[0073] Figure 5 This is a functional simulation of the SRAM storage cell of the SRAM that is resistant to soft errors according to an embodiment of the present invention;
[0074] Figure 6 This is a soft error simulation of the SRAM storage cell of the soft error resistant SRAM according to an embodiment of the present invention;
[0075] Figure 7This is a comparison table of performance parameters of the SRAM storage cell of the soft error resistant SRAM of the present invention and various existing soft error resistant SRAMs.
[0076] Figure 8 This is a comparison chart of the electrical quality parameters of the SRAM memory cell of the soft error resistant SRAM of the present invention and the SRAM memory cells of various existing soft error resistant SRAMs. Detailed Implementation
[0077] like Figure 3 The diagram shown is a circuit diagram of the SRAM storage cell of the SRAM resistant to soft errors according to an embodiment of the present invention; as shown... Figure 4 The diagram shown is a layout of the SRAM storage cell of the soft-error resistant SRAM according to an embodiment of the present invention. The SRAM storage cell of the soft-error resistant SRAM according to an embodiment of the present invention has a dual interlocking structure, including:
[0078] A first NMOS transistor N101 and a second NMOS transistor N102 are connected in common source configuration. The drain of the first NMOS transistor N101 is connected to the first memory node S0, and the drain of the second NMOS transistor N102 is connected to the second memory node S1. The sources of the first NMOS transistor N101 and the second NMOS transistor N102 are both grounded. The gate of the first NMOS transistor N101 is connected to the second memory node S1, and the gate of the second NMOS transistor N102 is connected to the first memory node S0. The first memory node S0 and the second memory node S1 are inversely related to each other.
[0079] A first PMOS transistor P101 and a second PMOS transistor P102 are connected in common-source configuration. The drain of the first PMOS transistor P101 is connected to the third memory node Q, and the drain of the second PMOS transistor P102 is connected to the fourth memory node QN. The sources of the first PMOS transistor P101 and the second PMOS transistor P102 are both grounded. The gate of the first PMOS transistor P101 is connected to the fourth memory node QN, and the gate of the second PMOS transistor P102 is connected to the third memory node Q. The third memory node Q and the fourth memory node QN are inversely related.
[0080] The gate and source of the common-drain fifth MOS transistor N105 are connected between the first memory node S0 and the third memory node Q, which are in phase, so that the first memory node S0 and the third memory node Q form a source follower relationship.
[0081] The gate and source of the sixth MOS transistor N106, which is connected to the common drain, are connected between the second memory node S1 and the fourth memory node QN, which are in phase, so that the second memory node S1 and the fourth memory node QN form a source follower relationship.
[0082] The gate of the third MOS transistor N103 is connected to the second memory node S1, and the source and drain of the third MOS transistor N103 are connected between the first memory node S0 and the third memory node Q. The third MOS transistor N103 serves as a switch.
[0083] The gate of the fourth MOS transistor N104 is connected to the first memory node S0, and the source and drain of the fourth MOS transistor N104 are connected between the second memory node S1 and the fourth memory node QN. The fourth MOS transistor N104 serves as a switch.
[0084] The SRAM storage unit further includes a first transmission transistor T101, a second transmission transistor T102, a third transmission transistor T103, and a fourth transmission transistor T104.
[0085] The first storage node S0 is connected to the input terminal of the first transmission tube T101.
[0086] The second storage node S1 is connected to the input terminal of the second transmission tube T102.
[0087] The third storage node Q is connected to the input terminal of the third transmission tube T103.
[0088] The fourth storage node QN is connected to the input terminal of the fourth transmission tube T104.
[0089] In this embodiment of the invention, the first transmission transistor T101, the second transmission transistor T102, the third transmission transistor T103, and the fourth transmission transistor T104 all have the same conductivity type. The gates of the first transmission transistor T101, the second transmission transistor T102, the third transmission transistor T103, and the fourth transmission transistor T104 are all connected to the word line WL.
[0090] The output terminals of the first transmission tube T101 and the third transmission tube T103 are both connected to the first bit line BL.
[0091] The output terminals of the second transmission tube T102 and the fourth transmission tube T104 are both connected to the second bit line BLB, and the first bit line BL and the second bit line BLB are opposite to each other.
[0092] The drain of the first transmission tube T101, the second transmission tube T102, the third transmission tube T103, and the fourth transmission tube T104 are used as input terminals and the source is used as output terminals.
[0093] In this embodiment of the invention, the first transmission transistor T101, the second transmission transistor T102, the third transmission transistor T103, and the fourth transmission transistor T104 are all NMOS transistors. In other embodiments, the first transmission transistor T101, the second transmission transistor T102, the third transmission transistor T103, and the fourth transmission transistor T104 can all be PMOS transistors.
[0094] Both the fifth MOS transistor N105 and the sixth MOS transistor N106 are NMOS transistors.
[0095] Both the third MOS transistor N103 and the fourth MOS transistor N104 are NMOS transistors.
[0096] like Figure 4 As shown, on the layout, the second NMOS transistor N102, the fourth MOS transistor N104, the fourth transmission transistor T104, the second transmission transistor T102, and the sixth MOS transistor N106 are all formed in the first active region 101.
[0097] The first PMOS transistor P101 is formed in the second active region 102.
[0098] The second PMOS transistor P102 is formed in the third active region 103.
[0099] The first NMOS transistor N101, the third MOS transistor N103, the third transmission transistor T103, the first transmission transistor T101, and the fifth MOS transistor N105 are all formed in the fourth active region 104.
[0100] Both the first active region 101 and the fourth active region 104 are N-type doped.
[0101] Both the second active region 102 and the third active region 103 are P-type doped.
[0102] Figure 4 The map includes multiple layers, including:
[0103] The four active regions, corresponding to the layer AC, are marked with labels 101 to 104 respectively.
[0104] The N+ injection area corresponds to the N+ layer, and the active area covered by the N+ injection area is the first active area 101 and the fourth active area 104.
[0105] The P+ injection area corresponds to the P+ layer, and the active area covered by the P+ injection area is the second active area 102 and the third active area 103.
[0106] The N-well corresponds to the NW layer, and the P+ injection region is located in the N-well.
[0107] Polysilicon gate 201, the corresponding layer is PO;
[0108] Contact hole 202, the corresponding layer is CT;
[0109] The first metal layer 203 corresponds to layer M1;
[0110] The first layer has a through-hole of 204, and the corresponding layer is V1;
[0111] The second metal layer 205 corresponds to layer M2.
[0112] To better understand the formation regions of each MOS transistor, Figure 4 The dashed boxes in the diagram illustrate the formation regions of the corresponding MOS transistors. Each MOS transistor is formed in its corresponding active region, including a corresponding polysilicon gate 201 and a source and drain region formed in the active regions on both sides of the polysilicon gate 201. The tops of the polysilicon gate 201, source region, and drain region of each MOS transistor are led out through corresponding contact holes 202, metal layers such as the first metal layer 203 and the second metal layer 205, and vias such as the first layer via 204.
[0113] like Figure 4 As shown, on the layout, the polysilicon gate 201 of the sixth MOS transistor N106 extends from the first active region 101 into the second active region 102 and forms the polysilicon gate 201 of the first PMOS transistor P101.
[0114] The polysilicon gate 201 of the fifth MOS transistor N105 extends from the fourth active region 104 into the third active region 103 and forms the polysilicon gate 201 of the second PMOS transistor P102.
[0115] The polysilicon gate 201 of the second NMOS transistor N102 and the polysilicon gate 201 of the fourth MOS transistor N104 are parallel and connected together outside the first active region 101.
[0116] The polysilicon gate 201 of the first NMOS transistor N101 and the polysilicon gate 201 of the third MOS transistor N103 are parallel and connected together outside the fourth active region 104.
[0117] The source region of the fourth transmission transistor T104 and the drain region of the fourth MOS transistor N104 are shared.
[0118] The source region of the third transmission transistor T103 and the drain region of the third MOS transistor N103 are shared.
[0119] The source region of the second transmission transistor T102 and the source region of the sixth MOS transistor N106 are shared.
[0120] The source region of the first transmission transistor T101 and the source region of the fifth MOS transistor N105 are shared.
[0121] The drain region of the second NMOS transistor N102 and the source region of the fourth MOS transistor N104 are shared.
[0122] The drain region of the first NMOS transistor N101 and the source region of the third MOS transistor N103 are shared.
[0123] The polysilicon gate 201 of the sixth MOS transistor N106, the drain region of the second PMOS transistor P102, and the drain region of the fourth MOS transistor N104 are all connected to the fourth memory node QN composed of the first metal layer 203 through the corresponding contact holes 202 at the top.
[0124] The polysilicon gate 201 of the fifth MOS transistor N105, the drain region of the first PMOS transistor P101, and the drain region of the third MOS transistor N103 are all connected to the third memory node Q composed of the first metal layer 203 through the corresponding contact holes 202 at the top.
[0125] The source region of the fourth MOS transistor N104, the source region of the sixth MOS transistor N106, and the polysilicon gate 201 of the first NMOS transistor N101 are all connected to the second memory node S1 composed of the second metal layer 205 through the corresponding top contact hole 202, the first metal layer 203, and the first layer through hole 204, respectively.
[0126] The source region of the third MOS transistor N103, the source region of the fifth MOS transistor N105, and the polysilicon gate 201 of the second NMOS transistor N102 are all connected to the first memory node S0 composed of the second metal layer 205 through the corresponding top contact hole 202, the first metal layer 203, and the first layer via 204, respectively.
[0127] The widths of the first active region 101 at the second NMOS transistor N102 and the fourth MOS transistor N104 are equal.
[0128] The width of the first active region 101 at the second NMOS transistor N102 is greater than the width of the first active region 101 at the sixth MOS transistor N106, so that the driving capability of the second NMOS transistor N102 and the fourth MOS transistor N104 is greater than the driving capability of the sixth MOS transistor N106.
[0129] The width of the first active region 101 at the second NMOS transistor N102 is greater than the width of the third active region 103, so that the driving capability of the second NMOS transistor N102 and the fourth MOS transistor N104 is greater than the driving capability of the second PMOS transistor P102.
[0130] The widths of the fourth active region 104 at the first NMOS transistor N101 and the third MOS transistor N103 are equal.
[0131] The width of the fourth active region 104 at the first NMOS transistor N101 is greater than the width of the fourth active region 104 at the fifth MOS transistor N105, so that the driving capability of the first NMOS transistor N101 and the third MOS transistor N103 is greater than the driving capability of the fifth MOS transistor N105.
[0132] The width of the fourth active region 104 at the first NMOS transistor N101 is greater than the width of the second active region 102, so that the driving capability of the first NMOS transistor and the third MOS transistor N103 is greater than the driving capability of the first PMOS transistor P101.
[0133] In this embodiment of the invention, the SRAM storage unit includes a write state, a hold state, and a read state.
[0134] During the write state, a pair of write signals that are inversely related are pre-applied to the first bit line BL and the second bit line BLB, and the word line WL is leveled to turn on the first transmission transistor T101, the second transmission transistor T102, the third transmission transistor T103 and the fourth transmission transistor T104.
[0135] When the SRAM memory cell is in a holding state, the word line WL is leveled to turn off the first transmission transistor T101, the second transmission transistor T102, the third transmission transistor T103, and the fourth transmission transistor T104.
[0136] When the SRAM memory cell is in read state, the first bit line BL and the second bit line BLB are pre-charged with a high potential, and the word line WL is charged to turn on the first transmission transistor T101, the second transmission transistor T102, the third transmission transistor T103, and the fourth transmission transistor T104.
[0137] The embodiments of the present invention have four interlocked storage nodes, which can resist not only the flipping of a single sensitive node, but also the flipping of multiple nodes, such as the flipping of the third storage node Q and the fourth storage node QN, i.e., the Q-QN dual-node flipping; the present invention can also improve rsnm and wnm.
[0138] The present invention, through layout settings, can increase the distance between the first inverted storage node S0 and the fourth storage node QN (S0-QN) and between the second storage node S1 and the third storage node Q (S1-Q), thereby avoiding charge sharing between node pairs S0-QN and S1-Q, and preventing single-particle multi-node flipping between these node pairs.
[0139] The working principle of the SRAM storage cell of the SRAM resistant to soft errors in this embodiment of the invention:
[0140] like Figure 3 As shown, there are four internal storage nodes Q, QB, S0, and S1, which ensure normal function and soft error resistance through a special internal feedback structure. The following analysis of all basic operations is illustrated using the storage of cell '1' as an example.
[0141] Hold Mode: In hold mode, bit line WL is set to GND (ground potential), and transmission transistors T101, T102, T103, and T104 are turned off. Bit lines BL and BLB are pre-charged to reduce wake-up time. For the case of storing '0', transistors P102, N101, N103, and N106 remain on, while transistors P101, N102, N104, and N105 remain off. Therefore, the cell can stably store '0'.
[0142] Writing: To write the new value '1' into the cell, bit lines BL and BLB are first set to '1' and '0' respectively. Then, bit line WL is set to VDD (the power supply voltage), and all access transistors T101-T104 are turned on. Bit line BL pulls up nodes Q and S0, and bit line BLB pulls down nodes QN and S1. The internal feedback structure further accelerates this process, and finally, with the help of the corresponding access transistors, the value is rewritten, successfully writing the '1' signal.
[0143] Read: During a read operation, bit lines BL and BLB are pre-charged to VDD. Bit line WL is set to GND and VDD. Therefore, access transistors T101, T102, T103, and T104 are turned on. Bit line BL discharges through T103 and T101 via N103 and N101, while BL remains at VDD. When the voltage difference between bit lines BL and BLB gradually reaches a sufficient level (100mV) to be detected by the sensitive amplifier, the data stored in the cell is read out, and the read operation is complete.
[0144] Soft error resistance principle:
[0145] The SRAM memory cells of this invention, which are resistant to soft errors, can recover correctly when a single node flip occurs at all internal sensitive nodes. A sensitive node refers to the memory node corresponding to the reverse-biased drain of a transistor that is in the off state. If the drain of a PMOS transistor is in state '0' and is affected by a soft error, a positive transient pulse is generated, which produces a single node flip from '0' to '1'. Conversely, if the drain of a PMOS transistor is in state '1' and is affected by a soft error, a glitch from '1' to '1' is generated. Similarly, if the drain of an NMOS transistor is in state '1' and is affected by a soft error, a negative transient pulse is generated, which produces a single node flip from '1' to '0'. Conversely, if the drain of an NMOS transistor is in state '0' and is affected by a soft error, a glitch from '0' to '0' is generated. Therefore, in this embodiment of the invention, when the SRAM memory cell stores '0', the internal nodes Q, QN, S0, and S1 are '0', '1', '0', and '1' respectively; where nodes Q, QN, and S1 are sensitive nodes.
[0146] Since transistor P101 is turned off, node Q corresponding to the drain of transistor P101 is a sensitive node.
[0147] N104 is off, therefore the node QN corresponding to the drain of N104 is a sensitive node;
[0148] Since N102 is off, node S1, which corresponds to the drain of N102, is a sensitive node.
[0149] 1) Node Q flips:
[0150] If node Q is affected by a soft error and flips from '0' to '1', transistor N105 is temporarily turned on, and P102 is temporarily turned off. Since node S1 is not affected, it remains at '1'. Because the driving capability of transistor N101 is greater than that of N105, node S0 remains at '0'. Eventually, transistors N101 and N103, now in the on state, pull node Q back to '0', restoring it to its initial correct value.
[0151] 2) Node QN flips:
[0152] If node QN is affected by a soft error and flips from '1' to '0', transistor P101 is temporarily turned on, and N106 is temporarily turned off. Since node S1 is not affected, it remains at '1'. Because the driving capability of transistors N101 and N103 is greater than that of P101, node Q remains at '0'. Eventually, transistor P102, which is in the on state, pulls node QN back to '1', restoring it to its initial correct value.
[0153] 3) Node S1 flips:
[0154] If node S1 is affected by a soft error and flips from '1' to '0', transistors N101 and N103 are temporarily turned off, while other nodes remain in their initial state due to their own capacitance. Eventually, transistor N106, which is now on, pulls node S1 back to '1', restoring it to its initial correct value.
[0155] 4) Nodes undergoing multi-node flipping in Q-QN pairs:
[0156] If nodes Q and QN flip simultaneously due to charge sharing, i.e., node Q flips from '0' to '1' and node QN flips from '1' to '0', transistors P101 and N105 are temporarily turned on, while P102 and N106 are temporarily turned off. Since node S1 is unaffected, it remains at '1'. Because the driving capability of transistor N101 is greater than that of N105, node S0 remains at '0'. Transistors N101 and N103 have a greater driving capability than P101; the on-state transistors N101 and N103 pull node Q down back to '0'. The return of node Q to '0' causes transistor P102 to turn on, pulling QN back to '1', restoring it to its initial correct value.
[0157] In summary, if a soft error affects memory nodes Q, QN, S1, or memory node pair Q-QN, the SRAM-resistant memory cell of this embodiment can be fully restored to the correct state. However, it should be noted that if memory node pair S1-Q or S0-QN is affected by incident particles and deposits a sufficient amount of charge, the cell state may become incorrect. In the layout design of the SRAM-resistant memory cell of this embodiment, the distance between memory node pairs S1-Q and S0-QN is maximized, thus avoiding charge sharing between these node pairs, i.e., single-event multi-node flips do not occur between these node pairs.
[0158] like Figure 5 The image shows a functional simulation of the SRAM storage cell of the SRAM resistant to soft errors according to an embodiment of the present invention; the SRAM storage cell of the embodiment of the present invention has normal read, write, and hold functions.
[0159] like Figure 6The figure shows a soft error simulation of the SRAM memory cell of the soft error-resistant SRAM according to an embodiment of the present invention. Transient pulses 301 are applied to nodes Q, QN, S0 and node pair Q-QN at 80ns, 150ns, 180ns, and 250ns respectively. The simulation waveforms show that when any node or node pair Q-QN of the SRAM memory cell is disturbed and flips, it can remain correct, and the flipped node can recover to the correct logic state. The SRAM memory cell of the soft error-resistant SRAM according to this embodiment of the present invention is abbreviated as HSLV memory cell. As can be seen from the above, the HSLV memory cell of this embodiment of the present invention is resistant to soft errors and has self-recovery capability.
[0160] like Figure 7 The table shown is a comparison of the performance parameters of the SRAM storage cell of the soft error resistant SRAM of the present invention and the SRAM storage cells of various existing soft error resistant SRAMs. Figure 7 In this document, HSLV12T represents the SRAM storage cell of the soft-error resistant SRAM in this embodiment of the invention, and 12T indicates that the storage cell contains 12 transistors. For the storage cells corresponding to Quatro10T, we-Quatro12T, QUCCE10T, QUCCE12T, RHD12T, RSP14T, NS10T, PS10T, SIS10T, and RHMD10T, please refer to [reference needed]. Figures 2A-2J As shown in the figures, the data in dashed boxes 302, 303, and 304 indicate that the HSLV memory cell in this embodiment exhibits higher RSNM, WNM, and faster write speed T. wa .
[0161] To comprehensively compare memory cells with high soft-fault resilience, we use the electrical quality metric (EQM) to evaluate their overall performance. The formula for calculating EQM is:
[0162]
[0163] Among them, I W Indicates the write current, Q crit Indicates the critical charge; Area represents the area of the storage cell; Power hold Indicates the energy consumption of the storage unit; T ra T represents the read speed. wa Indicates the write speed.
[0164] Figure 7 In the diagram, the data within the dashed box 305 represents the value of EQM; for example... Figure 8The figure shown is a comparison of the electrical quality parameters of the SRAM memory cell of the soft error resistant SRAM of the present invention and the SRAM memory cells of various existing soft error resistant SRAMs; it can be seen that the HSLV memory cell of the present invention has the highest EQM index.
[0165] As can be seen from the above, the soft-error resistant storage unit of the present invention can achieve high-reliability applications, and the HSLV unit can recover from single-node flips induced on all its sensitive nodes. Furthermore, the HSLV unit of the present invention can also recover from multi-node flips induced on its storage node pairs Q-QN.
[0166] The HSLV cell in this embodiment of the invention also exhibits the highest read static noise margin RSNM and write noise margin WNM, which enables the storage cell to have more stable read operations under low voltage.
[0167] The HSLV unit of this invention has the highest overall performance index (EQM), making it a better choice for high-reliability applications.
[0168] The present invention has been described in detail above through specific embodiments, but these are not intended to limit the invention. Many modifications and improvements can be made by those skilled in the art without departing from the principles of the invention, and these should also be considered within the scope of protection of the present invention.
Claims
1. A soft-error resistant SRAM, characterized in that, SRAM memory cells have a dual interlocking structure, including: A first NMOS transistor and a second NMOS transistor are connected by a common source. The drain of the first NMOS transistor is the first storage node, and the drain of the second NMOS transistor is the second storage node. The sources of the first NMOS transistor and the second NMOS transistor are both grounded. The gate of the first NMOS transistor is connected to the second storage node, and the gate of the second NMOS transistor is connected to the first storage node. The first storage node and the second storage node are inversely related to each other. A first PMOS transistor and a second PMOS transistor are connected by a common source. The drain of the first PMOS transistor is the third storage node, and the drain of the second PMOS transistor is the fourth storage node. The sources of the first PMOS transistor and the second PMOS transistor are both connected to the power supply voltage. The gate of the first PMOS transistor is connected to the fourth storage node, and the gate of the second PMOS transistor is connected to the third storage node. The third storage node and the fourth storage node are inversely related to each other. The gate and source of the common-drain fifth MOS transistor are connected between the first memory node and the third memory node in phase, so that the first memory node and the third memory node form a source follower relationship; The gate and source of the sixth MOS transistor with common drain connection are connected between the second memory node and the fourth memory node in phase, so that the second memory node and the fourth memory node form a source follower relationship; The gate of the third MOS transistor is connected to the second memory node, and the source and drain of the third MOS transistor are connected between the first memory node and the third memory node. The third MOS transistor serves as a switch. The gate of the fourth MOS transistor is connected to the first memory node, and the source and drain of the fourth MOS transistor are connected between the second memory node and the fourth memory node. The fourth MOS transistor serves as a switch.
2. The soft-error resistant SRAM as described in claim 1, characterized in that: The SRAM storage unit further includes a first transmission transistor, a second transmission transistor, a third transmission transistor, and a fourth transmission transistor; The first storage node is connected to the input end of the first transmission tube; The second storage node is connected to the input of the second transmission tube; The third storage node is connected to the input end of the third transmission tube; The fourth storage node is connected to the input of the fourth transmission tube.
3. The soft-error resistant SRAM as described in claim 2, characterized in that: The first transmission tube, the second transmission tube, the third transmission tube, and the fourth transmission tube all have the same conductivity type.
4. The soft-error resistant SRAM as described in claim 3, characterized in that: The gates of the first transmission transistor, the second transmission transistor, the third transmission transistor, and the fourth transmission transistor are all connected to word lines.
5. The soft-error resistant SRAM as described in claim 4, characterized in that: The output terminals of both the first transmission tube and the third transmission tube are connected to the first bit line; The output terminals of the second transmission tube and the fourth transmission tube are both connected to the second bit line, and the first bit line and the second bit line are opposite to each other; The drain of the first transmission tube, the second transmission tube, the third transmission tube, and the fourth transmission tube are used as input terminals and the source is used as output terminals.
6. The soft-error resistant SRAM as described in claim 5, characterized in that: The first transmission transistor, the second transmission transistor, the third transmission transistor, and the fourth transmission transistor are all PMOS transistors.
7. The soft-error resistant SRAM as described in claim 5, characterized in that: The first transmission transistor, the second transmission transistor, the third transmission transistor, and the fourth transmission transistor are all NMOS transistors.
8. The soft-error resistant SRAM as described in claim 7, characterized in that: Both the fifth MOS transistor and the sixth MOS transistor are NMOS transistors.
9. The soft-error resistant SRAM as described in claim 8, characterized in that: Both the third MOS transistor and the fourth MOS transistor are NMOS transistors.
10. The soft-error resistant SRAM as described in claim 9, characterized in that: In the layout, the second NMOS transistor, the fourth MOS transistor, the fourth transmission transistor, the second transmission transistor, and the sixth MOS transistor are all formed in the first active region; The first PMOS transistor is formed in the second active region; The second PMOS transistor is formed in the third active region; The first NMOS transistor, the third MOS transistor, the third transmission transistor, the first transmission transistor, and the fifth MOS transistor are all formed in the fourth active region; Both the first active region and the fourth active region are N-type doped; Both the second active region and the third active region are P-type doped.
11. The soft-error resistant SRAM as described in claim 10, characterized in that: In the layout, the polysilicon gate of the sixth MOS transistor extends from the first active region into the second active region and forms the polysilicon gate of the first PMOS transistor; The polysilicon gate of the fifth MOS transistor extends from the fourth active region into the third active region and forms the polysilicon gate of the second PMOS transistor. The polysilicon gate of the second NMOS transistor and the polysilicon gate of the fourth MOS transistor are parallel and connected together outside the first active region; The polysilicon gates of the first NMOS transistor and the third MOS transistor are parallel and connected together outside the fourth active region; The source region of the fourth transmission transistor and the drain region of the fourth MOS transistor are shared. The source region of the third transmission transistor and the drain region of the third MOS transistor are shared. The source region of the second transmission transistor and the source region of the sixth MOS transistor are shared. The source region of the first transmission transistor and the source region of the fifth MOS transistor are shared. The drain region of the second NMOS transistor and the source region of the fourth MOS transistor are shared. The drain region of the first NMOS transistor and the source region of the third MOS transistor are shared.
12. The soft-error resistant SRAM as described in claim 11, characterized in that: The polysilicon gate of the sixth MOS transistor, the drain region of the second PMOS transistor, and the drain region of the fourth MOS transistor are all connected to the fourth memory node composed of the first metal layer through corresponding contact holes at the top.
13. The soft-error resistant SRAM as described in claim 11, characterized in that: The polysilicon gate of the fifth MOS transistor, the drain region of the first PMOS transistor, and the drain region of the third MOS transistor are all connected to the third memory node composed of the first metal layer through corresponding contact holes at the top.
14. The soft-error resistant SRAM as described in claim 11, characterized in that: The source regions of the fourth MOS transistor, the sixth MOS transistor, and the polysilicon gate of the first NMOS transistor are all connected to the second memory node composed of the second metal layer through corresponding top contact holes, the first metal layer, and the first layer via, respectively.
15. The soft-error resistant SRAM as described in claim 11, characterized in that: The source regions of the third MOS transistor, the fifth MOS transistor, and the polysilicon gate of the second NMOS transistor are all connected to the first memory node composed of the second metal layer through corresponding top contact holes, the first metal layer, and the first layer via, respectively.
16. The soft-error resistant SRAM as described in claim 10, characterized in that: The widths of the first active regions at the second NMOS transistor and the fourth MOS transistor are equal; The width of the first active region at the second NMOS transistor is greater than the width of the first active region at the sixth MOS transistor, so that the driving capability of both the second NMOS transistor and the fourth MOS transistor is greater than the driving capability of the sixth MOS transistor. The width of the first active region at the second NMOS transistor is greater than the width of the third active region, so that the driving capability of both the second NMOS transistor and the fourth MOS transistor is greater than the driving capability of the second PMOS transistor. The widths of the fourth active regions at the first NMOS transistor and the third MOS transistor are equal. The width of the fourth active region at the first NMOS transistor is greater than the width of the fourth active region at the fifth MOS transistor, so that the driving capability of both the first NMOS transistor and the third MOS transistor is greater than the driving capability of the fifth MOS transistor. The width of the fourth active region at the first NMOS transistor is greater than the width of the second active region, so that the driving capability of both the first NMOS transistor and the third MOS transistor is greater than the driving capability of the first PMOS transistor.