Reconfigurable processor chip architecture and applications for accelerating genetic sequencing

Abstract

The application relates to a reconfigurable processor chip architecture and application for accelerating gene sequencing, which comprises a configuration manager, a reconfigurable detection array, a post-processing and recording module, a first storage unit, a second storage unit and peripherals, the peripherals comprise a preprocessing module for converting a FASTQ file of a sample gene sequence to be detected into ASCII code; the first storage unit is used for storing the ASCII code of the sample gene sequence to be detected; the second storage unit is used for storing the ASCII code of a reference gene sequence; the configuration manager is connected with the reconfigurable detection array, the post-processing and recording module and the peripherals through a control bus; the peripherals are connected with the first storage unit and the second storage unit through the control bus; the input end of the reconfigurable detection array is connected with the first storage unit and the second storage unit, and the output end is connected with the post-processing and recording module. The application can greatly improve the sequencing speed.

Description

Technical Field

[0001] The present invention relates to the field of gene sequencing technology, and in particular to a reconfigurable processor chip architecture and application for accelerating gene sequencing. Background Art

[0002] As gene sequencing enters the era of big data, sequencing projects involve enormous amounts of data, and traditional computer systems are no longer able to adapt to the typical demands of big data. Currently, platforms suitable for big data processing can be divided into two categories: software processing platforms and hardware processing platforms.

[0003] Cloud computing platform and GPGPU platform are the two most mainstream big data software processing platforms.

[0004] 1) Cloud computing platform

[0005] Generally speaking, cloud computing platforms consist of a large number of homogeneous, CPU-based, single-node servers that work together collaboratively. Cloud computing platform programming models can be broadly categorized into two types: Map-Reduce-based and graph-based. Both models leverage task-level parallelism and dataset parallelism to accelerate application execution.

[0006] 2) GPGPU Platform

[0007] The GPGPU platform is a popular parallel acceleration platform. Each GPGPU processor chip is typically composed of multiple SMs, each SM consisting of multiple SPs, each of which is a computing unit. Essentially, GPGPU leverages data-level parallelism using SIMD to accelerate task execution. Currently, programming standards such as CUDA, OpenCL, and OpenACC have been proposed and implemented for GPGPU platforms. This has significantly lowered the barrier to entry for developing GPGPU-based applications, making GPGPU a widely used parallel acceleration platform.

[0008] While cloud computing and GPGPU platforms can indeed accelerate the execution of gene sequencing algorithms, they each have their own limitations. For cloud computing platforms, maintaining cluster operations requires significant overhead, and from an efficiency perspective, the computational efficiency of a single node is not very high. While each GPU chip in a GPGPU platform boasts high computational efficiency, it also consumes a significant amount of power, often consuming significant amounts of energy to process tasks. From a granular perspective, each node in a cloud computing platform typically utilizes a standard CPU architecture. However, the general-purpose design of a CPU may not provide ideal performance for specific gene sequencing algorithm tasks. Each GPU chip in a GPGPU platform is primarily suited to processing tasks that require data-level parallelism. While most gene sequencing algorithms are well-suited to data-level parallelism, some are not. Furthermore, to enhance versatility, GPU chips integrate many functional components not required by gene sequencing algorithms, resulting in a larger chip area and significant additional power consumption.

[0009] The hardware platforms mainly include application-specific integrated circuits (ASICs) and field-programmable gate arrays (FPGAs).

[0010] 1) ASIC

[0011] Compared to cloud platforms and GPGPUs, ASICs utilize improved hardware architectures to accelerate algorithms. As specialized integrated circuits, ASICs offer high computational efficiency for specific applications and algorithms. However, their specialized nature also results in limited flexibility and high development costs. The high barrier to entry for hardware design also results in long design and development cycles and significant development complexity.

[0012] 2) FPGA

[0013] Compared to ASICs, FPGAs have a much shorter design cycle and implementation complexity. They incorporate a large number of gate-level reconfigurable logic units with programmable interconnects, simulating the various parallel computations of hardware like CPUs and GPUs, thereby accelerating data processing. However, due to the fine-grained nature of FPGAs based on lookup tables (LUTs), reconfiguration is slow, and they consume more area and power than dedicated chips. Detection speed is a key metric in gene sequencing.

[0014] CGRA is a coarse-grained reconfigurable architecture. It improves efficiency by building modules internally and reducing interconnections. By configuring different functional areas, data flow is driven. At the next moment, the unit can be quickly configured with a different function, driving the data flow again. This is a data-driven, dynamically reconfigurable computing model that features high-speed data parallelism, fast routing, and compilation, improving system performance. Summary of the Invention

[0015] The technical problem to be solved by the present invention is to provide a reconfigurable processor chip architecture and application for accelerating gene sequencing. Through high-speed parallel processing of data and pipeline operation, high performance and low power consumption of the system can be achieved in a limited array. The high-speed and highly flexible reconfigurable function can also be used to simultaneously compare multiple special gene sequences, greatly improving the sequencing speed.

[0016] The technical solution adopted by the present invention to solve its technical problems is as follows: providing a reconfigurable processor chip architecture for accelerating gene sequencing, including a configuration manager, a reconfigurable detection array, a post-processing and recording module, a first storage unit, a second storage unit and a peripheral device, wherein the peripheral device includes at least one pre-processing module for converting a FASTQ file of a gene sequence of a sample to be detected into ASCII code; the first storage unit is used to store the ASCII code of the gene sequence of the sample to be detected, and the second storage unit is used to store the ASCII code of the reference gene sequence; the configuration manager is connected to the reconfigurable detection array, the post-processing and recording module and the peripheral device via a control bus, respectively; the peripheral device is connected to the first storage unit and the second storage unit via a control bus, respectively; the input end of the reconfigurable detection array is connected to the first storage unit and the second storage unit, respectively, and the output end is connected to the post-processing and recording module;

[0017] The configuration manager is used to configure the functions of the reconfigurable detection array and the post-processing and recording module through the control bus. The reconfigurable detection array and the post-processing and recording module run according to the configured functions of the configuration manager.

[0018] The reconfigurable detection array includes m×n reconfigurable detection units PE arranged in an array, and two adjacent reconfigurable detection units PE are interconnected to form a grid structure; the reconfigurable detection units PE execute processing according to the tasks configured by the configuration manager.

[0019] The reconfigurable detection unit PE includes an SPM, a configuration memory module, a first multiplexer MUX, a second multiplexer MUX, a calculation structure ALU and a counter Couter, wherein the configuration memory module and the first multiplexer MUX are respectively connected to the calculation structure ALU, and the SPM is connected to the calculation structure ALU through the second multiplexer MUX; the configuration memory module is respectively connected to the first multiplexer MUX and the second multiplexer MUX;

[0020] The SPM is used to store the reference gene sequence input by the second storage unit;

[0021] The configuration memory module contains configuration information written by the configuration manager, which is used to control the functions and output paths performed by the computing structure ALU;

[0022] The configuration memory module controls the first multiplexer MUX to input operands from the upper, lower, left, and right reconfigurable detection units PE to the calculation structure ALU;

[0023] The configuration memory module controls the second multiplexer MUX to input operands from the SPM to the calculation structure ALU.

[0024] The post-processing and recording module includes a third storage unit and several index recording units. The third storage unit is used to store the output results of the reconfigurable detection array. The index recording unit is used to find the fragments matching the reference gene sequence from the gene sequence of the sample to be detected, as well as the position index of the matching fragments in the gene sequence of the sample to be detected.

[0025] The index recording unit includes a selection control logic, a multi-input AND module, a third multiplexer MUX, an adder Adder, an index recording module Index and a reference gene fragment length recording module;

[0026] The selection control logic is used to connect the calculation structure ALU output of the reconfigurable detection unit PE that performs target sequence comparison to the AND module, and connect the counter Counter output of the reconfigurable detection unit PE that performs target sequence comparison to the third multiplexer MUX;

[0027] The reference gene fragment length recording module is used to output the length of the reference gene sequence minus 1 as an operand to the adder Adder and perform an addition operation;

[0028] The AND module connects the outputs of all reconfigurable detection units PE used in the reconfigurable detection array for the reference gene sequence detected by its own index recording unit; when the output of the AND module is 1, the AND module controls the third multiplexer MUX and the adder Adder to enable and perform corresponding operations;

[0029] The third multiplexer MUX connects the outputs of the counters Couter of all reconfigurable detection units PE used in the reconfigurable detection array for the reference gene sequence detected by its own index recording unit, and the output of the AND module and the selection control logic control the output of the counter Couter of the last reconfigurable detection unit in the data path, and inputs the selected result as an operand to the adder Adder and writes it to the start of the index in the index recording module Index;

[0030] The adder Adder is controlled by the output of the AND module, and adds the data selected by the third multiplexer MUX to the length of the reference gene sequence required for detection by the corresponding reconfigurable detection unit PE output by the reference gene fragment length recording module -1 to obtain the last index of the matching gene sequence in the gene sequence of the sample to be detected, and then writes it to the end of the index in the index recording module Index;

[0031] The index recording module Index is used to record the position index of the gene fragment identical to the reference gene sequence in the gene sequence of the sample to be detected.

[0032] The first storage unit, the second storage unit and the third storage unit are all static random access memories.

[0033] The technical solution adopted by the present invention to solve the technical problem is to provide a gene sequence alignment method for the above-mentioned reconfigurable processor chip architecture for accelerating gene sequencing, comprising the following steps:

[0034] (1) Reference gene sequence loading: The configuration manager controls the reference gene sequence for sequence comparison in the second storage unit to be input into the 6×6 reconfigurable detection array, and sequentially passes through the first reconfigurable detection unit PE of the first row, the first reconfigurable detection unit PE of the second row, the first reconfigurable detection unit PE of the third row, the first reconfigurable detection unit PE of the fourth row, the first reconfigurable detection unit PE of the fifth row, the first reconfigurable detection unit PE of the sixth row, the sixth reconfigurable detection unit PE of the second row, and the sixth reconfigurable detection unit PE of the third row according to the set detection path, and stores the reference gene sequence in the SPM of the corresponding reconfigurable detection unit PE;

[0035] (2) Reconfigurable detection unit PE loading: The configuration manager controls the computing structure ALU of the reconfigurable detection unit PE to enable the comparator function. The input of the second multiplexer MUX in the reconfigurable detection unit PE comes from the SPM of the unit and is output to the index recording unit in the post-processing and recording module.

[0036] (3) Post-processing and recording module loading: The configuration manager records the length of the set detection path to the reference gene fragment length recording module and configures the task of the selection control logic. The selection control logic controls the AND module to select all reconfigurable detection units PE connected to the set detection path;

[0037] (4) The configuration manager controls the second storage unit to input the gene sequence of the sample to be detected from the first reconfigurable detection unit PE in the first row into the 6×6 reconfigurable detection array, and starts indexing and recording. After each gene to be detected enters the reconfigurable detection unit PE, it is compared with the reference gene stored in its own SPM. If they are equal, the calculation structure ALU outputs 1, otherwise the output is 0.

[0038] (5) When the first gene of the gene sequence of the sample to be detected enters the sixth reconfigurable detection unit PE in the third row for comparison operation, the counter Counter of the sixth reconfigurable detection unit PE in the third row starts working and counts from 0;

[0039] (6) When the 8th gene of the sample gene sequence to be detected enters the 6th reconfigurable detection unit PE in the 3rd row, if the calculation structure ALU comparison outputs of all the reconfigurable detection units PE on the detection path are set to 1, the counter Counter of the 6th reconfigurable detection unit PE in the 3rd row is 5; and all the inputs of the AND gate of the 8-input AND module in the AND module are 1, then the output of the AND module is 1, and the control enables the third multiplexer MUX and the adder Adder; the third multiplexer MUX selects to read the Counter value of the 6th reconfigurable detection unit PE in the 3rd row as 5, and the sequence length -1 in the reference gene fragment length recording module is 5 as two operands input to the adder Adder for addition operation, and the output is 12;

[0040] (7) The value passed through the third multiplexer MUX is written to the index start of the index recording module Index, and the output of the adder Adder is written to the index end of the index recording module Index, thus completing a successful sequence match and obtaining the index [5 12] of the corresponding sequence in the gene sequence of the sample to be detected. The post-processing and recording module finally transmits the index [5 12] back to the configuration manager through the control bus for subsequent operations.

[0041] Beneficial effects

[0042] Due to the adoption of the above technical solution, the present invention has the following advantages and positive effects compared with the prior art: The technical problem to be solved by the present invention is to achieve high performance and low power consumption of the system in a limited array through high-speed parallel processing of data and pipeline operation in the hardware architecture of accelerated gene sequencing, and to achieve the comparison of multiple special gene sequences at the same time through high-speed and high-flexibility reconfigurable functions, thereby greatly improving the sequencing speed; the reconfigurable processor chip architecture of the present invention can improve the following aspects: (1) General-purpose processors are usually equipped with several functional components such as floating-point arithmetic units, fixed-point arithmetic units and branch prediction logic, while gene The matching algorithm has the characteristics of low computational density and high parallelism. These components not only occupy the area of ​​the processor silicon chip, but also consume a large amount of electrical energy. However, in the present invention, the acceleration unit is customized to accelerate the gene matching algorithm, the floating-point operation unit in the processor is removed and the fixed-point operation unit is added, thereby meeting the low computational density characteristics of the gene matching algorithm; (2) Compared with ASIC, the present invention has high flexibility and can reconstruct the detection path detection unit according to the gene sequence to be detected, thereby reducing the development cycle and development cost; (3) Compared with FPGA, the present invention has coarse granularity and fast reconstruction speed, which speeds up the detection speed and reduces power consumption. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] Figure 1 This is a basic flow chart of gene sequencing according to an embodiment of the present invention;

[0044] Figure 2 This is a diagram of the architecture of a reconfigurable processor chip for accelerating gene sequencing according to an embodiment of the present invention;

[0045] Figure 3 Schematic diagram of the internal structure of the reconfigurable detection unit PE according to an embodiment of the present invention;

[0046] Figure 4 Schematic diagram of the internal structure of the post-processing and recording module according to an embodiment of the present invention;

[0047] Figure 5 Schematic diagram of the internal structure of the index recording unit according to an embodiment of the present invention;

[0048] Figure 6 Schematic diagram of the gene sequence comparison method according to the embodiment of the present invention. DETAILED DESCRIPTION

[0049] Below in conjunction with specific embodiment, further set forth the present invention.Should be understood that these embodiments are only used to illustrate the present invention and are not used in limiting the scope of the present invention.In addition, should be understood that after reading the content taught by the present invention, those skilled in the art can make various changes or modifications to the present invention, and these equivalent forms fall equally within the scope limited by the appended claims of the application.

[0050] The embodiment of the present invention relates to a reconfigurable processor chip architecture for accelerating gene sequencing, see Figure 1 This figure illustrates the basic process of gene sequencing, which involves extracting the original FASTQ file from the sample to be tested, performing preprocessing, sequence alignment, tag deduplication, and variant detection, and finally generating an analysis report. The architecture of the present invention is primarily applicable to the sequence alignment step.

[0051] See also Figure 2 The figure shows the overall layout of the reconfigurable processor chip architecture for accelerating gene sequencing. It is mainly composed of peripherals, configuration manager, reconfigurable detection array, post-processing and recording module, first storage unit (Sample SRAM), second storage unit (Library SRAM) and control bus, which are introduced in detail below.

[0052] The peripheral device includes, but is not limited to, a preprocessing module. The FASTQ raw file generated after extraction of the sample to be tested is passed through the preprocessing module, where the base sequence to be compared is extracted as a string. This is then converted into its corresponding ASCII code and stored in the Sample SRAM via the control bus. The reference gene sequence for sequence comparison is then transferred from the peripheral device to the Library SRAM via the control bus.

[0053] The configuration manager is bidirectionally interconnected with peripherals through a control bus, reading and writing data from peripherals and controlling the data flow into the corresponding SRAM (Sample SRAM or Library SRAM). At the same time, the configuration manager is also responsible for configuring the functions performed by each reconfigurable detection unit (PE) in the reconfigurable detection array, the data flow path when aligning different sequences, and controlling the specific functions of the post-processing and recording modules.

[0054] The reconfigurable detection array consists of m×n reconfigurable detection units (PEs). Each reconfigurable detection unit PE can be configured by the configuration manager to implement different functions. The four-way interconnection between the reconfigurable detection units PEs forms a mesh topology, which supports high-parallel data pipelining and can detect different reference gene sequences by reconfiguring the data path.

[0055] The Sample SRAM stores the ASCII code converted from the gene sequence of the sample to be detected, and the configuration manager controls the input of data into the array from different positions in the leftmost column of the reconfigurable detection array.

[0056] The library SRAM stores the ASCII codes of the reference gene sequence fragments required for detection. The configuration manager controls the input of data from different positions in the top row of the reconfigurable detection array and temporarily stores them in the SPM in the reconfigurable detection unit PE on the corresponding data flow path.

[0057] The post-processing and recording module is responsible for collecting detection results and processing data according to the functions configured by the configuration manager, so as to perform the next step.

[0058] Referring to Figure 3 , the figure shows the internal structure of each reconfigurable detection unit PE in the m*n reconfigurable detection array (omitting internal data wiring and control wiring). Each reconfigurable detection unit PE includes an SPM, a configuration memory module (i.e. Config Memory module) containing configuration information, two multiplexers MUX (first multiplexer MUX, second multiplexer MUX), a computing structure ALU, and a counter Couter, which are described in detail below.

[0059] The SPM is responsible for storing the reference gene sequence input from the Library SRAM.

[0060] The Config Memory module contains configuration information written by the configuration manager, which specifically controls the functions performed by the computing structure ALU and the output path, and the selection of the two multiplexers MUX.

[0061] The first multiplexer MUX or the second multiplexer MUX can select one of the five paths from above, below, left, right, or SPM to input operands to the computing structure ALU through the Config Memory module.

[0062] The computing structure ALU is determined by the Config Memory module to perform operations and output results to the SRAM in the post-processing and recording module or to the corresponding index recording unit or adjacent reconfigurable detection unit PE. When performing index recording operations, the computing structure ALU functions as a comparator, which outputs 1 when the two operands are equal, and 0 otherwise.

[0063] The counter Couter is used for counting. From the completion of loading all configuration information and reference gene sequences, the reconfigurable detection unit PE where it is located starts counting from the first data received after the sequence comparison begins (it does not work before receiving the data to be processed, and it starts counting from 0 after receiving the first data).

[0064] Referring to Figure 4 , the figure shows the internal structure of the post-processing and recording module, which includes a third storage unit SRAM and M index recording units, which are described in detail below.

[0065] The third storage unit SRAM is used to store the results output by the reconfigurable detection array.

[0066] M index record units support the simultaneous testing of M reference gene sequences. These units are enabled during the index record operation during sequence comparison and are responsible for finding fragments in the gene sequence of the sample being tested that match the reference gene sequence, as well as indexing the positions of the matching fragments in the gene sequence of the sample being tested. Each index record unit is responsible for comparison to one reference gene sequence. The configuration manager determines the number of index record units to enable by configuring parallel comparisons for multiple reference gene sequences.

[0067] See also Figure 5 The figure shows the internal structure of the index recording unit. The index recording unit includes selection control logic, a multi-input AND module, a third multiplexer (MUX), an adder (Adder), an index recording module (Index), and a reference gene fragment length recording module. These are described in detail below.

[0068] The selection control logic is used to select and connect the computing structure ALU output of the reconfigurable detection unit PE that performs target sequence comparison to the AND module, and to connect the counter Counter output of the reconfigurable detection unit PE that performs target sequence comparison to the third multiplexer MUX, and to control the third multiplexer MUX to select the counter Counter output of the last reconfigurable detection unit PE through which the data flow passes when the sequence is compared.

[0069] The reference gene fragment length recording module outputs the reference gene sequence length - 1 in the sequencing gene library as an operand to the adder for addition operation.

[0070] The AND module connects the reference gene sequence detected by the index recording unit to the outputs of all reconfigurable detection units (PEs) used in the reconfigurable detection array. When the outputs of all reference gene sequences are 1, the AND module controls the third MUX selector and the Adder adder to enable and perform the corresponding operation.

[0071] The third multiplexer MUX connects the outputs of the counters Couter in all the reconfigurable detection units PE used in the reconfigurable detection array for the reference gene sequence detected by the index recording unit. The output of the AND module and the selection control logic control the output of the counter Couter of the last reconfigurable detection unit PE in the data path, and the selected result is input as an operand to the adder Adder and written to the beginning of the index (i.e., begin) in the index recording module Index.

[0072] The adder Adder is controlled by the output of the AND module. It adds the data selected by the third multiplexer MUX to the length of the reference gene sequence required to be detected by the unit PE output by the reference gene fragment length recording module -1 to obtain the last index of the matching gene sequence in the gene sequence of the sample to be detected, and then writes it to the end of the index (i.e., end) in the index recording module Index.

[0073] The index recording module Index is used to record the position index of the gene fragment identical to the reference gene sequence in the gene sequence of the sample to be tested.

[0074] The embodiment of the present invention also relates to a gene sequence alignment method of a reconfigurable processor chip architecture for accelerating gene sequencing, which realizes Figure 1 In the "sequence alignment" step, for ease of understanding, this embodiment sets the size of the reconfigurable detection array to 6×6, the reference gene sequence to be compared is AATCCTAC, and the sample sequence to be tested is ATACTCATCCTAATTATACT... (To simplify understanding, the gene sequences to be compared are represented by capital letters in the embodiment. In practice, they need to be converted into the ASCII code corresponding to each letter for comparison). The specific implementation process is as follows:

[0075] Configuration loading:

[0076] Reference gene sequence loading: First, the configuration manager controls the search for the reference gene sequence AATCCTAC from the gene sequence library in the Library SRAM and inputs it into the 6×6 reconfigurable detection array. The configuration manager configures the sequencing path, see Figure 6 : Pass through PE1-1 (store A), PE1-2 (store A), PE1-3 (store T), PE1-4 (store C), PE1-5 (store C), PE1-6 (store T), PE2-6 (store A), PE3-6 (store C) in sequence, and store the reference gene sequence into the SPM of the corresponding reconfigurable detection unit PE of the set path.

[0077] Reconfigurable detection unit PE loading: The configuration manager controls the ALU of the reconfigurable detection unit PE to enable the comparator function. The input of one of the MUXs in the reconfigurable detection unit PE comes from the SPM of the unit and is output to the index recording unit of the post-processing and recording module.

[0078] Post-processing and recording module loading: The configuration manager records the length of the set detection path (i.e., the number of reconfigurable detection units PE that needs to be passed) to the reference gene fragment length recording module, and configures the task of selecting the control logic. The selection control logic controls the AND module to select all reconfigurable detection units PE that the set path passes through.

[0079] Index record:

[0080] The configuration manager controls the Sample SRAM to input the gene sequence of the sample to be tested from PE1-1 into the 6×6 reconfigurable detection array and start index recording. After each letter representing a gene enters the PE, it is compared with the reference letter in the SPM in the PE. If they are equal, the ALU output is 1, otherwise it is 0. When the first gene (letter) of the sample sequence to be tested enters PE3-6 for comparison, the Counter of PE3-6 starts working and counts from 0. When the 8th gene (letter) of the sample sequence to be tested enters PE3-6, if the ALU comparator output of all reconfigurable detection units PE on the detection path is set to 1, the counter of the last PE3-6 will count to 5. At this time, all inputs of the 8-input AND gate in the AND module are 1, and the AND module output is 1, which controls the activation of the third multiplexer MUX and adder Adder. The third multiplexer MUX selects to read the Counter value (5) of PE3-6 and the sequence length -1 (5) in the reference gene fragment length recording module as two operands to input the adder Adder for addition operation, and the output is 12. The value passed through the third multiplexer MUX is written to the begin of the index recording module Index, and the output of the adder Adder is written to the end of the index recording module Index, thus completing a successful sequence match and obtaining the index of the corresponding sequence in the gene sequence of the sample to be detected as [5 12]. The post-processing and recording module finally transmits the index [5 12] back to the configuration manager through the control bus to help it perform subsequent operations such as clipping.

[0081] Due to space limitations, the reconfigurable detection array presented in this embodiment is relatively small in scale and only demonstrates the sequencing (index recording) process of a single gene sequence. The reconfigurable detection array of the present invention can simultaneously detect multiple reference gene sequences in parallel by configuring different sequencing paths, using the same method as described above.

[0082] The foregoing descriptions of specific exemplary embodiments of the present invention are for purposes of illustration and description. These descriptions are not intended to limit the invention to the precise forms disclosed, and it is apparent that many variations and modifications are possible in light of the foregoing teachings. The exemplary embodiments have been selected and described for the purpose of explaining the specific principles of the invention and their practical application, thereby enabling those skilled in the art to realize and utilize a variety of exemplary embodiments of the invention and various options and modifications. The scope of the invention is intended to be defined by the claims and their equivalents.

Claims

1. A reconfigurable processor chip architecture for accelerating gene sequencing, characterized in that: The system comprises a configuration manager, a reconfigurable detection array, a post-processing and recording module, a first storage unit, a second storage unit, and a peripheral device, wherein the peripheral device comprises at least one pre-processing module for converting a FASTQ file of a gene sequence of a sample to be detected into ASCII code; the first storage unit is used to store the ASCII code of the gene sequence of the sample to be detected, and the second storage unit is used to store the ASCII code of the reference gene sequence; the configuration manager is connected to the reconfigurable detection array, the post-processing and recording module, and the peripheral device via a control bus, respectively; the peripheral device is connected to the first storage unit and the second storage unit via a control bus, respectively; the input end of the reconfigurable detection array is connected to the first storage unit and the second storage unit, respectively, and the output end is connected to the post-processing and recording module; The configuration manager is used to configure the functions of the reconfigurable detection array and the post-processing and recording module through the control bus, and the reconfigurable detection array and the post-processing and recording module operate according to the functions configured by the configuration manager; The reconfigurable detection array includes m×n reconfigurable detection units PE arranged in an array, and two adjacent reconfigurable detection units PE are interconnected to form a grid structure; the reconfigurable detection units PE execute processing according to the tasks configured by the configuration manager; The post-processing and recording module includes a third storage unit and several index recording units. The third storage unit is used to store the output results of the reconfigurable detection array. The index recording unit is used to find the fragments matching the reference gene sequence from the gene sequence of the sample to be detected, as well as the position index of the matching fragments in the gene sequence of the sample to be detected.

2. The reconfigurable processor chip architecture for accelerating gene sequencing according to claim 1, characterized in that: The reconfigurable detection unit PE includes an SPM, a configuration memory module, a first multiplexer MUX, a second multiplexer MUX, a calculation structure ALU and a counter Couter, wherein the configuration memory module and the first multiplexer MUX are respectively connected to the calculation structure ALU, and the SPM is connected to the calculation structure ALU through the second multiplexer MUX; the configuration memory module is respectively connected to the first multiplexer MUX and the second multiplexer MUX; The SPM is used to store the reference gene sequence input by the second storage unit; The configuration memory module contains configuration information written by the configuration manager, which is used to control the functions and output paths performed by the computing structure ALU; The configuration memory module controls the first multiplexer MUX to input operands from the upper, lower, left, and right reconfigurable detection units PE to the calculation structure ALU; The configuration memory module controls the second multiplexer MUX to input operands from the SPM to the calculation structure ALU.

3. The reconfigurable processor chip architecture for accelerating gene sequencing according to claim 1, characterized in that: The index recording unit includes a selection control logic, a multi-input AND module, a third multiplexer MUX, an adder Adder, an index recording module Index and a reference gene fragment length recording module; The selection control logic is used to connect the calculation structure ALU output of the reconfigurable detection unit PE that performs target sequence comparison to the AND module, and connect the counter Counter output of the reconfigurable detection unit PE that performs target sequence comparison to the third multiplexer MUX; The reference gene fragment length recording module is used to output the length of the reference gene sequence minus 1 as an operand to the adder Adder and perform an addition operation; The AND module connects the outputs of all reconfigurable detection units PE used in the reconfigurable detection array for the reference gene sequence detected by its own index recording unit; when the output of the AND module is 1, the AND module controls the third multiplexer MUX and the adder Adder to enable and perform corresponding operations; The third multiplexer MUX connects the outputs of the counters Couter of all reconfigurable detection units PE used in the reconfigurable detection array for the reference gene sequence detected by its own index recording unit, and the output of the AND module and the selection control logic control the output of the counter Couter of the last reconfigurable detection unit in the data path, and inputs the selected result as an operand to the adder Adder and writes it to the start of the index in the index recording module Index; The adder Adder is controlled by the output of the AND module, and adds the data selected by the third multiplexer MUX to the length of the reference gene sequence required for detection by the corresponding reconfigurable detection unit PE output by the reference gene fragment length recording module -1 to obtain the last index of the matching gene sequence in the gene sequence of the sample to be detected, and then writes it to the end of the index in the index recording module Index; The index recording module Index is used to record the position index of the gene fragment identical to the reference gene sequence in the gene sequence of the sample to be detected.

4. The reconfigurable processor chip architecture for accelerating gene sequencing according to claim 2, characterized in that: The first storage unit, the second storage unit and the third storage unit are all static random access memories.

5. A gene sequence alignment method using the reconfigurable processor chip architecture for accelerating gene sequencing according to any one of claims 1 to 4, characterized in that: The following steps are involved: (1) Reference gene sequence loading: The configuration manager controls the reference gene sequence for sequence comparison in the second storage unit to be input into the 6×6 reconfigurable detection array, and sequentially passes through the first reconfigurable detection unit PE in the first row, the first reconfigurable detection unit in the second row, the first reconfigurable detection unit in the third row, the first reconfigurable detection unit in the fourth row, the first reconfigurable detection unit in the fifth row, the first reconfigurable detection unit in the sixth row, the sixth reconfigurable detection unit in the second row, and the sixth reconfigurable detection unit in the third row according to the set detection path, and stores the reference gene sequence in the SPM of the corresponding reconfigurable detection unit PE; (2) Loading the reconfigurable detection unit PE: The configuration manager controls the computing structure ALU of the reconfigurable detection unit PE to enable the comparator function. The input of the second multiplexer MUX in the reconfigurable detection unit PE comes from the SPM of the unit and is output to the index recording unit in the post-processing and recording module. (3) Post-processing and recording module loading: The configuration manager records the length of the set detection path to the reference gene fragment length recording module and configures the task of the selection control logic. The selection control logic controls the AND module to select all reconfigurable detection units PE connected to the set detection path; (4) The configuration manager controls the second storage unit to input the gene sequence of the sample to be detected from the first reconfigurable detection unit PE in the first row into the 6×6 reconfigurable detection array, and starts indexing and recording. After each gene to be detected enters the reconfigurable detection unit PE, it is compared with the reference gene stored in its own SPM. If they are equal, the calculation structure ALU outputs 1, otherwise the output is 0. (5) When the first gene of the gene sequence of the sample to be detected enters the sixth reconfigurable detection unit PE in the third row for comparison operation, the counter Counter of the sixth reconfigurable detection unit PE in the third row starts working and counts from 0; (6) When the 8th gene of the sample gene sequence to be detected enters the 6th reconfigurable detection unit PE in the 3rd row, if the calculation structure ALU comparison outputs of all the reconfigurable detection units PE on the detection path are set to 1 (, then the counter Counter of the 6th reconfigurable detection unit PE in the 3rd row is 5; and all the inputs of the AND gate of the 8-input AND module in the AND module are 1, then the output of the AND module is 1, and the control enables the third multiplexer MUX and the adder Adder; the third multiplexer MUX selects to read the Counter value of the 6th reconfigurable detection unit PE in the 3rd row as 5, and the sequence length -1 in the reference gene fragment length recording module is 5 as two operands input to the adder Adder for addition operation, and the output is 12; (7) The value passed through the third multiplexer MUX is written to the index start of the index recording module Index, and the output of the adder Adder is written to the index end of the index recording module Index, thereby completing a successful sequence match and obtaining the index [512] of the corresponding sequence in the gene sequence of the sample to be detected. The post-processing and recording module finally transmits the index [512] back to the configuration manager through the control bus for subsequent operations.

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