Harmonic rejection transceiver with duty cycle control

Abstract

An architecture for an N-phase transmitter and receiver is proposed, which can achieve harmonic performance similar to that of an N-phase system with a higher N value using a lower N value and a lower VCO frequency. Unlike conventional N-phase systems, the local oscillator clocks are overlapped. In the example of a three-phase system, the VCO frequency can be 1.5 times the local oscillator frequency, and the three-phase clocks use a 50% duty cycle. Each component (0, 120, 240) of the N-phase input signal and its inverse (180, 300, 60) are mixed with the corresponding components (Clk0, Clk120, Clk240) and their inverses (Clk0b, Clk120b, Clk240b) of the N-phase clock signal, respectively, wherein these mixed pairs are combined separately before being mixed with other such pairs.

Description

[0001] This application claims priority to U.S. Provisional Patent Application No. 63 / 032,588, filed May 30, 2020, entitled “HARMONICS REJECTION TRANSCEIVER WITH DUTY RATIO CONTROL” by Jiang et al., the entire contents of which are incorporated herein by reference. TECHNICAL FIELD

[0002] The present disclosure relates generally to an architecture for reducing unwanted harmonic content in a transceiver. BACKGROUND

[0003] In wireless terminals such as cellular telephones, there are typically clock harmonics generated by the local oscillator clock that are undesirable. On the transmitter side, these clock harmonics can be mixed back through non-linearities to near the frequency of the desired signal and create near channel distortion and affect other wireless terminals using similar carrier frequencies in the vicinity. On the receiver side, blocker signals at clock harmonic frequencies close to the desired signal can fall on top of the desired signal frequency when mixed back down to baseband frequencies through the down conversion process and degrade the received signal’s distortion figure and signal to noise ratio. It is desirable to reduce the impact of these clock harmonics as much as possible. SUMMARY

[0004] According to one aspect of the disclosure, a transmitter has N-phase signal sources, where N is an integer greater than 2, the N-phase signal sources configured to provide N input signals forming an N-phase input signal and an inverted input signal for each of the N input signals. The transmitter also includes a frequency synthesizer configured to generate N clock signals forming an N-phase clock signal and an inverted clock signal for each of the N clock signals, each of the N clock signals having a phase corresponding to one of the N input signals. The transmitter further includes a harmonic rejection mixer having a first set of N mixer pairs configured to receive the N-phase input signal and the inverted N-phase input signal, receive the N-phase clock signal and the inverted N-phase clock signal, and generate a first output signal. Each mixer pair in the first set includes a first mixer configured to receive a respective one of the input signals and a respective one of the clock signals and mix the respective one of the input signals with the respective one of the clock signals, and a second mixer configured to receive an inverted input signal of the respective one of the input signals and an inverted clock signal of the respective one of the clock signals and mix the inverted input signal of the respective one of the input signals with the inverted clock signal of the respective one of the clock signals. The harmonic rejection mixer is configured to form N first intermediate signals by combining, for each mixer pair in the first set, an output of the first mixer with an output of the second mixer, and combine the N first intermediate signals to form the first output signal.

[0005] Optionally, in the foregoing aspect, the transmitter further includes N amplifiers each configured to receive a respective one of the first intermediate signals, and amplify the respective one of the first intermediate signals prior to combining the N first intermediate signals to form the first output signal.

[0006] Optionally, in any of the preceding aspects, the harmonic rejection mixer further comprises a second set of N mixer pairs configured to receive the N-phase input signal and an inverse of the N-phase input signal, receive the N-phase clock signal and an inverse of the N-phase clock signal, and generate a second output signal. Each mixer pair in the second set comprises: a first mixer configured to receive a respective one of the input signals and an inverse of a respective one of the clock signals and mix the respective one of the input signals with the inverse of the respective one of the clock signals; and a second mixer configured to receive an inverse of the respective one of the input signals and the respective one of the clock signals and mix the inverse of the respective one of the input signals with the respective one of the clock signals. The harmonic rejection mixer is configured to form N second intermediate signals by combining an output of the first mixer with an output of the second mixer for each mixer pair in the second set, and combine the N second intermediate signals to form the second output signal.

[0007] Optionally, in the preceding aspect, the transmitter further comprises an inductive coupler comprising: a first coil configured to receive the first output signal at a first terminal and the second output signal at a second terminal; and a second coil inductively coupled to the first coil, the second coil having a first terminal configured to provide a single-ended output of the transmitter and a second terminal connected to ground.

[0008] Optionally, in the preceding aspect, the transmitter further comprises a power amplifier configured to receive and amplify the single-ended output.

[0009] Optionally, in the preceding aspect, the transmitter further comprises an antenna configured to receive and transmit the single-ended output.

[0010] Optionally, in any of the preceding aspects, the frequency synthesizer comprises: a voltage-controlled oscillator configured to generate a positive oscillator signal and a negative oscillator signal; and a local oscillator clock generator configured to generate, from the positive oscillator signal and the negative oscillator signal, N clock signals forming the N-phase clock signal and an inverse clock signal for each of the N clock signals.

[0011] Optionally, in the preceding aspect, the voltage-controlled oscillator is configured to generate the positive oscillator signal and the negative oscillator signal at a frequency that is 1 / 2N times a frequency of the N-phase clock signal.

[0012] Optionally, in any of the foregoing aspects, the N-phase signal source is configured to receive an input signal in an in-phase / quadrature format, thereby generating N input signals that form the N-phase input signal and an inverted input signal for each of the N input signals.

[0013] Alternatively, in any of the foregoing aspects, N equals 3.

[0014] Optionally, in the foregoing aspect, the frequency synthesizer is configured to generate N clock signals with a duty cycle of 1 / 2, and to generate an inverted clock signal with a duty cycle of 1 / 2.

[0015] Alternatively, in any of the foregoing aspects, N equals 4.

[0016] Optionally, in the foregoing aspect, the frequency synthesizer is configured to generate N clock signals with a duty cycle of 1 / 3 and to generate an inverted clock signal with a duty cycle of 2 / 3.

[0017] According to another aspect of this disclosure, a method for transmitting a signal is provided, the method comprising: receiving N input signals forming an N-phase input signal and an inverted input signal for each of the N input signals; and receiving N clock signals forming an N-phase clock signal and an inverted clock signal for each of the N clock signals, each of the N clock signals having a phase corresponding to one of the N input signals. The method further includes generating a first output signal by performing the following operations for each of the N input signals and their inverted phases, based on the N-phase input signals and their inverted phases, and based on the N-phase clock signals and their inverted phases: mixing the input signals with a corresponding clock signal from the clock signals; mixing the inverted input signal of the corresponding input signal with the inverted clock signal of the corresponding clock signal from the clock signals; combining the mixed input signal with the corresponding clock signal and the inverted input signal of the mixed input signal with the inverted clock signal of the corresponding clock signal from the clock signals to form a first intermediate signal; and combining N first intermediate signals to form a first output signal.

[0018] Optionally, in the foregoing aspect, the method further includes: amplifying the N first intermediate signals before combining the N first intermediate signals to form the first output signal.

[0019] Optionally, in either of the foregoing two aspects, the method further generates a second output signal based on the N-phase input signals and their inverted counterparts, and based on the N-phase clock signals and their inverted counterparts, by the following operations: for each of the N input signals and their inverted counterparts, mixing the input signal with the inverted clock signal of a corresponding clock signal; mixing the inverted input signal of a corresponding input signal with the corresponding clock signal; and combining the mixed input signal with the inverted clock signal of the corresponding clock signal and the mixed input signal with the corresponding clock signal to form a second intermediate signal. The method further includes combining N second intermediate signals to form a second output signal.

[0020] Optionally, in the foregoing aspects, the method further includes: applying an output signal and a second output signal to a first terminal and a second terminal of a first coil of an inductive coupler, respectively; receiving and amplifying the output from a second coil of the inductive coupler, the second coil being inductively coupled to the first coil; and transmitting the amplified output.

[0021] Optionally, in any of the foregoing aspects of the method of transmitting a signal, the method further includes: receiving an input signal in an in-phase / quadrature format; and generating N input signals forming an N-phase input signal and an inverted input signal for each of the N input signals based on the input signal.

[0022] Optionally, in any of the foregoing aspects of the method of transmitting the signal, the method further includes: generating the positive oscillator signal and the negative oscillator signal by a voltage-controlled oscillator configured to generate the positive oscillator signal and the negative oscillator signal; and generating N clock signals forming an N-phase clock signal and an inverted clock signal for each of the N clock signals based on the positive oscillator signal and the negative oscillator signal.

[0023] Optionally, in the foregoing aspect, the voltage-controlled oscillator generates a positive oscillator signal and a negative oscillator signal with a frequency that is 1 / 2N times the frequency of the N-phase clock signal.

[0024] Optionally, in either of the two aspects mentioned above: N equals 3, and the method further includes generating N clock signals with a duty cycle of 1 / 2 and generating an inverted clock signal with a duty cycle of 1 / 2; or alternatively, N equals 4, and the method further includes generating N clock signals with a duty cycle of 1 / 3 and generating an inverted clock signal with a duty cycle of 2 / 3.

[0025] According to another aspect of this disclosure, the receiver includes: a frequency synthesizer configured to generate N clock signals forming an N-phase clock signal and an inverted clock signal for each of the N clock signals, wherein N is an integer greater than 2; and a harmonic suppression mixer. The harmonic suppression mixer includes a first group of N mixer pairs configured to: receive an input signal, receive an N-phase clock signal and an inverted version of the N-phase clock signal, and generate N first output signals forming an N-phase output signal and an inverted output signal for each of the N first output signals, each of the N first output signals having a phase corresponding to one of the N clock signals. The first group includes: a first mixer configured to receive the input signal and a corresponding clock signal and mix the input signal with the corresponding clock signal to generate a corresponding first output signal; and a second mixer configured to receive the input signal and an inverted clock signal of the corresponding clock signal and mix the input signal with the inverted clock signal of the corresponding clock signal to generate an inverted output signal of the corresponding first output signal.

[0026] Optionally, in the foregoing aspects, the receiver further includes an N-phase to quadrature converter configured to receive the N-phase output signal and convert the N-phase output signal into an in-phase / quadrature format.

[0027] Optionally, in any of the foregoing aspects of the receiver, the receiver further includes N amplifiers, each of which is configured to: receive and amplify the input signal; and supply the amplified input signal to a corresponding mixer pair in the mixer pair.

[0028] Optionally, in any of the foregoing aspects of the receiver, the harmonic suppression mixer further includes a second set of N mixer pairs, the second set of N mixer pairs being configured to: receive an input signal, receive an N-phase clock signal and an inverted N-phase clock signal, and generate N second output signals forming an N-phase output signal and an inverted output signal for each of the N second output signals, each of the N second output signals having a phase corresponding to one of the N clock signals, the second set including: a first mixer configured to receive the input signal and an inverted clock signal of a corresponding clock signal and mix the input signal with the inverted clock signal of the corresponding clock signal to generate a corresponding second output signal; and a second mixer configured to receive the input signal and a corresponding clock signal and mix the input signal with the corresponding clock signal to generate an inverted output signal of the corresponding second output signal.

[0029] Optionally, in any of the foregoing aspects of the receiver, the receiver further includes an antenna configured to receive input signals.

[0030] Optionally, in any of the foregoing aspects of the receiver, the frequency synthesizer includes: a voltage-controlled oscillator configured to generate a positive oscillator signal and a negative oscillator signal; and a local oscillator clock generator configured to generate N clock signals forming an N-phase clock signal and an inverted clock signal for each of the N clock signals based on the positive oscillator signal and the negative oscillator signal.

[0031] Optionally, in the foregoing aspect, the voltage-controlled oscillator is configured to generate a positive oscillator signal and a negative oscillator signal with a frequency that is 1 / 2N times the frequency of the N-phase clock signal.

[0032] Alternatively, in any of the aforementioned aspects of the receiver, N equals 3.

[0033] Optionally, in the foregoing aspect, the frequency synthesizer is configured to generate N clock signals with a duty cycle of 1 / 2 and to generate an inverted clock signal with a duty cycle of 1 / 2.

[0034] Alternatively, in any of the aforementioned aspects of the receiver, N equals 4.

[0035] Optionally, in the foregoing aspect, the frequency synthesizer is configured to generate N clock signals with a duty cycle of 1 / 3 and to generate an inverted clock signal with a duty cycle of 2 / 3.

[0036] According to another aspect of this disclosure, a method for receiving a signal is provided, the method comprising: receiving an input signal; receiving N clock signals forming an N-phase clock signal and an inverted clock signal for each of the N clock signals, wherein N is an integer greater than 2; and generating N first output signals forming an N-phase first output signal and an inverted output signal for each of the N first output signals by means of the input signal and the inversion of the N-phase clock signals and the N-phase clock signals, each of the N first output signals having a phase corresponding to one of the clock signals: in a first mixer of each of the N first mixer pairs, mixing the input signal with a corresponding clock signal to generate a corresponding first output signal; and in a second mixer of each of the N first mixer pairs, mixing the input signal with an inverted clock signal of a corresponding clock signal to generate an inverted output signal of a corresponding first output signal.

[0037] Optionally, in the foregoing aspects of the method of receiving signals, the method further includes converting the N-phase first output signal into an in-phase / quadrature format.

[0038] Optionally, in any of the foregoing aspects of the method of receiving a signal, the method further includes: amplifying the input signal in each of the N amplifiers; and supplying the amplified input signal from each of the N amplifiers to a corresponding first mixer pair in the first mixer pair.

[0039] Optionally, in any of the foregoing aspects of the method of receiving a signal, the method further includes: generating N second output signals forming a second N-phase output signal and an inverted output signal for each of the N second output signals by the following operations based on the input signal and based on the N-phase clock signal and the inversion of the N-phase clock signal, each of the N second output signals having a phase corresponding to one of the clock signals: in the first mixer of each of the N second mixer pairs, mixing the input signal with a corresponding inverted clock signal of one of the clock signals to generate a corresponding second output signal among the second output signals; and in the second mixer of each of the N second mixer pairs, mixing the input signal with a corresponding clock signal among the clock signals to generate an inverted output signal of the corresponding second output signal among the second output signals.

[0040] Optionally, in any of the foregoing aspects of the method of receiving signals, the method further includes: generating positive oscillator signals and negative oscillator signals by a voltage-controlled oscillator configured to generate positive oscillator signals and negative oscillator signals; and generating N clock signals forming an N-phase clock signal and an inverted clock signal for each of the N clock signals based on the positive oscillator signals and negative oscillator signals.

[0041] Alternatively, in the aforementioned aspects of the method for receiving signals, the voltage-controlled oscillator generates a positive oscillator signal and a negative oscillator signal with a frequency that is 1 / 2N times the frequency of the N-phase clock signal.

[0042] Optionally, in either of the two aspects of the method of receiving signals, N equals 3, and the method further includes generating N clock signals with a duty cycle of 1 / 2 and generating an inverted clock signal with a duty cycle of 1 / 2; or alternatively, N equals 4, and the method further includes generating N clock signals with a duty cycle of 1 / 3 and generating an inverted clock signal with a duty cycle of 2 / 3.

[0043] The present invention is provided to introduce, in a simplified form, a series of concepts further described in the detailed embodiments below. The present invention is not intended to identify key or essential features of the claimed subject matter, nor is it intended to be used as an aid in determining the scope of the claimed subject matter. The claimed subject matter is not limited to implementations that address any or all of the shortcomings mentioned in the background art. Attached Figure Description

[0044] Various aspects of this disclosure are shown by way of example and are not limited to the accompanying drawings, in which similar reference numerals indicate elements.

[0045] Figure 1 A wireless network used for transmitting data is shown.

[0046] Figure 2 It can be used for, for example Figure 1 A block diagram of a wireless communication system in a network.

[0047] Figure 3 This is a block diagram of a first embodiment of the transmitter, illustrating improved harmonic suppression with duty cycle control.

[0048] Figure 4 It is shown Figure 3 A diagram illustrating a six-phase implementation of the LO clock in the proposed implementation.

[0049] Figure 5 It shows Figure 3 Simulation results of the performance of the power amplifier in the implementation method.

[0050] Figure 6 It is shown as follows Figure 3 A flowchart of the first embodiment of the operation of the transceiver in the implementation method.

[0051] Figure 7 This is an implementation of a four-phase transmitter system using harmonic suppression with duty cycle control.

[0052] Figure 8 yes Figure 7 The spectrum at the output of the power amplifier in the embodiment.

[0053] Figure 9 This is a block diagram illustrating an implementation of a three-phase receiver system that suppresses blocking at or near the second, third, and fourth clock harmonics.

[0054] Figure 10 It is shown as follows Figure 9 A flowchart illustrating the implementation of the receiver's operation in the proposed implementation. Detailed Implementation

[0055] This disclosure will now be described with reference to the accompanying drawings. The disclosure generally relates to techniques for reducing unwanted harmonic content from transmitters and receivers. An embodiment of an N-phase transmitter and receiver is presented, which can generate a local oscillator clock signal from a voltage-controlled oscillator operating at a frequency 1 / 2N times the local oscillator frequency, and can reduce unwanted harmonics to a level typically required when the voltage-controlled oscillator operates at N times (or higher) the local oscillator frequency by using duty cycle control of the local oscillator clock signal. In the following architecture, an N-phase clock signal and its inverted components are generated, and these clock signals are mixed with an N-phase input signal and its inverted components. Unlike typical mixer configurations, each component of the input signal and its inverted phase are mixed in pairs with the corresponding phase and its inverted phase of the clock signal, and these pairs are combined and amplified individually. For example, in a three-phase implementation, the duty cycle of all components of the N-phase clock signal (and their inverse components) is 50%, thereby suppressing unwanted second harmonics, which would have required a six-phase clock signal in previous implementations.

[0056] It should be understood that embodiments of this disclosure can be implemented in many different forms, and the scope of the claims should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the inventive concept to those skilled in the art. In fact, this disclosure is intended to cover alternatives, modifications, and equivalents to these embodiments included within the scope and spirit of this disclosure as defined by the appended claims. Furthermore, numerous specific details are set forth in the following detailed description of the present embodiments of this disclosure in order to provide a thorough understanding. However, it will be apparent to those skilled in the art that embodiments of this disclosure can be practiced without such specific details.

[0057] Figure 1 A wireless network for transmitting data is shown. Communication system 10 includes, for example, user equipment 11A to 11C, radio access networks (RANs) 12A to 12B, a core network 13, a public switched telephone network (PSTN) 14, the Internet 15, and other networks 16. Additional or alternative networks include private packet networks and public packet networks, including corporate intranets. Although a specific number of these components or elements are shown in the figure, system 10 may include any number of these components or elements.

[0058] In one implementation, the wireless network may be a fifth-generation (5G) network, comprising at least one 5G base station employing orthogonal frequency-division multiplexing (OFDM) and / or non-OFDM with a transmission time interval (TTI) of less than 1 millisecond (ms) (e.g., 100 microseconds or 200 microseconds) to communicate with the communication device. Typically, the reference to a base station can refer to either an eNB or a 5G base station (gNB). Furthermore, the network may also include a network server for processing information received from the communication device via at least one eNB or gNB base station.

[0059] System 10 enables multiple wireless users to send and receive data and other content. System 10 can implement one or more channel access methods, such as, but not limited to, code division multiple access (CDMA), time division multiple access (TDMA), frequency division multiple access (FDMA), orthogonal FDMA (OFDMA), or single-carrier FDMA (SC-FDMA).

[0060] User equipment (UE) 11A to 11C are configured to operate and / or communicate in system 10. For example, UE 11A to 11C are configured to transmit and / or receive wireless or wired signals. Each UE 11A to 11C represents any suitable end-user device and may include (or be referred to as) devices such as: user equipment / device, wireless transmit / receive unit (UE), mobile station, fixed or mobile subscriber unit, pager, cellular phone, personal digital assistant (PDA), smartphone, laptop computer, computer, touchpad, wireless sensor, wearable device, or consumer electronics device.

[0061] In the depicted implementation, RAN 12A to RAN 12B each include one or more base stations 17A, 17B (collectively referred to as base stations 17). Each of the base stations 17 is configured to radio interface with one or more UEs 11A, 11B, 11C to access the core network 13, PSTN 14, Internet 15, and / or other networks 16. For example, base station (BS) 17 may include one or more of the following known devices: such as a base transceiver station (BTS) with wired or wireless networks, a Node B (NodeB), an evolved Node B (eNB), a next (fifth) generation (5G) Node B (gNB), a home Node B, a home eNode B, a site controller, an access point (AP) or wireless router, or a server, router, switch, or other processing entity.

[0062] In one implementation, base station 17A forms part of RAN 12A, which may include other base stations, elements, and / or devices. Similarly, base station 17B forms part of RAN 12B, which may include other base stations, elements, and / or devices. Each of the base stations 17 operates to transmit and / or receive radio signals within a specific geographical area or region (sometimes referred to as a "cell"). In some implementations, multiple-input multiple-output (MIMO) technology with multiple transceivers may be employed for each cell.

[0063] Base station 17 communicates with one or more user equipment 11A to 11C via one or more air interfaces (not shown) using wireless communication links. The air interfaces can utilize any suitable radio access technology.

[0064] It is conceivable that system 10 may use multi-channel access capabilities, including, for example, schemes in which base station 17 and user equipment 11A to 11C are configured to implement Long Term Evolution (LTE), LTE Advanced (LTE-A), and / or LTE Multimedia Broadcast Multicast Service (MBMS). In other embodiments, base station 17 and user equipment 11A to 11C are configured to implement UMTS, HSPA, or HSPA+ standards and protocols. Of course, other multiple access schemes and radio protocols may be utilized.

[0065] RANs 12A to RAN 12B communicate with core network 13 to provide voice, data, application, Voice over Internet Protocol (VoIP), or other services to user equipment 11A to 11C. As understood, RANs 12A to RAN 12B and / or core network 13 can communicate directly or indirectly with one or more other RANs (not shown). Core network 13 can also serve as a gateway access for other networks (e.g., PSTN 14, Internet 15, and other networks 16). Furthermore, some or all of user equipment 11A to 11C may include functionality for communicating with different wireless networks via different wireless links using different wireless technologies and / or protocols.

[0066] RAN 12A to RAN 12B may also include millimeter and / or micrometer wave access points (APs). An AP may be part of base station 17 or may be located remotely from base station 17. An AP may include, but is not limited to, a base station 17 capable of mmW communication (e.g., an mmW base station) or a connection point (mmW CP). An mmW AP may transmit and receive signals in a frequency range, for example, from 24 GHz to 100 GHz, but is not required to operate across that entire range. As used herein, the term "base station" is used to refer to a base station and / or a wireless access point.

[0067] although Figure 1 An example of a communication system is shown, but it is possible to... Figure 1 Various modifications can be made. For example, the communication system 10 may include any number of user equipment, base stations, networks, or other components of any suitable configuration. It should also be understood that the term "user equipment" can refer to any type of wireless device that communicates with a radio network node in a cellular or mobile communication system. Non-limiting examples of user equipment are target devices, device-to-device (D2D) user equipment, machine-type user equipment or user equipment capable of machine-to-machine (M2M) communication, laptop computers, PDAs, iPads, tablet computers, mobile terminals, smartphones, laptop embedded equipped (LEE), laptop mounted equipment (LME), and USB dongles.

[0068] Figure 2 This is a block diagram of a wireless communication system 100, such as a mobile phone or user equipment 11A to 11C or a base station 17, showing some of the elements discussed below. To transmit an output signal from the circuitry of processor 111, transmitter (Tx) RF / analog section 101 upconverts the output signal from the intermediate frequency (IF) range to the radio frequency (RF) range, amplifies and filters the output signal, and may perform other processing before supplying the transmitted signal to antenna 105. The output signal is in in-phase / quadrature (I / Q) format as in-phase and quadrature signals I generated by Tx digital baseband block 107. Tx and Q Tx Provided to the Tx RF / analog section 101. Although the Tx digital baseband block 107 is in Figure 2These elements are shown as separate blocks from the Tx RF / analog section 101, but according to implementations, these elements may be combined differently as circuit elements and implemented in hardware, firmware, software, or a combination thereof.

[0069] The signal is received by antenna 105 and supplied to receiver (Rx) RF / analog section 102. Before passing the signal to other components on the device represented by processor 111, Rx section 102 performs any necessary or desired signal processing, such as downsampling from the radio frequency (RF) range to the intermediate frequency (IF) range and filtering. Figure 2 In this implementation, the output of the Rx RF / analog section 102 is in I / Q format, and the Rx digital baseband section 117 converts this output into a receive signal supplied to the processor. Although the Rx digital baseband section 117... Figure 2 These elements are shown as a separate block from the Rx RF / analog section 102, but according to embodiments, these elements can be combined differently as circuit elements and implemented in hardware, firmware, software, or a combination thereof. Furthermore, although... Figure 2 The Tx RF / analog section 101 and Rx RF / analog section 102 are represented as separate elements, but depending on the implementation, the transmitter path and receiver path may share many elements or be implemented as a combined transceiver. In the following text, "transceiver" can generally be used to refer to a combined transmitter / receiver, separate transmitter and receiver sections, or an implementation that shares one or more components (e.g., a local oscillator) between the transmitter and receiver.

[0070] In transceivers such as mobile phones, there are often unwanted clock harmonics generated from a local oscillator. On the transmitter side, these clock harmonics can be non-linearly mixed back to frequencies close to the desired signal, producing near-channel distortion (e.g., CIM2, CIM3, CIM5, where CIMx is the x-th order counter intermodulation) and also affecting other nearby wireless terminals using near carrier frequencies. On the receiver side, a blocking signal close to the desired signal clock harmonic frequency can be used, but when this blocking signal is mixed back to the baseband frequency, it can fall on top of the desired signal frequency during downconversion and degrade the received signal.

[0071] Typically, some of these unwanted harmonics can be removed through multiphase (N-phase) mixer design with appropriate selection of N, where a higher N value removes more harmonics. Therefore, a high N value is preferred for harmonic suppression. However, for N-phase mixer design, a high N value requires the oscillator (e.g., a voltage-controlled oscillator or VCO) to operate at a high frequency. (Typically, the minimum VCO frequency is f...) LO *N / 2, where f LO(This is the local oscillator carrier frequency.) This leads to high power consumption in the VCO and makes VCO design challenging.

[0072] The following describes an implementation of a Harmonic Rejection Mixer (HRM) that can operate at a lower N value, thereby reducing VCO frequency requirements while suppressing more harmonics than a conventional N-phase HRM.

[0073] To transmit quadrature IQ signals (in-phase / quadrature or IQ format signals), a minimum value of N=3 is used, i.e., a three-phase system. To minimize the VCO frequency as much as possible, the first set of implementations uses a three-phase transmitter system as an example to demonstrate aspects of the concepts presented in the following discussion.

[0074] To generate three phases in a standard three-phase system, the VCO clock needs to operate at at least 1.5 times the local oscillator (LO) clock rate, utilizing both the rising and falling edges of the VCO signal. For example, if the carrier frequency is 7.15 GHz, the VCO frequency needs to be at least 7.15 * 1.5 = 10.725 GHz. In practice, lower harmonics (e.g., second and third harmonics) are more critical than higher harmonics in terms of which harmonics should be suppressed. Although three-phase systems are efficient, typical three-phase implementations do not suppress even-order LO clock harmonics such as the strong second harmonic. This even-order clock harmonic will be nonlinearly mixed back to near the desired transmitter signal frequency by an even-order post-mixer, ultimately producing CIM2 and CIM4. The implementation presented here adjusts the duty cycle of the LO clock so that the transceiver can suppress more clock harmonics.

[0075] More specifically, in the first set of embodiments, for the three-phase system example, the VCO is allowed to operate at 1.5X while suppressing harmonics associated with the second, third, and fourth order LO clocks. This can provide similar clock harmonic performance to a six-phase system (corresponding to N=6, and requiring the VCO to operate at 3X), but at half the VCO frequency. Figure 3 This is a block diagram of such an implementation method.

[0076] Figure 3 This is a block diagram of a first embodiment of the transmitter, illustrating improved harmonic suppression using duty cycle control. Considering at a higher level... Figure 3 IQ Source 107—it can Figure 2The Tx digital baseband block 107 internally generates the signal to be transmitted. The signal from the IQ source 107 is in I / Q format and is converted into a three-phase signal as described below. The components of this three-phase signal provide the source signal in analog three-phase format to the harmonic suppression block HRM 200. The frequency synthesizer 230 supplies a set of clock signals to the HRM 200. The output of the HRM 200 is supplied to the antenna 105 through a set of variable gain amplifiers VGA 221-i and VGA 223-i, an inductive coupler 251, a power amplifier PA 253, and a filter 255.

[0077] In this embodiment, within the frequency synthesizer 230 block, the VCO 231 generates a differential output of positive output p and negative output n at a frequency of 1.5 times the local oscillator frequency, i.e., fVCO = 1.5 * fLO. The duty cycle adjustment block 233 adjusts the duty cycle of the VCO signal so that the LO clock generation block 235 can generate an LO clock with a 1 / 2 (50%) duty cycle, instead of the conventional 1 / 3 (33%) duty cycle. (It should be understood that in actual circuits, for example, a clock signal generated with a 50% duty cycle will actually differ slightly from this nominal value: for example, see below...) Figure 5 The waveform shown illustrates an example of an actual signal with a duty cycle of 49.7878%. For the output of the LO clock generation block 235, the final LO signal is a three-phase signal clk0, clk120, and clk240, along with complementary LO clock signals clk0b, clk120b, and clk240b. These three-phase signals and the complementary LO clock signals are also generated with a 50% duty cycle.

[0078] Calculating all three phases with a final LO clock duty cycle of 50%, the output of frequency synthesizer 230 is an overlapping LO clock system. For typical passive mixer designs used in cellular applications, these overlapping clock signals introduce crosstalk, which is undesirable. To address this issue, the architecture of the proposed implementation uses a segmented variable gain amplifier (VGA), grouping the mixer into different segments of each segmented VGA, and grouping these components such that each segment has no LO clock overlap. The summation of the different segments occurs at the output of the VGA. Figure 3 As shown, in a two-ended differential implementation, this technique can be applied to both the positive side (p side) and the negative side (n side).

[0079] The three p-side intermediate outputs of the HRM 200 each lead to one of the corresponding VGAs 221-1, VGA 221-2, or VGA 221-3. The input to each of these VGAs is a combined output from a pair of mixers receiving the LO clock signal and one of its inverted phases: the input to VGA 221-1 is a combined output from mixer 201 receiving clk0 and mixer 202 receiving clk0b, which generates the first p-side intermediate output; the input to VGA 221-2 is a combined output from mixer 203 receiving clk120 and mixer 204 receiving clk120b, which generates the second p-side intermediate output; and the input to VGA 221-3 is a combined output from mixer 205 receiving clk240 and mixer 206 receiving clk240b, which generates the third p-side intermediate output. (As in...) Figure 3 Each of these mixers, as described above, has a 50% duty cycle for each of these LO signals. Although each LO signal and its inverting phase have a 50% duty cycle, the mixers are paired so that the LO signals in each pair are complementary and do not overlap.

[0080] A similar arrangement is used on the n-side intermediate outputs of the HRM 200, with each of the n-side intermediate outputs of the HRM 200 leading to one of the corresponding VGA 223-1, VGA 223-2, or VGA 223-3. The inputs of each of these VGAs are the combined outputs of a pair of mixers that receive the LO clock signal and one of its inverted phases: VGA223-1's input is the combined output of mixer 211 receiving clk0 and mixer 212 receiving clk0b, which is used to generate a first n-side intermediate output; VGA 223-2's input is the combined output of mixer 213 receiving clk120 and mixer 214 receiving clk120b, which is used to generate a second n-side intermediate output; and VGA 223-3's input is the combined output of mixer 215 receiving clk240 and mixer 216 receiving clk240b, which is used to generate a third n-side intermediate output. As described above again for each of these mixers, each of these LO signals has a 50% duty cycle.

[0081] Each segment path within the HRM 200 uses complementary signals (i.e., clk0 and clk0b pairs, clk120 and clk120b pairs, clk240 and clk240b pairs) such that the sum of the non-overlapping clock duty cycles in each segment is 100%. For example, in the first segment of mixers 201 and 202, which are combined to provide input to the VGA 221-1, clk0 and clk0b are non-overlapping, each having a 50% duty cycle, so the total duty cycle between them is 100%. With the clocks completely non-overlapping at 100%, the mixer's on / off state can be performed correctly, allowing the baseband IQ signal to be correctly sampled by the LO clock.

[0082] Figure 4 It is shown Figure 3 The schematic diagram illustrates a six-phase implementation of the LO clock in the embodiment, namely clk0 / clk120 / clk240 / clk0b / clk120b / clk240b from the LO clock generation block 235. As can be seen, the components of the three-phase LO signals clk0 / clk120 / clk240 overlap. However, the clk0 / clk0b pair, the clk120 / clk120b pair, and the clk240 / clk240b pair do not overlap.

[0083] Return to Figure 3 In the signal path, the IQ data from IQ source 107 is digitally converted into three-phase baseband signals (0, 120, 240) in conversion block 243. Then, three digital-to-analog converters (DACs) DAC_0 245-1, DAC_120 245-2, and DAC_240 245-3 convert the three-phase digital signals into analog signals. These analog signals are then filtered by low-pass filters (LPFs) LPF_0 247-1, LPF_120 247-2, and LPF_240 247-3 to remove unwanted distortion and noise. Typically, the DACs and LPFs are differential circuits relatively unaffected by other noise sources within the transceiver. This means that, in addition to the 0, 120, and 240 signals, complementary signals (180, 300, 60) are also created and provided to HRM 200. Components 107, 243, 245-1, 245-2, 245-3, 247-1, 247-2, and 247-3 together form an N=3 phase signal source 241.

[0084] The Harmonic Rejection Mixer (HRM) 200 combines the output of the LPF with the LO clock to generate the RF output. For example... Figure 3As shown, on the p side, the 0 output and 180 output from LPF 247-1 are mixed with clk0 at mixer 201 and with clk0b at mixer 202, respectively; the 120 output and 300 output from LPF 247-2 are mixed with clk120 at mixer 203 and with clk120b at mixer 204, respectively; and the 240 output and 60 output from LPF 247-3 are mixed with clk240 at mixer 205 and with clk240b at mixer 206, respectively. The n-side is similarly configured, but the outputs from each of the LPFs are swapped: the 180 and 0 outputs from LPF 247-1 are mixed with clk0 at mixer 211 and with clk0b at mixer 212, respectively; the 300 and 120 outputs from LPF 247-2 are mixed with clk120 at mixer 213 and with clk120b at mixer 214, respectively; and the 60 and 240 outputs from LPF 247-3 are mixed with clk240 at mixer 215 and with clk240b at mixer 216, respectively.

[0085] The RF output from the p-side mixer is amplified by VGA 221-1, VGA 221-2, and VGA 221-3 and combined to provide the p-side output signal from HRM 200. Similarly, the RF output from the n-side mixer is amplified by VGA 223-1, VGA 223-2, and VGA 223-3 and combined to provide the n-side output signal from HRM 200. To convert the RF output from the VGAs to a single-ended output, an inductive coupler 251 can be used, wherein the combined p-side output and the combined n-side output are connected across the first coil of the inductive coupler 251, and one side of the second coil of the inductive coupler 251 is grounded and the other side provides a single-ended signal at the output. Power amplifier PA 253 amplifies the single-ended output, and the PA output is filtered by RF filter 255 to remove unwanted distortion. Finally, the filtered RF output is fed to antenna 105.

[0086] Figure 5 It shows Figure 3 Simulation results of the output performance of the power amplifier according to the implementation method. More specifically, Figure 5 The graph, plotted in decibels (dB), shows the output of the three-phase power amplifier as a function of frequency, normalized to achieve the desired transmitter (Tx) signal at 0 dB. Figure 5 In the curve graph, for the purpose of rapid simulation, the desired signal frequency (approximately 1.2288 x 10⁻⁶) is... 8The frequency (Hz) was chosen to be lower than the actual target RF frequency. In the simulation, the duty cycle was taken as 49.7878%, instead of exactly 50%, to represent what might occur in a real-world implementation. Figure 3 The circuit exhibited less-than-ideal operation. In addition to the expected Tx signal, at slightly lower frequencies, the peak value dropped by approximately -60 dB due to LO leakage, while the peak value dropped by more than -80 dB due to image distortion.

[0087] Regarding harmonics, and for second-order anti-intermodulation, Figure 5 The peak value on the positive side CIM2p decreased by -80 dB, and the peak value on the negative side CIM2n decreased by approximately -70 dB. CIM2 decreases further if the duty cycle approaches 50%. There is no third-order CIM3 peak, and the only other significant spike is with respect to CIM5, which decreases by approximately -100 dB. Therefore, Figure 5 The simulation results show that: VGA structure with LO clock duty cycle adjustment and segmentation Figure 3 The output performance of the power amplifier PA 253, based on a three-phase HRM architecture, achieves harmonic suppression comparable to that of a standard six-phase HRM. The system's spectrum shows that all CIM distortion levels are sufficiently low for cellular applications.

[0088] Figure 6 It is shown as follows Figure 3 A flowchart of the first embodiment of the transceiver operation in the implementation is provided. At 601, the HRM receives N components of an N-phase input signal and the inversion of these input signals. Figure 3 In the three-phase implementation, this includes the components of the three-phase input signals (0, 120, 240) and the inversions of these input signals (180, 300, 60). Figure 3 In this implementation, these signals are generated from the I / Q signals of the IQ source 107 by the three-phase converter block, DAC 245-1, DAC 245-2, DAC 245-3 and LPF247-1, LPF 247-2, LPF 247-3.

[0089] At position 603, frequency synthesizer 230 generates an LO clock signal, and HRM 200 receives this LO clock signal. The LO clock signal comprises N components of an N-phase clock signal and inverted clock signals of these N components. Figure 3 In the three-phase implementation, these LO clock signals are clock signals Clk0, Clk120, and Clk240, and their inverses Clk0b, Clk120b, and Clk240b, all of which have a 1 / 2 (50%) duty cycle. Although Figure 6The flowchart presents its elements in a specific order, but it should be understood that these elements can be executed simultaneously (i.e., 601, 603, and subsequent elements are all executed concurrently) to achieve the desired effect. Figure 3 The circuit generates an output signal while transmitting.

[0090] At position 605, for each N-phase input signal, the input signal is mixed with the corresponding clock signal. For example, in Figure 3 In the implementation, on the p-side of the HRM 200, the input signal components (0, 120, 240) are mixed with the three-phase components (clk0, clk120, clk240) in mixers 201, 203, and 205, respectively. For Figure 3 In the dual-ended implementation, the inverted input signal components (180, 300, 60) are mixed with (clk0, clk120, clk240) in mixers 211, 213 and 215, respectively.

[0091] At position 607, for each N-phase input signal, the inverted component of the N-phase input signal is mixed with the inverted component of the corresponding clock signal. For example, in Figure 3 In the implementation, on the p-side of the HRM 200, the input signal components (180, 300, 60) are mixed with (clk0b, clk120b, clk240b) in mixers 202, 204, and 206, respectively. For Figure 3 In the dual-ended implementation, the inverted (i.e., the component itself) (0, 120, 240) of the inverted input signal component is mixed with (clk0b, clk120b, clk240b) in mixers 212, 214 and 216, respectively.

[0092] At position 609, for each of the N-phase input signal components, the mixing signal pairs from 605 and 607 are combined to form a set of N intermediate outputs. Figure 3 In the three-phase implementation, this corresponds to combining the outputs of mixers (201, 202), (203, 204), and (205, 206) to obtain N p-side intermediate outputs. In such a case... Figure 3 In the dual-ended implementation shown, in order to also generate N n-side intermediate outputs, the outputs of the mixer (211, 212), (213, 214) and (215, 216) are combined.

[0093] At position 611, the N intermediate outputs are amplified individually and then combined to provide the output signal. Figure 3In the three-phase implementation, on the p-side, this corresponds to the outputs of mixer pairs (201, 202), (203, 204), and (205, 206) being amplified in the corresponding VGA 221-1, VGA 221-2, and VGA 221-3. These VGA outputs are then combined to provide the p-side output signal for the HRM 200. Figure 6 In the dual-ended implementation, on the n-side, the outputs of mixer pairs (211, 212), (213, 214), and (215, 216) are amplified in corresponding VGA 223-1, VGA 223-2, and VGA 223-3, and then the outputs of these VGAs are combined to provide the output signal on the n-side of the HRM 200.

[0094] Then, the output signal is sent in 613. (As shown in...) Figure 3 In the dual-ended implementation, the p-side output and n-side output are converted into single-ended outputs at the coil of inductive coupler 251. The single-ended output is then amplified in power amplifier PA 253, filtered in filter 255, and then transmitted from antenna 105.

[0095] Figure 7 This is an implementation of a four-phase transmitter system using harmonic suppression with duty cycle control. In a typical four-phase transmitter system, the duty cycle of the non-overlapping clock is 25%. This typical four-phase system suffers from the CIM3 problem due to the presence of the third harmonic in the four-phase system. If the duty cycle of the LO clock is instead adjusted to 1 / 3 (33.33%), the third harmonic will not initially appear in the LO signal, meaning that this improved four-phase system will not have a significant third harmonic and therefore does not involve the major CIM3 problem.

[0096] Figure 7 The implementation method will Figure 3 The circuitry related to the mixer and VGA is extended to a four-phase system. Other components of the transmitter circuitry (LPF, DAC, LO generation) can be derived from the three-phase example discussed earlier, where the LO clock and associated complementary clock are four-phase. In the frequency synthesizer 730, the VCO frequency is N / 2 times the LO frequency, where N is the number of LO clock phases; therefore, for an implementation where N = 4, fVCO = 2 * fLO. Figure 7Also in a two-ended implementation, the p and n outputs of VCO 731 are directed to a duty cycle adjustment block, which gives the p-side component a 1 / 3 duty cycle and the n-side component a complementary 2 / 3 duty cycle. Then, the LO clock generation block 735 generates the N-phase clock signal components Clk0, Clk90, Clk180, and Clk270, each with a 1 / 3 (33.33%) duty cycle, and their inverted counterparts Clk0b, Clk90b, Clk180b, and Clk270b will have a 2 / 3 duty cycle. It should be noted that in this implementation, these inverted phases are not redundant (i.e., Clk0 is different from Clk180b), because these inverted phases have a 66.67% duty cycle. In total, the duty cycle of each LO component and its inverted counterpart combination will be 100%.

[0097] For the four-phase input signal, the signal from IQ source 107 provides the I component to DAC_I 745-1, which in turn provides the dual-ended inputs I and Ib to filter LPF_I 747_1 to filter the in-phase input of HRM 700. The Q component is directed to DAC_Q 745-2, which in turn provides the dual-ended inputs Q and Qb to filter LPF_Q 747_2 to filter the quadrature input of HRM 700. In the four-phase implementation, since I and Ib are 180 degrees out of phase, and Q and Qb are 180 degrees out of phase, these four signals (I, Q, Ib, Qb) together form the four-phase input signal, the inverse of which is (Ib, Qb, I, Q), thus requiring only two DACs and two LPFs. (That is to say, the inversion of the components of the four-phase input signal does not need to be generated separately, but only needs to be reset according to the components of the four-phase input signal.) Components 107, 745-1, 745-2, 747-1 and 747-2 together form N=4 phase signal source 741.

[0098] and Figure 3Similarly, on the p-side of the HRM 700, the four-phase input signals (I, Q, Ib, Qb) are mixed with the corresponding components of the four-phase LO clock signals (Clk0, Clk90, Clk180, Clk270) in mixers 701, 703, 705, and 707, respectively. The inverted phases of the four-phase input signals (Ib, Qb, I, Q) are mixed with the corresponding inverted components of the four-phase LO clock signals (Clk0b, Clk90b, Clk180b, Clk270b) in mixers 702, 704, 706, and 708, respectively. To generate four intermediate p-side outputs, the outputs from mixer pairs (701, 702), (703, 704), (705, 706), and (707, 708) are mixed and amplified in the corresponding VGA 721-1, VGA 721-2, VGA 721-3, and VGA 721-4. The outputs from the p-side VGAs are then combined to generate the p-side outputs.

[0099] On the n-side of the HRM 700, the inverted components (Ib, Qb, I, Q) of the four-phase input signals are mixed with the corresponding components of the four-phase LO clock signals (Clk0, Clk90, Clk180, Clk270) in mixers 711, 713, 715, and 717, respectively. The four-phase input signals (I, Q, Ib, Qb) are mixed with the corresponding inverted components (Clk0b, Clk90b, Clk180b, Clk270b) of the four-phase LO clock signals in mixers 712, 714, 716, and 718, respectively. To generate four intermediate n-side outputs, the outputs from mixer pairs (711, 712), (713, 714), (715, 716), and (717, 718) are mixed and amplified in the corresponding VGA 723-1, VGA 723-2, VGA 723-3, and VGA 723-4. The outputs of the n-side VGAs are then combined to generate the n-side outputs.

[0100] because Figure 7 The implementation is also a two-ended implementation, so the p-side output and n-side output are connected across the first coil of the inductive coupler 751, while the second coil provides a single-ended output to the power amplifier PA 753. The amplified output from PA 753 can then be filtered at 755 and transmitted from antenna 105.

[0101] Figure 8 yes Figure 7 A graph showing the spectrum at the output of the power amplifier PA 753 in the embodiment of the present invention. Figure 8 The curve is set to be similar to Figure 5 The graph shows the frequency in Hz x 10. 8The values ​​are expressed in dB, and the levels are normalized to ensure the desired output is at 0 dB. There is a drop of approximately -80 dB in LO leakage, and CIM distortion exists at the third and fifth harmonics on both the p and n sides. In all cases, the peak value drops by approximately -65 dB for CIM3n, approximately -85 dB for CIM3p, and more than -100 dB for CIM5. The CIM3n and CIM3p peak values ​​are generated by higher harmonics, but their levels are low enough not to cause significant problems in cellular applications.

[0102] Regarding duty cycle adjustment, for example in Figure 3 Block 235 of the implementation method and Figure 7 In block 735, in order to suppress even harmonics (such as in...) Figure 3 In the three-phase example for suppressing the second harmonic, the LO clock duty cycle is set to 50% in the duty cycle adjustment block. Depending on the situation, in the original unadjusted LO clock used in the previous method, the duty cycle would be 33.333% or 66.667%. To suppress the third harmonic (such as...), Figure 7 In the four-phase example, the LO clock duty cycle is set to 33.333% or 66.667%. In the original unadjusted LO clock used in the previous method, the duty cycle is typically 25%.

[0103] The architecture described in the example above allows the duty cycle to be adjusted so that the N-phase HRM can eliminate more harmonics than a standard N-phase HRM with the same N value. To achieve similar performance in reducing clock harmonics, previous implementations required the N-phase system to operate at a higher N value, which translates to a higher VCO frequency. For example, Figure 3 The implementation uses a three-phase system in which the VCO operates at 1.5x the local oscillator frequency, while to achieve similar performance, the existing method would require operation as a six-phase system in which the VCO operates at 3x the local oscillator frequency. Similarly, Figure 7 The implementation can operate with fVCO = 2 * fLO, whereas to achieve similar performance, the previous method would require an eight-phase system with fVCO = 4 * fLO.

[0104] The above is used for transmitters, for example Figure 2 The architecture of the Tx section 101 is also suitable for receivers such as Figure 2 The RX section 102. Much of the discussion above regarding the transmitter case continues into the receiver case. Although discussed separately, the transmitter and receiver implementations can share many components or be implemented in a combined transceiver.

[0105] Figure 9This is a block diagram illustrating an implementation of a three-phase receiver system that suppresses blocking at or near the second, third, and fourth clock harmonics. Roughly speaking, except for the reversed signal path... Figure 9 The overall structure of the receiver implementation method and Figure 3 The transmitter implementation is similar. A four-phase receiver system can be similarly based on... Figure 7 The transmitter implementation is described above. In the receiver implementation presented herein, a segmented low noise amplifier (LNA) is used to avoid overlapping crosstalk.

[0106] More specifically, the frequency synthesizer 930 can be used with Figure 3 The frequency synthesizer 230 has the same or similar structure, wherein the VCO 931, duty cycle adjustment block 933 and LO clock generation block 935 can operate as described above with respect to the corresponding elements 231, 233 and 235.

[0107] because Figure 9 Also a two-ended implementation, the HRM 900 now generates three-phase output signals (0, 120, 240) and their inverted values ​​(180, 300, 60), instead of receiving the inverted signals of the three-phase input signals and their components. The complementary output signal pairs serve as differential inputs to a set of low-pass filters and an analog-to-digital converter. More specifically, the (0, 180) pair is a differential input to the LPF_0947-1, the output of which is then fed to the ADC_0945-1 to give the (single-ended) first (0-degree phase) component of the three-phase output. Similarly, the (120, 300) pair is a differential input to LPF_120 947-2, the output of which is then fed to ADC_120 945-2 to give the (single-ended) second (120-degree phase) component of the three-phase output; and the (240, 60) pair is a differential input to LPF_240 947-3, the output of which is then fed to ADC_240 945-3 to give the (single-ended) third (240-degree phase) component of the three-phase output.

[0108] The input to the HRM 900 comes from segmented LNAs 921-1, LNA 921-2, and LNA 921-3, each of which is connected to receive signals from antenna 105 via RF filter 955. The outputs of each of LNAs 921-1, LNA 921-2, and LNA 921-3 are differential, with each having a p-side output leading to a corresponding pair of p-side mixers in the HRM 900, and an n-side output leading to a corresponding pair of n-side mixers in the HRM 900.

[0109] Within the HRM 900, the p-side output-to-mixer pairs 901 and 902 from the LNA 921-1 mix with Clk0 and Clk0b, respectively, to generate differential output components 0 and 180. The n-side output-to-mixer pairs 911 and 912 from the LNA 921-1 mix with Clk0 and Clk0b, respectively, to generate inverted differential output components 180 and 0. Similarly, the p-side output-to-mixer pairs 903 and 904 from the LNA 921-2 mix with Clk120 and Clk120b, respectively, to generate differential output components 120 and 300. The n-side output-to-mixer pairs 913 and 914 from the LNA 921-2 mix with Clk120 and Clk120b, respectively, to generate inverted differential output components 300 and 120. The p-side output of the LNA 921-3 is directed to mixer pairs 905 and 906 to mix with Clk240 and Clk240b, respectively, to generate differential output components 240 and 60. The n-side output of the LNA 921-3 is directed to mixer pairs 915 and 916 to mix with Clk240 and Clk240b, respectively, to generate inverse differential output components 60 and 240.

[0110] Figure 10 It is shown as follows Figure 9 A flowchart illustrating the operation of the receiver in the implementation scheme. At point 1001, an input signal is received. (Refer to...) Figure 9 In this implementation, the input signal is received by antenna 105 and then passed to segmented LNA 921-1, LNA 921-2 and LNA 921-3. The differential outputs of segmented LNA 921-1, LNA 921-2 and LNA 921-3 are supplied to the p side and n side of HRM900.

[0111] At position 1003, the frequency synthesizer 930 generates the LO clock signal, and the HRM 900 receives this LO clock signal. The LO clock signal consists of N components of an N-phase clock signal and the inverted clock signals of these N components. Figure 9In the three-phase implementation, these LO clock signals are clock signals Clk0, Clk120 and Clk240 and their inverses Clk0b, Clk120b and Clk240b, all of which have a 1 / 2 (50%) duty cycle.

[0112] At position 1005, for each component of the N-phase clock signal, the corresponding input signal from the LNA is mixed with the clock signal to generate the corresponding N-phase output signal. Figure 9 In this implementation, on the p-side, the output of LNA 921-1 is connected to mixer 901, where the output of LNA 921-1 is mixed with Clk0 to provide the 0-phase component of the output signal. Similarly, the p-side output of LNA 921-2 is connected to mixer 903, where the p-side output of LNA 921-2 is mixed with Clk120 to provide the 120-phase component of the output signal; and the p-side output of LNA 921-3 is connected to mixer 905, where the p-side output of LNA 921-3 is mixed with Clk240 to provide the 240-phase component of the output signal. The outputs of mixers 901, 903, and 905 together provide a three-phase output signal.

[0113] At position 1007, for each component of the N-phase clock signal, the corresponding input signal from the LNA is mixed with the inverted clock signal to generate the corresponding inverted N-phase output signal. Figure 9 In this implementation, on the p-side, the output of LNA 921-1 is connected to mixer 902, where the output of LNA 921-1 is mixed with Clk0b to provide a 180° phase component of the inverted output signal. Similarly, the p-side output of LNA 921-2 is connected to mixer 904, where the p-side output of LNA 921-2 is mixed with Clk120b to provide a 300° phase component of the inverted output signal; and the p-side output of LNA 921-3 is connected to mixer 906, where the p-side output of LNA 921-3 is mixed with Clk240b to provide a 60° phase component of the inverted output signal. The outputs of mixers 902, 904, and 906 together provide the inversion of the components of the three-phase output signal.

[0114] For example Figure 9 In the dual-ended implementation, the n-side output of the LNA is also mixed with the N-phase clock signal components and their inverse phase. Figure 9In the implementation, on the n-side, the output of LNA 921-1 is connected to mixer 911, where the output of LNA 921-1 is mixed with Clk0 to provide a 180-phase component of the output signal. Similarly, the n-side output of LNA 921-2 is connected to mixer 913, where the n-side output of LNA 921-2 is mixed with Clk120 to provide a 300-phase component of the output signal; and the n-side output of LNA 921-3 is connected to mixer 915, where the n-side output of LNA 921-3 is mixed with Clk240 to provide a 60-phase component of the output signal. In the differential implementation, the outputs of mixers 911, 913, and 915 together provide an inverted three-phase output signal.

[0115] exist Figure 9 In this implementation, on the n-side, the output of LNA 921-1 also connects to mixer 912, where the output of LNA 921-1 is mixed with Clk0b to provide the 0-phase component of the n-side inverted output signal. Similarly, the n-side output of LNA 921-2 connects to mixer 914, where the n-side output of LNA 921-2 is mixed with Clk120b to provide the 120-phase component of the n-side inverted output signal; and the n-side output of LNA 921-3 connects to mixer 916, where the n-side output of LNA 921-3 is mixed with Clk240b to provide the 240-phase component of the n-side inverted output signal. The outputs of mixers 912, 914, and 916 together provide the three-phase output signal on the n-side.

[0116] As described above, for both receiver and transmitter implementations, the architecture allows for harmonic performance similar to conventional higher N-phase (larger N-value) systems using lower VCO frequencies. Unlike conventional N-phase systems, the LO clocks are overlapping clocks, but are paired in a way that allows for the use of lower N-values.

[0117] The techniques described herein can be implemented using hardware, firmware, software, or a combination thereof. The software or firmware used can be stored on one or more processor-readable storage devices for... Figures 3 to 10The processor-readable storage device may be programmed in one or more blocks to perform the functions described herein. The processor-readable storage device may include computer-readable media, such as volatile and non-volatile media, removable and non-removable media. By way of example and not limitation, the computer-readable medium may include computer-readable storage media and communication media. The computer-readable storage medium may be implemented in any method or technique for storing information such as computer-readable instructions, data structures, program modules, or other data. Examples of computer-readable storage media include RAM, ROM, EEPROM, flash memory or other memory technologies, CD-ROM, digital versatile disks (DVDs) or other optical disc storage devices, magnetic tape, magnetic tape, disk storage devices or other magnetic storage devices, or any other medium that can be used to store desired information and can be accessed by the components described above. One or more computer-readable media do not include propagated, modulated, or transient signals.

[0118] Communication media typically implement computer-readable instructions, data structures, program modules, or other data in propagated, modulated, or transient data signals such as carrier waves or other transmission mechanisms, and include any information delivery medium. The term "modulated data signal" means a signal having one or more characteristics that are set or altered in such a way as to encode information in the signal. By way of example and not limitation, communication media include wired media such as wired networks or direct wired connections, and wireless media such as RF and other wireless media. Any combination of the above media is also included within the scope of computer-readable media.

[0119] In alternative implementations, some or all of the software or firmware may be replaced by dedicated hardware logic components. Examples, but not limited to, illustrative types of hardware logic components that may be used include Field-programmable Gate Arrays (FPGAs), Application-specific Integrated Circuits (ASICs), Application-specific Standard Products (ASSPs), System-on-a-chip systems (SOCs), Complex Programmable Logic Devices (CPLDs), dedicated computers, etc. In one implementation, software implementing one or more implementations (stored on a storage device) is used to program one or more processors. One or more processors may communicate with one or more computer-readable media / storage devices, peripheral devices, and / or communication interfaces.

[0120] It should be understood that this subject matter can be implemented in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided to make the subject matter thorough and complete, and to fully convey the contents of this disclosure to those skilled in the art. In fact, this subject matter is intended to cover alternatives, modifications, and equivalents to these embodiments, which are included within the scope and spirit of the subject matter as defined by the appended claims. Furthermore, numerous specific details are set forth in the following detailed description of this subject matter to provide a thorough understanding of it. However, it will be apparent to those skilled in the art that this subject matter can be practiced without these specific details.

[0121] This document describes aspects of the present disclosure with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the present disclosure. It should be understood that each block in the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via a processor of the computer or other programmable instruction execution apparatus, create mechanisms for implementing the functions / actions specified in the flowchart illustrations and / or one or more block diagram blocks.

[0122] This disclosure has been described for purposes of illustration and description, but it is not intended to be exhaustive or to limit the disclosure to its disclosed form. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of this disclosure. The aspects of the disclosure herein were chosen and described in order to best illustrate the principles and practical applications of this disclosure and to enable others skilled in the art to understand it, thereby adapting various modifications to suit the particular purpose contemplated.

[0123] For the purposes of this document, each process associated with the disclosed technology may be performed sequentially and by one or more computing devices. Each step in the process may be performed by the same or different computing devices used in other steps, and each step need not necessarily be performed by a single computing device.

[0124] Although the subject matter has been described in language specific to structural features and / or methodological actions, it should be understood that the subject matter defined in the appended claims is not necessarily limited to the specific features or actions described above. Rather, the specific features and actions described above are disclosed as exemplary forms for implementing the claims.

Claims

1. A transmitter comprising: N-phase signal sources, where N is an integer greater than 2, the N-phase signal sources configured to provide N input signals forming an N-phase input signal and an inverted input signal for each of the N input signals; a frequency synthesizer configured to generate N clock signals forming an N-phase clock signal and an inverted clock signal for each of the N clock signals, each of the N clock signals having a phase corresponding to one of the N input signals; and a harmonic rejection mixer comprising: a first set of N mixer pairs configured to receive the N-phase input signal and an inversion of the N-phase input signal, to receive the N-phase clock signal and an inversion of the N-phase clock signal, and to generate a first output signal, each mixer pair in the first set comprising: a first mixer configured to receive a respective one of the input signals and a respective one of the clock signals and to mix the respective one of the input signals with the respective one of the clock signals; and a second mixer configured to receive an inverted input signal of the respective one of the input signals and an inverted clock signal of the respective one of the clock signals and to mix the inverted input signal of the respective one of the input signals with the inverted clock signal of the respective one of the clock signals, wherein the harmonic rejection mixer is configured to: form N first intermediate signals by combining, for each mixer pair in the first set, an output of the first mixer with an output of the second mixer, and combine the N first intermediate signals to form the first output signal.

2. The transmitter of claim 1, further comprising: N amplifiers each configured to: receive a respective one of the first intermediate signals; and amplify the respective one of the first intermediate signals prior to combining the N first intermediate signals to form the first output signal.

3. The transmitter of claim 1, the harmonic rejection mixer further comprising: a second set of N mixer pairs configured to receive the N-phase input signal and an inversion of the N-phase input signal, to receive the N-phase clock signal and an inversion of the N-phase clock signal, and to generate a second output signal, each mixer pair in the second set comprising: a first mixer configured to receive a respective one of the input signals and an inversion of a respective one of the clock signals and to mix the respective one of the input signals with the inversion of the respective one of the clock signals; and a second mixer configured to receive an inverted input signal of the respective one of the input signals and an inverted clock signal of the respective one of the clock signals and to mix the inverted input signal of the respective one of the input signals with the inverted clock signal of the respective one of the clock signals. ​ a second mixer configured to receive an inverted input signal of a respective one of the input signals and a respective one of the clock signals and to mix the inverted input signal of the respective one of the input signals and the respective one of the clock signals, wherein the harmonic rejection mixer is configured to: form N second intermediate signals by combining the output of the first mixer with the output of the second mixer for each of the second group of mixers, and combine the N second intermediate signals to form the second output signal.

4. The transmitter of claim 3, further comprising: an inductive coupler comprising: a first coil configured to receive the first output signal at a first terminal and the second output signal at a second terminal; and a second coil inductively coupled to the first coil, the second coil having a first terminal configured to provide a single-ended output of the transmitter and a second terminal connected to ground.

5. The transmitter of claim 4, further comprising: a power amplifier configured to receive and amplify the single-ended output.

6. The transmitter of claim 5, further comprising: an antenna configured to receive and transmit the single-ended output.

7. The transmitter of any one of claims 1 to 6, wherein, the frequency synthesizer comprises: a voltage controlled oscillator configured to generate a positive oscillator signal and a negative oscillator signal; and a local oscillator clock generator configured to generate, from the positive oscillator signal and the negative oscillator signal, the N clock signals forming an N-phase clock signal and the inverted clock signal for each of the N clock signals.

8. The transmitter of claim 7, wherein, the voltage controlled oscillator is configured to generate the positive oscillator signal and the negative oscillator signal at a frequency that is 1 / 2N times a frequency of the N-phase clock signal.

9. The transmitter of any one of claims 1 to 6, wherein: the N-phase signal source is configured to receive input signals in a same phase / quadrature format and to generate therefrom the N input signals forming an N-phase input signal and the inverted input signal for each of the N input signals.

10. The transmitter of any one of claims 1 to 6, wherein, N is equal to 3.

11. The transmitter of claim 10, wherein, the frequency synthesizer is configured to generate the N clock signals at a duty cycle of 1 / 2 and to generate the inverted clock signals at a duty cycle of 1 / 2.

12. The transmitter of any one of claims 1 to 6, wherein, N is equal to 4.

13. The transmitter of claim 12, wherein, the frequency synthesizer is configured to generate the N clock signals at a duty cycle of 1 / 3 and to generate the inverted clock signals at a duty cycle of 2 / 3.

14. A method of transmitting a signal, comprising: receiving N input signals forming an N-phase input signal and an inverted input signal for each of the N input signals; receiving N clock signals forming an N-phase clock signal and an inverted clock signal for each of the N clock signals, each of the N clock signals having a phase corresponding to one of the N input signals; and generating a first output signal according to the N-phase input signals and inverses of the N-phase input signals and according to the N-phase clock signals and inverses of the N-phase clock signals by performing the following operations for each of the N input signals and inverses of the N input signals: mixing the input signal with a respective one of the clock signals, mixing an inverse of the respective one of the input signals with an inverse of the respective one of the clock signals, and combining the mixed respective one of the input signal and clock signal and the mixed respective one of the inverse of the input signal and the inverse of the clock signal to form N first intermediate signals; and combining the N first intermediate signals to form the first output signal.

15. The method of claim 14, further comprising: amplifying the N first intermediate signals prior to combining the N first intermediate signals to form the first output signal.

16. The method of claim 14, further comprising: generating a second output signal according to the N-phase input signals and inverses of the N-phase input signals and according to the N-phase clock signals and inverses of the N-phase clock signals by performing the following operations for each of the N input signals and inverses of the N input signals: mixing the input signal with an inverse of a respective one of the clock signals; mixing an inverse of the respective one of the input signals with the respective one of the clock signals; and combining the mixed respective one of the input signal and the inverse of the clock signal and the mixed respective one of the inverse of the input signal and the clock signal, to form N second intermediate signals; and combining the N second intermediate signals to form the second output signal.

17. The method of claim 16, further comprising: applying the output signal and the second output signal to first and second terminals, respectively, of a first coil of an inductive coupler; receiving and amplifying an output from a second coil of the inductive coupler, the second coil of the inductive coupler being inductively coupled to the first coil; and transmitting the amplified output.

18. The method of any one of claims 14 to 17, wherein: input signals are received in a same phase / quadrature format; and the N input signals forming the N-phase input signals and the inverse input signals for each of the N input signals are generated from the input signals.

19. The method of any one of claims 14 to 17, further comprising: generating positive and negative oscillator signals from a voltage controlled oscillator configured to generate the positive and negative oscillator signals; and generating the N clock signals forming an N-phase clock signal and the inverted clock signals for each of the N clock signals from the positive oscillator signal and the negative oscillator signal.

20. The method of claim 19, wherein, the voltage-controlled oscillator generates the positive oscillator signal and the negative oscillator signal at a frequency that is 1 / 2N times a frequency of the N-phase clock signal.

21. The method of claim 19, wherein, N equals 3, and the method further comprises: generating the N clock signals at a duty cycle of 1 / 2, and generating the inverted clock signals at a duty cycle of 1 / 2.

22. The method of claim 19, wherein, N equals 4, and the method further comprises: generating the N clock signals at a duty cycle of 1 / 3, and generating the inverted clock signals at a duty cycle of 2 / 3.

23. A receiver comprising: a frequency synthesizer configured to generate N clock signals forming an N-phase clock signal and an inverted clock signal for each of the N clock signals, where N is an integer greater than 2; and a harmonic rejection mixer comprising: a first set of N mixer pairs configured to receive an input signal, receive the N-phase clock signal and an inversion of the N-phase clock signal, and generate N first output signals forming an N-phase output signal and an inverted output signal for each of the N first output signals, each of the N first output signals having a phase corresponding to one of the N clock signals, the first set comprising: a first mixer configured to receive the input signal and a respective one of the clock signals and mix the input signal with the respective one of the clock signals to generate a respective one of the first output signals; and a second mixer configured to receive the input signal and an inversion of the respective one of the clock signals and mix the input signal with the inversion of the respective one of the clock signals to generate an inverted output signal of the respective one of the first output signals.

24. The receiver of claim 23, further comprising: an N-phase to quadrature converter configured to receive the N-phase output signal and convert the N-phase output signal to an in-phase / quadrature format.

25. The receiver of claim 23, further comprising: N amplifiers each configured to: receive and amplify the input signal; and supply the amplified input signal to a respective one of the mixer pairs.

26. The receiver of claim 23, the harmonic rejection mixer further comprising: a second set of N mixer pairs configured to receive the input signal, receive the N-phase clock signals and the inverse of the N-phase clock signals, and generate N second output signals forming an N-phase output signal and an inverse output signal for each of the N second output signals, each of the N second output signals having a phase corresponding to one of the N clock signals, the second set comprising: a first mixer configured to receive the input signal and an inverse of a respective one of the clock signals and mix the input signal with the inverse of the respective one of the clock signals to generate a respective one of the second output signals; and a second mixer configured to receive the input signal and the respective one of the clock signals and mix the input signal with the respective one of the clock signals to generate an inverse of the respective one of the second output signals.

27. The receiver of claim 23, further comprising: an antenna configured to receive an input signal.

28. The receiver of claim 23, wherein, the frequency synthesizer comprises: a voltage controlled oscillator configured to generate a positive oscillator signal and a negative oscillator signal; and a local oscillator clock generator configured to generate the N clock signals forming an N-phase clock signal and the inverse clock signals for each of the N clock signals from the positive oscillator signal and the negative oscillator signal.

29. The receiver of claim 28, wherein, the voltage controlled oscillator is configured to generate the positive oscillator signal and the negative oscillator signal at a frequency that is 1 / 2N times a frequency of the N-phase clock signal.

30. The receiver of any one of claims 23 to 29, wherein, N is equal to 3.

31. The receiver of claim 30, wherein, the frequency synthesizer is configured to generate the N clock signals with a duty cycle of 1 / 2, and generate the inverse clock signals with a duty cycle of 1 / 2.

32. The receiver of any one of claims 23 to 29, wherein, N is equal to 4.

33. The receiver of claim 32, wherein, the frequency synthesizer is configured to generate the N clock signals with a duty cycle of 1 / 3, and generate the inverse clock signals with a duty cycle of 2 / 3.

34. A method of receiving a signal, comprising: receiving an input signal; receiving N clock signals forming an N-phase clock signal and an inverse clock signal for each of the N clock signals, where N is an integer greater than 2; and generating N first output signals forming an N-phase first output signal and an inverse output signal for each of the N first output signals from the input signal and from the N-phase clock signal and the inverse of the N-phase clock signal, each of the N first output signals having a phase corresponding to one of the N clock signals, by: mixing, in a first mixer of each of N first mixer pairs, the input signal with a respective one of the clock signals to generate a respective one of the first output signals, and mixing, in a second mixer of each of the N first mixer pairs, the input signal with the respective one of the clock signals to generate the inverse of the respective one of the first output signals. in a second mixer of each of the N pairs of first mixers, mixing the input signal with a respective inverse of one of the clock signals to generate an inverse of a respective one of the first output signals.

35. The method of claim 34, further comprising: converting the N-phase first output signals into in-phase / quadrature format.

36. The method of claim 34, further comprising: amplifying the input signal in each of N amplifiers; and supplying the amplified input signal from each of the N amplifiers to a respective one of the pairs of first mixers.

37. The method of claim 34, further comprising: generating N second output signals forming a second N-phase output signal and an inverse of each of the N second output signals, each of the N second output signals having a phase corresponding to one of the N clock signals, from an input signal and from the N-phase clock signals and inverses of the N-phase clock signals by: in a first mixer of each of N pairs of second mixers, mixing the input signal with a respective inverse of one of the clock signals to generate a respective one of the second output signals, and in a second mixer of each of the N pairs of second mixers, mixing the input signal with a respective one of the clock signals to generate an inverse of a respective one of the second output signals.

38. The method of claim 34, further comprising: generating a positive oscillator signal and a negative oscillator signal from a voltage controlled oscillator configured to generate the positive oscillator signal and the negative oscillator signal; and generating the N clock signals forming the N-phase clock signals and the inverse clock signals for each of the N clock signals from the positive oscillator signal and the negative oscillator signal.

39. The method of claim 38, wherein, the voltage controlled oscillator generates the positive oscillator signal and the negative oscillator signal at a frequency that is 1 / 2N times a frequency of the N-phase clock signals.

40. The method of any one of claims 38-39, wherein, N equals 3, and the method further comprises: generating the N clock signals with a duty cycle of 1 / 2, and generating the inverse clock signals with a duty cycle of 1 / 2.

41. The method of any one of claims 38-39, wherein, N equals 4, and the method further comprises: generating the N clock signals with a duty cycle of 1 / 3, and generating the inverse clock signals with a duty cycle of 2 / 3.

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