A field effect cell culture dish system measurement circuit

Abstract

A field effect cell culture dish system measurement circuit is composed of an amplifier array, an ADC array, a microprocessor, a USB interface, etc. The amplifier array corresponds one-to-one to the sensors of the field effect tube array, the ADC array analog signal input corresponds one-to-one to the amplifier array, and the microprocessor continuously scans the ADC array digital signal output and generates interrupts at a scanning rate of 20kHz. During the interruption, the microprocessor collects all the signals of the amplifier array, and under the control of the clock pulse, converts all the collected data into a serial digital signal sequence and outputs it from the USB interface. The measurement circuit is beneficial in that the action potential of a cell in the cell culture dish is converted into a drain current through the corresponding field effect sensor, and the current is screened out from the sensor array, converted into a voltage for amplification and analog-to-digital conversion, and becomes a digital signal and is transmitted to an external computer, solving the problem of digitalization of cell membrane action potential detection.

Description

Technical Field

[0001] The invention belongs to the field of biological instruments and relates to a field effect cell culture dish system, in particular to a measurement circuit of a cell culture dish system for detecting cell membrane potential. Background Art

[0002] Chinese invention patent 201210282543.8 invented a field effect cell culture dish system, which consists of a cell culture dish body and a measurement circuit. The bottom of the cell culture dish body is made of an N×N field effect tube (FET) sensor array, where N is the number of rows and columns of the sensor array. The cell membrane potential acts as the gate of the field effect tube to control the change of the field effect tube channel resistance, and the field effect tube channel current is the drain-source current of the field effect tube. When the drain potential of the field effect tube is constant, according to Ohm's law, the drain-source current is inversely proportional to the channel resistance. In this way, by detecting the drain-source current of the field effect tube, the channel resistance can be detected, and the change of the cell membrane potential can be detected from the transfer characteristics of the field effect tube. The technical requirements for the measurement circuit of this system are:

[0003] (1) Detect the drain-source current of the field effect tube. When a cell covers a sensor on the sensor array, its cell membrane potential controls the gate potential of the field effect tube sensor, and the measurement circuit detects the change in the drain-source current of the field effect tube;

[0004] (2) When the system is initialized, search for sensors covered with cells. The cells are attached to the wall and dispersed on the field effect tube sensors at the bottom of the culture dish. Some sensors are covered by cells, and some sensors are not covered by cells. The system is initialized to find sensors covered with cells. Cells are randomly distributed, and sensors covered with cells are also randomly distributed. The measurement circuit must search for all field effect tube sensors covered with cells in the sensor array;

[0005] (3) When the system is working, the sensor of interest can be freely selected from the sensor array and the amplifier can be connected to the selected sensor. Among all the sensors covered by cells, the cell membrane potential on some sensors is of interest and some is not. The measurement circuit should be positioned on the sensor of interest, and the amplifier can be freely connected to the selected sensor of interest;

[0006] (4) Lower the temperature at the bottom of the cell culture dish. If all the field effect transistors on the field effect transistor sensor array at the bottom of the cell culture dish are working, the working current will be very large. In this way, the temperature at the bottom of the cell culture dish will rise, which will heat the cells and cause cell death. The measurement circuit only selects a few sensors of interest, and the sensors that are not selected will not have working current, so the temperature of the cell culture dish will not rise.

[0007] The measuring circuit invented by Chinese invention patent 201210282543.8 consists of a power supply, a galvanometer, a reference electrode, an addressing switch and an addressing controller. The ground (GND) end of the addressing switch is connected to the reference electrode on the base of the culture dish body, and the reference electrode is connected to the source of the field effect sensor. The input end of the addressing switch is respectively connected to the drain of each field effect sensor on the sensor array of the culture dish body. The output end and the GND end of the addressing switch are connected in series with the power supply and the galvanometer. The galvanometer consists of a detection resistor and an amplifier, and the detection resistor is connected in parallel with the amplifier. The addressing controller outputs two addressing lines, radial addressing (LON) and latitude addressing (LAT), which are input to the control end of the addressing switch. The number of bits of radial addressing and latitude addressing is 10 bits, and 1024×1024 encoding can be made to meet the selection requirements of 700×700 field effect sensors. At the same time, the output of the 10-bit radial addressing line and the latitude addressing line has only one bit as 1, and the rest are 0. When the addresses of radial addressing and latitude addressing are 1, the corresponding switches are turned on. This measurement circuit only solves the addressing method of selecting one field effect sensor from the field effect tube sensor array, and does not solve the technical methods of field effect tube sensor drain-source current detection, amplification, analog-to-digital conversion, and data serial output.

[0008] The purpose of the present invention is to provide a field effect cell culture dish system measurement circuit to solve the technical methods of field effect tube sensor drain-source current detection, amplification, analog-to-digital conversion, and data series output. Summary of the invention

[0009] A field effect cell culture dish system measurement circuit 5 is composed of an amplifier array 1, an ADC array 2, a microprocessor 3, a USB interface 4, etc. The input of the amplifier array 1 comes from the field effect cell culture dish body 6, the output of the amplifier array 1 is connected to the input of the ADC array 2, the output of the ADC array 2 is connected to the input of the microprocessor 3, the output of the microprocessor 3 is connected to the input of the USB interface 4, and the output of the USB interface 4 is the output of the measurement circuit, which is connected to the computer system PC.

[0010] Amplifier array 1 is an array of N×N amplifiers, each of which is numbered A. ij , i represents the row, the value range is 1≤i≤N; j represents the column, the value range is 1≤j≤N. The field effect tube is numbered as FET ij , i represents the row, the value range is 1≤i≤N; j represents the column, the value range is 1≤j≤N. Amplifier A ij Used to amplify field effect tube FET ij The sensor signal corresponds to the sensor of the field effect tube array one by one. ij The number N can be selected in the range of 10≤N≤700 according to the cell culture dish specifications.

[0011] Amplifier A ij Including operational amplifier OA 11 , resistor R 11 , R 12 , R 13 , R 14 , R 15 , capacitor C 11 , C 12 , C 13 Resistor R 11 Used to convert the sensor drain-source current I D Converted to sensing voltage V 11 , as the galvanometer 14 to detect the sensor drain current I D , R 11 At 1kΩ≤R 11 ≤100kΩ range selection. The amplifier gain is determined by the resistor R 12 , R 13 , R 14 , R 15 OK. When , the amplifier multiple is:

[0012]

[0013] The current I1 will affect I D The detection requires I1<<I D , generally I1 is smaller than I D An order of magnitude, that is, I1<I D / 10. To achieve this requirement, R 12 >>R 11 , generally R 12 Greater than R 11 An order of magnitude, that is, R 12 >10R 11 . Capacitor C 11 It plays a filtering role and improves the amplifier output's ability to resist high-frequency interference. 16 and R 17 A voltage divider is formed to provide a static working potential for the N-type silicon semiconductor substrate 10. Generally, R 16 and R 17 Both are greater than 100KΩ.

[0014] The operational amplifier should use a positive power supply, V DD and negative power supply V SS Power supply, parallel capacitor C 12 , C 13 To improve the stability of power supply. 12 can be 10μF, C 13 It can be 0.1μF.

[0015] ADC array 2 is composed of multiple (n) analog-to-digital converters ADC121, ADC222, ........, ADC n 2n. One ADC is allocated to every 8 amplifiers until the allocation is completed. The data bus of ADC array 2 is: the analog signal input channels AIN0~AIN7 of the first ADC are connected to the outputs of the 1st to 8th amplifiers respectively, and the digital signal output channel DOUT1 is connected to the data bus Out 1 of the microprocessor 3; the analog signal input channels AIN0~AIN7 of the second ADC are connected to the outputs of the 9th to 16th amplifiers respectively, and the digital signal output channel DOUT2 is connected to the data bus Out 2 of the microprocessor 3; ..., the analog signal input channels AIN0~AIN7 of the nth ADC are connected to the outputs of the 8th×(n-1)+1th to the N×Nth amplifiers respectively, and the digital signal output channel DOUTn is connected to the data bus Out n of the microprocessor 3. The control bus of ADC array 2 is: the chip select signal CS, SPI data input signal DIN, shutdown and reset signal PD / RET, SPI clock SCLK, output busy TM_BUSY and other control lines of all ADCs in ADC array 2 are connected in parallel, and are the control bus of ADC array 2.

[0016] The digital power supply and analog power supply of the analog-to-digital converter (ADC) can use a common power supply, and the shutdown and reset signals PD / RET) can be directly connected to the digital power supply. After PD / RET and DVDD are shorted, they can be connected to the digital power supply 3.3V power supply. When the internal temperature information of the chip is not used, TM_BUSY can be left floating.

[0017] The microprocessor 3 is connected to the USB interface 4, and the output of the USB interface 4 is the output of the measurement circuit.

[0018] When the output signal data of each amplifier is 16 bits and the sampling frequency is 20kHz, the SPI clock frequency of microprocessor 3 is at least 20kHz / channel × N × N channels × 16bit. Considering that some instructions will take up a lot of CPU time, the main frequency of microprocessor 3 should be much higher than 32MHz. The clock signal SCLK of all ADCs in ADC array 2 is connected to the same control signal, and the chip select signal CS and SPI data input signal DIN are also connected to the same control signal. In this way, the three control signals make all ADCs act at the same time and remain consistent.

[0019] The control program of microprocessor 3 is as follows: After the program starts, it is initialized first, and then enters the loop body While (1). The program continuously scans each amplifier at a scanning rate of 20kHz. When 20kHz is met, the program interrupts, performs analog-to-digital conversion processing, and saves it in the register in microprocessor 3. The timer regularly interrupts at 20kHz. During the interruption, all signals (N×N channels) in amplifier array 1 are collected once. When controlling the input / output IO port, library functions cannot be used, but the input / output IO port should be controlled by directly controlling the register.

[0020] The interrupt program and its USB communication are as follows: Microprocessor 3 detects serial data on data bus Out1~Out21. The effective data volume of one detection cycle is 16bit / channel×8channel / chip×nchip. In order to improve the operating efficiency of microprocessor 3 and meet the 20kHz sampling of N×N channels, the data collected by microprocessor 3 is the raw data of input / output IO port, which needs some analysis to be converted into real data. The data sent by microprocessor 3 is specified by pointer. Under the control of clock pulse, microprocessor 3 converts all data collected from ADC array 2 into serial digital signal sequence and outputs it from USB interface.

[0021] The present invention is beneficial in that:

[0022] The action potential of a cell in the cell culture dish is converted into a drain current through the corresponding field effect sensor, and the current is screened out from the sensor array, converted into a voltage, amplified and analog-to-digital converted, and transmitted to an external computer as a digital signal, solving the problem of digitalization of cell membrane action potential detection. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Figure 1 It is a measurement circuit structure diagram of a field effect cell culture dish system.

[0024] Figure 2 This is a schematic diagram of the field effect cell culture dish system.

[0025] Figure 3 This is a diagram of the working principle of the cell-field effect sensor.

[0026] Figure 4 It is a schematic diagram of the cell-field effect sensing characteristics and sensing process.

[0027] Figure 5 is a diagram of the amplifier array.

[0028] Figure 6 This is the amplifier schematic.

[0029] Figure 7 It is a diagram of the ADC array.

[0030] Figure 8 It is a diagram of the microprocessor structure.

[0031] Fig. 9 It is the control program block diagram of microprocessor 3.

[0032] Fig.10 It is a data structure diagram. DETAILED DESCRIPTION

[0033] The present invention is described in detail below with reference to the accompanying drawings.

[0034] Embodiment 1:

[0035] See also Figure 1 A field effect cell culture dish system measurement circuit 5 is composed of an amplifier array 1, an ADC array 2, a microprocessor 3, a USB interface 4, etc. The input of the amplifier array 1 comes from the field effect cell culture dish body 6, the output of the amplifier array 1 is connected to the input of the ADC array 2, the output of the ADC array 2 is connected to the input of the microprocessor 3, the output of the microprocessor 3 is connected to the input of the USB interface 4, and the output of the USB interface 4 is the output of the measurement circuit, which is connected to an external computer PC.

[0036] See also Figure 2 The field effect cell culture dish system is composed of a cell culture dish body 6 and a measuring circuit 5. The output of the culture dish body 6 is connected to the input of the measuring circuit 5. The cell culture dish body 6 is composed of a dish base and a dish wall, forming a U-shaped volume body for storing cells and their culture fluid. The dish base is a silicon wafer on which a sensor array 7 and a reference electrode 8 are prepared on an N-type silicon semiconductor substrate. The sensor array 7 includes no more than 700×700 field effect sensors 9, each of which is independent of each other and is used to sense the cell membrane potential. The sensor 9 transmits the sensing signal to the connector at the edge of the dish base through a connecting wire for connection with the measuring circuit 5. The reference electrode 8 is exposed on the surface of the dish base inside the U-shaped volume body as a 0 potential reference point, and is connected to the edge of the dish base for connection with the measuring circuit 5.

[0037] See also Figure 3The field effect sensor 9 is composed of an N-type silicon semiconductor substrate 10, a source 11, a drain 16, and a SiO2 insulating layer 17. It is made by using microelectronic technology on an N-type silicon semiconductor substrate 10 with a low doping concentration and a high resistivity to make two highly doped P-type semiconductor regions, one for the source 11 and the other for the drain 16. Then, a very thin SiO2 insulating layer 17 is grown on the surface of one side of the N-type silicon semiconductor substrate 10. The outer side of the SiO2 insulating layer 17 can be in contact with the cell fluid and is suitable for the culture of adherent cells 19. The other side of the N-type silicon semiconductor substrate 10 is connected to the edge of the dish base with metal wires in the two P-type semiconductor regions for cell membrane potential output.

[0038] The working principle of the cell field effect sensor 9 is as follows:

[0039] The cell 19 grows on the surface of the SiO2 insulating layer 17 and is immersed in the cell culture medium 18. When the cell 19 is in a resting state, the total number of ions in the cell is negative, the cell membrane potential 20 is negative, and an electric field with negative inside the cell membrane and positive outside is formed between the source 11 and the cell 19. The electric field forms an inversion layer 12 and a depletion layer 15 on one side of the SiO2 insulating layer 17, wherein the inversion layer 12 is a P-type conductive channel with positive charges (holes) as the majority carriers, connecting the source 11 and the drain 16. The depletion layer 15 repels the majority carriers (electrons) in the N-type silicon semiconductor substrate 10, forming a space charge isolation band, so that the positive charges (holes) in the conductive channel do not diffuse to the N-type silicon semiconductor substrate 10. When the cell 19 is in an excited state, the cell membrane potential 20 is partially negative, indicating that the total number of ions in the cell is decreasing in negativity, and the other part is positive, indicating that the total number of ions in the cell is positive. In the former case, the width of the inversion layer 12 is small, the resistance of the conductive channel increases, and when the voltage of the power supply 13 remains unchanged, the current I D In the latter case, the inversion layer 12 disappears, and the conductive channel disappears as well. Even when the total number of ions in the cell is deeply positive, the depletion layer 15 disappears. At this time, the source 11-N-type silicon semiconductor substrate 10 is a reverse PN junction, and the drain 16-N-type silicon semiconductor substrate 10 is a forward PN junction. They are two back-to-back diodes and cannot conduct electricity, that is, the galvanometer 14 current I D is 0. This field effect sensing method is called depletion type p-channel field effect sensing.

[0040] In summary, the sensing characteristic V of the field effect sensor 9 is m -I D like Figure 4 As shown. When the cell membrane potential 20 changes with time to V m (t), through the field effect sensor 9 sensing characteristic V m -I D, the drain current I can be obtained by the galvanometer 14 D (t), the cell membrane potential 20 is sensed by the field effect sensor 9 as the current I of the galvanometer 14 D (t) purpose.

[0041] See also Figure 5 , the amplifier array 1 is an array composed of N×N amplifiers, each amplifier is numbered A ij , i represents the row, the value range is 1≤i≤N; j represents the column, the value range is 1≤j≤N. The field effect tube is numbered as FET ij , i represents the row, the value range is 1≤i≤N; j represents the column, the value range is 1≤j≤N. Amplifier A ij Used to amplify field effect tube FET ij The sensor signal I D , corresponding one to one with the sensors in the field effect tube array. ij The number N can be selected in the range of 10≤N≤700 according to the cell culture dish specifications.

[0042] Embodiment 2:

[0043] See also Figure 6 , is the sensing signal I of the field effect sensor 9 D (t) is an amplifier consisting of an operational amplifier OA 11 , resistor R 11 , R 12 , R 13 , R 14 , R 15 , capacitor C 11 , C 12 , C 13 Assume that the potential of node 1 is V1 and the potential of node 2 is V2. 11 It has the function of a galvanometer 14. When the sensor drain current I D Flow through R 11 , in R 11 The sensing voltage V generated at both ends 11 for:

[0044] V 11 =V1-V2=R 11 I D (2)

[0045] The drain-source operating current of the field effect tube does not exceed 1mA, and the sensing voltage V 11 does not exceed 1V, so R 11 At 1kΩ≤R 11 ≤100kΩ range selection. According to the ideal operational amplifier characteristics, the current flowing through R 12 The current flowing through R13 The current of the operational amplifier OA is the same. 11 Positive terminal potential V + With node 1 potential V1 and OA 11 Output potential V o have:

[0046]

[0047] After sorting:

[0048]

[0049] Similarly, the operational amplifier OA 11 Reverse terminal potential V - The potential V2 of node 2 is:

[0050]

[0051] After sorting:

[0052]

[0053] According to the ideal operational amplifier characteristics, we have:

[0054] V + =V - (7)

[0055] Substituting equation (4) and equation (6) into equation (7), the operational amplifier OA 11 Output V o :

[0056]

[0057] when

[0058] have:

[0059] The amplifier must comply with Conditions, magnification:

[0060]

[0061] At node 1, there is a shunt current I D and I1. I1 will affect I D The detection requires I1<<I D , generally I1 is smaller than I D An order of magnitude, that is, I1<I D / 10. To achieve this requirement, R 12 >>R 11 , generally R 12 Greater than R11 An order of magnitude, that is, R 12 >10R 11 . Capacitor C 11 It plays a filtering role and improves the amplifier output's ability to resist high-frequency interference. 16 and R 17 A voltage divider is formed to provide a static working potential for the N-type silicon semiconductor substrate 10. Generally, R 16 and R 17 Both are greater than 100KΩ.

[0062] The operational amplifier should be a zero-drift, low-noise, low-power amplifier, such as the AD8628, and use a positive power supply V DD and negative power supply V SS Power supply, parallel capacitor C 12 , C 13 To improve the stability of power supply. 12 can be 10μF, C 13 It can be 0.1μF.

[0063] Embodiment 3:

[0064] See also Figure 7 ADC array 2 is composed of multiple (n) analog-to-digital converters ADC121, ADC222, ........, ADC n 2n. Generally, an analog-to-digital converter (ADC) has 8 analog signal inputs. When amplifier array 1 has N×N amplifiers, then n≥(N×N) / 8. When N×N is a multiple of 8, take the equal sign; when it is not a multiple of 8, take the greater than sign. If amplifier array 1 has 10×10 amplifiers, then n=13. One ADC is assigned to every 8 amplifiers until the assignment is completed, and no numbering is performed. The 1st to 8th amplifiers are assigned to the first ADC121, the 9th to 16th amplifiers are assigned to the second ADC222, and so on, until the N×N amplifier is assigned to the nth ADC n 2n.

[0065] The analog-to-digital converter (ADC) can be selected from TI's chip ADS8028. ADS8028 is an 8-channel 12-bit, 1 million samples per second (MSPS), successive approximation register (SAR) digital-to-analog converter (ADC) with internal reference and internal temperature sensor. The chip data and control signal definitions are shown in Table 1.

[0066] Table 1 ADS8028 data and control pin definitions

[0067]

[0068]

[0069] The data bus of ADC array 2 is: the analog signal input channels AIN0 to AIN7 of the first ADC are respectively connected to the outputs of the 1st to 8th amplifiers, and the digital signal output channel DOUT1 is connected to the data bus Out 1 of the microprocessor 3; the analog signal input channels AIN0 to AIN7 of the second ADC are respectively connected to the outputs of the 9th to 16th amplifiers, and the digital signal output channel DOUT2 is connected to the data bus Out 2 of the microprocessor 3; ..., the analog signal input channels AIN0 to AIN7 of the nth ADC are respectively connected to the outputs of the 8th×(n-1)+1th to the N×Nth amplifiers, and the digital signal output channel DOUTn is connected to the data bus Out n of the microprocessor 3. For example, when N=10, the first ADC input AIN0~AIN7 is connected to the 1st to 8th amplifiers, and the output DOUT1 is connected to the microprocessor 3Out 1; the second ADC input AIN0~AIN7 is connected to the 9th to 16th amplifiers, and the output DOUT2 is connected to the microprocessor 3Out 2; ..., the 13th ADC analog signal input channels AIN0~AIN7 are respectively connected to the 97th to 100th amplifiers, and the output channel DOUT13 is connected to the microprocessor 3Out13.

[0070] The ADC array 2 control bus is: the chip select signal CS, SPI data input signal DIN, shutdown and reset signal PD / RET, SPI clock SCLK, output busy TM_BUSY and other control lines of all ADCs in ADC array 2 are connected in parallel and serve as the control bus of ADC array 2.

[0071] The digital power supply and analog power supply of the analog-to-digital converter (ADC) can use a common power supply, and the shutdown and reset signals PD / RET) are directly connected to the digital power supply, and cannot be connected to the control terminal of the microprocessor 3. DD After shorting, connect to the digital power supply 3.3V. When the internal temperature information of the chip is not needed, TM_BUSY can be directly left floating.

[0072] Embodiment 4:

[0073] See also Figure 8A microprocessor 3 is composed of a single chip, such as STM32F407, and the microprocessor 3 is connected to the USB interface 4. The output of the USB interface 4 is the output of the measurement circuit. The microprocessor 3 has an SPI data bus and a control bus. The SPI data bus P0~P15, D3~D7, a total of 21 signal outputs are connected to the input of the analog-to-digital converter ADC of the ADC array 2, and there are no more than 21 ADCs in total, that is, n≤21. In this way, the microprocessor 3 can measure the sensor signals of no more than 8×21=168 amplifiers. Three control lines are connected to the ADC array 2 control bus CS, SCLK, DIN. The data bus and control bus of the microprocessor 3 are defined as shown in Table 2.

[0074] Table 2 Definition of microprocessor 3 data bus and control bus

[0075] SPI protocol signals Pin Name Data Bus MCU CS D0 Control bus PD14 SCLK D1 Control bus PD15 DIN D2 Control bus PD0 Out1 D3 Data Bus PD1 Out 2 D4 Data Bus PE7 Out 3 D5 Data Bus PE8 Out 4 D6 Data Bus PE9 Out 5 D7 Data Bus PE10 Out 6 P0 Data Bus PB6 Out 7 P1 Data Bus PB7 Out 8 P2 Data Bus PB8 Out 9 P3 Data Bus PB9 Out 10 P4 Data Bus PA15 Out 11 P5 Data Bus PC10 Out 12 P6 Data Bus PC11 Out 13 P7 Data Bus PC12 Out 14 P8 Data Bus PE7 Out 15 P9 Data Bus PA0 Out 16 P10 Data Bus PA7 Out 17 P11 Data Bus PA6 Out 18 P12 Data Bus PB3 Out 19 P13 Data Bus PA4 Out 20 P14 Data Bus PA8 Out 21 P15 Data Bus PC9

[0076] In Table 2: SPI protocol signals include CS, SCLK, DIN and DOUT, where DOUT is the output Out1 to Out21 of the ADC array 2 and is distributed to the data buses P0 to P15 and D3 to D7 of the microprocessor 3.

[0077] The microprocessor 3 controls the ADC array 2 as follows: Assume that the sampling frequency of each amplifier output signal is 20kHz and the analog-to-digital conversion data is 16 bits. In this way, the SPI clock frequency f of the microprocessor 3 is at least:

[0078] f=20kHz / channel×N×N channels×16bit (12)

[0079] For example, when N = 10, the SPI clock frequency of microprocessor 3 is at least 20kHz × 10 × 10 channels × 16 bits = 32MHz. Considering that some instructions will take up a lot of CPU time, the main frequency of microprocessor 3 should be much higher than 32MHz. The microprocessor 3 used in this system is STM32F407, whose main frequency is 168MHz, which meets the design requirements.

[0080] Considering the limited data bus resources of microprocessor 3, in order to reduce the system complexity, the clock signals SCLK of all ADCs in ADC array 2 are connected to the same control signal, and the chip select signal CS and SPI data input signal DIN are also connected to the same control signal. In this way, the three signals enable all ADCs to operate at the same time and remain consistent.

[0081] See also Fig. 9The working principle of the microprocessor 3 control program is as follows: after the program starts, it is initialized first, and then enters the loop body While (1). The program continuously scans each amplifier at a scanning rate of 20kHz. When 20kHz is met, the program is interrupted, analog-to-digital conversion is performed, and the data is saved in the register of the microprocessor 3. The timer is interrupted at 20kHz. During the interruption, all signals (N×N channels) in the amplifier array 1 are collected once. Pay special attention to the optimization of the program. When controlling the input / output IO port, library functions cannot be used, but the input / output IO port should be controlled by directly controlling the register.

[0082] The interrupt program and its USB communication are as follows: The microprocessor 3 detects the serial data on the data bus Out1~Out21. The effective data volume of one detection cycle is 16bit / channel×8channel / chip×nchips. For example, the 10×10 amplifier array 1 has 13 ADCs, and the effective data volume of one detection cycle is 16bit / channel×8channel / chip×13chips=1664bit=208byte. In order to improve the operating efficiency of the microprocessor 3 and meet the 20kHz sampling of N×N signals, the data collected by the microprocessor 3 is the raw data of the input / output IO port, which requires some analysis to be converted into real data. The format of these data is as follows:

[0083] Microprocessor 3 collects ADC data according to the clock, and each clock collects bit data from n ADCs. The number of clocks in a complete ADC sampling cycle is 16 / channel × 8 channels = 128. Define a 16-bit array uint16 D

[128] , then D[i], i∈[1, 128] stores the n-bit data collected by microprocessor 3 at the i-th clock. In specific implementation, these n-bit data are stored in the high n bits of D[i], such as n=13. D

[128] stores all the results of a sampling. When the PC receives this data, it is necessary to parse the data of each channel according to the above description. See Fig.10 , is a python script with all the data structures.

[0084] The data unit for the computer system to communicate with the USB is a package. For each communication, the host computer will determine the number of packages (DataNum) and the size of each package (PackageSize, in bytes) that the microprocessor 3 sends to the computer system. When the host computer successfully sends the two data, DataNum and PackageSize, to the microprocessor 3, the microprocessor 3 will receive the two data and send DataNum packages to the computer system in a loop. The data sent by the microprocessor 3 is specified by a pointer. In specific implementation, the amount of data sampled by a complete ADC is 2byte×128=256byte. Using N×N sampling points as a package, the size of a package is 256byte×N×N, for example, 100 ADCs have 25.6KByte. Under the control of the clock pulse of the microprocessor 3, the data of the package is converted into a serial digital signal sequence and output from the USB interface. The number of data packets can be specified arbitrarily, and can generally be set to infinity.

[0085] When setting up and using the system, you must first install the USB driver on Windows. Choose to install the corresponding DPInst32.exe or DPInst64.exe according to the system bit number (32-bit or 64-bit). Note that Windows 8 and above systems must first disable the driver's mandatory signature before normal installation. After the installation is complete, first power on the amplifier, and then use the USB to connect the microprocessor 3 to use it.

Claims

1. A field effect cell culture dish system measurement circuit comprises an amplifier array (1), an ADC array (2), a microprocessor (3), and a USB interface (4); the input of the amplifier array (1) comes from a field effect cell culture dish body (6), the output of the amplifier array (1) is connected to the input of the ADC array (2), the output of the ADC array (2) is connected to the input of the microprocessor (3), the output of the microprocessor (3) is connected to the input of the USB interface (4), and the output of the USB interface (4) is the output of the measurement circuit and is connected to an external computer system PC; the amplifier array (1) is an array composed of a plurality of amplifiers, corresponding one to one to the sensors of the field effect tube array; each amplifier A ij The operational amplifier OA 11 , resistor R 11 , R 12 , R 13 , R 14 , R 15 , capacitor C 11 , C 12 , C 13 Composition, resistor R 11 Connect in series with power supply V DD and the drain electrode (16) of the field effect sensor (9), and the sensor drain-source current I D Converted to sensing voltage V 11 To realize the galvanometer (14) to detect the sensing current I D Function; R 12 and R 13 Connect in series with power supply V DD With operational amplifier OA 11 Output 11 Between, and R 12 and R 13 The connection point with the operational amplifier OA 11 The positive terminal connection, R 14 and R 15 is connected in series between the drain (16) of the field effect sensor (9) and the circuit ground, and R 14 and R 15 The connection point with the operational amplifier OA 11 The inverting end of the resistor R is connected; thus, the amplifier gain is determined by the resistor R 12 , R 13 , R 14 , R 15 OK, when When the amplifier gain is Capacitor C 11 Connected in parallel to the operational amplifier OA 11 Output 11 Between the circuit ground, it plays a filtering role to improve the amplifier output's ability to resist high-frequency interference. The capacitor C 12 and C 13 Connected in parallel to the operational amplifier OA 11 Positive power supply V DD and negative power supply V ss The ADC array (2) is composed of a plurality of n analog-to-digital converters, one ADC is allocated to every eight amplifiers, and until the allocation is completed, the ADC analog signal input is connected to the output of each amplifier in the amplifier array (1) in a one-to-one correspondence; the ADC digital signal output is connected to the data bus of the microprocessor (3); the chip select signal CS of all ADCs in the ADC array (2), the data input signal DIN of the serial peripheral interface SPI, the SPI clock SCLK, the shutdown and reset signal PD / RET, and the output busy TM_BUSY control line are connected in parallel and form the control bus of the ADC array (2), wherein CS, DIN, SCLK are connected to the control bus of the microprocessor (3), PD / RET is connected to the digital power supply, and when the internal temperature information of the chip is not needed, TM_BUSY is directly left floating; the control program of the microprocessor (3) is as follows: after the program is started, it is first initialized, and then enters the loop body While (1), the program continuously scans each amplifier at a scanning rate of 20kHz; when 20kHz is met, the interrupt program performs analog-to-digital conversion processing and saves the data in the register of the microprocessor (3); the timer is interrupted at a fixed time of 20kHz, and during the interruption period, the microprocessor (3) performs analog-to-digital conversion on all amplifiers in the amplifier array (1). There is a signal acquisition; when controlling the input / output IO port, library functions cannot be used, but the input / output IO port should be controlled by directly controlling the register; the interrupt program is as follows: the microprocessor (3) detects the serial data on the data bus Out1~Out21. The effective data volume of one detection cycle is 16bit / channel×8channel / chip×nchip. The collected data is the original data of the input / output IO port. These data need to be analyzed to be converted into real data. The analysis method is that the microprocessor (3) collects ADC data according to the clock. Each clock collects bit data from n ADCs. One ADC complete sampling cycle requires It takes 128 clocks for a 16-bit array D[i] (i∈[1, 128]) to store the n-bit data collected by the i-th clock microprocessor (3). In specific implementation, these n-bit data are stored in the high n bits of the array D[i]. In this way, the array D[128] stores all the results of a sampling. When the PC receives these data, it is necessary to parse out the real data of each channel according to the above description. The data sent by the microprocessor (3) is specified by a pointer. Under the control of the clock pulse, the microprocessor (3) converts all the data collected from the ADC array (2) into a serial digital signal sequence and outputs it from the USB interface.

2. A field effect cell culture dish system measurement circuit according to claim 1, characterized in that: The number of rows N and the number of columns N of the amplifier array (1) are selected in the range of 10≤N≤700 according to the specifications of the cell culture dish; the resistor R in the amplifier 11 At 1kΩ≤R 11 ≤≤100kΩ range selection; resistor R 12 Greater than R 11 An order of magnitude, and R 16 and R 17 Both are greater than 100KΩ; capacitor C 12 can be 10μF, C 13 can be 0.1μF; and R 16 and R 17 Both are greater than 100KΩ, resistor R 16 and R 17 A voltage divider is formed to provide a static working potential for an N-type silicon semiconductor substrate (10).

3. A field effect cell culture dish system measurement circuit according to claim 1, characterized in that: The main frequency of the microprocessor 3 should be higher than 32MHz.

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