Array substrate and its testing method, display device

Abstract

This disclosure provides an array substrate, a detection method thereof, and a display device. The array substrate comprises multiple touch electrodes forming multiple touch rows and columns, and multiple pixel units forming multiple pixel rows and columns. The orthographic projection of each touch unit onto the array substrate at least partially overlaps with the orthographic projection of the multiple pixel units onto the array substrate. Each pixel unit includes multiple sub-pixels. At least one adjacent pixel column is provided with a touch lead group, which includes at least a first lead and a second lead arranged side-by-side. The first lead is connected to a touch electrode in one touch row, and the second lead is connected to another touch electrode in an adjacent touch row. This disclosure reduces the number of leads, increases the space for sub-pixels, and improves the pixel aperture ratio by providing touch lead groups between adjacent pixel units, which is beneficial for improving the resolution of the display device.

Description

Technical Field

[0001] This article relates to, but is not limited to, the field of display technology, specifically to an array substrate and its detection method, and a display device. Background Technology

[0002] With the rapid development of display technology, touch screen panels have gradually become ubiquitous in people's lives. Touch screen panels can be categorized by their structure into add-on, on-cell, and in-cell types. Add-on touch screen panels involve manufacturing the touch module and display module separately and then bonding them together to create a touch-enabled panel. This method has disadvantages such as higher manufacturing costs, lower light transmittance, and a thicker module. In contrast, in-cell touch screen panels embed the touch electrodes of the touch module within the display module. This significantly reduces the overall thickness of the module and greatly lowers manufacturing costs, gradually becoming the mainstream type of capacitive touch screen panel.

[0003] Currently, embedded touch display devices suffer from problems such as low pixel aperture ratio. Summary of the Invention

[0004] The following is an overview of the subject matter described in detail herein. This overview is not intended to limit the scope of the claims.

[0005] The technical problem to be solved by this disclosure is to provide an array substrate and its detection method and display device to solve the problems of low pixel aperture ratio in existing embedded touch display devices.

[0006] On one hand, this disclosure provides an array substrate including a display area, the display area including at least: a plurality of touch electrodes constituting a plurality of touch rows and a plurality of touch columns, and a plurality of pixel units constituting a plurality of pixel rows and a plurality of pixel columns, wherein the orthographic projection of the touch unit on the array substrate at least partially overlaps with the orthographic projection of the plurality of pixel units on the array substrate, and the pixel unit includes a plurality of sub-pixels; a touch lead group is disposed between at least one adjacent pixel column, the touch lead group including at least a first lead and a second lead disposed in parallel, the first lead being connected to a touch electrode in a touch row, and the second lead being connected to another touch electrode in an adjacent touch row.

[0007] In an exemplary embodiment, at least one touch column includes N touch electrodes arranged sequentially along the direction of the pixel column. The orthographic projection of the touch column on the array substrate at least partially overlaps with the orthographic projection of N / 2 pixel columns on the array substrate. A first lead located between the i-th pixel column and the (i+1)-th pixel column is connected to the touch electrodes in the (2i-1)-th touch row. A second lead located between the i-th pixel column and the (i+1)-th pixel column is connected to the touch electrodes in the 2i-th touch row. N is an even number greater than 1, and i is a positive integer greater than or equal to 1 and less than or equal to N / 2.

[0008] In an exemplary embodiment, at least one pixel unit includes a first sub-pixel, a second sub-pixel, and a third sub-pixel arranged sequentially along the pixel row direction. Each sub-pixel includes a gate line, a data line, a thin-film transistor, and a pixel electrode. The thin-film transistor is connected to the gate line, the data line, and the pixel electrode, respectively. The touch electrode is multiplexed as a common electrode, and the first lead and the second lead are multiplexed as a common electrode line. The first lead is disposed on the side of the third sub-pixel away from the first sub-pixel, and the second lead is disposed on the side of the first lead away from the first sub-pixel.

[0009] In an exemplary embodiment, in at least one pixel row, a first connecting block is provided on the first lead, and the first connecting block is connected to a touch electrode through a first via.

[0010] In an exemplary embodiment, in at least one pixel row, the first lead includes at least a first straight segment, a second straight segment, and a bent segment located between the first straight segment and the second straight segment. The first end of the bent segment is connected to the first straight segment, the second end of the bent segment is connected to the second straight segment, and the middle part of the bent segment protrudes in a direction away from the second lead. The first connecting block is disposed in the area formed by the bend of the bent segment.

[0011] In an exemplary embodiment, the orthographic projection of the first connecting block on the array substrate at least partially overlaps with the orthographic projection of the gate line on the array substrate.

[0012] In an exemplary embodiment, the orthographic projection of the first via on the array substrate at least partially overlaps with the orthographic projection of the gate line on the array substrate.

[0013] In an exemplary embodiment, in at least one pixel row, a second connecting block is provided on the second lead, and the second connecting block is connected to another touch electrode through a second via.

[0014] In an exemplary embodiment, in at least one pixel row, the first lead includes at least a first straight segment, a second straight segment, and a bent segment located between the first straight segment and the second straight segment. The first end of the bent segment is connected to the first straight segment, the second end of the bent segment is connected to the second straight segment, the middle part of the bent segment protrudes in a direction away from the second lead, and the second connecting block is disposed in the area formed by the bend of the bent segment.

[0015] In an exemplary embodiment, the orthographic projection of the second connecting block on the array substrate at least partially overlaps with the orthographic projection of the gate line on the array substrate.

[0016] In an exemplary embodiment, the orthographic projection of the second via on the array substrate at least partially overlaps with the orthographic projection of the gate line on the array substrate.

[0017] In an exemplary embodiment, in at least one pixel unit, the touch electrode includes an electrode portion and a connecting portion. The electrode portion is disposed within the pixel unit, and the connecting portion is disposed between adjacent pixel units and connected to the electrode portion within the adjacent pixel unit.

[0018] In an exemplary embodiment, in at least one pixel unit, the orthographic projection of the electrode portion on the array substrate does not overlap with the orthographic projection of the gate line on the array substrate, the orthographic projection of the electrode portion on the array substrate does not overlap with the orthographic projection of the first lead on the array substrate, and the orthographic projection of the electrode portion on the array substrate does not overlap with the orthographic projection of the second lead on the array substrate.

[0019] In an exemplary embodiment, in at least one pixel unit, the orthographic projection of the connecting portion on the array substrate at least partially overlaps with the orthographic projection of the gate line on the array substrate, the orthographic projection of the connecting portion on the array substrate at least partially overlaps with the orthographic projection of the first lead on the array substrate, and the orthographic projection of the connecting portion on the array substrate at least partially overlaps with the orthographic projection of the second lead on the array substrate.

[0020] In an exemplary embodiment, in at least one pixel unit, at least one connecting portion is connected to the first lead through a first via, or at least one connecting portion is connected to the second lead through a second via.

[0021] In an exemplary embodiment, the array substrate further includes a bonding area located on one side of the display area and an upper frame area located on the side of the display area away from the bonding area; the bonding area includes at least a plurality of pins, and the upper frame area includes at least a test circuit, the test circuit being connected to the plurality of pins of the bonding area via a plurality of connecting lines, the test circuit being configured to detect short circuit defects of the array substrate.

[0022] In an exemplary embodiment, the test circuit includes multiple test units, each corresponding to a multiple touch column. At least one test unit includes a first test line, a second test line, a switch control line, a first switch, and a second switch. The first test line is connected to a first lead in the display area via the first switch, and the second test line is connected to a second lead in the display area via the second switch. The switch control line is connected to the control terminals of the first and second switches. The first test line is configured to transmit a first grayscale voltage to the first lead under the control of the switch control line, and the second test line is configured to transmit a second grayscale voltage to the second lead under the control of the switch control line. The voltage value of the first grayscale voltage is greater than the voltage value of the second grayscale voltage, or the voltage value of the first grayscale voltage is less than the voltage value of the second grayscale voltage.

[0023] In an exemplary embodiment, the test unit further includes a first data lead, a second data lead, a third data lead, a third switch, a fourth switch, and a fifth switch. The first data lead is connected to the data line of a first sub-pixel in the display area via the third switch. The second data lead is connected to the data line of a second sub-pixel in the display area via the fourth switch. The third data lead is connected to the data line of a third sub-pixel in the display area via the fifth switch. The switch control line is connected to the control terminals of the third, fourth, and fifth switches. The first, second, and third data leads are configured to transmit a common reference voltage to the data lines of the display area under the control of the switch control line.

[0024] On the other hand, this disclosure also provides a display device including the aforementioned array substrate.

[0025] Furthermore, this disclosure also provides a method for detecting an array substrate employing the aforementioned array substrate, comprising:

[0026] A turn-on voltage is provided to multiple gate lines in the display area, causing the thin-film transistors of multiple sub-pixels in the display area to conduct; a common reference voltage is provided to multiple data lines in the display area, causing the pixel electrodes of multiple sub-pixels in the display area to have a common reference voltage;

[0027] A first grayscale voltage is provided to a first lead in the display area, such that a plurality of touch electrodes connected to the first lead in the display area have a first grayscale voltage; a second grayscale voltage is provided to a second lead in the display area, such that a plurality of touch electrodes connected to the second lead in the display area have a second grayscale voltage; the voltage value of the first grayscale voltage is greater than the voltage value of the second grayscale voltage, or the voltage value of the first grayscale voltage is less than the voltage value of the second grayscale voltage.

[0028] In an exemplary embodiment, when there is no short circuit on the array substrate, the touch electrode in one touch row displays a first gray level, and the touch electrode in the adjacent touch row displays a second gray level, and the display area presents a vertically alternating bright and dark display image; when there is a short circuit on the array substrate, at least one touch electrode in one touch row displays the same gray level as at least one touch electrode in the adjacent touch row.

[0029] The array substrate and its detection method and display device provided in this disclosure reduce the number of leads, increase the space of sub-pixels, and improve the pixel aperture ratio by setting touch lead groups between adjacent pixel units. The touch lead groups may include first leads and second leads arranged in parallel, which is beneficial to improving the resolution of the display device.

[0030] After reading and understanding the accompanying diagrams and detailed descriptions, the other aspects can be understood. Attached Figure Description

[0031] The accompanying drawings are used to provide an understanding of the technical solutions of this disclosure and form part of the specification. They are used together with the embodiments of this disclosure to explain the technical solutions of this disclosure and do not constitute a limitation on the technical solutions of this disclosure.

[0032] Figure 1 A schematic cross-sectional view of a liquid crystal display device;

[0033] Figure 2 This is a schematic diagram of the planar structure of a liquid crystal display device;

[0034] Figure 3 This is a schematic diagram of a planar structure of an array substrate;

[0035] Figure 4 This is a schematic diagram of the structure of an in-box touch panel;

[0036] Figure 5 This is a schematic diagram of a planar structure of an array substrate, which is an exemplary embodiment of the present disclosure.

[0037] Figure 6 This is a schematic diagram of a planar structure of a display area, which is an exemplary embodiment of the present disclosure.

[0038] Figure 7a for Figure 6 Enlarged view of region A in the middle;

[0039] Figure 7b for Figure 6 Enlarged view of region B in the middle;

[0040] Figure 8a and Figure 8b This is a schematic diagram of the array substrate after the first conductive layer pattern has been formed;

[0041] Figure 9a and Figure 9b This is a schematic diagram of the array substrate after the semiconductor layer pattern has been formed.

[0042] Figure 10a and Figure 10b This is a schematic diagram of the array substrate after the second conductive layer pattern has been formed;

[0043] Figure 11a and Figure 11b This is a schematic diagram of the array substrate after the second insulating layer pattern has been formed;

[0044] Figure 12a and Figure 12b This is a schematic diagram of the array substrate after the third conductive layer pattern has been formed;

[0045] Figure 13a and Figure 13b This is a schematic diagram of the array substrate after the third insulating layer pattern has been formed;

[0046] Figure 14 This is a schematic diagram of the planar structure of the bonding region and the border region in the array substrate of this disclosure;

[0047] Figures 15 to 19 A schematic diagram of the test circuit fabricated for the array substrate of this disclosure;

[0048] Figure 20 and Figure 21 A schematic diagram of the short-circuit detection circuit of this disclosure;

[0049] Figure 22 This is a schematic diagram of the detection timing when performing short-circuit detection for the detection circuit of this disclosure.

[0050] Explanation of reference numerals in the attached figures:

[0051] 10—Thin-film transistor; 20—Gate line; 21—Gate electrode;

[0052] 22—Active layer; 23—Source electrode; 24—Drain electrode;

[0053] 30—Data cable; 40—Pixel electrode; 50—Touch electrode;

[0054] 51—Electrode section; 52—Connecting section; 53—Opening;

[0055] 60—Pixel unit; 61—First lead; 61-1—First connecting block;

[0056] 62—Second lead; 62-1—Second connector block; 70—Test unit;

[0057] 71—First test lead; 72—Second test lead; 73—First data lead;

[0058] 74—Second data lead; 75—Third data lead; 76—Switch control line;

[0059] 76-1—First control line; 76-2—Second control line; 76-3—Third control line;

[0060] 76-4—Fourth control line; 76-5—Fifth control line; 81—First connecting line;

[0061] 82—Second connecting line; 83—Third connecting line; 84—Fourth connecting line;

[0062] 85—Fifth connecting line; 91—First switch; 92—Second switch;

[0063] 93—Third switch; 94—Fourth switch; 95—Fifth switch;

[0064] 100—Display area; 111—First gate block; 112—Second gate block;

[0065] 113—Third gate block; 114—Fourth gate block; 115—Fifth gate block;

[0066] 121—First active layer; 122—Second active layer; 123—Third active layer;

[0067] 124—Fourth active layer; 125—Fifth active layer; 131—First source electrode;

[0068] 132—Second source electrode; 133—Third source electrode; 134—Fourth source electrode;

[0069] 135—Fifth source electrode; 141—First drain electrode; 142—Second drain electrode;

[0070] 143—Third drain electrode; 144—Fourth drain electrode; 145—Fifth drain electrode;

[0071] 151—First lap joint; 152—Second lap joint; 153—Third lap joint;

[0072] 154—Fourth lap joint block; 155—Fifth lap joint block; 161—First lap joint electrode;

[0073] 162—Second lap electrode; 163—Third lap electrode; 164—Fourth lap electrode;

[0074] 165—Fifth bonding electrode; 200—Binding area; 210—First test pin;

[0075] 220—Second test pin; 230—First data pin; 240—Second data pin;

[0076] 250—Third data pin; 260—Switch control pin; 270—Gate line control pin;

[0077] 280—Driver chip; 300—Border area; 310—Top border area;

[0078] 320—Side frame area; 330—Gate drive circuit. Detailed Implementation

[0079] The embodiments of this disclosure will be described in detail below with reference to the accompanying drawings. Note that the implementation can be carried out in many different forms. Those skilled in the art will readily understand that the methods and content can be varied in many ways without departing from the spirit and scope of this disclosure. Therefore, this disclosure should not be construed as limited to the contents described in the following embodiments. Without conflict, the embodiments and features in the embodiments of this disclosure can be arbitrarily combined with each other.

[0080] The scale of the figures in this disclosure can be used as a reference in actual processes, but is not limited thereto. For example, the aspect ratio of the channel, the thickness and spacing of each film layer, and the width and spacing of each signal line can be adjusted according to actual needs. The number of pixels in the array substrate and the number of sub-pixels in each pixel are not limited to the quantities shown in the figures. The figures described in this disclosure are only schematic diagrams of the structure, and one aspect of this disclosure is not limited to the shapes or values ​​shown in the figures.

[0081] The ordinal numbers “first,” “second,” and “third” used in this specification are used to avoid confusion among the constituent elements, not to limit their quantity.

[0082] In this specification, for convenience, terms such as "middle," "upper," "lower," "front," "rear," "vertical," "horizontal," "top," "bottom," "inner," and "outer" are used to indicate orientation or positional relationships in conjunction with the accompanying drawings. This is solely for the purpose of facilitating the description and simplification, and does not imply that the device or component referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, it should not be construed as a limitation of this disclosure. The positional relationships of the constituent elements may be appropriately varied depending on the orientation of each constituent element being described. Therefore, the use of terms not limited to those described in the specification may be appropriately replaced as needed.

[0083] In this specification, unless otherwise expressly specified and limited, the terms "installation," "connection," and "joining" should be interpreted broadly. For example, they may refer to a fixed connection, a detachable connection, or an integral connection; a mechanical connection or an electrical connection; a direct connection, an indirect connection via an intermediate component, or a connection within two components. Those skilled in the art will understand the specific meaning of these terms in this disclosure based on the specific circumstances.

[0084] In this specification, a transistor is a device that includes at least three terminals: a gate electrode, a drain electrode, and a source electrode. A transistor has a channel region between the drain electrode (drain electrode terminal, drain region, or drain electrode) and the source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. Note that in this specification, the channel region refers to the region through which current primarily flows.

[0085] In this specification, the first electrode can be the drain electrode and the second electrode can be the source electrode, or vice versa. In cases where transistors with opposite polarities are used or the current direction changes during circuit operation, the functions of the "source electrode" and "drain electrode" may sometimes be interchanged. Therefore, in this specification, the "source electrode" and "drain electrode" can be interchanged, and the "source terminal" and "drain terminal" can be interchanged.

[0086] In this specification, "connection" includes the situation where constituent elements are connected together by a component having a certain electrical function. There are no particular limitations on the "component having a certain electrical function," as long as it enables the transmission and reception of electrical signals between the connected constituent elements. Examples of "components having a certain electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other components with various functions.

[0087] In this specification, "parallel" refers to the state where the angle formed by two straight lines is greater than or equal to -10° and less than 10°, and therefore also includes the state where the angle is greater than or equal to -5° and less than 5°. Similarly, "perpendicular" refers to the state where the angle formed by two straight lines is greater than or equal to 80° and less than 100°, and therefore also includes the state where the angle is greater than or equal to 85° and less than 95°.

[0088] In this specification, the terms "film" and "layer" may be interchanged. For example, "conductive layer" may sometimes be replaced with "conductive film." Similarly, "insulating film" may sometimes be replaced with "insulating layer."

[0089] In this specification, triangles, rectangles, trapezoids, pentagons, or hexagons are not strictly defined; they can be approximate triangles, rectangles, trapezoids, pentagons, or hexagons. Small deformations due to tolerances are possible, as are chamfers, curved edges, and other variations.

[0090] In this disclosure, “about” means a value that is not strictly limited and allows for process and measurement errors.

[0091] Liquid crystal displays (LCDs) are widely used due to their small size, low power consumption, and lack of radiation. A liquid crystal array substrate consists of a thin film transistor array (TFT) substrate (cells) and a color filter (CF) substrate. Liquid crystal (LC) molecules are disposed between the array substrate and the color filter substrate. By controlling the common electrode and pixel electrode, an electric field is formed to drive the liquid crystal deflection, thus achieving grayscale display.

[0092] Figure 1 This is a cross-sectional structural diagram of a liquid crystal display device. Figure 1As shown, a liquid crystal display device may include a first substrate A1 and a second substrate A2 disposed opposite to each other, and a liquid crystal layer A3 disposed between the first substrate A1 and the second substrate A2. The first substrate A1 may include a first structural layer A1-2 disposed on the side of the first substrate A1-1 facing the second substrate A2, and the second substrate A2 may include a second structural layer A2-2 disposed on the side of the second substrate A2-1 facing the first substrate A1. According to the display mode, liquid crystal display devices can be classified into Twisted Nematic (TN) display mode, In-Plane Switching (IPS) display mode, Fringe Field Switching (FFS) display mode, and Advanced Super Dimension Switching (ADS) display mode, etc. For the ADS display mode, in an exemplary embodiment, the first structural layer A1-2 may include gate lines, data lines, thin-film transistors, pixel electrodes, and common electrodes, and the second structural layer A2-2 may include a black matrix and a filter unit.

[0093] Figure 2 This is a schematic diagram of the planar structure of a liquid crystal display device. Figure 2 As shown, the liquid crystal display device may include a plurality of pixel units 60 arranged in a matrix. At least one of the plurality of pixel units 60 may include a first sub-pixel P1 emitting a first color light, a second sub-pixel P2 emitting a second color light, and a third sub-pixel P3 emitting a third color light. Each of the three sub-pixels may include a thin-film transistor, a pixel electrode, and a common electrode. In an exemplary embodiment, the first sub-pixel P1 may be a red sub-pixel emitting red (R) light, the second sub-pixel P2 may be a green sub-pixel emitting green (G) light, and the third sub-pixel P3 may be a blue sub-pixel emitting blue (B) light. The shape of the sub-pixels in the pixel unit may be rectangular, rhomboid, pentagonal, or hexagonal, etc., and the sub-pixels in the pixel unit may be arranged horizontally side by side, vertically side by side, or in a triangular arrangement. In an exemplary embodiment, the pixel unit may include four sub-pixels, which is not limited herein.

[0094] Figure 3 This is a schematic diagram of a planar structure of an array substrate. For example... Figure 3As shown, in an exemplary embodiment, the array substrate may include a display area and a border area. The display area may include multiple gate lines (S1 to Sm) and multiple data lines (D1 to Dn). The multiple gate lines may extend horizontally and be arranged sequentially in a vertical direction, and the multiple data lines may extend vertically and be arranged sequentially in a horizontal direction. The intersecting multiple gate lines and multiple data lines define a plurality of regularly arranged sub-pixels Pxij, where m, n, i, and j can be natural numbers. In an exemplary embodiment, at least one sub-pixel Pxij may include a thin-film transistor, a pixel electrode, and a common electrode. The thin-film transistor is connected to the gate lines, data lines, and pixel electrode, respectively.

[0095] In an exemplary embodiment, the array substrate may further include multiple common electrode lines (E1 to Eo). The multiple common electrode lines may extend in the horizontal direction and be arranged sequentially in the vertical direction, or the multiple common electrode lines may extend in the vertical direction and be arranged sequentially in the horizontal direction. The multiple common electrode lines are connected to the common electrodes in multiple sub-pixels Pxij.

[0096] In an exemplary embodiment, multiple gate lines are connected to a scan driver, and multiple data lines are connected to a data driver. At least a portion of the scan driver and the data driver can be formed on an array substrate.

[0097] In an exemplary embodiment, an external control device (such as a timing controller) can provide grayscale values ​​and control signals of specifications suitable for the data driver to the data driver. The data driver can use the received grayscale values ​​and control signals to generate data voltages to be provided to data lines D1, D2, D3, ..., Dn. For example, the data driver can sample grayscale values ​​using a clock signal and apply data voltages corresponding to the grayscale values ​​to data lines D1 to Dn on a pixel-by-pixel basis. The external control device can also provide clock signals, scan start signals, etc., of specifications suitable for the scan driver to the scan driver. The scan driver can use the clock signals, scan start signals, etc., to generate scan signals to be provided to scan signal lines S1, S2, S3, ..., Sm. For example, the scan driver can sequentially provide scan signals with on-level pulses to scan signal lines S1 to Sm. For example, the scan driver can be configured as a shift register and can generate scan signals by sequentially transmitting scan start signals, provided in the form of on-level pulses, to the next stage circuit under the control of a clock signal.

[0098] In exemplary embodiments, liquid crystal display devices integrating touch functionality mainly include On-Cell structures and In-Cell structures. On-Cell structures typically have the touch structure disposed on the side of the color filter substrate away from the array substrate, while In-Cell structures typically have the touch structure disposed in the first structural layer of the array substrate. Compared to On-Cell structures, In-Cell structures enable the liquid crystal display device to be thinner and lighter.

[0099] In exemplary embodiments, the In-Cell structure is mainly divided into mutual capacitance structure and self-capacitance structure. The mutual capacitance structure consists of a driving electrode and a sensing electrode overlapping or close to each other to form a mutual capacitance, and position detection is performed using changes in this mutual capacitance. The self-capacitance structure consists of a touch electrode and the human body forming a self-capacitance, and position detection is performed using changes in this self-capacitance. Compared to the mutual capacitance structure, the self-capacitance structure is a single-layer structure, featuring low power consumption and a simple structure.

[0100] Figure 4 This is a schematic diagram of the structure of an in-box touch panel. Figure 4 As shown, the in-cell touch panel (In-Cell Touch LCD) may include multiple touch electrodes 50 arranged in a regular pattern and multiple touch leads (also called sensing signal lines, Tx signal lines) 50A. Each touch electrode 50 is connected to the touch driving circuit through the touch lead 50A. During operation, the touch of a human finger causes a change in the self-capacitance of the corresponding touch electrode 50. The touch driving circuit determines the specific position of the finger based on the change in capacitance of the touch electrode 50. In an exemplary embodiment, the in-cell touch panel uses a common electrode layer that provides a common voltage as the touch layer, and the common electrode layer is "segmented" to form... Figure 4 The block-shaped touch electrode 50 is shown. In an exemplary embodiment, the shape of the touch electrode can be rectangular, rhomboid, triangular, or polygonal, etc., and is not limited herein.

[0101] In an exemplary embodiment Figure 4 The touch panel inside the box, as shown, employs a time-division multiplexing driving mode, processing the drive signals for the display period and the touch period separately. During the display period, the data lines are supplied with display signals by the data driver, the touch electrodes are multiplexed as common electrodes, and the touch signal lines are multiplexed as common electrode lines. The touch signal lines provide a common voltage to the touch electrodes, and no touch signal scanning is performed, ensuring normal display. During the touch period, the touch drive circuit scans the touch signals through the touch signal lines. At this time, one frame of display has been completed, and the display state is largely unaffected by the touch signals; the two operate independently in a time-division manner.

[0102] In an exemplary embodiment, a touch electrode can be a rectangle of approximately 4*4mm or 5*5mm, covering multiple sub-pixels, and controlled by a touch lead. The touch lead can be positioned between adjacent sub-pixels. Since a touch electrode covers multiple sub-pixels, the number of touch leads is much smaller than the number of sub-pixels covered by the touch electrode. Therefore, to avoid having touch leads between some sub-pixels while not having them between others, and to ensure the consistency of the pixel structure and the uniformity of etching, existing array substrates typically have leads positioned between each adjacent sub-pixel. A portion of these leads serves as touch leads controlling the touch electrode, while the remainder are dummy lines with no signal input.

[0103] In recent years, high-resolution display devices have gradually become an industry trend. The resolution (Pixels Per Inch, or PPI) of a display device is related to the pixel aperture ratio of the array substrate; the higher the pixel aperture ratio, the higher the resolution of the display device. The inventors of this application have discovered that, due to the presence of touch leads or dummy lines between adjacent sub-pixels in existing array substrates, a large number of dummy lines occupy the space of the sub-pixels, resulting in a low pixel aperture ratio in existing array substrates, which hinders the improvement of display device resolution.

[0104] An exemplary embodiment of this disclosure provides an array substrate including a display area, the display area including at least: a plurality of touch electrodes constituting a plurality of touch rows and a plurality of touch columns, and a plurality of pixel units constituting a plurality of pixel rows and a plurality of pixel columns, wherein the orthographic projection of the touch units on the array substrate at least partially overlaps with the orthographic projection of the plurality of pixel units on the array substrate, and the pixel units include a plurality of sub-pixels; a touch lead group is disposed between at least one adjacent pixel column, the touch lead group including at least a first lead and a second lead disposed in parallel, the first lead being connected to a touch electrode in a touch row, and the second lead being connected to another touch electrode in an adjacent touch row.

[0105] In an exemplary embodiment, at least one touch column includes N touch electrodes arranged sequentially along the direction of the pixel column. The orthographic projection of the touch column on the array substrate at least partially overlaps with the orthographic projection of N / 2 pixel columns on the array substrate. A first lead located between the i-th pixel column and the (i+1)-th pixel column is connected to the touch electrodes in the (2i-1)-th touch row. A second lead located between the i-th pixel column and the (i+1)-th pixel column is connected to the touch electrodes in the 2i-th touch row. N is an even number greater than 1, and i is a positive integer greater than or equal to 1 and less than or equal to N / 2.

[0106] In an exemplary embodiment, at least one pixel unit includes a first sub-pixel, a second sub-pixel, and a third sub-pixel arranged sequentially along the pixel row direction. Each sub-pixel includes a gate line, a data line, a thin-film transistor, and a pixel electrode. The thin-film transistor is connected to the gate line, the data line, and the pixel electrode, respectively. The touch electrode is multiplexed as a common electrode, and the first lead and the second lead are multiplexed as a common electrode line. The first lead is disposed on the side of the third sub-pixel away from the first sub-pixel, and the second lead is disposed on the side of the first lead away from the first sub-pixel.

[0107] In an exemplary embodiment, the array substrate further includes a bonding area located on one side of the display area and an upper frame area located on the side of the display area away from the bonding area; the bonding area includes at least a plurality of pins, and the upper frame area includes at least a test circuit, the test circuit being connected to the plurality of pins of the bonding area via a plurality of connecting lines, the test circuit being configured to detect short circuit defects of the array substrate.

[0108] In an exemplary embodiment, the test circuit includes multiple test units, each corresponding to a multiple touch column. At least one test unit includes a first test line, a second test line, a switch control line, a first switch, and a second switch. The first test line is connected to a first lead in the display area via the first switch, and the second test line is connected to a second lead in the display area via the second switch. The switch control line is connected to the control terminals of the first and second switches. The first test line is configured to transmit a first grayscale voltage to the first lead under the control of the switch control line, and the second test line is configured to transmit a second grayscale voltage to the second lead under the control of the switch control line. The voltage value of the first grayscale voltage is greater than the voltage value of the second grayscale voltage, or the voltage value of the first grayscale voltage is less than the voltage value of the second grayscale voltage.

[0109] In an exemplary embodiment, the test unit further includes a first data lead, a second data lead, a third data lead, a third switch, a fourth switch, and a fifth switch. The first data lead is connected to the data line of a first sub-pixel in the display area via the third switch. The second data lead is connected to the data line of a second sub-pixel in the display area via the fourth switch. The third data lead is connected to the data line of a third sub-pixel in the display area via the fifth switch. The switch control line is connected to the control terminals of the third, fourth, and fifth switches. The first, second, and third data leads are configured to transmit a common reference voltage to the data lines of the display area under the control of the switch control line.

[0110] Figure 5 This is a schematic diagram of a planar structure of an array substrate, as an exemplary embodiment of this disclosure. Figure 5 As shown, the array substrate may include a display area 100, a bonding area 200 located on one side of the display area 100, and a border area 300 located on other sides of the display area 100. In an exemplary embodiment, the display area 100 may be a flat area, including a plurality of pixel units constituting a pixel array and a plurality of touch electrodes constituting a touch array. The plurality of pixel units are configured to display dynamic or still images, and the plurality of touch electrodes are configured to implement touch control. In an exemplary embodiment, the display area 100 may be referred to as the effective area (AA).

[0111] In an exemplary embodiment, the bonding area 200 may include at least a fan-out area, a driver chip area, and a bonding pin area arranged sequentially along a direction away from the display area. The fan-out area may be connected to the display area 100 and may include at least data transmission lines and touch transmission lines. Multiple data transmission lines are configured to connect to the data lines of the display area in a fan-out routing manner, and multiple touch transmission lines are configured to connect to the touch lines of the display area. The driver chip area may be connected to the fan-out area and may include at least an integrated circuit (IC). The IC is configured to connect to the multiple data transmission lines and the multiple touch transmission lines. The bonding pin area may be connected to the driver chip area and may include at least multiple pins. The multiple pins are configured to bond to an external flexible printed circuit (FPC).

[0112] In an exemplary embodiment, the bezel region 300 may include an upper bezel region 310 located on the side of the display region 100 away from the bonding region 200 and side bezel regions 320 located on both sides of the display region 100. The upper bezel region 310 may include at least a test circuit connected to multiple data lines and touch traces in the display region, and the test circuit is configured to detect short-circuit defects in the array substrate. The side bezel regions 320 may include a circuit region and a lead region arranged sequentially along a direction away from the display region 100. The circuit region may be connected to the display region 100 and may include at least multiple cascaded gate drive circuits (GOAs) connected to multiple gate lines in the display region 100. The lead region may be connected to the circuit region and may include at least multiple connecting lines, the first ends of which may be connected to multiple pins in the bonding region 200, and the second ends of which may be connected to the test circuit in the upper bezel region 310, so that an external test device can transmit test signals to the test circuit through the multiple connecting lines.

[0113] Figure 6 This is a schematic diagram of a planar structure of a display area as an exemplary embodiment of the present disclosure. Figure 6 As shown, in an exemplary embodiment, the display area of ​​the array substrate may include at least a plurality of touch electrodes 50 constituting a plurality of touch rows and a plurality of touch columns, and a plurality of pixel units 60 constituting a plurality of pixel rows and a plurality of pixel columns. The plurality of pixel units 60 constitute a pixel array and are configured to display dynamic or still images. The plurality of touch electrodes 50 constitute a touch array and are configured to implement touch control. Each touch row may include a plurality of touch electrodes 50 arranged sequentially along a first direction X, and the plurality of touch rows may be spaced apart along a second direction Y. Each touch column may include a plurality of touch electrodes 50 arranged sequentially along the second direction Y, and the plurality of touch columns may be spaced apart along the first direction X. Each pixel row may include a plurality of pixel units 60 arranged sequentially along the first direction X, and the plurality of pixel rows may be spaced apart along the second direction Y. Each pixel column may include a plurality of pixel units 60 arranged sequentially along the second direction Y, and the plurality of pixel columns may be spaced apart along the first direction X. In the exemplary embodiment, the first direction X intersects the second direction Y.

[0114] In an exemplary embodiment, the orthographic projection of at least one touch electrode 50 on the array substrate may include the orthographic projection of multiple pixel units 60 on the array substrate, that is, one touch electrode 50 may cover multiple pixel units 60, and a pixel unit 60 may include multiple sub-pixels.

[0115] In an exemplary embodiment, the display area may include N touch rows, that is, a touch column may include N touch electrodes 50 arranged sequentially along the second direction Y. The orthographic projection of at least one touch column on the array substrate at least partially overlaps with the orthographic projection of N / 2 pixel columns on the array substrate, that is, the positions of the N touch electrodes 50 of a touch column may correspond to the positions of the plurality of pixel units 60 of the N / 2 pixel columns, where N is an even number greater than 1.

[0116] In an exemplary embodiment, among the N / 2 pixel columns corresponding to a touch column, at least one adjacent pixel column is provided with a touch lead group. In an exemplary embodiment, the touch lead group may include a first lead 61 and a second lead 62. The first lead 61 and the second lead 62 may be line shapes extending along a second direction Y (pixel column direction), and the second lead 62 may be disposed on one side of the first lead 61 in a first direction X (pixel row direction).

[0117] In an exemplary embodiment, for the first lead 61 and the second lead 62 located between the i-th pixel column and the i+1-th pixel column, the first lead 61 can be connected to the touch electrode 50 in the 2i-1-th touch row, and the second lead 62 can be connected to the touch electrode 50 in the 2i-th touch row, where i is a positive integer greater than or equal to 1 and less than or equal to N / 2.

[0118] In an exemplary embodiment, when multiple first leads 61 are connected to touch electrodes 50 in an odd number of touch rows, multiple second leads 62 are connected to touch electrodes 50 in an even number of touch rows.

[0119] In an exemplary implementation, for Figure 6 The first touch column shown on the left corresponds to N / 2 pixel columns. For the first lead 61 and the second lead 62 between the first and second pixel columns, the first lead 61 is connected to the first touch electrode 50 of the touch column (the touch electrode 50 of the first touch row), and the second lead 62 is connected to the second touch electrode 50 of the touch column (the touch electrode 50 of the second touch row). For the first lead 61 and the second lead 62 between the second and third pixel columns, the first lead 61 is connected to the third touch electrode 50 of the touch column (the touch electrode 50 of the third touch row), and the second lead 62 is connected to the fourth touch electrode 50 of the touch column (the touch electrode 50 of the fourth touch row). For the first lead 61 and the second lead 62 between the (N / 2)th pixel column and the (N / 2+1)th pixel column, the first lead 61 is connected to the (N-1)th touch electrode 50 of the touch column (the touch electrode 50 of the (N-1)th touch row), and the second lead 62 is connected to the Nth touch electrode 50 of the touch column (the touch electrode 50 of the Nth touch row). The (N / 2+1)th pixel column is the first pixel column corresponding to the second touch column.

[0120] In an exemplary embodiment, a pixel unit 60 may include 3 sub-pixels or 4 sub-pixels. Taking a pixel unit 60 including a first sub-pixel, a second sub-pixel, and a third sub-pixel arranged sequentially along a first direction X as an example, the first lead 61 and the second lead 62 may be arranged between the third sub-pixel in the i-th pixel column and the first sub-pixel in the (i+1)-th pixel column, while no first lead or second lead is arranged between the first sub-pixel and the second sub-pixel, or between the second sub-pixel and the third sub-pixel in each pixel column.

[0121] In an exemplary embodiment, the display area may include multiple touch columns, and the structure of each touch column and its corresponding multiple pixel columns may be the same as that of the first touch column.

[0122] In an exemplary embodiment, on a plane perpendicular to the array substrate, the array substrate may include a substrate and a plurality of conductive layers disposed on the substrate. The first lead 61 and the second lead 62 may be disposed in the same conductive layer, and the touch electrode 50 may be disposed in another conductive layer. The first lead 61 and the second lead 62 may be connected to the touch electrode 50 through vias.

[0123] In one type of array substrate, leads are typically disposed between each adjacent sub-pixel; that is, a pixel unit comprising three sub-pixels has three leads, some of which serve as touch leads and others as dummy lines. Since each lead occupies space within a sub-pixel, this type of array substrate suffers from low pixel aperture ratio, affecting the improvement of display device resolution. The array substrate provided by the exemplary embodiments of this disclosure, by disposing of two touch leads between adjacent pixel units, results in only two touch leads per pixel unit. Compared to disposing of three leads in a pixel unit, this disclosure not only reduces the number of leads, increases sub-pixel space, and improves pixel aperture ratio, but also increases the light transmittance of the array substrate, which is beneficial for improving display device resolution. Furthermore, since each lead is connected to a corresponding touch electrode through a via, the consistency of the pixel structure and etching uniformity are ensured, which is beneficial for improving the quality of the fabrication process.

[0124] In an exemplary embodiment Figure 6 The structure shown is merely an illustrative example, and the structure can be modified according to actual needs. For example, the touch lead group may include three or more touch leads. Since existing array substrates place the three leads separately between sub-pixels, this disclosure places the three touch leads between adjacent pixel units, which can also increase the space of the sub-pixels, improve the pixel aperture ratio, and benefit the improvement of the display device resolution. Alternatively, two or more pixel units can be used as a repeating unit, and the touch lead group can be placed between adjacent repeating units; this disclosure does not limit this.

[0125] Figure 7a for Figure 6 Enlarged view of region A in the middle. Figure 7b for Figure 6 An enlarged view of region B. In region A, the pixel unit is the pixel unit in the m1-th pixel row and n-th pixel column; in region B, the pixel unit is the pixel unit in the m2-th pixel row and n-th pixel column. Both regions include a first sub-pixel P1, a second sub-pixel P2, and a third sub-pixel P3 arranged sequentially along the first direction X.

[0126] In an exemplary embodiment, the display area of ​​the array substrate may include at least a plurality of gate lines 20 and a plurality of data lines 30. The shape of the gate lines 20 may be a line shape extending along a first direction X. The plurality of gate lines 20 may be arranged sequentially along a second direction Y. The shape of the data lines 30 may be a line shape extending along the second direction Y. The plurality of data lines 30 may be arranged sequentially along the first direction X. The intersecting plurality of gate lines 20 and the plurality of data lines 30 define a plurality of regularly arranged sub-pixels. Each sub-pixel is provided with a thin film transistor and a pixel electrode. The thin film transistor may be connected to the gate lines 20, the data lines 30 and the pixel electrode respectively.

[0127] In an exemplary embodiment, the display area of ​​the array substrate may further include multiple touch lead groups multiplexed as common electrode lines, and multiple touch electrodes 50 multiplexed as common electrodes. Touch lead groups may be disposed between adjacent pixel units in the first direction X, and at least one touch lead group may include at least a first lead 61 and a second lead 62 arranged in parallel, with the first lead 61 and the second lead 62 respectively connected to the corresponding touch electrode 50.

[0128] In an exemplary embodiment, the thin-film transistor in each sub-pixel is configured to receive the data voltage transmitted by the data line 30 and output it to the pixel electrode under the control of the gate line 20, thereby controlling the formation of an electric field between the pixel electrode and the common electrode to drive the liquid crystal deflection and achieve grayscale display.

[0129] In an exemplary embodiment, the first lead 61 and the second lead 62 can be shaped like a broken line extending along the second direction Y. In one pixel row (such as the m1th pixel row), the first lead 61 can be connected to a touch electrode 50 through a first via K1. In another pixel row (such as the m2th pixel row), the second lead 62 can be connected to another touch electrode 50 through a second via K2.

[0130] In an exemplary embodiment, a first connecting block 61-1 may be provided on the first lead 61 in a pixel row. The first connecting block 61-1 can be connected to the corresponding touch electrode 50 through the first via K1.

[0131] In an exemplary embodiment, in a pixel row, the first lead 61 may include a first straight line segment, a second straight line segment, and a bent segment located between the first straight line segment and the second straight line segment. The first end of the bent segment is connected to the first straight line segment, and the second end of the bent segment is connected to the second straight line segment. The middle part of the bent segment may protrude in a direction away from the second lead 62. The first connecting block 61-1 may be disposed on the side of the bent segment close to the second lead 62, that is, the first connecting block 61-1 may be disposed in the area formed by the bend of the bent segment.

[0132] In an exemplary embodiment, in another pixel row, a second connecting block 62-1 may be provided on the second lead 62, and the second connecting block 62-1 may be connected to another touch electrode 50 through the second via K2.

[0133] In an exemplary embodiment, in another pixel row, the first lead 61 may include a first straight line segment, a second straight line segment, and a bent segment located between the first straight line segment and the second straight line segment. The first end of the bent segment is connected to the first straight line segment, the second end of the bent segment is connected to the second straight line segment, and the middle part of the bent segment may protrude in a direction away from the second lead 62, so that the second connecting block 62-1 can be disposed in the area formed by the bend of the bent segment.

[0134] In an exemplary embodiment, the orthographic projection of the first connecting block 61-1 on the substrate at least partially overlaps with the orthographic projection of the grid line 20 on the substrate, and the orthographic projection of the second connecting block 62-1 on the substrate at least partially overlaps with the orthographic projection of the grid line 20 on the substrate.

[0135] In an exemplary embodiment, at least one touch electrode 50 in a pixel unit may include an electrode portion 51 and a connecting portion 52. The electrode portion 51 may be disposed within the pixel unit, and the connecting portion 52 may be disposed between adjacent pixel units and connected to the electrode portion 51 in the adjacent pixel unit, thereby connecting multiple electrode portions 51 in multiple pixel units into a single unit.

[0136] In an exemplary embodiment, the connecting portion 52 may be disposed between adjacent pixel units in the first direction X, or the connecting portion 52 may be disposed between adjacent pixel units in the second direction Y, or the connecting portion 52 may be disposed between adjacent pixel units in the first direction X and adjacent pixel units in the second direction Y.

[0137] In an exemplary embodiment, the orthographic projection of the electrode portion 51 on the substrate does not overlap with the orthographic projection of the gate line 20 on the substrate, the orthographic projection of the electrode portion 51 on the substrate does not overlap with the orthographic projection of the first lead 61 on the substrate, and the orthographic projection of the electrode portion 51 on the substrate does not overlap with the orthographic projection of the second lead 62 on the substrate.

[0138] In an exemplary embodiment, the orthographic projection of the connecting portion 52 on the substrate at least partially overlaps with the orthographic projection of the gate line 20 on the substrate, the orthographic projection of the connecting portion 52 on the substrate at least partially overlaps with the orthographic projection of the first lead 61 on the substrate, and the orthographic projection of the connecting portion 52 on the substrate at least partially overlaps with the orthographic projection of the second lead 62 on the substrate.

[0139] In an exemplary embodiment, at least one connection portion 52 of one touch electrode 50 is connected to the first lead 61 through a first via K1, and at least one connection portion 52 of the other touch electrode 50 is connected to the second lead 62 through a second via K2.

[0140] In an exemplary embodiment, the orthographic projection of the first via K1 on the substrate at least partially overlaps with the orthographic projection of the gate line 20 on the substrate, and the orthographic projection of the second via K2 on the substrate at least partially overlaps with the orthographic projection of the gate line 20 on the substrate.

[0141] In an exemplary embodiment, at least one opening 53 may be provided on the electrode portion 51 in the pixel unit. The shape of the opening 53 may be a broken line extending along the second direction Y, so that the electrode portion 51 forms a plurality of strip electrodes spaced apart along the first direction X, which can ensure that a horizontal electric field is formed between the planar pixel electrode 40 and the strip common electrode (touch electrode).

[0142] The following description uses the fabrication process of an array substrate as an example. The "patterning process" described in this disclosure includes, for metallic, inorganic, or transparent conductive materials, processes such as photoresist coating, mask exposure, development, etching, and photoresist stripping; for organic materials, it includes processes such as organic material coating, mask exposure, and development. Deposition can be performed using any one or more of sputtering, evaporation, and chemical vapor deposition; coating can be performed using any one or more of spraying, spin coating, and inkjet printing; etching can be performed using any one or more of dry etching and wet etching. This disclosure does not limit the methods used. A "thin film" refers to a thin film made of a material on a substrate using deposition, coating, or other processes. If the "thin film" does not require a patterning process during the entire fabrication process, it can also be called a "layer." If the "thin film" requires a patterning process during the entire fabrication process, it is called a "thin film" before the patterning process and a "layer" after the patterning process. The "layer" after the patterning process contains at least one "pattern." The phrase "A and B are arranged in the same layer" in this disclosure means that A and B are formed simultaneously through the same patterning process, and the "thickness" of the film layer is the dimension of the film layer in the direction perpendicular to the array substrate. In the exemplary embodiments of this disclosure, "the orthographic projection of B is within the range of the orthographic projection of A" or "the orthographic projection of A includes the orthographic projection of B" means that the boundary of the orthographic projection of B falls within the boundary range of the orthographic projection of A, or the boundary of the orthographic projection of A overlaps with the boundary of the orthographic projection of B.

[0143] In an exemplary embodiment, the fabrication of the array substrate may include the following operations.

[0144] (1) Forming a first conductive layer pattern. In an exemplary embodiment, forming the first conductive layer pattern may include: depositing a first conductive thin film on a substrate, patterning the first conductive thin film using a patterning process, and forming a first conductive layer pattern on the substrate. The first conductive layer pattern includes at least gate lines 20 and gate electrodes 21, such as... Figure 8a and Figure 8b As shown, Figure 8a for Figure 6 Enlarged view of region A in the middle. Figure 8b for Figure 6 A magnified view of region B in the middle.

[0145] In an exemplary embodiment, the gate line 20 can be a straight line extending along the first direction X of the main body. The gate line 20 of each sub-pixel can be disposed on one side of the sub-pixel in the second direction Y (the position of the sub-pixel near the next row of sub-pixels). The gate line 20 is configured to be connected to the thin film transistor in the sub-pixel to provide a scan signal to the thin film transistor.

[0146] In an exemplary embodiment, the gate electrode 21 can be rectangular in shape. The gate electrode 21 can be disposed in each sub-pixel and connected to the gate line 20. This is equivalent to widening the gate line 20 in the area where the transistor is formed, so that the overlap area between the gate line 20 and the subsequently formed data line is smaller, which can reduce the parasitic capacitance between the gate line 20 and the data line and improve the electrical performance of the array substrate.

[0147] In an exemplary embodiment, the gate line 20 and the gate electrode 21 in the plurality of sub-pixels can be an integral structure interconnected with each other.

[0148] (2) Forming a semiconductor layer pattern. In an exemplary embodiment, forming a semiconductor layer pattern may include: sequentially depositing a first insulating film and a semiconductor layer film on a substrate on which the aforementioned pattern is formed; patterning the semiconductor layer film using a patterning process to form a first insulating layer covering the first conductive layer pattern; and a semiconductor layer pattern disposed on the first insulating layer, such as... Figure 9a and Figure 9b As shown, Figure 9a for Figure 6 Enlarged view of region A in the middle. Figure 9b for Figure 6 A magnified view of region B in the middle.

[0149] In an exemplary embodiment, the semiconductor layer pattern includes at least an active layer 22 disposed in each sub-pixel, and the orthographic projection of the active layer 22 on the substrate may be within the range of the orthographic projection of the gate electrode 21 on the substrate.

[0150] In an exemplary embodiment, the shape and position of the active layer 22 in each sub-pixel can be the same, which can simplify the structure of the thin-film transistor.

[0151] (3) Forming a second conductive layer pattern. In an exemplary embodiment, forming a second conductive layer pattern may include: depositing a second conductive film on a substrate having the aforementioned pattern, and patterning the second conductive film using a patterning process to form a second conductive layer pattern, such as... Figure 10a and Figure 10b As shown, Figure 10a for Figure 6 Enlarged view of region A in the middle. Figure 10b for Figure 6 A magnified view of region B in the middle.

[0152] In an exemplary embodiment, the second conductive layer pattern includes at least: a source electrode 23, a drain electrode 24, a data line 30, a first lead 61, and a second lead 62.

[0153] In an exemplary embodiment, the data line 30, the first lead 61 and the second lead 62 can be in the shape of a broken line extending along the second direction Y of the main body portion, and the extension directions of each broken line in the data line 30, the first lead 61 and the second lead 62 can be substantially the same.

[0154] In an exemplary embodiment, each sub-pixel is provided with a data line 30, which can be located on the side (left side) opposite to the first direction X of each sub-pixel. The data line 30 is configured to connect to the thin-film transistor in the sub-pixel and provide a data signal to the thin-film transistor.

[0155] In an exemplary embodiment, the source electrode 23 and the drain electrode 24 can be disposed in each sub-pixel. A portion of the data line 30 serves as the source electrode 23 of each sub-pixel, and the drain electrode 24 of each sub-pixel can be a separately disposed "L" shape. The source electrode 23 is connected to the active layer 22, the first end of the drain electrode 24 is connected to the active layer 22, and the second end of the drain electrode 24 extends away from the active layer 22 and is configured to be connected to the pixel electrode formed subsequently. A conductive channel is formed between the source electrode 23 and the drain electrode 24.

[0156] In an exemplary embodiment, the gate electrode 21, active layer 22, source electrode 23 and drain electrode 24 in each sub-pixel constitute a thin film transistor. The gate electrode 21 is connected to the gate line, the source electrode 23 is connected to the data line 30, and the drain electrode 24 is connected to the pixel electrode.

[0157] In an exemplary embodiment, the first lead 61 and the second lead 62 may be disposed between adjacent pixel units in the first direction X. The first lead 61 and the second lead 62 are configured to be connected to a subsequently formed touch electrode (multiplexed as a common electrode) to provide a touch signal or a common voltage signal to the touch electrode.

[0158] In an exemplary embodiment, the first lead 61 and the second lead 62 may be disposed between the (n-1)th pixel column and the nth pixel column, and between the nth pixel column and the (n+1)th pixel column. For the nth pixel column, the first lead 61 may be disposed on the side of the third sub-pixel P3 away from the first sub-pixel P1, and the second lead 62 may be disposed on the side of the first lead 61 away from the first sub-pixel P1.

[0159] like Figure 10a As shown, in the m1-th pixel row, the shape of the first lead 61 between the n-th pixel column and the (n+1)-th pixel column is different from the shape of the first lead 61 between other adjacent pixel columns, while the shape of the second lead 62 is basically the same as the shape of the second lead 62 between other adjacent pixel columns.

[0160] In an exemplary embodiment, the first lead 61 may include a first straight segment 61A, a second straight segment 61B, and a bent segment 61C located between the first straight segment 61A and the second straight segment 61B. A first connecting block 61-1 is provided on the first lead 61, and the first connecting block 61-1 is configured to be connected to a subsequently formed touch electrode through a via.

[0161] In an exemplary embodiment, the first end of the bent segment 61C is connected to the first straight segment 61A, the second end of the bent segment 61C is connected to the second straight segment 61B, the middle part of the bent segment 61C can protrude in the opposite direction of the first direction X (away from the second lead 62), and the first connecting block 61-1 is disposed on the side of the bent segment 61C in the first direction X (near the second lead 62), that is, the first connecting block 61-1 is disposed in the area formed by the bending of the bent segment 61C.

[0162] In an exemplary embodiment, the first straight segment 61A, the second straight segment 61B, the bent segment 61C, and the first connecting block 61-1 can be an integral structure that is interconnected.

[0163] In an exemplary embodiment, the orthographic projection of the bent segment 61C on the substrate at least partially overlaps with the orthographic projection of the gate line 20 on the substrate, and the orthographic projection of the first connecting block 61-1 on the substrate at least partially overlaps with the orthographic projection of the gate line 20 on the substrate, such that the connection point of the first lead 61 and the touch electrode is located in the non-aperture region of the sub-pixel, thereby improving the aperture ratio of the sub-pixel.

[0164] like Figure 10b As shown, in the m2-th pixel row, the shape of the first lead 61 between the n-th pixel column and the (n+1)-th pixel column is different from the shape of the first lead 61 between other adjacent pixel columns, and the shape of the second lead 62 is different from the shape of the second lead 62 between other adjacent pixel columns.

[0165] In an exemplary embodiment, the second lead 62 may be provided with a second connecting block 62-1, which is configured to connect to another touch electrode subsequently formed through a via. The second connecting block 62-1 may be located on the side opposite to the first direction X of the second lead 62 (towards the first lead 61), and the shape of the second connecting block 62-1 may be a trapezoidal shape protruding towards the first lead 61.

[0166] In an exemplary embodiment, the first lead 61 may include a first straight segment 61A, a second straight segment 61B, and a bent segment 61C located between the first straight segment 61A and the second straight segment 61B. The first end of the bent segment 61C is connected to the first straight segment 61A, and the second end of the bent segment 61C is connected to the second straight segment 61B. The middle portion of the bent segment 61C may protrude in the opposite direction to the first direction X, allowing the second connecting block 62-1 to be disposed within the area formed by the bend in the bent segment 61C.

[0167] In an exemplary embodiment, the orthographic projection of the second connecting block 62-1 on the substrate at least partially overlaps with the orthographic projection of the gate line 20 on the substrate, such that the connection point of the second lead 61 and the touch electrode is located in the non-aperture region of the sub-pixel, thereby improving the aperture ratio of the sub-pixel.

[0168] In an exemplary embodiment, the first straight segment 61A, the second straight segment 61B, and the bent segment 61C can be an integral structure that is interconnected.

[0169] In an exemplary embodiment, the second lead 62 and the second connecting block 62-1 can be an integral structure that is interconnected.

[0170] In an exemplary embodiment, the shapes of the first straight line segment 61A, the second straight line segment 61B, and the bent segment 61C in the first lead 61 located between the nth pixel column and the (n+1)th pixel column can be substantially the same in the m1th pixel row and the m2th pixel row.

[0171] (4) Forming a second insulating layer pattern. In an exemplary embodiment, forming a second insulating layer pattern may include: depositing a second insulating film on a substrate having the aforementioned pattern, patterning the second insulating film using a patterning process to form a second insulating layer pattern covering the second conductive pattern, wherein a plurality of vias are formed on the second insulating layer, such as... Figure 11a and Figure 11b As shown, Figure 11a for Figure 6 Enlarged view of region A in the middle. Figure 11b for Figure 6 A magnified view of region B in the middle.

[0172] In an exemplary embodiment, the plurality of vias may include at least a connection via K disposed in each sub-pixel. The orthographic projection of the connection via K onto the substrate may be within the range of the orthographic projection of the drain electrode 24 onto the substrate. The second insulating layer within the connection via K is etched away, exposing the surface of the drain electrode 24. The connection via K is configured to allow a subsequently formed pixel electrode to be connected to the drain electrode 24 through the via.

[0173] In an exemplary embodiment, the shape of the connecting via K can be any one or more of the following: square, rectangle, circle, and ellipse.

[0174] (5) Forming a third conductive layer pattern. In an exemplary embodiment, forming a third conductive layer pattern may include: depositing a third conductive film on a substrate having the aforementioned pattern, patterning the third conductive film using a patterning process, and forming the third conductive layer pattern on a second insulating layer, such as... Figure 12a and Figure 12b As shown, Figure 12a for Figure 6 Enlarged view of region A in the middle. Figure 12b for Figure 6 A magnified view of region B in the middle.

[0175] In an exemplary embodiment, the third conductive layer pattern may include at least a pixel electrode 40 disposed in each sub-pixel.

[0176] In an exemplary embodiment, the pixel electrode 40 in each sub-pixel can be in the shape of a whole surface, located in the area enclosed by the gate line 20 and the data line 30, and the orthographic projection of the pixel electrode 40 on the substrate at least partially overlaps with the orthographic projection of the drain electrode 24 on the substrate. The pixel electrode 40 is connected to the drain electrode 24 of the thin film transistor through a connecting via K.

[0177] (6) Forming a third insulating layer pattern. In an exemplary embodiment, forming a third insulating layer pattern may include: depositing a third insulating film on a substrate having the aforementioned pattern, patterning the third insulating film using a patterning process to form a third insulating layer pattern covering the third conductive pattern, wherein a plurality of vias are formed on the third insulating layer, such as... Figure 13a and Figure 13b As shown, Figure 13a for Figure 6 Enlarged view of region A in the middle. Figure 13b for Figure 6 A magnified view of region B in the middle.

[0178] In an exemplary embodiment, the plurality of vias may include at least a first via K1 disposed in the m1 pixel row and n pixel column and a second via K2 disposed in the m2 pixel row and n pixel column.

[0179] In an exemplary embodiment, the orthographic projection of the first via K1 on the substrate may be within the range of the orthographic projection of the first connecting block 61-1 of the first lead 61 on the substrate. The second and third insulating layers in the first via K1 are etched away, exposing the surface of the first connecting block 61-1. The first via K1 is configured to allow a subsequently formed touch electrode to be connected to the first connecting block 61-1 through the via.

[0180] In an exemplary embodiment, the orthographic projection of the first via K1 on the substrate at least partially overlaps with the orthographic projection of the gate line 20 on the substrate, such that the connection point of the first lead 61 and the touch electrode is located in the non-aperture region of the sub-pixel, thereby improving the aperture ratio of the sub-pixel.

[0181] In an exemplary embodiment, the orthogonal projection of the second via K2 on the substrate may be within the range of the orthogonal projection of the second connecting block 62-1 of the second lead 62 on the substrate. The second insulating layer and the third insulating layer in the second via K2 are etched away, exposing the surface of the second connecting block 62-1. The second via K2 is configured to allow another touch electrode formed subsequently to be connected to the second connecting block 62-1 through the via.

[0182] In an exemplary embodiment, the orthographic projection of the second via K2 on the substrate at least partially overlaps with the orthographic projection of the gate line 20 on the substrate, such that the connection point of the second lead 62 and the touch electrode is located in the non-aperture region of the sub-pixel, thereby improving the aperture ratio of the sub-pixel.

[0183] In an exemplary embodiment, the shape of the first via K1 and the second via K2 can be any one or more of the following: square, rectangle, circle, and ellipse.

[0184] (7) Forming a fourth conductive layer pattern. In an exemplary embodiment, forming a fourth conductive layer pattern may include: depositing a fourth conductive film on a substrate having the aforementioned pattern, patterning the fourth conductive film using a patterning process, and forming the fourth conductive layer pattern on a third insulating layer, such as... Figure 7a and Figure 7b As shown.

[0185] In an exemplary embodiment, the fourth conductive layer pattern includes at least a plurality of touch electrodes 50 arranged in a regular pattern, and the plurality of touch electrodes 50 are reused as a common electrode.

[0186] In an exemplary embodiment, the touch electrode 50 covering the m1-th pixel row and the nth pixel column is connected to the first connecting block 61-1 through the first via K1. Since the first connecting block 61-1 is connected to the first lead 61, the first lead 61 is connected to a touch electrode 50, and the first lead 61 can provide a touch signal or a common voltage signal to the touch electrode 50.

[0187] In an exemplary embodiment, the touch electrode 50 covering the m2-th pixel row and n-th pixel column is connected to the second connecting block 62-1 through the second via K2. Since the second connecting block 62-1 is connected to the second lead 62, the second lead 62 is connected to another touch electrode 50, and the second lead 62 can provide a touch signal or a common voltage signal to the touch electrode 50.

[0188] In an exemplary embodiment, in at least one pixel unit, the touch electrode 50 may include an electrode portion 51 and a connecting portion 52. The electrode portion 51 may be disposed within the pixel unit, that is, the electrode portion 51 may be disposed within the area enclosed by the first lead 61, the second lead 62, and the two gate lines 20. The connecting portion 52 may be disposed between adjacent pixel units and connected to the electrode portion 51 within the adjacent pixel unit, thereby connecting multiple electrode portions 51 within multiple pixel units into a single block-shaped touch electrode 50.

[0189] In an exemplary embodiment, the connecting portion 52 may be disposed between adjacent pixel units in the first direction X to connect multiple electrode portions 51 in a pixel row into one unit; or, the connecting portion 52 may be disposed between adjacent pixel units in the second direction Y to connect multiple electrode portions 51 in a pixel column into one unit; or, the connecting portion 52 may be disposed between adjacent pixel units in the first direction X and between adjacent pixel units in the second direction Y to connect multiple electrode portions 51 in multiple pixel rows and multiple pixel columns into one unit.

[0190] In an exemplary embodiment, the orthographic projection of the electrode portion 51 on the substrate does not overlap with the orthographic projection of the gate line 20 on the substrate, the orthographic projection of the electrode portion 51 on the substrate does not overlap with the orthographic projection of the first lead 61 on the substrate, and the orthographic projection of the electrode portion 51 on the substrate does not overlap with the orthographic projection of the second lead 62 on the substrate, so as to reduce the influence of the signals transmitted by the gate line 20, the first lead 61 and the second lead 62 on the touch electrode (common electrode).

[0191] In an exemplary embodiment, the orthographic projection of the connecting portion 52 on the substrate at least partially overlaps with the orthographic projection of the gate line 20 on the substrate, the orthographic projection of the connecting portion 52 on the substrate at least partially overlaps with the orthographic projection of the first lead 61 on the substrate, and the orthographic projection of the connecting portion 52 on the substrate at least partially overlaps with the orthographic projection of the second lead 62 on the substrate.

[0192] In an exemplary embodiment, at least one connection portion 52 of one touch electrode 50 can be connected to the first connection block 61-1 through a first via K1, and at least one connection portion 52 of another touch electrode 50 can be connected to the second connection block 62-1 through a second via K2, so that the connection points of the first lead 61 and the second lead 62 with the touch electrode are both located in the non-aperture area of ​​the sub-pixel, thereby improving the aperture ratio of the sub-pixel.

[0193] In an exemplary embodiment, at least one opening 53 may be provided on the electrode portion 51 in the pixel unit, and the fourth conductive film within the opening 53 is etched away to expose the third insulating layer. The shape of the opening 53 may be a zigzag line extending along the second direction Y, such that the electrode portion 51 forms a plurality of strip electrodes spaced apart along the first direction X, which can ensure that a horizontal electric field is formed between the planar pixel electrode 40 and the strip-shaped common electrode (touch electrode).

[0194] In an exemplary embodiment, the substrate can be glass or quartz, etc. The first and second conductive layers can be made of metallic materials, such as any one or more of silver (Ag), copper (Cu), aluminum (Al), and molybdenum (Mo), or alloys of the above metals, such as aluminum-neodymium alloy (AlNd) or molybdenum-niobium alloy (MoNb). They can be single-layer structures or multi-layer composite structures, such as Mo / Cu / Mo. The first conductive layer can be called a gate metal layer, and the second conductive layer can be called a source-drain metal layer (SD). The third and fourth conductive layers can be made of transparent conductive materials, such as indium tin oxide (ITO) or indium zinc oxide (IZO). The first, second, and third insulating layers can be made of any one or more of silicon oxide (SiOx), silicon nitride (SiNx), and silicon oxynitride (SiON), and can be single-layer, multi-layer, or composite layers. The first insulating layer can be called a gate insulating layer (GI), the second insulating layer can be called an interlayer insulating layer (ILD), and the third insulating layer can be called a passivation (PVX) layer. The active layer can be made of amorphous indium gallium zinc oxide (a-IGZO), zinc oxynitride (ZnON), indium zinc tin oxide (IZTO), amorphous silicon (a-Si), polycrystalline silicon (p-Si), hexathiophene, or polythiophene, etc. That is, this disclosure applies to transistors manufactured based on oxide technology, silicon technology, or organic technology.

[0195] This completes the fabrication of the array substrate according to the exemplary embodiments of this disclosure. On a plane perpendicular to the array substrate, the array substrate may include a first conductive layer disposed on a substrate, a first insulating layer disposed on the side of the first conductive layer away from the substrate, a semiconductor layer disposed on the side of the first insulating layer away from the substrate, a second conductive layer disposed on the side of the semiconductor layer away from the substrate, a second insulating layer disposed on the side of the second conductive layer away from the substrate, a third conductive layer disposed on the side of the second insulating layer away from the substrate, a fourth insulating layer disposed on the side of the third conductive layer away from the substrate, and a fourth conductive layer disposed on the side of the fourth insulating layer away from the substrate. On a plane parallel to the array substrate, the array substrate may include multiple sub-pixels. Each sub-pixel may include a thin-film transistor, a pixel electrode, and a touch electrode multiplexed as a common electrode. The thin-film transistor may include a gate electrode, an active layer, a first electrode, and a second electrode. The gate electrode is connected to a gate line, the first electrode is connected to a data line, the second electrode is connected to the pixel electrode, and the touch electrode is connected to a first lead or a second lead. A horizontal electric field is formed between the pixel electrode and the common electrode.

[0196] As can be seen from the structure and fabrication process of the array substrate in the exemplary embodiments of this disclosure, by setting touch lead groups between adjacent pixel units, the touch lead groups may include first and second leads arranged in parallel, which not only reduces the number of leads, increases the space of sub-pixels, and improves the pixel aperture ratio, which is beneficial to improving the resolution of the display device, but also ensures the consistency of the pixel structure and the uniformity of etching since each lead is connected to the corresponding touch electrode through a via, which is beneficial to improving the quality of the fabrication process.

[0197] Figure 14 This is a schematic diagram of a planar structure of a binding region and a border region, as an exemplary embodiment of this disclosure. Figure 14 As shown, the array substrate may include a display area 100, a bonding area 200 located on one side of the display area 100, an upper bezel area 310 located on the side of the display area 100 away from the bonding area 200, and side bezel areas 320 located on both sides of the display area 100.

[0198] In an exemplary embodiment, the display area 100 may include at least a plurality of touch electrodes 50 constituting a touch array and a plurality of pixel units 60 constituting a pixel array. At least one pixel unit 60 may include three sub-pixels. At least one sub-pixel may include a thin film transistor 10, a gate line 20, a data line 30 and a pixel electrode 40. The thin film transistor 10 is connected to the gate line 20, the data line 30 and the pixel electrode 40 respectively. The touch electrodes 50 may be reused as a common electrode.

[0199] In an exemplary embodiment, the display area 100 may further include a plurality of touch lead groups, which are respectively disposed between adjacent pixel columns. At least one touch lead group may include at least a first lead 61 and a second lead 62 disposed in parallel. The first lead 61 and the second lead 62 are multiplexed as a common electrode line. The first lead 61 may be connected to the touch electrodes 50 in an odd number of touch rows, and the second lead 62 may be connected to the touch electrodes 50 in an even number of touch rows.

[0200] In an exemplary embodiment, the bonding area 200 may include at least a driver chip 280 and multiple pins. The driver chip 280 can be connected to multiple data lines and multiple touch leads (first leads and second leads) in the display area via multiple connection lines. During normal display, the driver chip 280 is configured to provide data signals and touch signals to the multiple data lines and multiple touch leads, respectively.

[0201] In an exemplary embodiment, the plurality of pins of the bonding region 200 may include at least one or more of the following: a first test pin 210, a second test pin 220, a first data pin 230, a second data pin 240, a third data pin 250, a switch control pin 260, and a gate line control pin 270. During testing, the plurality of pins are configured to be bonded to an external test device, causing the external test device to output corresponding signals to the corresponding signal lines.

[0202] In an exemplary embodiment, the first test pin 210, the first data pin 230, the switch control pin 260, and the gate line control pin 270 may be located on the opposite side of the first direction X of the bonding region 200, and the second test pin 220, the second data pin 240, the third data pin 250, and the gate line control pin 270 may be located on the first direction X of the bonding region 200.

[0203] In an exemplary embodiment, the first test pin 210, the first data pin 230, the switch control pin 260, and the gate line control pin 270 can be arranged sequentially along the first direction X, and the gate line control pin 270, the second data pin 240, the third data pin 250, and the second test pin 220 can be arranged sequentially along the first direction X.

[0204] In an exemplary embodiment, the upper bezel area 310 may include at least a test circuit. The array substrate of this disclosure arranges touch lead groups between adjacent pixel units. Multiple leads in the touch lead groups are adjacent to each other. When a short circuit occurs between adjacent leads due to process defects or dust (particles), it may cause abnormal touch functionality. To screen out such defects before assembling the module, this disclosure provides a test circuit in the upper bezel area 310, configured to detect short-circuit defects in the array substrate.

[0205] In an exemplary embodiment, the test circuit may include a plurality of test units 70, which may be arranged sequentially along the first direction X, and the positions of the plurality of test units 70 correspond one-to-one with the positions of the plurality of touch columns in the display area 100.

[0206] In an exemplary embodiment, at least one test unit may include at least a first test line 71, a second test line 72, a first data lead 73, a second data lead 74, a third data lead 75, a switch control line 76, a first switch 91, a second switch 92, a third switch 93, a fourth switch 94, and a fifth switch 95.

[0207] In an exemplary embodiment, the switch control line 76, the first data lead 73, the second data lead 74, the third data lead 75, the second test line 72, and the first test line 71 can be arranged sequentially along a direction away from the display area, and all of the above signal lines are line shapes extending along the first direction X.

[0208] In an exemplary embodiment, the third switch 93, the fourth switch 94, the fifth switch 95, the first switch 91, and the second switch 92 can be arranged sequentially along the first direction X.

[0209] In an exemplary embodiment, the first pole of the first switch 91 is connected to the first test line 71, the second pole of the first switch 91 is connected to the first lead 61 in the display area 100, and the control pole of the first switch 91 is connected to the switch control line 76. That is, the first test line 71 is connected to the first lead 61 in the display area 100 through the first switch 91. The first test line 71 is configured to transmit a first test signal to the first lead 61 under the control of the switch control line 76 and the first switch 91.

[0210] In an exemplary embodiment, the first pole of the second switch 92 is connected to the second test line 72, the second pole of the second switch 92 is connected to the second lead 62 in the display area 100, and the control pole of the second switch 92 is connected to the switch control line 76. That is, the second test line 72 is connected to the second lead 62 in the display area 100 through the second switch 92. The second test line 72 is configured to transmit a second test signal to the second lead 62 under the control of the switch control line 76 and the second switch 92.

[0211] In an exemplary embodiment, the voltage value of the first test signal is greater than the voltage value of the second test signal, or the voltage value of the first test signal is less than the voltage value of the second test signal, that is, the voltage values ​​of the first test signal and the second test signal are not equal.

[0212] In an exemplary embodiment, the first pole of the third switch 93 is connected to the first data lead 73, the second pole of the third switch 93 is connected to the data line 30 of the first sub-pixel in the display area 100, and the control pole of the third switch 93 is connected to the switch control line 76. That is, the first data lead 73 is connected to the data line 30 of the first sub-pixel in the display area 100 through the third switch 93. The first data lead 73 is configured to transmit a first data signal to the data line 30 of the first sub-pixel under the control of the switch control line 76 and the third switch 93.

[0213] In an exemplary embodiment, the first pole of the fourth switch 94 is connected to the second data lead 74, the second pole of the fourth switch 94 is connected to the data line 30 of the second sub-pixel in the display area 100, and the control pole of the fourth switch 94 is connected to the switch control line 76. That is, the second data lead 74 is connected to the data line 30 of the second sub-pixel in the display area 100 through the fourth switch 94. The second data lead 74 is configured to transmit a second data signal to the data line 30 of the second sub-pixel under the control of the switch control line 76 and the fourth switch 94.

[0214] In an exemplary embodiment, the first pole of the fifth switch 95 is connected to the third data lead 75, the second pole of the fifth switch 95 is connected to the data line 30 of the third sub-pixel in the display area 100, and the control pole of the fifth switch 95 is connected to the switch control line 76. That is, the third data lead 75 is connected to the data line 30 of the third sub-pixel in the display area 100 through the fifth switch 95. The third data lead 75 is configured to transmit a third data signal to the data line 30 of the third sub-pixel under the control of the switch control line 76 and the fifth switch 95.

[0215] In an exemplary embodiment, the first switch 91, the second switch 92, the third switch 93, the fourth switch 94, and the fifth switch 95 may be thin-film transistors.

[0216] In an exemplary embodiment, the side bezel area 320 may include at least a gate driving circuit 330 and multiple connecting lines, and the gate driving circuit 330 may be disposed on the side of the multiple connecting lines close to the display area.

[0217] In an exemplary embodiment, the side bezel region 320 may include a left bezel and a right bezel. The left bezel may include at least a gate drive circuit 330, a first connection line 81, a third connection line 83, and a sixth connection line 86, and the right bezel may include at least a gate drive circuit 330, a second connection line 82, a fourth connection line 84, and a fifth connection line 85.

[0218] In an exemplary embodiment, the test terminals of the gate driving circuit 330 disposed within the left and right bezels are respectively connected to the gate line control pins 270 in the bonding area 200 via connecting lines, and the output terminals of the gate driving circuit 330 are respectively connected to multiple gate lines 20 in the display area 100. During testing, the test terminals and output terminals of the gate driving circuit 330 are connected, and the gate driving circuit 330 is configured to output an enable voltage to the multiple gate lines 20 in the display area 100.

[0219] In an exemplary embodiment, the first end of the first connecting line 81 is connected to the first test pin 210 in the bonding area 200, and the second end of the first connecting line 81 extends toward the upper frame area 310 and is connected to the first test line 71 in the upper frame area 310, thereby realizing the connection between the first test line 71 and the first test pin 210.

[0220] In an exemplary embodiment, the first end of the second connecting line 82 is connected to the second test pin 220 in the bonding area 200, and the second end of the second connecting line 82 extends toward the upper frame area 310 and is connected to the second test line 72 in the upper frame area 310, thereby realizing the connection between the second test line 72 and the second test pin 220.

[0221] In an exemplary embodiment, the first end of the third connection line 83 is connected to the first data pin 230 in the bonding area 200, and the second end of the third connection line 83 extends toward the upper frame area 310 and is connected to the first data lead 73 in the upper frame area 310, thereby realizing the connection between the first data lead 73 and the first data pin 230.

[0222] In an exemplary embodiment, the first end of the fourth connection line 84 is connected to the second data pin 240 in the bonding area 200, and the second end of the fourth connection line 84 extends toward the upper frame area 310 and is connected to the second data lead 74 in the upper frame area 310, thereby realizing the connection between the second data lead 74 and the second data pin 240.

[0223] In an exemplary embodiment, the first end of the fifth connection line 85 is connected to the third data pin 250 in the bonding area 200, and the second end of the fifth connection line 85 extends toward the upper frame area 310 and is connected to the third data lead 75 in the upper frame area 310, thereby realizing the connection between the third data lead 75 and the third data pin 250.

[0224] In an exemplary embodiment, the first end of the sixth connecting line 86 is connected to the switch control pin 260 in the bonding area 200, and the second end of the sixth connecting line 86 extends toward the upper frame area 310 and is connected to the switch control line 76 in the upper frame area 310, thereby realizing the connection between the switch control line 76 and the switch control pin 260.

[0225] In an exemplary embodiment, the fabrication of the test circuit of this disclosure may include the following operations.

[0226] (11) When forming the first conductive layer pattern in the display area, the first conductive layer pattern further includes a first test line 71, a second test line 72, a first data lead 73, a second data lead 74, a third data lead 75, and a control line group located in the upper border area, such as... Figure 15 As shown.

[0227] In an exemplary embodiment, the control line group, the first data lead 73, the second data lead 74, the third data lead 75, the second test line 72, and the first test line 71 can be arranged sequentially along a direction away from the display area.

[0228] In an exemplary embodiment, the control line group may include at least a first control line 76-1, a second control line 76-2, a third control line 76-3, a fourth control line 76-4, and a fifth control line 76-5 arranged sequentially along a direction away from the display area.

[0229] In an exemplary embodiment, a plurality of first gate blocks 111 and a plurality of second gate blocks 112 may be disposed between the third control line 76-3 and the fifth control line 76-5. The first ends of the plurality of first gate blocks 111 and the plurality of second gate blocks 112 are connected to the third control line 76-3, the second ends of the plurality of first gate blocks 111 and the plurality of second gate blocks 112 are connected to the fifth control line 76-5, and the middle portions of the plurality of first gate blocks 111 and the plurality of second gate blocks 112 are connected to the fourth control line 76-4, such that the third control line 76-3, the fourth control line 76-4 and the fifth control line 76-5 are connected into an integral structure through the plurality of first gate blocks 111 and the plurality of second gate blocks 112. The plurality of first gate blocks 111 are configured as gate electrodes of the first switch 91, and the plurality of second gate blocks 112 are configured as gate electrodes of the second switch 92.

[0230] In an exemplary embodiment, a plurality of fourth gate blocks 114 may be provided between the fourth control line 76-4 and the fifth control line 76-5. The first end of the plurality of fourth gate blocks 114 is connected to the fourth control line 76-4, and the second end of the plurality of fourth gate blocks 114 is connected to the fifth control line 76-5. The plurality of fourth gate blocks 114 are configured as gate electrodes of the fourth switch 94.

[0231] In an exemplary embodiment, a plurality of third gate blocks 113 and a plurality of fifth gate blocks 115 may be disposed between the first control line 76-1 and the second control line 76-2. The first ends of the plurality of third gate blocks 113 and the plurality of fifth gate blocks 115 are connected to the first control line 76-1, and the second ends of the plurality of third gate blocks 113 and the plurality of fifth gate blocks 115 are connected to the second control line 76-2, so that the first control line 76-1 and the second control line 76-2 are connected into an integral structure through the plurality of third gate blocks 113 and the plurality of fifth gate blocks 115. The plurality of third gate blocks 113 are configured as gate electrodes of the third switch 93, and the plurality of fifth gate blocks 115 are configured as gate electrodes of the fifth switch 95.

[0232] This disclosure uses multiple control lines and multiple gate blocks to form a control line group, which can effectively reduce the area occupied by the switch and reduce the bezel width, thus facilitating the achievement of a narrow bezel.

[0233] (12) When forming a semiconductor layer pattern in the display area, the semiconductor layer pattern further includes a first active layer 121, a second active layer 122, a third active layer 123, a fourth active layer 124, and a fifth active layer 125 located in the upper border area, such as Figure 16 As shown.

[0234] In an exemplary embodiment, the orthographic projection of the first active layer 121 onto the substrate may be within the range of the orthographic projection of the first gate block 111 onto the substrate, and the first active layer 121 is configured as the active layer of the first switch 91.

[0235] In an exemplary embodiment, the orthographic projection of the second active layer 122 onto the substrate may be within the range of the orthographic projection of the second gate block 112 onto the substrate, and the second active layer 122 is configured as the active layer of the second switch 92.

[0236] In an exemplary embodiment, the orthogonal projection of the third active layer 123 onto the substrate may be within the range of the orthogonal projection of the third gate block 113 onto the substrate, and the third active layer 123 is configured as the active layer of the third switch 93.

[0237] In an exemplary embodiment, the orthographic projection of the fourth active layer 124 onto the substrate may be within the range of the orthographic projection of the fourth gate block 114 onto the substrate, and the fourth active layer 124 is configured as the active layer of the fourth switch 94.

[0238] In an exemplary embodiment, the orthographic projection of the fifth active layer 125 onto the substrate may be within the range of the orthographic projection of the fifth gate block 115 onto the substrate, and the fifth active layer 125 is configured as the active layer of the fifth switch 95.

[0239] (13) When forming the second conductive layer pattern in the display area, the second conductive layer pattern further includes a first source electrode 131, a second source electrode 132, a third source electrode 133, a fourth source electrode 134, a fifth source electrode 135, a first drain electrode 141, a second drain electrode 142, a third drain electrode 143, a fourth drain electrode 144, a fifth drain electrode 145, a first overlapping block 151, a second overlapping block 152, a third overlapping block 153, a fourth overlapping block 154, and a fifth overlapping block 155 located in the upper border area, such as Figure 17 As shown.

[0240] In an exemplary embodiment, the first end of the first source electrode 131 is connected to the first active layer 121, and the second end of the first source electrode 131 extends away from the display area and is connected to the first overlap block 151. The first overlap block 151 can be disposed on the side of the first test line 71 near the display area, and the first overlap block 151 is configured to connect with the subsequently formed first overlap electrode. The first end of the first drain electrode 141 is connected to the first active layer 121, and the second end of the first drain electrode 141 extends towards the display area and is connected to the first lead of the display area. A conductive channel is formed between the first source electrode 131 and the first drain electrode 141, and the first gate block 111, the first active layer 121, the first source electrode 131, and the first drain electrode 141 constitute the first switch 91.

[0241] In an exemplary embodiment, the first end of the second source electrode 132 is connected to the second active layer 122, and the second end of the second source electrode 132 extends away from the display area and is connected to the second overlap block 152. The second overlap block 152 can be disposed on the side of the second test line 72 near the display area, and the second overlap block 152 is configured to connect with the subsequently formed second overlap electrode. The first end of the second drain electrode 142 is connected to the second active layer 122, and the second end of the second drain electrode 142 extends towards the display area and is connected to the second lead of the display area. A conductive channel is formed between the second source electrode 132 and the second drain electrode 142. The second gate block 112, the second active layer 122, the second source electrode 132, and the second drain electrode 142 constitute the second switch 92.

[0242] In an exemplary embodiment, the first end of the third source electrode 133 is connected to the third active layer 123, and the second end of the third source electrode 133 extends away from the display area and is connected to the third overlap block 153. The third overlap block 153 can be disposed on the side of the first data lead 73 near the display area, and the third overlap block 153 is configured to be connected to the subsequently formed third overlap electrode. The first end of the third drain electrode 143 is connected to the third active layer 123, and the second end of the third drain electrode 143 extends towards the display area and is connected to the data line of the first sub-pixel in the display area. A conductive channel is formed between the third source electrode 133 and the third drain electrode 143, and the third gate block 113, the third active layer 123, the third source electrode 133, and the third drain electrode 143 constitute the third switch 93.

[0243] In an exemplary embodiment, the first end of the fourth source electrode 134 is connected to the fourth active layer 124, and the second end of the fourth source electrode 134 extends away from the display area and is connected to the fourth overlap block 154. The fourth overlap block 154 can be disposed on the side of the second data lead 74 near the display area, and the fourth overlap block 154 is configured to connect with the subsequently formed fourth overlap electrode. The first end of the fourth drain electrode 144 is connected to the fourth active layer 124, and the second end of the fourth drain electrode 144 extends towards the display area and is connected to the data line of the second sub-pixel in the display area. A conductive channel is formed between the fourth source electrode 134 and the fourth drain electrode 144, and the fourth gate block 114, the fourth active layer 124, the fourth source electrode 134, and the fourth drain electrode 144 constitute the fourth switch 94.

[0244] In an exemplary embodiment, the first end of the fifth source electrode 135 is connected to the fifth active layer 125, and the second end of the fifth source electrode 135 extends away from the display area and is connected to the fifth overlap block 155. The fifth overlap block 155 can be disposed on the side of the third data lead 75 near the display area, and the fifth overlap block 155 is configured to connect with the subsequently formed fifth overlap electrode. The first end of the fifth drain electrode 145 is connected to the fifth active layer 125, and the second end of the fifth drain electrode 145 extends towards the display area and is connected to the data line of the third sub-pixel in the display area. A conductive channel is formed between the fifth source electrode 135 and the fifth drain electrode 145, and the fifth gate block 115, the fifth active layer 125, the fifth source electrode 135, and the fifth drain electrode 145 constitute the fifth switch 95.

[0245] (14) When forming the second insulating layer pattern in the display area, the multiple vias on the second insulating layer also include the eleventh via V11, the twelfth via V12, the thirteenth via V13, the fourteenth via V14, the fifteenth via V15, the sixteenth via V16, the seventeenth via V17, the eighteenth via V18, the nineteenth via V19, and the twentieth via V20 located in the upper frame area, such as... Figure 18 As shown.

[0246] In an exemplary embodiment, the orthographic projection of the eleventh via V11 on the substrate may be within the range of the orthographic projection of the first lap block 151 on the substrate. The eleventh via V11 exposes the surface of the first lap block 151. The eleventh via V11 is configured to allow the subsequently formed first lap electrode to be connected to the first lap block 151 through the via.

[0247] In an exemplary embodiment, the orthographic projection of the twelfth via V12 on the substrate may be within the range of the orthographic projection of the second overlap block 152 on the substrate. The twelfth via V12 exposes the surface of the second overlap block 152. The twelfth via V12 is configured to allow a subsequently formed second overlap electrode to be connected to the second overlap block 152 through the via.

[0248] In an exemplary embodiment, the orthographic projection of the thirteenth via V13 on the substrate may be within the range of the orthographic projection of the third lap block 153 on the substrate. The thirteenth via V13 exposes the surface of the third lap block 153. The thirteenth via V13 is configured to allow the subsequently formed third lap electrode to be connected to the third lap block 153 through the via.

[0249] In an exemplary embodiment, the orthographic projection of the fourteenth via V14 on the substrate may be within the range of the orthographic projection of the fourth overlap block 154 on the substrate. The fourteenth via V14 exposes the surface of the fourth overlap block 154. The fourteenth via V14 is configured to allow the subsequently formed fourth overlap electrode to be connected to the fourth overlap block 154 through the via.

[0250] In an exemplary embodiment, the orthographic projection of the fifteenth via V15 on the substrate may be within the range of the orthographic projection of the fifth overlap block 155 on the substrate. The fifteenth via V15 exposes the surface of the fifth overlap block 155. The fifteenth via V15 is configured to allow the subsequently formed fifth overlap electrode to be connected to the fifth overlap block 155 through the via.

[0251] In an exemplary embodiment, the orthographic projection of the sixteenth via V16 on the substrate may be within the range of the orthographic projection of the first test line 71 on the substrate. The sixteenth via V16 exposes the surface of the first test line 71 and is configured to allow the subsequently formed first lap electrode to be connected to the first test line 71 through the via.

[0252] In an exemplary embodiment, the orthographic projection of the seventeenth via V17 on the substrate may be within the range of the orthographic projection of the second test line 72 on the substrate. The seventeenth via V17 exposes the surface of the second test line 72 and is configured to allow a subsequently formed second lap electrode to be connected to the second test line 72 through the via.

[0253] In an exemplary embodiment, the orthographic projection of the eighteenth via V18 on the substrate may be within the range of the orthographic projection of the first data lead 73 on the substrate. The eighteenth via V18 exposes the surface of the first data lead 73 and is configured to allow a subsequently formed third lap electrode to be connected to the first data lead 73 through the via.

[0254] In an exemplary embodiment, the orthographic projection of the nineteenth via V19 on the substrate may be within the range of the orthographic projection of the second data lead 74 on the substrate. The nineteenth via V19 exposes the surface of the second data lead 74 and is configured to allow a subsequently formed fourth lap electrode to be connected to the second data lead 74 through the via.

[0255] In an exemplary embodiment, the orthographic projection of the twentieth via V20 onto the substrate may be within the range of the orthographic projection of the third data lead 75 onto the substrate. The twentieth via V20 exposes the surface of the third data lead 75. The twentieth via V20 is configured to allow a subsequently formed fifth lap electrode to be connected to the third data lead 75 through the via.

[0256] The eleventh via V11 to the twentieth via V20 can be multiple vias arranged sequentially along the first direction X to improve connection reliability.

[0257] (15) When forming the third conductive layer pattern in the display area, the third conductive layer pattern further includes a first lap electrode 161, a second lap electrode 162, a third lap electrode 163, a fourth lap electrode 164, and a fifth lap electrode 165 located in the upper border area, such as Figure 19 As shown.

[0258] In an exemplary embodiment, the first end of the first lap electrode 161 is connected to the first lap block 151 through the eleventh via V11, and the second end of the first lap electrode 161 is connected to the first test line 71 through the sixteenth via V16.

[0259] In an exemplary embodiment, the first end of the second lap electrode 162 is connected to the second lap block 152 through the twelfth through hole V12, and the second end of the second lap electrode 162 is connected to the second test line 72 through the seventeenth through hole V17.

[0260] In an exemplary embodiment, the first end of the third lap electrode 163 is connected to the third lap block 153 through the thirteenth via V13, and the second end of the third lap electrode 163 is connected to the first data lead 73 through the eighteenth via V18.

[0261] In an exemplary embodiment, the first end of the fourth lap electrode 164 is connected to the fourth lap block 154 through the fourteenth via V14, and the second end of the fourth lap electrode 164 is connected to the second data lead 74 through the nineteenth via V19.

[0262] In an exemplary embodiment, the first end of the fifth lap electrode 165 is connected to the fifth lap block 155 through the fifteenth via V15, and the second end of the fifth lap electrode 165 is connected to the third data lead 75 through the twentieth via V20.

[0263] The first lap electrode 161 to the fifth lap electrode 165 can be multiple lap electrodes arranged sequentially along the first direction X to improve connection reliability.

[0264] Thus, the fabrication of the test circuit of the exemplary embodiment of this disclosure is completed. The test circuit may include multiple test units, which may be arranged sequentially along the first direction X. At least one test unit may include at least a first test line 71, a second test line 72, a first data lead 73, a second data lead 74, a third data lead 75, a switch control line 76, a first switch 91, a second switch 92, a third switch 93, a fourth switch 94, and a fifth switch 95.

[0265] In an exemplary embodiment, the process by which the test circuit detects multiple touch electrodes in the display area may include:

[0266] (1) After the external test device is bonded to multiple pins in the bonding area, the external test device provides an enable signal to the gate line control pin 270, an enable signal to the switch control pin 260, and data signals to the first data pin 230, the second data pin 240, and the third data pin 250, respectively. In an exemplary embodiment, the enable and enable signals can be high-level voltages (VGH), and the data signals can be common reference voltages (VCOM). The enable signal provided by the external test device causes the gate drive circuit 330 to output an enable voltage to the multiple gate lines 20 in the display area, thereby turning on the thin-film transistors of the multiple sub-pixels in the display area. The conduction signal provided by the external testing device turns on the first switch 91, second switch 92, third switch 93, fourth switch 94, and fifth switch 95 of the multiple test units 70 in the upper frame area. The data signal provided by the external testing device is respectively provided to multiple data lines 30 in the display area through the first data lead 73 and the turned-on third switch 93, second data lead 74 and the turned-on fourth switch 94, third data lead 75 and the turned-on fifth switch 95, and transmitted to the pixel electrodes 40 of multiple sub-pixels through the turned-on thin-film transistors, so that the pixel electrodes 40 of multiple sub-pixels in the display area are charged with a common reference voltage. In this stage, the signal is turned on in advance, charging the pixel electrodes with a common reference voltage before the arrival of the first test signal and the second test signal.

[0267] (2) An external testing device provides a first test signal to the first test pin 210 and a second test signal to the second test pin 220. In an exemplary embodiment, the first test signal may be a first grayscale voltage, and the second test signal may be a second grayscale voltage. The voltage value of the first grayscale voltage may be greater than the voltage value of the second grayscale voltage, or the voltage value of the first grayscale voltage may be less than the voltage value of the second grayscale voltage. The first test signal provided by the external testing device is provided to the first lead 61 of the display area through the first test line 71 and the first switch 91, and transmitted to the plurality of touch electrodes 50 connected to the first lead 61, so that the plurality of sub-pixels corresponding to these touch electrodes 50 display the first grayscale. The second test signal provided by the external testing device is provided to the second lead 62 of the display area through the second test line 72 and the second switch 92, and transmitted to the plurality of touch electrodes 50 connected to the second lead 62, so that the plurality of sub-pixels corresponding to these touch electrodes 50 display the second grayscale.

[0268] In an exemplary embodiment, since the pixel electrodes 40 of all sub-pixels in the display area have a common reference voltage, and the touch electrodes 50 multiplexed as common electrodes have a first gray level voltage and a second gray level voltage respectively, all sub-pixels in the display area display the first gray level and the second gray level respectively.

[0269] Figure 20and Figure 21 This is a schematic diagram of the short-circuit detection circuit of this disclosure. Figure 20 This is the normal test screen when there is no short circuit. Figure 21 This is an abnormal detection screen when there is a short circuit. In an exemplary embodiment, the first lead is connected to the touch electrode 50 of the odd-numbered touch rows, and the second lead is connected to the touch electrode 50 of the even-numbered touch rows.

[0270] In an exemplary embodiment, when there is no short circuit on the array substrate, the touch electrodes 50 of the odd-numbered touch rows display a first gray level, and the touch electrodes 50 of the even-numbered touch rows display a second gray level, thus achieving a uniform display image with alternating bright and dark areas in the vertical direction. Figure 20 As shown.

[0271] In an exemplary embodiment, when there is a short circuit defect on the array substrate, such as a short circuit point Q appearing on adjacent first and second leads, since the voltages of the short-circuited first and second leads are the same, the voltage of a touch electrode 50 in an odd-numbered row is the same as that of a touch electrode 50 in an adjacent even-numbered row. Therefore, the areas where two adjacent touch electrodes 50 are located display the same grayscale, which differs from a normal display image. This allows for the screening of defective substrates. Figure 21 As shown.

[0272] Figure 22 This is a schematic diagram of the timing sequence for short-circuit detection using the detection circuit of this disclosure. Figure 22 As shown, in an exemplary embodiment, to prevent image retention caused by unidirectional polarization of the liquid crystal, the first grayscale voltage and the second grayscale voltage provided to the first test line and the second test line undergo polarity reversal between frames. For example, in frame M, the first grayscale voltage +Lo is provided to the first test line, and the second grayscale voltage +Le is provided to the second test line. In frame M+1, the first grayscale voltage -Lo is provided to the first test line, and the second grayscale voltage -Le is provided to the second test line.

[0273] As can be seen from the structure, fabrication process, and testing process of the test circuit of the exemplary embodiments of this disclosure, two touch leads are arranged between adjacent pixel units. One touch lead connects to the touch electrodes of the odd-numbered touch rows, and the other touch lead connects to the touch electrodes of the even-numbered touch rows. By providing different grayscale voltages to the two touch leads respectively, when there is no short circuit defect in the array substrate, multiple touch rows present a vertically alternating bright and dark display image. When there is a short circuit defect in the array substrate, vertically adjacent touch electrodes will display the same grayscale, thereby filtering out array substrates with short circuit defects. The test circuit of this disclosure has a simple structure and a concise detection method, which can effectively filter out defective substrates, reduce module material waste, lower production costs, and improve yield.

[0274] An exemplary embodiment of this disclosure also provides a display device, which may include a first substrate and a second substrate disposed opposite to each other, a liquid crystal layer disposed between the first substrate and the second substrate, the first substrate may be the aforementioned array substrate, and the second substrate may include a black matrix and a filter unit.

[0275] In exemplary embodiments, the display device disclosed herein can be any product or component with display function, such as a mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, or navigator. The embodiments of the present invention are not limited thereto.

[0276] An exemplary embodiment of this disclosure also provides a detection method using the array substrate described above, comprising:

[0277] A turn-on voltage is provided to multiple gate lines in the display area, causing the thin-film transistors of multiple sub-pixels in the display area to conduct; a common reference voltage is provided to multiple data lines in the display area, causing the pixel electrodes of multiple sub-pixels in the display area to have a common reference voltage;

[0278] A first grayscale voltage is provided to a first lead in the display area, such that a plurality of touch electrodes connected to the first lead in the display area have a first grayscale voltage; a second grayscale voltage is provided to a second lead in the display area, such that a plurality of touch electrodes connected to the second lead in the display area have a second grayscale voltage; the voltage value of the first grayscale voltage is greater than the voltage value of the second grayscale voltage, or the voltage value of the first grayscale voltage is less than the voltage value of the second grayscale voltage.

[0279] In an exemplary embodiment, when there is no short circuit on the array substrate, the touch electrode in one touch row displays a first gray level, and the touch electrode in the adjacent touch row displays a second gray level, and the display area presents a vertically alternating bright and dark display image; when there is a short circuit on the array substrate, at least one touch electrode in one touch row displays the same gray level as at least one touch electrode in the adjacent touch row.

[0280] While the embodiments disclosed herein are as described above, the content is merely for the purpose of facilitating understanding of this disclosure and is not intended to limit the invention. Any person skilled in the art may make any modifications and changes to the form and details of the implementation without departing from the spirit and scope of this disclosure; however, the patent protection scope of this invention shall still be determined by the scope defined in the appended claims.

Claims

1. An array substrate, characterized in that, The system includes a display area, which includes at least: multiple touch electrodes constituting multiple touch rows and multiple touch columns, and multiple pixel units constituting multiple pixel rows and multiple pixel columns. At least one pixel unit includes a first sub-pixel, a second sub-pixel, and a third sub-pixel arranged sequentially along the direction of the pixel row. The orthographic projection of the touch unit on the array substrate at least partially overlaps with the orthographic projection of the multiple pixel units on the array substrate. The pixel unit includes multiple sub-pixels. At least one adjacent pixel column is provided with a touch lead group, which includes at least a first lead and a second lead arranged side by side. The first lead is connected to a touch electrode in one touch row, and the second lead is connected to another touch electrode in an adjacent touch row. The array substrate further includes: a bonding area located on one side of the display area and an upper bezel area located on the side of the display area away from the bonding area; the bonding area includes at least a plurality of pins; the upper bezel area includes at least a test circuit, the test circuit being connected to the plurality of pins of the bonding area via multiple connecting lines; the test circuit includes a plurality of test units, the plurality of test units corresponding to the positions of a plurality of touch columns; at least one test unit includes a first test line, a second test line, a switch control line, a first switch, a second switch, a first data lead, a second data lead, a third data lead, a third switch, a fourth switch, and a fifth switch; the first test line is connected to a first lead in the display area via the first switch, the second test line is connected to a second lead in the display area via the second switch, and the switch control line is connected to the control terminals of the first switch and the second switch; the first test line is configured to transmit a first grayscale voltage to the first lead under the control of the switch control line, and the second test line is configured to transmit a first grayscale voltage to the second lead under the control of the switch control line. The first grayscale voltage is supplied with a second grayscale voltage; the voltage value of the first grayscale voltage is greater than the voltage value of the second grayscale voltage, or the voltage value of the first grayscale voltage is less than the voltage value of the second grayscale voltage; the first data lead is connected to the data line of the first sub-pixel in the display area through the third switch, the second data lead is connected to the data line of the second sub-pixel in the display area through the fourth switch, and the third data lead is connected to the data line of the third sub-pixel in the display area through the fifth switch; the switch control line is connected to the control terminals of the third, fourth, and fifth switches; the first, second, and third data leads are configured to transmit a common reference voltage to the data lines of the display area under the control of the switch control line; the test circuit is configured to: under the control of the switch control line, first provide a common reference voltage to the data lines through the first data lead to the third data lead, and then provide different grayscale voltages to the first and second leads respectively through the first and second test lines to detect short-circuit defects in the array substrate.

2. The array substrate according to claim 1, characterized in that, At least one touch column includes N touch electrodes arranged sequentially along the direction of the pixel column. The orthographic projection of the touch column on the array substrate at least partially overlaps with the orthographic projection of N / 2 pixel columns on the array substrate. A first lead located between the i-th pixel column and the (i+1)-th pixel column is connected to the touch electrode in the (2i-1)-th touch row. A second lead located between the i-th pixel column and the (i+1)-th pixel column is connected to the touch electrode in the 2i-th touch row. N is an even number greater than 1, and i is a positive integer greater than or equal to 1 and less than or equal to N / 2.

3. The array substrate according to claim 1, characterized in that, The sub-pixel includes a gate line, a data line, a thin-film transistor, and a pixel electrode. The thin-film transistor is connected to the gate line, the data line, and the pixel electrode respectively. The touch electrode is multiplexed as a common electrode. The first lead and the second lead are multiplexed as a common electrode line. The first lead is disposed on the side of the third sub-pixel away from the first sub-pixel, and the second lead is disposed on the side of the first lead away from the first sub-pixel.

4. The array substrate according to claim 3, characterized in that, In at least one pixel row, a first connecting block is provided on the first lead, and the first connecting block is connected to a touch electrode through a first via.

5. The array substrate according to claim 4, characterized in that, In at least one pixel row, the first lead includes at least a first straight segment, a second straight segment, and a bent segment located between the first straight segment and the second straight segment. The first end of the bent segment is connected to the first straight segment, and the second end of the bent segment is connected to the second straight segment. The middle part of the bent segment protrudes in a direction away from the second lead. The first connecting block is disposed in the area formed by the bend of the bent segment.

6. The array substrate according to claim 4, characterized in that, The orthographic projection of the first connecting block on the array substrate at least partially overlaps with the orthographic projection of the gate line on the array substrate.

7. The array substrate according to claim 4, characterized in that, The orthographic projection of the first via on the array substrate at least partially overlaps with the orthographic projection of the gate line on the array substrate.

8. The array substrate according to claim 3, characterized in that, In at least one pixel row, a second connecting block is provided on the second lead, and the second connecting block is connected to another touch electrode through a second via.

9. The array substrate according to claim 8, characterized in that, In at least one pixel row, the first lead includes at least a first straight segment, a second straight segment, and a bent segment located between the first straight segment and the second straight segment. The first end of the bent segment is connected to the first straight segment, and the second end of the bent segment is connected to the second straight segment. The middle part of the bent segment protrudes in a direction away from the second lead, and the second connecting block is disposed in the area formed by the bend of the bent segment.

10. The array substrate according to claim 8, characterized in that, The orthographic projection of the second connecting block on the array substrate at least partially overlaps with the orthographic projection of the gate line on the array substrate.

11. The array substrate according to claim 8, characterized in that, The orthographic projection of the second via on the array substrate at least partially overlaps with the orthographic projection of the gate line on the array substrate.

12. The array substrate according to claim 3, characterized in that, In at least one pixel unit, the touch electrode includes an electrode portion and a connecting portion. The electrode portion is disposed within the pixel unit, and the connecting portion is disposed between adjacent pixel units and connected to the electrode portion within the adjacent pixel unit.

13. The array substrate according to claim 12, characterized in that, In at least one pixel unit, the orthographic projection of the electrode portion on the array substrate does not overlap with the orthographic projection of the gate line on the array substrate, the orthographic projection of the electrode portion on the array substrate does not overlap with the orthographic projection of the first lead on the array substrate, and the orthographic projection of the electrode portion on the array substrate does not overlap with the orthographic projection of the second lead on the array substrate.

14. The array substrate according to claim 12, characterized in that, In at least one pixel unit, the orthographic projection of the connecting portion on the array substrate at least partially overlaps with the orthographic projection of the gate line on the array substrate, the orthographic projection of the connecting portion on the array substrate at least partially overlaps with the orthographic projection of the first lead on the array substrate, and the orthographic projection of the connecting portion on the array substrate at least partially overlaps with the orthographic projection of the second lead on the array substrate.

15. The array substrate according to claim 12, characterized in that, In at least one pixel unit, at least one connection portion is connected to the first lead through a first via, or at least one connection portion is connected to the second lead through a second via.

16. A display device, characterized in that, Includes the array substrate as described in any one of claims 1 to 15.

17. A detection method using an array substrate as described in any one of claims 1 to 15, characterized in that, include: By providing an enable voltage to multiple gate lines in the display area, the thin-film transistors of multiple sub-pixels in the display area are turned on; A common reference voltage is provided to multiple data lines in the display area, so that the pixel electrodes of multiple sub-pixels in the display area have a common reference voltage; A first grayscale voltage is provided to a first lead in the display area, such that a plurality of touch electrodes connected to the first lead in the display area have a first grayscale voltage; a second grayscale voltage is provided to a second lead in the display area, such that a plurality of touch electrodes connected to the second lead in the display area have a second grayscale voltage; the voltage value of the first grayscale voltage is greater than the voltage value of the second grayscale voltage, or the voltage value of the first grayscale voltage is less than the voltage value of the second grayscale voltage.

18. The detection method according to claim 17, characterized in that, When there is no short circuit on the array substrate, the touch electrode in one touch row displays the first gray level, and the touch electrode in the adjacent touch row displays the second gray level, and the display area presents a vertically alternating bright and dark display image; when there is a short circuit on the array substrate, at least one touch electrode in one touch row and at least one touch electrode in the adjacent touch row display the same gray level.

Images