A digital closed-loop control method and system for a resonant accelerometer

Abstract

This invention discloses a digital closed-loop control method for a resonant accelerometer, comprising: Step 1: acquiring the capacitance value between the two sets of capacitors inside the accelerometer and detecting the comb teeth; Step 2: amplifying the acquired capacitance value; and converting the amplified capacitance value signal into a digital capacitance value signal via an analog-to-digital converter (ADC) and inputting it into an FPGA module; Step 3: the FPGA module performs noise reduction processing on the input digital capacitance value signal; Step 4: performing Kalman filtering on the noise-reduced digital capacitance value signal to predict the theoretical phase of the capacitance value after the total processing cycle of the FPGA module; Step 5: the FPGA module uses the theoretical phase of the capacitance value lags by 90 degrees as the phase of the excitation signal and calculates the amplitude of the excitation signal corresponding to this phase; Step 6: converting the amplitude of the excitation signal into an analog excitation signal output via an ADC; Step 7: using the analog excitation signal after output shaping to drive the two sets of capacitors and driving the comb teeth.

Description

Technical Field

[0001] This invention pertains to the closed-loop control method technology of resonant sensors, and relates to the field of avionics, specifically to a digital closed-loop control method and system for a resonant accelerometer. Background Technology

[0002] Inertial navigation systems utilize gyroscopes and accelerometers to simultaneously measure the angular velocity and angular acceleration of an inertial body, calculating its current attitude and velocity in three-dimensional space, and thus obtaining the necessary navigation information. As a core component of the inertial navigation system, the performance of the accelerometer directly affects the overall performance of the system; therefore, accelerometer technology is one of the most important technologies in inertial navigation.

[0003] Compared to commonly used pendulum accelerometers, resonant silicon micro accelerometers offer advantages such as high long-term repeatability, small size, and low power consumption due to their near-digital output. They also possess significant advantages compared to other types of MEMS accelerometers. Therefore, resonant silicon micro accelerometers have become a research hotspot in high-precision accelerometers in recent years and represent a promising direction for the next generation of high-precision accelerometers.

[0004] The working principle of the resonant silicon micro accelerometer is that the mass block senses the acceleration and generates an inertial force, which in turn generates a load on the axis of the double-ended fixed tuning fork, causing the resonant frequency of the double-ended fixed tuning fork to change. The change in resonant frequency is obtained by electrostatic excitation combined with capacitor detection, and then the acceleration value in the sensitive axis direction is obtained.

[0005] Since the goal is to precisely detect the natural frequency of the resonant beam, it is necessary to excite the beam while simultaneously detecting its frequency. Silicon is a non-piezoelectric material and is typically excited using electrostatic drive to induce reciprocating motion in the resonant beam. Resonance occurs when the frequency of the driving voltage matches the natural frequency of the beam. The natural frequency of the resonant beam is obtained by detecting the frequency of capacitance changes. Therefore, the control circuit has a crucial impact on the measurement accuracy of the resonant silicon micro-accelerometer.

[0006] Currently, the control circuit of silicon micro-resonant accelerometers mainly uses analog circuit boards for amplitude detection, automatic gain control, and precise phase shift. However, since the closed-loop control is implemented using an analog circuit scheme, there are many components, and the temperature has a significant impact, which makes it impossible to guarantee the accuracy of the phase shift. Furthermore, the resistors, capacitors, and operational amplifiers in the circuit can also produce uncertain phase shifts, which can cause a certain error in the final measured resonant frequency of the resonant beam, thus reducing its accuracy. Summary of the Invention

[0007] In view of this, and to address the problems existing in the prior art, this invention provides a digital closed-loop control method for resonant accelerometers, capable of closed-loop control of resonant silicon micro accelerometers. This improves the acceleration measurement accuracy of the resonant silicon micro accelerometer and reduces the number and complexity of its circuit components, while also mitigating the impact of circuit temperature effects on start-up performance and measurement accuracy.

[0008] Firstly, a digital closed-loop control method for a resonant accelerometer is provided, comprising the following steps:

[0009] Step 1: Collect the capacitance value between the two sets of capacitors inside the accelerometer and the detection comb teeth;

[0010] Step 2: The acquired capacitance value is amplified by an amplifier circuit; the amplified capacitance value signal is then converted into a digital capacitance value signal by an AD converter and input into the FPGA module.

[0011] Step 3: The FPGA module performs noise reduction processing on the input capacitance value digital signal;

[0012] Step 4: Perform Kalman filtering on the denoised digital capacitance signal to predict the theoretical phase of the capacitance value after the total processing cycle of the FPGA module.

[0013] Step 5: The FPGA module uses the theoretical phase lag of the capacitance value by 90 degrees as the phase of the excitation signal, and calculates the amplitude of the excitation signal corresponding to this phase.

[0014] Step 6: Convert the amplitude of the excitation signal into an analog excitation signal output using a DA converter;

[0015] Step 7: The analog excitation signal is shaped and then used to drive the comb teeth of the two sets of capacitors.

[0016] Furthermore, in step two, the collected capacitance value is a weak signal at the millivolt level. The amplifier circuit amplifies it into a volt-level signal to facilitate subsequent analog-to-digital conversion and FPGA processing.

[0017] Furthermore, in step three, the noise reduction process includes: performing wavelet threshold noise reduction filtering on the input digital capacitance value signal.

[0018] Furthermore, the wavelet threshold denoising filter includes:

[0019] The input digital capacitance signal is subjected to a first wavelet threshold denoising filter to remove additive noise.

[0020] After performing a logarithmic operation on the digital signal of capacitance value after removing additive noise, a second wavelet threshold denoising filter is performed to remove multiplicative noise. Then, an exponential operation is performed on the digital signal of capacitance value after removing multiplicative noise to restore it.

[0021] Furthermore, the FPGA module will extract the frequency of the digital signal of the denoised capacitance value, and after temperature compensation, use the frequency data as the accelerometer to measure the acceleration value.

[0022] Furthermore, in step seven, the output shaping involves reducing the analog excitation signal after DA conversion to within the amplitude range of the excitation signal required for driving the capacitive comb teeth. The signal required to excite the capacitive comb teeth is a small signal at the millivolt level, so the excitation signal voltage needs to be adjusted here. However, the FPGA needs a larger signal amplitude, at the volt level, to generate the excitation signal. At the same time, to avoid reducing the signal-to-noise ratio due to a small signal amplitude, the large signal is adjusted to a small signal near the end of the capacitive comb teeth.

[0023] Furthermore, the method also includes: locking the rising and falling edges of the FPGA crystal oscillator signal via a digital phase-locked loop, using it as the internal clock signal of the FPGA.

[0024] In a second aspect, a resonant accelerometer digital closed-loop control system is provided, the system being used to implement the method described above, the system comprising, in sequence: a capacitor detection circuit, an amplifier circuit, an AD conversion circuit, an FPGA module, a DA conversion circuit, an output shaping circuit, and a capacitor excitation circuit.

[0025] The capacitance detection circuit is used to acquire the capacitance value between the two sets of capacitance detection combs inside the accelerometer; the amplification circuit is used to amplify the acquired capacitance value signal; the AD conversion circuit is used to convert the amplified signal into a digital signal and transmit it to the FPGA module.

[0026] The FPGA module is used to denoise the input capacitance value digital signal and perform Kalman filtering on the denoised capacitance value digital signal to predict the theoretical phase of the capacitance value after the total processing cycle of the FPGA module; then, the theoretical phase of the capacitance value is lagped by 90 degrees as the phase of the excitation signal, and the amplitude of the excitation signal corresponding to this phase is calculated and output.

[0027] The DA conversion module is used to convert the excitation signal amplitude into an analog signal, and the output shaping circuit is used to reduce the amplitude of the analog excitation signal after DA conversion to the range of the input signal amplitude required by the capacitor excitation circuit.

[0028] The capacitor excitation circuit is used to output the reduced amplitude of the excitation signal to two sets of capacitor-driven comb teeth to drive the comb teeth to move.

[0029] The all-digital phase-locked loop module locks the clock signal of the crystal oscillator in phase to improve the verticality of the rising and falling edges of the clock signal and the accuracy of the frequency.

[0030] Control signal prediction calculation is used to accurately predict the magnitude of the excitation signal at the moment of the output signal after passing through the FPGA circuit, in order to prevent the excitation signal from having a certain phase difference due to the calculation of the FPGA circuit.

[0031] Phase compensation is used to generate an excitation signal from the predicted data so that the resonant beam operates at the resonant frequency;

[0032] The data output interface outputs the measured acceleration values ​​from the meter in a digital format.

[0033] Compared with current closed-loop control methods using analog circuits, the present invention has the following significant advantages:

[0034] 1. The digital closed-loop control scheme has strong anti-interference ability, high integration, and low power consumption;

[0035] 2. The parameters are easy to adjust to accommodate subtle differences in the meter head structure caused by different meter heads and machining errors;

[0036] 3. Due to the complexity of resonant sensor control algorithms, fully digital solutions can more easily implement complex closed-loop control algorithms.

[0037] 4. The final output format of acceleration and sensitive acceleration measurements can be easily customized according to user requirements, making it more compatible with the backend system;

[0038] 5. Using algorithms for predictive calculations takes into account the time involved in the calculation process, thereby improving the accuracy of the accelerometer. Attached Figure Description

[0039] Figure 1 A flowchart of a closed-loop control circuit method is provided in an embodiment of the present invention;

[0040] Figure 2 This is a schematic diagram of the internal digital control loop of an FPGA processor provided in an embodiment of the present invention;

[0041] Figure 3 This is a schematic diagram of the wavelet filtering algorithm provided in an embodiment of the present invention;

[0042] Figure 4 A schematic diagram of the Kalman filter algorithm provided in an embodiment of the present invention. Detailed Implementation

[0043] To better understand the present invention, the following embodiments further illustrate the content of the present invention, but the present invention is not limited to the following embodiments.

[0044] Example 1

[0045] This invention provides a method for a fully digital closed-loop control circuit for a resonant silicon micro-accelerometer, such as... Figure 1As shown, it consists of a resonant accelerometer with a single-ended tuning fork, a closed-loop circuit, and an output circuit. The closed-loop circuit includes a capacitance detection interface, an amplifier circuit, an AD converter, an FPGA chip, a DA converter, a shaping circuit, and a capacitor-driven comb. The FPGA chip consists of a digital phase-locked loop module, an excitation prediction module, a phase compensation module, and a data output module.

[0046] To achieve precise driving of the resonant accelerometer, and to detect and track the natural frequency of the resonant beam, ensuring it operates at its natural frequency and detecting that frequency, the closed-loop control principle of its circuit is introduced below.

[0047] The detection interface is electrically connected to the resonator, sensing changes in its capacitance. An operational amplifier circuit amplifies the output signal, maintaining its amplitude at a constant value. An analog-to-digital converter (ADC) converts this analog signal into a digital signal, which is then used as input to the FPGA chip. The excitation prediction module processes the input signal, predicting the excitation magnitude at the calculated time. A phase compensation module compensates for the phase difference of the excitation signal towards the resonant point of the resonant beam and outputs it to the closed-loop circuit. A DA converter converts the digital signal back to an analog signal, and a shaping circuit shapes the analog signal, reducing its amplitude. This shaping is then applied to the capacitor-driven comb teeth, completing the closed-loop control of the system.

[0048] Example 2

[0049] Figure 2 This diagram illustrates the internal digital control loop of the FPGA processor. The loop primarily consists of an excitation prediction module, a clock signal shaping module, and a phase compensation module. Because the rising and falling edges of the FPGA clock signal are not precise enough, a digital phase-locked loop (PLL) module is used to lock the rising and falling edges of the clock signal, making the FPGA's internal clock frequency more accurate. The output of the AD converter is directly connected to the control signal prediction module. Since the capacitance change detected by the capacitance sensor is extremely small, secondary amplification is required. This introduces a large amount of noise, causing waveform instability, necessitating noise reduction. The input digital signal after the AD converter undergoes a wavelet threshold denoising filter to remove additive noise. Then, the signal with additive noise removed is logarithmically calculated. The logarithmically calculated signal is then subjected to another wavelet threshold denoising filter before exponential calculation to remove multiplicative noise. Next, the signal after noise filtering is processed using Kalman filtering, which is used to calculate the required time period by introducing the FPGA chip. The phase after the required time period of the algorithm is predicted. The calculation result is compensated by the excitation signal obtained by 90° phase shift of the filtered signal through the phase compensation module, and then output as the final excitation signal.

[0050] Example 3

[0051] Figure 3 This is a schematic diagram of the wavelet noise filtering algorithm. This invention uses two wavelet algorithms to perform noise filtering operations. The model for a one-dimensional signal containing multiplicative and additive noise is: F(t) = Y(t)V(t) + U(t), where U(t) is the input signal, Y(t) is the original signal, contaminated by multiplicative noise V(t) and additive noise F(t). After a wavelet filtering operation, the additive noise is removed, and the signal becomes Y(t)V(t). Then, a logarithmic transformation is performed, resulting in ln(Y(t)V(t)) = ln(Y(t)) + ln(V(t)). Another wavelet filtering operation removes the additive noise, resulting in ln(Y(t)). Finally, an exponential transformation is performed on the denoised signal to obtain the original signal Y(t). Since the output signal from the capacitor detection terminal is a sinusoidal function, wavelet transform is convenient. Denoising methods include modulus maxima denoising, spatial correlation, and wavelet thresholding. Wavelet thresholding is a simple algorithm with good denoising effect. Therefore, the steps of the wavelet thresholding algorithm are described in this embodiment as follows:

[0052] The first step is to select a wavelet basis that matches the signal to be processed and define the number of wavelet transform layers. Then, perform wavelet decomposition on the noise signal to obtain the corresponding wavelet decomposition coefficients.

[0053] The second step is to process the obtained wavelet coefficients using a threshold value. A reasonable threshold value is selected by using a threshold selection rule. Wavelet coefficients that are greater than the threshold value are retained, while wavelet coefficients that are lower than the threshold value are filtered out.

[0054] The third step is to reconstruct the wavelet coefficients and scaling coefficients obtained after processing with the critical value to obtain a new signal, which is the filtered signal.

[0055] Example 4

[0056] Figure 4 The diagram shows the Kalman filter algorithm. Since the circuit calculation takes a certain number of clock cycles, the calculated signal value will lag. The subsequent phase compensation module will also take a certain number of clock cycles, for a total of T clock cycles. Therefore, Kalman filtering is required to obtain the signal value after T clock cycles and the excitation value that should be applied.

Claims

1. A digital closed-loop control method for a resonant accelerometer, characterized in that: The method includes the following steps: Step 1: Collect the capacitance value between the two sets of capacitors inside the accelerometer and the detection comb teeth; Step 2: The acquired capacitance value is amplified by an amplifier circuit; the amplified capacitance value signal is then converted into a digital capacitance value signal by an AD converter and input into the FPGA module. Step 3: The FPGA module performs noise reduction processing on the input capacitance value digital signal. The noise reduction processing includes: performing wavelet threshold noise reduction filtering on the input capacitance value digital signal; performing a first wavelet threshold noise reduction filtering on the input capacitance value digital signal to remove additive noise; performing a logarithmic operation on the capacitance value digital signal after removing additive noise, followed by a second wavelet threshold noise reduction filtering to remove multiplicative noise; and finally performing an exponential operation on the capacitance value digital signal after removing multiplicative noise to restore it. Step 4: Perform Kalman filtering on the denoised digital capacitance signal to predict the theoretical phase of the capacitance value after the total processing cycle of the FPGA module. Step 5: The FPGA module uses the theoretical phase lag of the capacitance value by 90 degrees as the phase of the excitation signal, and calculates the amplitude of the excitation signal corresponding to this phase. Step 6: Convert the amplitude of the excitation signal into an analog excitation signal output using a DA converter; Step 7: The analog excitation signal is shaped and then used to drive the comb teeth of the two sets of capacitors.

2. The method according to claim 1, characterized in that: In step two, the collected capacitance value is a weak signal, which is amplified into a large signal by the amplifier circuit.

3. The method according to claim 1, characterized in that: The FPGA module also extracts the frequency of the digital signal of the denoised capacitance value, and after temperature compensation, outputs the frequency data as the acceleration value measured by the accelerometer.

4. The method according to claim 1, characterized in that: In step seven, the output shaping involves reducing the analog excitation signal after DA conversion to within the amplitude range of the excitation signal required for capacitor-driven comb teeth.

5. The method according to claim 1, characterized in that: The method further includes: locking the rising and falling edges of the FPGA crystal oscillator signal via a digital phase-locked loop, and using it as the internal clock signal of the FPGA.

6. A resonant accelerometer digital closed-loop control system, said system being used to implement the method according to any one of claims 1-5, characterized in that: The system comprises, in sequence: a capacitance detection circuit, an amplifier circuit, an AD conversion circuit, an FPGA module, a DA conversion circuit, an output shaping circuit, and a capacitance excitation circuit. The capacitance detection circuit is used to collect the capacitance value between the two sets of capacitance detection comb teeth inside the accelerometer. The amplifier circuit is used to amplify the acquired capacitance value signal; the AD conversion circuit is used to convert the amplified signal into a digital signal and then transmit it to the FPGA module. The FPGA module is used to denoise the input capacitance value digital signal and perform Kalman filtering on the denoised capacitance value digital signal to predict the theoretical phase of the capacitance value after the total processing cycle of the FPGA module; then, the theoretical phase of the capacitance value is lagped by 90 degrees as the phase of the excitation signal, and the amplitude of the excitation signal corresponding to this phase is calculated and output. The DA conversion module is used to convert the excitation signal amplitude into an analog signal, and the output shaping circuit is used to reduce the amplitude of the analog excitation signal after DA conversion to the range of the input signal amplitude required by the capacitor excitation circuit. The capacitor excitation circuit is used to output the reduced amplitude of the excitation signal to two sets of capacitor-driven comb teeth to drive the capacitor-driven comb teeth to move.

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