Memory device detecting out-of-range operating temperature

Abstract

A memory device detects an out-of-range operating temperature. The memory device includes a memory die that includes an internal supply powered thermometer to: determine a first measured operating temperature value of the memory die; detect that the first measured operating temperature value satisfies one of a first condition or a second condition; and generate a first signal indicating an out-of-range operating temperature of the memory die in response to the first measured operating temperature value satisfying one of the first condition or the second condition. The memory die also includes an external supply powered thermometer to: determine a second measured operating temperature value of the memory die; detect that the second measured operating temperature value satisfies one of the first condition or the second condition; and generate a second signal indicating an out-of-range operating temperature of the memory die in response to the second measured operating temperature value satisfying one of the first condition or the second condition.

Description

Technical Field

[0001] Embodiments of this disclosure generally relate to memory subsystems, and more specifically, to memory devices that manage operation at out-of-range operating temperatures of memory dies. Background Technology

[0002] The memory subsystem may include one or more memory devices for storing data. The memory devices may be, for example, non-volatile memory devices and volatile memory devices. Generally, a host system may utilize the memory subsystem to store data at the memory devices and retrieve data from the memory devices. Summary of the Invention

[0003] Embodiments of this disclosure provide a memory device comprising: a memory die, including: an internally powered thermometer that performs a first operation including: determining a first measured operating temperature value of the memory die; detecting that the first measured operating temperature value satisfies one of a first condition or a second condition; and generating a first signal indicating an out-of-range operating temperature of the memory die in response to the first measured operating temperature value satisfying one of the first condition or the second condition; and an externally powered thermometer that performs a second operation including: determining a second measured operating temperature value of the memory die; detecting that the second measured operating temperature value satisfies one of the first condition or the second condition; and generating a second signal indicating the out-of-range operating temperature of the memory die in response to the second measured operating temperature value satisfying one of the first condition or the second condition.

[0004] Another embodiment of this disclosure provides a memory subsystem comprising: a memory device including a memory die, the memory die including: a first thermometer that generates a first signal indicating an out-of-range operating temperature of the memory die; and a second thermometer that generates a second signal indicating the out-of-range operating temperature of the memory die; and control logic operatively coupled to the first thermometer and the second thermometer to perform operations including: receiving at least one of the first signal or the second signal; and transmitting an alarm associated with at least one of the first signal or the second signal to a host system.

[0005] Another embodiment of this disclosure provides a memory die comprising: a first thermometer that generates a first signal indicating an out-of-range operating temperature of the memory die; a second thermometer that generates a second signal indicating the out-of-range operating temperature of the memory die; and a dedicated pad that receives at least one of the first signal or the second signal, wherein the dedicated pad is monitored by a memory subsystem controller communicatively coupled to a host system. Attached Figure Description

[0006] This disclosure will be more fully understood in light of the detailed description provided below and the accompanying drawings of various embodiments thereof.

[0007] Figure 1 An example computing system including a memory subsystem is shown according to some embodiments of the present disclosure.

[0008] Figure 2 This is a block diagram of a memory device communicating with a memory subsystem controller of a memory subsystem according to some embodiments of the present disclosure.

[0009] Figure 3A This is an illustrative illustration of an example memory die according to embodiments of the present disclosure, which includes a set of thermometers to monitor the operating temperature of the memory die.

[0010] Figure 3B A graphical representation of measured temperature values ​​monitored by a set of thermometers to identify the out-of-range operating temperature of a memory die, according to an embodiment of the present disclosure.

[0011] Figure 4 As an illustrative description of an example memory device including a memory die according to embodiments of the present disclosure, the memory die includes a plurality of thermometers to generate corresponding flag signals associated with detecting out-of-range operating temperatures of the memory die.

[0012] Figure 5A and 5B As an illustrative description of an example memory device including a memory die according to embodiments of the present disclosure, the memory die has a plurality of thermometers and associated circuitry to generate a flag signal associated with detecting an out-of-range operating temperature of the memory die.

[0013] Figure 6 This is a flowchart of an example method for generating a signal indicating an out-of-range operating temperature of a memory die comprising a set of thermometers, according to one or more embodiments of the present disclosure.

[0014] Figure 7 A block diagram of an example computer system in which embodiments of the present disclosure may be operated. Detailed Implementation

[0015] This disclosure relates to a memory subsystem comprising a memory device having a memory die having a plurality of thermometers for monitoring the operating temperature of the memory die. The memory subsystem may be a memory device, a memory module, or a hybrid of a memory device and a memory module. The following is in conjunction with… Figure 1 Describe examples of storage devices and memory modules. Typically, a host system may use a memory subsystem that includes one or more components, such as a memory device for storing data. The host system can provide data to be stored in the memory subsystem and can request to retrieve data from the memory subsystem.

[0016] The memory subsystem may include high-density non-volatile memory devices, where data retention is required when no power is supplied to the memory devices. An example of a non-volatile memory device is a NAND flash memory device. The following section combines... Figure 1 Other examples of non-volatile memory devices are described. A non-volatile memory device is a package of one or more dies. Each memory die may consist of one or more planes. For some types of non-volatile memory devices (e.g., NAND devices), each plane consists of a set of physical blocks. Each block consists of a set of pages. Each page consists of a set of memory cells (“cells”). A cell is an electronic circuit that stores information. Depending on the cell type, a cell may store one or more bits of binary information and has various logic states associated with the number of bits stored. Logic states may be represented by binary values ​​such as “0” and “1” or combinations of such values.

[0017] The host system can initiate memory access operations (e.g., programming, reading, erasing operations) associated with a memory array of one or more memory dies of the memory device. To ensure proper operation during memory access operations, the memory device is designed to have an acceptable operating temperature (e.g., a temperature range) whereby the memory device operates and functions appropriately and according to design specifications. If the memory device experiences operating temperatures outside the acceptable operating temperature range (e.g., 0°C to 70°C), it will adversely affect the operation of the memory device. In this regard, if the memory device operates outside the acceptable temperature range, the data associated with the one or more memory access operations may be corrupted. For example, if a read operation is performed while the memory device is operating outside the acceptable temperature range, the data read and returned to the host system may be incorrect or inaccurate.

[0018] In certain applications or implementations of host systems where the operation of the memory device is critical, data corruption can present a significant risk. For example, a memory device implemented in a vehicle may be responsible for critical functions (e.g., automatic pilot features), which could pose a serious risk to vehicle operators if the memory device operates outside its acceptable temperature range (e.g., experiencing data corruption related to memory access operations). Furthermore, memory devices can be implemented in a wide variety of applications and host systems with varying ambient temperatures that affect their operating temperature. For example, a memory device implemented in a vehicle may be exposed to a wide range of ambient temperatures based on the vehicle's geographical location. In such cases, it is crucial to detect when the memory device is operating outside its acceptable temperature range due to, for example, ambient temperature conditions. Moreover, simply measuring the ambient temperature does not provide sufficient information to determine the impact on the operating temperature of the memory device or on the reliability or accuracy of the data processed by the memory device.

[0019] In some cases, an internally powered thermometer on the memory die is used to detect the operating temperature of the memory die. However, because the thermometer is internally powered, the operation of the internal voltage supply becomes unstable and supplies incorrect voltage levels to the thermometer when the operating temperature of the memory die is outside the acceptable range (e.g., too high or too low). Therefore, if the internal voltage level is incorrect, the operation of the internally powered thermometer is adversely affected, leading to inaccurate temperature measurements. As a result, due to the instability and unreliability in the operation of both the internal voltage supply and the thermometer, and due to the influence of the memory die's out-of-range operating temperature, the operating temperature cannot be accurately measured using a single internally powered thermometer.

[0020] This disclosure addresses the above and other shortcomings by implementing a memory device having one or more memory dies, the memory die including a set of thermometer circuitry comprising a first thermometer circuit powered by an internal power supply and one or more thermometer circuits powered by one or more external power supplies to detect or measure the operating temperature of the memory die and generate a flag or alarm signal (also referred to as a "temperature flag signal") indicating when the operating temperature is outside an acceptable temperature range (e.g., out-of-range temperature). In embodiments, the internally powered thermometer and one or more dedicated externally powered thermometers each measure the memory die temperature associated with the memory die (also referred to as the "measured temperature"). The measured temperature is compared to one or more threshold temperature levels (e.g., the minimum and maximum acceptable operating temperatures within an acceptable operating temperature range) to determine whether the measured temperature is within or outside an acceptable range. In embodiments, in response to determining that the measured temperature is outside an acceptable operating temperature range (e.g., below the minimum temperature threshold level or above the maximum temperature threshold level), one or more thermometers generate a temperature flag signal. In one embodiment, the externally powered thermometer is directly coupled to an external power pad (e.g., Vccp). In another embodiment, the externally powered thermometer is not coupled to a Vccr line or voltage regulator.

[0021] In one embodiment, the local media controller receives temperature flag signals from one or more thermometers and provides these signals to a memory subsystem controller, which communicates with the host system controller to indicate to the host system that an out-of-range operating temperature of the memory die has been detected. In another embodiment, the memory device includes a dedicated pad or pin for receiving the temperature flag signal, wherein the dedicated pad can be detected "directly" by the memory subsystem controller. In another embodiment, the temperature flag signal enables the host controller to perform one or more responsive actions. For example, responsive actions may include terminating an ongoing operation (e.g., a read operation, a write operation, an erase operation, etc.), switching to a redundant memory system, discarding relevant data provided by the out-of-range memory die, etc.

[0022] Advantageously, an internally powered thermometer and one or more externally powered thermometers provide a redundant system for detecting out-of-range operating temperatures of the memory die and provide corresponding flag signals to alert the host system. According to an embodiment, any one of the set of redundant thermometers can generate a flag signal in response to detecting an out-of-range operating temperature of the memory die.

[0023] Figure 1Example computing system 100 including memory subsystem 110 according to some embodiments of the present disclosure is illustrated. Memory subsystem 110 may include media, such as one or more volatile memory devices (e.g., memory device 140), one or more non-volatile memory devices (e.g., memory device 130), or a combination of the like.

[0024] The memory subsystem 110 may be a storage device, a memory module, or a combination of both. Examples of storage devices include solid-state drives (SSDs), flash drives, universal serial bus (USB) flash drives, embedded multimedia controller (eMMC) drives, universal flash memory (UFS) drives, secure digital storage (SD) drives, and hard disk drives (HDDs). Examples of memory modules include dual in-line memory modules (DIMMs), small outline DIMMs (SO-DIMMs), and various types of non-volatile dual in-line memory modules (NVDIMMs).

[0025] The computing system 100 may be a computing device, such as a desktop computer, laptop computer, web server, mobile device, vehicle (e.g., airplane, drone, train, car or other means of transport), Internet of Things (IoT) enabled device, embedded computer (e.g., computer contained in a vehicle, industrial equipment or networked commercially available device), or such computing device that includes memory and processing means (e.g., processor).

[0026] The computing system 100 may include a host system 120 coupled to one or more memory subsystems 110. In some embodiments, the host system 120 is coupled to different types of memory subsystems 110. Figure 1 An example of a host system 120 coupled to a memory subsystem 110 is shown. As used herein, “coupled to” or “coupled with” generally refers to a connection between components, which can be an indirect or direct communication connection (e.g., without an intermediate component), whether wired or wireless, including connections such as electrical, optical, magnetic, etc.

[0027] Host system 120 may include a processor chipset and software stack executed by the processor chipset. The processor chipset may include one or more cores, one or more caches, a memory controller (e.g., an NVDIMM controller), and a storage protocol controller (e.g., a PCIe controller, a SATA controller). Host system 120 uses memory subsystem 110 to, for example, write data to memory subsystem 110 and read data from memory subsystem 110.

[0028] Host system 120 can be coupled to memory subsystem 110 via a physical host interface. Examples of physical host interfaces include, but are not limited to, Serial Advanced Technology Attachment (SATA) interfaces, Peripheral Component Interconnect High Speed ​​(PCIe) interfaces, Universal Serial Bus (USB) interfaces, Fibre Channel, Serial Attached SCSI (SAS), Dual Data Rate (DDR) memory buses, Small Computer System Interface (SCSI), Dual In-line Memory Module (DIMM) interfaces (e.g., DIMM sockets supporting Dual Data Rate (DDR)), etc. The physical host interface can be used to transfer data between host system 120 and memory subsystem 110. When memory subsystem 110 is coupled to host system 120 via a physical host interface (e.g., a PCIe bus), host system 120 can further utilize an NVM High Speed ​​(NVMe) interface to access components (e.g., memory device 130). The physical host interface provides an interface for transferring control, address, data, and other signals between memory subsystem 110 and host system 120. Figure 1 Memory subsystem 110 is shown as an example. Generally, host system 120 can access multiple memory subsystems via the same communication connection, multiple separate communication connections, and / or a combination of communication connections.

[0029] Memory devices 130 and 140 may comprise any combination of different types of non-volatile memory devices and / or volatile memory devices. Volatile memory devices (e.g., memory device 140) may be, but are not limited to, random access memory (RAM), such as dynamic random access memory (DRAM) and synchronous dynamic random access memory (SDRAM).

[0030] Some examples of non-volatile memory devices (e.g., memory device 130) include NAND flash memory and in-place write memory, such as three-dimensional crosspoint (“3D crosspoint”) memory devices, which are crosspoint arrays of non-volatile memory cells. The crosspoint array of non-volatile memory can be combined with a stackable cross-grid data access array to perform bit storage based on changes in volume resistance. Furthermore, compared to many flash-based memories, crosspoint non-volatile memory can perform in-place write operations, where non-volatile memory cells can be programmed without pre-erasing them. NAND flash memory includes, for example, two-dimensional NAND (2D NAND) and three-dimensional NAND (3D NAND).

[0031] Each of the memory devices 130 may include one or more arrays of memory cells. One type of memory cell, such as a single-level cell (SLC), may store one bit per cell. Other types of memory cells, such as multi-level cell (MLC), three-level cell (TLC), four-level cell (QLC), and five-level cell (PLC), may store multiple bits per cell. In some embodiments, each of the memory devices 130 may include one or more arrays of memory cells, such as SLC, MLC, TLC, QLC, or any combination of such arrays. In some embodiments, a particular memory device may include an SLC portion, an MLC portion, a TLC portion, a QLC portion, or a PLC portion of memory cells. The memory cells of the memory device 130 may be grouped into pages, which may refer to logical cells of the memory device used to store data. For some types of memory (e.g., NAND), pages may be grouped to form blocks.

[0032] Although non-volatile memory components such as 3D cross-point arrays of non-volatile memory cells and NAND flash memory (e.g., 2D NAND, 3D NAND) are described, memory device 130 may be based on any other type of non-volatile memory, such as read-only memory (ROM), phase-change memory (PCM), auto-select memory, other chalcogenide-based memories, ferroelectric transistor random access memory (FeTRAM), ferroelectric random access memory (FeRAM), magnetic random access memory (MRAM), spin-transfer torque (STT)-MRAM, conductive bridged RAM (CBRAM), resistive random access memory (RRAM), oxide-based RRAM (OxRAM), NOR flash memory, and electrically erasable programmable read-only memory (EEPROM).

[0033] The memory subsystem controller 115 (for simplicity, controller 115) can communicate with the memory device 130 to perform operations, such as reading data, writing data, erasing data, and other such operations at the memory device 130. The memory subsystem controller 115 may include hardware, such as one or more integrated circuits and / or discrete components, buffer memories, or combinations thereof. The hardware may include digital circuitry with dedicated (i.e., hard-decoded) logic to perform the operations described herein. The memory subsystem controller 115 may be a microcontroller, a dedicated logic circuit system (e.g., a field-programmable gate array (FPGA), an application-specific integrated circuit (ASIC), etc.), or another suitable processor.

[0034] The memory subsystem controller 115 may be a processing device that includes one or more processors (e.g., processor 117) configured to execute instructions stored in local memory 119. In the illustrated example, the local memory 119 of the memory subsystem controller 115 includes embedded memory configured to store instructions for performing various processes, operations, logical flows, and routines for controlling the operation of the memory subsystem 110 (including handling communication between the memory subsystem 110 and the host system 120).

[0035] In some embodiments, local memory 119 may include memory registers storing memory pointers, retrieved data, etc. Local memory 119 may also include read-only memory (ROM) for storing microcode. Although... Figure 1 The instance memory subsystem 110 is shown to include a memory subsystem controller 115, but in another embodiment of this disclosure, the memory subsystem 110 does not include a memory subsystem controller 115 and may instead rely on external control (e.g., provided by an external host or by a processor or controller separate from the memory subsystem).

[0036] Typically, the memory subsystem controller 115 receives commands or operations from the host system 120 and translates these commands or operations into instructions or appropriate commands to perform the desired access to the memory device 130. The memory subsystem controller 115 may handle other operations such as wear leveling, garbage collection, error detection and error correction (ECC) operations, encryption, caching, and address translation between logical addresses (e.g., logical block addresses, namespaces) and physical addresses (e.g., physical block addresses) associated with the memory device 130. The memory subsystem controller 115 may further include a host interface circuitry for communicating with the host system 120 via a physical host interface. The host interface circuitry can translate commands received from the host system into instructions for accessing the memory device 130, and translate responses associated with the memory device 130 into information for the host system 120.

[0037] The memory subsystem 110 may also include additional circuitry or components not shown. In some embodiments, the memory subsystem 110 may include a cache or buffer (e.g., DRAM) and an address circuitry (e.g., a row decoder and a column decoder) that can receive and decode addresses from the memory subsystem controller 115 to access the memory device 130.

[0038] In some embodiments, memory device 130 includes a local media controller 135 that operates in conjunction with memory subsystem controller 115 to perform operations on one or more memory cells of memory device 130. An external controller (e.g., memory subsystem controller 115) may externally manage memory device 130 (e.g., perform media management operations on memory device 130). In some embodiments, memory subsystem 110 is a managed memory device that includes the original memory device 130 having on-die control logic (e.g., local media controller 135) and a controller (e.g., memory subsystem controller 115) for media management within the same memory device package. An example of a managed memory device is a managed NAND (MNAND) device.

[0039] In one embodiment, memory subsystem 110 includes memory interface component 113. Memory interface component 113 is responsible for handling interactions between memory subsystem controller 115 and memory devices (e.g., memory device 130) of memory subsystem 110. For example, memory interface component 113 may send memory access commands corresponding to requests received from host system 120 to memory device 130, such as programming commands, read commands, or other commands. Additionally, memory interface component 113 may receive data from memory device 130, such as data retrieved in response to confirmation of a read command or successful execution of a programming command. For example, memory subsystem controller 115 may include processor 117 (processing means) configured to execute instructions stored in local memory 119 for performing the operations described herein.

[0040] In one embodiment, the memory device 130 includes a memory die 138 that includes a set of thermometers 139 (e.g., thermometer circuitry). In another embodiment, the set of thermometers 139 includes a first thermometer circuit powered by an internal power supply and one or more thermometer circuits powered by one or more external power supplies to detect or measure the operating temperature of the memory die and generate a flag or alarm signal (also referred to as a "temperature flag signal") indicating when the operating temperature is outside an acceptable temperature range (e.g., out-of-range temperature). In another embodiment, the temperature flag signal can be provided to a thermometer manager 136 of a local media controller 135. The thermometer manager 136 is configured to provide indication of the temperature flag signal to a memory subsystem controller 115 to issue an alarm to the host system regarding an out-of-range operating temperature of the memory die. In another embodiment, a dedicated "extra" pad or pin can be added to the memory device 130 that is directly accessible by the memory subsystem controller 115. The temperature flag signal can be transmitted to the memory subsystem controller 115 via the dedicated pad. For example, when a temperature indicator signal is generated by one or more of a set of thermometers, the voltage of the dedicated pad can be set to a low voltage level (e.g., 0V), and the memory subsystem controller 115 can detect the low voltage level of the dedicated pad and issue an alarm for out-of-range operating temperature to the host system. The following section discusses... Figure 3A-7 A more detailed description is given of aspects of a set of thermometers 139 and thermometer manager 136.

[0041] Figure 2 This is a simplified block diagram illustrating communication between a first device in the form of a memory device 130 and a second device in the form of a memory subsystem controller 115 of a memory subsystem (e.g., memory subsystem 110 of FIG. 1). Examples of electronic systems include personal computers, personal digital assistants (PDAs), digital cameras, digital media players, digital recorders, games, electrical equipment, vehicles, wireless devices, mobile phones, and the like. The memory subsystem controller 115 (e.g., a controller external to memory device 130) may be a memory controller or other external host device.

[0042] Memory device 130 includes an array 204 of memory cells logically arranged in rows and columns. Memory cells in logical rows are typically connected to the same access line (e.g., a word line), while memory cells in logical columns are typically selectively connected to the same data line (e.g., a bit line). A single access line may be associated with memory cells in more than one logical row, and a single data line may be associated with more than one logical column. At least a portion of the memory cells in the memory cell array 204 ( Figure 2 (not shown) can be programmed as one of at least two target data states.

[0043] Row decoding circuitry 208 and column decoding circuitry 210 are provided to decode address signals. Address signals are received and decoded to access memory cell array 204. Memory device 130 also includes input / output (I / O) control circuitry 212 for managing inputs of commands, addresses, and data to memory device 130, as well as outputs of data and status information from memory device 130. According to an embodiment, I / O control interface 212 manages communication between local media controller 135 and the corresponding memory die containing memory cell array 204. Address register 214 communicates with I / O control circuitry 212, row decoding circuitry 208, and column decoding circuitry 210 to latch address signals before decoding. Command register 224 communicates with I / O interface 212 and local media controller 135 to latch incoming commands.

[0044] A controller (e.g., a local media controller 135 within memory device 130) controls access to memory cell array 204 in response to commands and generates status information for external memory subsystem controller 115, i.e., the local media controller 135 is configured to perform access operations (e.g., read operations, program operations, and / or erase operations) on memory cell array 204. The local media controller 135 communicates with row decoding circuitry 208 and column decoding circuitry 210 to control them in response to addresses. In one embodiment, the local media controller 135 includes instructions that can be combined with the operation and functionality of a set of thermometers 139 and thermometer manager 136, as described herein.

[0045] The local media controller 135 also communicates with cache register 218. Cache register 218 latches incoming or outgoing data, such as data initiated by the local media controller 135, to temporarily store data while the memory cell array 204 is busy writing or reading other data. During programming operations (e.g., write operations), data can be transferred from cache register 218 to data register 220 for transfer to memory cell array 204; then, new data can be latched from I / O control circuitry 212 into cache register 218. During read operations, data can be transferred from cache register 218 to I / O control circuitry 212 for output to memory subsystem controller 115; then, new data can be transferred from data register 220 to cache register 218. Cache register 218 and / or data register 220 may form a page buffer (e.g., a portion thereof) of memory device 130. The page buffer may further include sensing devices ( Figure 2(Not shown) to sense the data status of the memory cells in the memory cell array 204, for example, by sensing the status of the data lines connected to the memory cells. The status register 222 can communicate with the I / O control circuitry system 212 and the local memory controller 135 to latch status information for output to the memory subsystem controller 115.

[0046] Memory device 130 receives control signals from local media controller 135 at memory subsystem controller 115 via control link 232. For example, control signals may include chip enable signal CE#, command latch enable signal CLE, address latch enable signal ALE, write enable signal WE#, read enable signal RE#, and write protection signal WP#. Depending on the nature of memory device 130, additional or alternative control signals (not shown) may be received on control link 232. In one embodiment, memory device 130 receives command signals (representing commands), address signals (representing addresses), and data signals (representing data) from memory subsystem controller 115 via multiplexed input / output (I / O) bus 234, and outputs data to memory subsystem controller 115 via I / O bus 234.

[0047] For example, commands can be received at I / O control circuitry 212 via input / output (I / O) pins [7:0] of I / O bus 234 and then written to command register 224. Addresses can be received at I / O control circuitry 212 via input / output (I / O) pins [7:0] of I / O bus 234 and then written to address register 214. Data can be received at one or more of I / O control interfaces 212 via input / output (I / O) pins [7:0] for 8-bit devices or input / output (I / O) pins [15:0] for 16-bit devices and then written to cache register 218. The data can then be written to data register 220 for programming memory cell array 204.

[0048] In this embodiment, the cache register 218 may be omitted, and data may be written directly to the data register 220. Data may also be output via input / output (I / O) pins [7:0] for 8-bit devices or input / output (I / O) pins [15:0] for 16-bit devices. While references may be made to I / O pins, they may include any conductive nodes, such as commonly used conductive pads or conductive bumps, that enable electrical connection to the memory device 130 via an external device (e.g., the memory subsystem controller 115).

[0049] Those skilled in the art should understand that additional circuitry and signals can be provided and have been simplified. Figure 2 The memory device 130. It should be understood that, reference Figure 2 The functionality of the various block components described need not be separated from the different components or component portions of the integrated circuit device. For example, a single component or component portion of the integrated circuit device may be adapted to perform the functionality of more than one block component of FIG2. Alternatively, one or more components or component portions of the integrated circuit device may be combined to perform... Figure 2 The functionality of a single block component. Furthermore, while specific I / O pins are described according to popular conventions for the reception and output of various signals, it should be noted that other combinations or numbers of I / O pins (or other I / O node structures) may be used in various embodiments.

[0050] Figure 3A This is a schematic illustration of an instance memory die having a set of multiple thermometers (thermometer A, thermometer B, and thermometer C) powered by respective power supplies. In an embodiment, the set of thermometers includes a first thermometer (thermometer A) powered by an internal voltage supply and one or more dedicated thermometers (e.g., thermometers B and thermometer C) powered by respective external voltage supplies provided by the host system. Figure 3A In the illustrated embodiment, a set of thermometers on the memory die includes an internally powered thermometer (thermometer A) and receives two externally powered thermometers (e.g., thermometer B and / or thermometer C) with corresponding external power supplies (e.g., thermometer B is supplied by external voltage 2 and thermometer C is supplied by external voltage 1). Although Figure 3A The diagram illustrates two dedicated externally powered thermometers. A memory die may contain one externally powered or dedicated thermometer (e.g., thermometer B or thermometer C) or multiple externally powered or dedicated thermometers (e.g., thermometer B and thermometer C, as shown). Figure 3A (As shown).

[0051] exist Figure 3A In the illustrated embodiment, the memory die includes an internal voltage supply (Vint) (e.g., approximately 2V) to the power thermometer A and receives multiple externally supplied voltage levels to power one or more dedicated thermometers on the memory die. Figure 3AIn the illustrated embodiment, the memory die is equipped with external voltage 0 (Vext0) (e.g., a ground voltage of approximately 0V); external voltage 1 (Vext1) (e.g., approximately 1.2V); and external voltage 2 (Vext2) (e.g., approximately 2.5V). In this embodiment, Vext1 represents the voltage level required to perform data transfer (input / output) to and from the memory die. In this embodiment, Vext0 is a ground voltage level (e.g., approximately 0V), Vext1 is a low voltage level (e.g., approximately 1.2V), and Vext2 is a high voltage level (e.g., approximately 2.5V). In this embodiment, the internally powered thermometer A may receive a voltage supply regulated by a regulator, such as... Figure 3A As shown. In one embodiment, one or more externally powered thermometers (e.g., thermometer B and / or thermometer C) are directly coupled to an external power pad (e.g., a power pad associated with one of Vext1 or Vext2). In another embodiment, one or more externally powered thermometers are not coupled to an internal voltage supply (Vint) or voltage regulator.

[0052] In one embodiment, a set of thermometers is configured to periodically measure the operating temperature of the memory die. In another embodiment, the measured temperature values ​​may be represented by DAC values, where each DAC value corresponds to an operating temperature, such as... Figure 3B The graphical representation is shown in the figure. In an embodiment, an acceptable operating temperature range is established, including a minimum acceptable operating temperature (Tmin) and a maximum acceptable operating temperature (Tmax). In an embodiment, Tmin and Tmax may be defined or set as part of the product specification or product requirements.

[0053] In one embodiment, the measured temperature value is compared with a first threshold corresponding to Tmin and a second threshold corresponding to Tmax to determine whether the measured temperature value (e.g., a DAC value corresponding to the operating temperature) is within or outside an acceptable range. In another embodiment, each of the set of thermometers generates a temperature flag signal in response to determining that the measured operating temperature of the memory die is outside an acceptable range. Figure 3A In the example shown, in response to the detection of an out-of-range operating temperature, thermometer A generates a flag signal A, thermometer B generates a flag signal B, and thermometer C generates a flag signal C.

[0054] Figure 4For the illustrative illustration of a memory die 438 comprising a set of thermometers 439, the set of thermometers includes a first internally powered thermometer (thermometer A) and one or more externally powered thermometers (e.g., thermometer B and / or thermometer C). In the example shown, the set of thermometers 439 includes thermometer A and thermometer B, and optionally includes thermometer C (as indicated by the dashed line).

[0055] In an embodiment, each thermometer periodically determines a measured temperature value (e.g., a DAC value) and compares the measured temperature value with threshold temperature values ​​(e.g., a first DAC value corresponding to Tmin and a second DAC value corresponding to Tmax). Based on this comparison, the thermometer determines whether the measured temperature value is within an acceptable or unacceptable range. If the measured temperature value is within an unacceptable range (e.g., above Tmax or below Tmin), then one or more thermometers generate a flag signal. Figure 3A As shown, thermometer A is configured to generate a flag signal A, thermometer B is configured to generate a flag signal B, and thermometer C is configured to generate a flag signal C. In an embodiment, since the thermometers may operate differently from each other (e.g., given different voltage supplies), one or more of the thermometers may generate a flag signal in response to determining that the measured temperature is within an unacceptable range.

[0056] In one embodiment, one or more flag signals generated by one or more thermometers from a set of thermometers 439 are transmitted to a local media controller 435 of the memory die 438. In another embodiment, the local media controller 435 may include a thermometer manager 436 to process the flag signals and provide corresponding signals to a memory subsystem controller 415 to issue an alarm to the host system 420 indicating an out-of-range operating temperature of the memory die 438. In yet another embodiment, the local media controller 435 may use pads or pins 416 of the memory die 438 monitored by the memory subsystem controller 415 to provide signals to the memory subsystem controller 415.

[0057] In another embodiment, a dedicated or “additional” pad 417 may optionally be provided (e.g., as indicated by the dashed lines on the pad and the corresponding communication paths of the flag signals) to receive one or more flag signals from one or more thermometers in a set of thermometers 439 for “direct” communication with the memory subsystem controller 415 to provide to the host system 420. In this embodiment, the memory subsystem controller 415 may monitor the dedicated pad 417 and detect the flag signals. For example, generating a flag signal may cause the voltage level associated with the dedicated pad to become approximately 0V, which is monitored and detected by the memory subsystem controller 415. In this example, the memory subsystem controller 415 may detect the approximately 0V voltage level of the dedicated pad 417 to determine that a flag signal has been generated and send a corresponding alarm to the host system 420.

[0058] In another embodiment, a ZQ calibration pad (e.g., a pad for calibrating the output impedance of the output driver and the on-die termination value across process, voltage, and temperature variations) can be shared and used for the flag signal. In this embodiment, instead of a dedicated pad, the flag signal is provided to a shared ZQ calibration pad for communication with the memory subsystem controller 415.

[0059] In an embodiment, the host system 420 may (e.g., via a local media controller 435 or "directly" via a dedicated pad) receive a flag signal alarm indicating an out-of-range operating temperature of the memory die 438 and perform a corresponding action. In an embodiment, the action performed by the host system may include, but is not limited to, terminating an ongoing memory access operation associated with the memory die 438. In an embodiment, all thermometers (e.g., internally powered thermometers and one or more externally powered thermometers) periodically measure the operating temperature of the memory die, and a minimum threshold level is compared to a maximum threshold level to achieve redundant out-of-range operating temperature detection and corresponding signal generation to alert the host system.

[0060] In an embodiment, each thermometer generates a value corresponding to the measured temperature (also referred to as the "measured temperature value"). In an embodiment, each thermometer includes a digital-to-analog converter (DAC) to generate a DAC value representing the measured temperature, wherein the DAC value is correlated with the measured temperature (e.g., the DAC value increases as the operating temperature of the memory die increases, and decreases as the operating temperature of the memory die decreases). The measured DAC value can be compared with one or more threshold levels (e.g., a first DAC value corresponding to the minimum temperature (Tmin) of the acceptable temperature range and a second DAC value corresponding to the maximum temperature (Tmax) of the acceptable temperature range) to determine whether the measured temperature is within or outside the acceptable range. As mentioned, if the measured operating temperature of the memory die is outside the acceptable range, then one or more thermometers generate a temperature flag signal to be provided to the host system. In an embodiment, the temperature flag signal can be provided directly to the host system (e.g., via the use of an additional pad disposed on the memory die) or via a local media controller.

[0061] In an embodiment, during a first moment of power-on operation of the memory die, the operating temperature of the memory die is determined by a set of thermometers to be within an acceptable operating temperature range. However, at a second moment after the power-on event, one or more thermometers determine that the operating temperature of the memory die is outside the acceptable temperature range (e.g., due to operating temperature changes caused by performing one or more memory access operations). In response to the detection of an out-of-range operating temperature by one of the thermometers, thermometer detection conditions (e.g., determining that the measured operating temperature is below a minimum acceptable temperature level or determining that the measured operating temperature is above a maximum acceptable temperature level) generate a corresponding temperature flag signal. In an embodiment, the temperature flag signal may be provided to a local media controller (e.g., Figure 4 The local media controller 435 or a dedicated temperature indicator pad. In an embodiment, if the local media controller 435 receives or detects a signal, the local media controller transmits the signal to the host system via the memory subsystem controller.

[0062] In an embodiment, at a first moment during the power-on operation of the memory die, the operating temperature of the memory die is determined by one or more thermometers to be outside the acceptable temperature range. In response to the detection of an out-of-range operating temperature by one of the thermometers, a thermometer detection condition generates a corresponding temperature flag signal. In an embodiment, the out-of-range temperature (e.g., a measured temperature below Tmin of the acceptable temperature range or above Tmax of the acceptable temperature range) may be detected by an internally powered thermometer (e.g., Figure 3A Thermometer A) or externally powered thermometer (e.g., Figure 3A Thermometer B or thermometer C) is used for testing.

[0063] In one embodiment, a temperature flag signal may be provided to a local media controller or a dedicated temperature flag pad monitored by the memory subsystem controller. In another embodiment, in response to the signal being detected by the local media controller 435, information relating to the signal is provided to the host system. In yet another embodiment, the host system may take action in response to issuing an alarm regarding an out-of-range operating temperature of the memory die.

[0064] Figure 5A and 5B This is a schematic illustration of instance memory dies 538A and 538B containing multiple thermometers, and associated instance circuitry configured to generate temperature flag signals and transmit them to dedicated temperature flag pads monitored by memory subsystem controllers 515A and 515B. In embodiments, as... Figure 5A As shown, the memory die 538A may include a set of thermometers (e.g., thermometer A, thermometer B, and / or thermometer C). In an embodiment, thermometer A is powered by an internal voltage supply, and thermometer B and / or thermometer C is powered by an external voltage supply, such as... Figure 3A As shown. Each thermometer is configured to generate a flag signal in response to determining that the measured operating temperature of the memory die 538A is outside an acceptable temperature range (e.g., below Tmin or above Tmax). The flag signal may be processed by circuitry (e.g., an "OR" circuit of open-drain N-type metal-oxide-semiconductor (NMOS) wiring as shown in FIG. 5A) such that a dedicated temperature flag pad goes low (e.g., approximately 0V) in response to the flag signal (e.g., flag signal A, flag signal B, or flag signal C). In an embodiment, the memory subsystem controller 515A monitors the dedicated temperature flag pads and identifies the flag signal (e.g., determines when the voltage level of the dedicated flag signal pad has gone low) to issue an alarm to the host system regarding the out-of-range operating temperature of the memory die 538A.

[0065] exist Figure 5B In the illustrated embodiment, the memory die 538B includes a set of thermometers (e.g., thermometer A and thermometer B and / or thermometer C) having an internally powered thermometer (e.g., thermometer A) and one or more externally powered thermometers (e.g., thermometer B and / or thermometer C). In this embodiment, each thermometer is configured to generate a flag signal in response to determining that a measured operating temperature of the memory die 538B is outside an acceptable temperature range (e.g., below Tmin or above Tmax). The flag signal may be generated by circuitry (e.g., such as...). Figure 5BThe open-drain P-type metal-oxide-semiconductor (PMOS) wiring shown is processed by an "OR" circuit such that, in response to a flag signal (e.g., flag signal A, flag signal B, or flag signal C), a dedicated temperature flag pad is set to a high voltage level (e.g., approximately Vint, Vext1, or Vext2, depending on the embodiment). In an embodiment, the memory subsystem controller 515B monitors the dedicated temperature flag pad and identifies the flag signal (e.g., determines when the voltage level of the dedicated flag signal pad has become high) to issue an alarm to the host system for an out-of-range operating temperature of the memory die 538B.

[0066] Figure 6 This is a flowchart illustrating an example method for generating a flag signal indicating that the operating temperature of a memory die is outside an acceptable temperature range, according to one or more embodiments of this disclosure. Method 600 may be performed by processing logic that may include hardware (e.g., processing means, circuitry, dedicated logic, programmable logic, microcode, device hardware, integrated circuits, etc.), software (e.g., instructions that run or execute on a processing means), or a combination thereof. In some embodiments, method 600 is performed by a thermometer manager 136 of a local media controller 135 and... Figure 1 A set of thermometers 139 performs the operation. Although shown in a specific order or sequence, the order of the processes may be modified unless otherwise specified. Therefore, it should be understood that the illustrated embodiments are merely examples, and the illustrated processes may be performed in different orders, and some processes may be performed in parallel. In addition, one or more processes may be omitted in various embodiments. Therefore, not all processes are required in each embodiment. Other process flows are also possible.

[0067] At operation 610, a first temperature value is determined. For example, an internal power supply thermometer of the memory die can determine the first measured operating temperature value of the memory die. In an embodiment, the internal power supply thermometer (e.g., Figure 3A The thermometer A) is powered by an internal voltage supply (e.g., Figure 3A The system is powered by Vint and the operating temperature of the memory die is measured to determine the first measured operating temperature value.

[0068] At operation 620, a second temperature value is determined. For example, an externally powered thermometer for the memory die can determine the second measured operating temperature value of the memory die. In an embodiment, the externally powered thermometer (e.g., Figure 3A The thermometer B or C) is supplied by an external voltage supply (e.g., Figure 3A The Vext1 or Vext2 is powered, and the operating temperature of the memory die is measured to determine the second measured operating temperature value.

[0069] At operation 630, either a first condition or a second condition is detected. For example, at least one of an internally powered thermometer or an externally powered thermometer detects that either a first measured operating temperature value or a second measured operating temperature value satisfies either the first condition or the second condition. In an embodiment, the first condition is satisfied if either the first measured operating temperature value or the second measured operating temperature value is below a minimum temperature threshold (Tmin) of the acceptable operating temperature range. In an embodiment, the second condition is satisfied if either the first measured operating temperature value or the second measured operating temperature value is above a maximum temperature threshold (Tmax) of the acceptable operating temperature range.

[0070] At operation 640, a signal is generated. For example, in response to the satisfaction of one of a first condition (e.g., the operating temperature is below a minimum acceptable operating temperature) or a second condition (e.g., the operating temperature is above a maximum acceptable operating temperature), at least one of an internal power supply thermometer or an external power supply thermometer may generate a signal indicating an out-of-range operating temperature of the memory die. In an embodiment, the signal (e.g., Figure 3A The flag signals A, B, and / or C can be transmitted to the processing logic of the local media controller 135 (e.g., Figure 1 The local media controller 135 (temperature manager 136). The local media controller 135 can also transmit signals to the memory subsystem controller (e.g., Figure 4 The memory subsystem controller 415) is used to issue an alarm to the host system that is operating out of range of the memory die. In an embodiment, the host system may be configured to perform an action in response to an alarm associated with out-of-range temperature detection (e.g., terminate an ongoing operation associated with the memory die, discard data returned by the memory die associated with a read operation, switch to a redundant memory system containing another memory die, etc.).

[0071] Figure 7 An example machine of computer system 700 is shown, within which an instruction set is executable to cause the machine to perform any one or more of the methods discussed herein. In some embodiments, computer system 700 may correspond to including, coupled to, or utilizing a memory subsystem (e.g., Figure 1 The host system (e.g., memory subsystem 110) of the memory subsystem 110 Figure 1 The host system 120, or may be used to perform controller operations (e.g., execute the operating system to execute instructions 726 to execute management instructions communicatively coupled to...). Figure 1The thermometer manager 136, with a set of thermometers 139, generates signals corresponding to the out-of-range operating temperature of the memory die. In alternative embodiments, the machine may be connected (e.g., networked) to other machines in a LAN, intranet, extranet, and / or the Internet. The machine may operate as a peer-to-peer (or distributed) network machine in a peer-to-peer (or distributed) network environment or as a server or client machine in a cloud computing infrastructure or environment, operating at the capacity of a server or client machine in a client-server network environment.

[0072] The machine may be a personal computer (PC), tablet PC, set-top box (STB), personal digital assistant (PDA), cellular phone, network device, server, network router, switch, or bridge, or any machine capable of executing a set of instructions (sequentially or otherwise) specifying actions to be performed by the machine. Furthermore, although a single machine is described, the term "machine" should be understood to include any set of machines that individually or collectively execute one or more sets of instructions to perform any one or more of the methods discussed herein.

[0073] The example computer system 700 includes a processing device 702, a main memory 704 (e.g., read-only memory (ROM), flash memory, dynamic random access memory (DRAM), such as synchronous DRAM (SDRAM) or Rambus DRAM (RDRAM), etc.), a static memory 706 (e.g., flash memory, static random access memory (SRAM), etc.), and a data storage system 718, which communicate with each other via a bus 730.

[0074] Processing device 702 represents one or more general-purpose processing devices, such as microprocessors, central processing units, etc. More specifically, the processing device may be a Complex Instruction Set Computing (CISC) microprocessor, a Reduced Instruction Set Computing (RISC) microprocessor, a Very Long Instruction Word (VLIW) microprocessor, or a processor implementing other instruction sets, or a combination of instruction sets. Processing device 702 may also be one or more special-purpose processing devices, such as application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), digital signal processors (DSPs), network processors, or the like. Processing device 702 is configured to execute instructions 726 for performing the operations and steps discussed herein. Computer system 700 may further include a network interface device 708 for communication via network 720.

[0075] The data storage system 718 may include a machine-readable storage medium 724 (also referred to as a computer-readable medium, such as a non-transitory computer-readable medium) on which one or more instruction sets 726 or software embodying any or more of the methods or functions described herein are stored. The instructions 726 may also reside wholly or at least partially within main memory 704 and / or processing device 702 during execution by computer system 700, the main memory 704 and processing device 702 also constituting machine-readable storage media. The machine-readable storage medium 724, the data storage system 718, and / or main memory 704 may correspond to... Figure 1 The memory subsystem 110.

[0076] In one embodiment, instruction 726 includes instructions for implementing the corresponding Figure 1 The machine-readable storage medium 724 contains functional instructions for multiple thermometers 139 and thermometer manager 136. While the machine-readable storage medium 724 is shown as a single medium in the exemplary embodiment, the term "machine-readable storage medium" should be considered to include a single medium or multiple media storing one or more sets of instructions. The term "machine-readable storage medium" should also be considered to include any medium capable of storing or encoding a set of instructions executable by a machine and causing the machine to perform any one or more of the methods of this disclosure. The term "machine-readable storage medium" may include, but is not limited to, solid-state memory, optical media, and magnetic media.

[0077] Some parts of the previously described algorithms and symbolic representations of operations on data bits within computer memory have been presented. These algorithms are described and represented in a way that those skilled in the art of data processing can most effectively communicate the essence of their work to others skilled in the art. In this paper, and generally in general, algorithms are conceived as self-consistent sequences of operations that produce desired results. An operation is an operation that requires physical manipulation of a physical quantity. Usually (but not always), these quantities take the form of electrical or magnetic signals that can be stored, combined, compared, and otherwise manipulated. It has been shown that it is sometimes convenient to refer to these signals as bits, values, elements, symbols, characters, items, numbers, etc., primarily for common use.

[0078] However, it should be remembered that all these and similar terms will be associated with appropriate physical quantities and are merely convenient notations for application to those quantities. This disclosure can refer to the actions and processes of a computer system or similar electronic computing device that manipulate and transform data represented as physical (electronic) quantities in the registers and memories of a computer system into other data similarly represented as physical quantities in the computer system's memory or registers or other such information storage systems.

[0079] This disclosure also relates to apparatus for performing the operations described herein. Such apparatus may be specifically constructed for the desired purpose, or may comprise a general-purpose computer selectively activated or reconfigured by a computer program stored in a computer. Such computer programs may be stored in computer-readable storage media, such as, but not limited to, any type of disk, including floppy disks, optical disks, CD-ROMs and magneto-optical disks, read-only memory (ROM), random access memory (RAM), EPROM, EEPROM, magnetic cards or optical cards, or any type of media suitable for storing electronic instructions, each coupled to a computer system bus.

[0080] The algorithms and displays presented herein are not inherently related to any particular computer or other device. Various general-purpose systems can be used with the programs taught herein, or it may prove convenient to construct more specialized devices to perform the methods described herein. The structures of various such systems will be presented as illustrated in the description below. Furthermore, this disclosure is described without reference to any particular programming language. It should be understood that the teachings of this disclosure as described herein can be implemented using various programming languages.

[0081] This disclosure may be provided as a computer program product or software, which may include a machine-readable medium having instructions stored thereon that can be used to program a computer system (or other electronic device) to perform processes according to this disclosure. The machine-readable medium includes any mechanism for storing information in a machine-readable (e.g., computer-readable) form. In some embodiments, the machine-readable (e.g., computer-readable) medium includes machine-readable (e.g., computer-readable) storage media, such as read-only memory (“ROM”), random access memory (“RAM”), disk storage media, optical storage media, flash memory components, etc.

[0082] In the foregoing description, embodiments of this disclosure have been described with reference to specific example embodiments thereof. It will be apparent that various modifications may be made to this disclosure without departing from the broader spirit and scope of the embodiments set forth in the appended claims. Therefore, the description and drawings should be viewed in an illustrative rather than restrictive sense.

Claims

1. A memory device comprising: Memory die, comprising: An internally powered thermometer, including a first temperature measuring circuit, performs a first operation including the following: Measure the first operating temperature value of the memory die; The measured operating temperature value satisfies either the first condition or the second condition; and A first signal indicating an out-of-range operating temperature of the memory die is generated in response to the first measured operating temperature value satisfying either the first condition or the second condition; and An externally powered thermometer, comprising a second temperature measuring circuit to perform a second operation including the following: The second measurement of the operating temperature value of the memory die; The measured operating temperature value of the second measurement satisfies either the first condition or the second condition; and A second signal indicating the out-of-range operating temperature of the memory die is generated in response to the second measured operating temperature value satisfying either the first condition or the second condition.

2. The memory device according to claim 1, further comprising: A controller, operatively coupled to the internally powered thermometer and the externally powered thermometer, performs operations including the following: The first signal or the second signal indicates the out-of-range operating temperature of the memory die; and An alarm associated with the first signal or the second signal is provided to the host system.

3. The memory device of claim 1, wherein the first condition is satisfied when either the first measured operating temperature value or the second measured operating temperature value is lower than a minimum temperature threshold of an acceptable operating temperature range associated with the memory die; and wherein the second condition is satisfied when either the first measured operating temperature value or the second measured operating temperature value is higher than a maximum temperature threshold of the acceptable operating temperature range associated with the memory die.

4. The memory device of claim 1, wherein the externally powered thermometer receives a first external voltage level from a voltage source of the host system.

5. The memory device of claim 1, wherein the memory die further includes a dedicated pad for receiving one or more of the first signal or the second signal indicating an out-of-range operating temperature of the memory die.

6. The memory device of claim 5, wherein the dedicated pad is monitored by the memory subsystem controller of the memory device to detect one or more of the first signal or the second signal indicating an out-of-range operating temperature of the memory die.

7. The memory device of claim 1, wherein the memory die further comprises a ZQ calibration pad configured to receive one or more of the first signal or the second signal indicating an out-of-range operating temperature of the memory die.

8. The memory device of claim 1, wherein the memory die includes an additional externally powered thermometer, wherein the externally powered thermometer receives a first external voltage level from a voltage source of the host system; and wherein the additional externally powered thermometer receives a second external voltage level from the voltage source of the host system.

9. A memory subsystem comprising: A memory device comprising: A first thermometer includes a first temperature measuring circuit to measure a first measured operating temperature value and generate a first signal indicating an out-of-range operating temperature of the memory device, wherein the first thermometer is powered by an internal voltage source of the memory device; and A second thermometer includes a second temperature measuring circuit to measure a second measured operating temperature value and generate a second signal indicating an out-of-range operating temperature of the memory device, wherein the second thermometer is powered by an external voltage source of the host system; and Control logic, operatively coupled to the first and second thermometers, performs operations including: Receive at least one of the first signal or the second signal; and An alarm associated with at least one of the first signal or the second signal is transmitted to the host system.

10. The memory subsystem of claim 9, wherein the first signal is generated in response to the determination by the first thermometer that the first measured operating temperature value of the memory device satisfies either a first condition or a second condition.

11. The memory subsystem of claim 10, wherein the second signal is generated in response to the second thermometer determining that a second measured operating temperature value of the memory device satisfies either the first condition or the second condition.

12. The memory subsystem of claim 11, wherein the first condition is satisfied when either the first measured operating temperature value or the second measured operating temperature value is below a minimum temperature threshold of an acceptable operating temperature range associated with the memory device; and wherein the second condition is satisfied when either the first measured operating temperature value or the second measured operating temperature value is above a maximum temperature threshold of the acceptable operating temperature range associated with the memory device.

13. The memory subsystem of claim 9, wherein the memory device includes a dedicated pad monitored by the control logic to receive at least one of the first signal or the second signal.

14. The memory subsystem of claim 9, wherein in response to the alarm, the host system performs one or more of the following actions: terminating the ongoing memory access operation, switching to a redundant memory subsystem, or discarding data associated with the memory device.

15. A memory device comprising: A first thermometer includes a first temperature measuring circuit to measure a first measured operating temperature value and generate a first signal indicating an out-of-range operating temperature of the memory device. An internal voltage source is used to provide a first voltage to power the first thermometer; A second thermometer includes a second temperature measuring circuit to measure a second measured operating temperature value and generate a second signal indicating an out-of-range operating temperature of the memory device, wherein the second thermometer is powered by a second voltage provided by an external voltage source of the host system. as well as A dedicated pad that receives at least one of the first signal or the second signal, wherein the dedicated pad is monitored by a memory subsystem controller communicatively coupled to the host system.

16. The memory device of claim 15, wherein the memory subsystem controller provides an alarm to the host system in response to detecting one of the first signal or the second signal.

17. The memory device of claim 15, wherein the first signal is generated in response to the determination by the first thermometer that the first measured operating temperature value of the memory device satisfies either a first condition or a second condition.

18. The memory device of claim 17, wherein the second signal is generated in response to the second thermometer determining that the second measured operating temperature value of the memory device satisfies either the first condition or the second condition.

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