Hashing operations in memory for data sharing

Abstract

Embodiments of the present disclosure relate to hash operations in memory for data sharing. A method includes receiving a command from a host to an address of a memory device, the command including a different address. The method also includes determining whether to perform a hash operation based on the address, accessing data stored in a memory cell having the different address in response to determining to perform the hash operation. The method further includes performing the hash operation using the data to generate a signature for the data, and providing access to the host to the signature to determine whether the data is duplicate data.

Description

TECHNICAL FIELD

[0001] Embodiments of the present disclosure generally relate to memory sub-systems, and more specifically, to performing hash operations in memory for data sharing. BACKGROUND

[0002] A memory sub-system can include one or more memory devices that store data. The memory devices can be, for example, non-volatile memory devices and volatile memory devices. Generally, a host system can utilize a memory sub-system to store data at and retrieve data from the memory devices. SUMMARY

[0003] According to one embodiment of the present disclosure, a method is provided. The method includes receiving a command from a host to an address of a memory device, the command including a different address, determining whether to perform a hash operation based on the address, in response to determining to perform the hash operation, accessing data stored in a memory cell having the different address, performing the hash operation in a memory sub-system using the data to generate a signature for the data, and providing access to the host to the signature to determine whether the data is duplicate data.

[0004] According to another embodiment of the present disclosure, an apparatus is provided. The apparatus includes a processing device. The processing device is configured to access a first system physical address of a memory cell of a memory device storing data, wherein the first system physical address is provided by a hypervisor, and wherein the first system physical address is associated with a first guest physical address, provide the first system physical address to a memory sub-system to perform a hash operation on the data, access a signature of the data generated using the hash operation, compare the signature to other signatures to determine whether the data and a different data are duplicate data, wherein the different data is stored in a different memory cell having a second system physical address associated with a second guest physical address, in response to determining that the data and the different data are duplicate data, update a translation table by associating the first guest physical address and the second guest physical address with the system physical address.

[0005] According to another embodiment of this disclosure, an apparatus is provided. The apparatus includes: a memory array; and a processing means coupled to the memory array. The processing means is configured to: receive from a host a command of a first address of a memory device, the command including a second address and a third address as metadata; determine whether to perform an operation based on the first address; in response to determining to perform the operation using the first address: accessing data stored in a memory cell of the memory device having the second address; accessing different data stored in different memory cells of the memory device having the third address; using the data to perform the operation to generate a first signature for the data and using the different data to generate a second signature; and in response to comparing the first signature and the second signature, providing an indication of whether the data and the different data are duplicate data. Attached Figure Description

[0006] This disclosure will be more fully understood from the detailed description given below and the accompanying drawings of various embodiments thereof.

[0007] Figure 1 This describes an example computing system including a memory subsystem according to some embodiments of the present disclosure.

[0008] Figure 2 This describes an example computing system including a memory subsystem according to some embodiments of the present disclosure.

[0009] Figure 3 This is a block diagram of a data hashing engine according to some embodiments of the present disclosure.

[0010] Figure 4 This is a block diagram of a memory array according to some embodiments of the present disclosure.

[0011] Figure 5 This is a block diagram of a conversion table according to some embodiments of the present disclosure.

[0012] Figure 6 This is a flowchart corresponding to a method for performing a hash operation for data sharing in a memory according to some embodiments of the present disclosure.

[0013] Figure 7 This is a block diagram of an example computer system in which embodiments of this disclosure may be operated. Detailed Implementation

[0014] Various aspects of this disclosure relate to sharing data stored in a memory subsystem—more precisely, a memory subsystem—that performs hash operations for data sharing. The memory subsystem can be a storage system, a storage device, a memory module, or a combination thereof. An example of a memory subsystem is, for example, a solid-state drive (SSD) storage system. The following is combined with… Figure 1 Examples of storage devices and memory modules are described. Generally, a host system may utilize a memory subsystem comprising one or more components, such as a memory device for storing data. The host system can provide data to be stored in the memory subsystem and can request data to be retrieved from the memory subsystem.

[0015] Computing systems running a supermanager with multiple virtual machines (VMs) are typically memory-constrained. Each VM has VM-specific memory pages. Various memory pages can be shared. Shared pages can contain pages with the same data. Shared pages can contain the same data across shared pages, such as program code or in-memory data. Read-only access can be provided to shared pages.

[0016] The super manager can attempt to find common pages with shared data using hashing techniques. Hashing summarizes content by passing the contents of contiguous data (e.g., memory pages comprising 4kB) through a hash algorithm and obtaining a small output as a signature (e.g., 64 bits or more). When the same hash algorithm is used on each page, each page can have a unique signature (e.g., a hash) associated with it. Therefore, the super manager's translation table (e.g., the super manager page table) can point to the same page across multiple VMs. Pointing various addresses to the same page is known as page sharing. Page sharing reduces the total number of pages required to operate one or more VMs. Reducing the total number of pages required to operate one or more VMs frees up space for more VMs or for additional operations.

[0017] The mechanism employed by the super manager during write operations to common pages containing shared data is called Copy-on-Write (CoW). This involves first copying the entire page's data, then writing specific data segments and updating the translation table (e.g., the page table). The super manager can run on a host's CPU core (e.g., a processing unit), utilizing the core's computational resources and cache. In computing systems running a super manager with several VMs, page sharing at the super manager and COW at the super manager can lead to memory resource constraints.

[0018] The aspects of this disclosure address the above and other shortcomings by implementing a Data Hash Engine (DHE) in the memory subsystem. The DHE offloads hashing operations performed by the host to the memory subsystem. The DHE may include hardware and / or firmware to perform hashing operations on data stored in the memory subsystem. The host may provide commands to the memory subsystem to trigger the execution of a hashing operation on data stored in the memory subsystem. The hashing operation may include generating a signature on the data stored in the memory subsystem. The signature (e.g., the hash) is provided to the host. The host may maintain control over the identification and management of common pages. However, the host can offload the execution of hashing operations to the memory subsystem. Offloading hashing operations to the memory subsystem allows the host to be more efficient with fewer operations available to it. Offloading hashing operations to the memory subsystem allows the host to operate more efficiently with resources available for performing hashing operations freed up for performing different operations.

[0019] The memory device can be a non-volatile memory device. An example of a non-volatile memory device is a three-dimensional cross-point memory device containing a cross-point array of non-volatile memory cells. The following section combines... Figure 1 Other examples of non-volatile memory devices are described. A non-volatile memory device (e.g., a three-dimensional cross-point memory device) may be a package of one or more memory components (e.g., memory dies). Each die may consist of one or more planes. Planes may be divided into logical units. For example, a non-volatile memory device may be assembled from multiple memory dies, each of which may individually form a component of the memory device.

[0020] An example of a non-volatile memory device is a NAND flash memory device (also known as flash memory). The following section combines... Figure 1 Other examples of non-volatile memory devices are described below. A non-volatile memory device is a package of one or more dies. Each die may consist of one or more planes. Planes may be grouped into logical units (LUNs). For some types of non-volatile memory devices (e.g., NAND devices), each plane consists of a set of physical blocks. Each block consists of a set of pages. Each page consists of a set of memory cells (“cells”). A cell is an electronic circuit for storing information. Hereinafter, a block refers to a cell of a memory device used to store data and may contain groups of memory cells, groups of word lines, word lines, or individual memory cells. For some memory devices, a block (also referred to below as a “memory block”) is the smallest erasable area. Pages cannot be erased individually; only the entire block can be erased.

[0021] Each memory device may contain one or more arrays of memory cells. Depending on the cell type, a cell may store one or more bits of binary information and has various logical states related to the number of bits stored. Logical states may be represented by binary values ​​(e.g., "0" and "1") or combinations of these values. Various types of cells exist, such as single-level cells (SLC), multi-level cells (MLC), three-level cells (TLC), and four-level cells (QLC). For example, an SLC may store one bit of information and have two logical states.

[0022] Some NAND memory devices employ a floating gate architecture, where memory access is controlled based on the relative voltage variation between the bit lines and word lines. Other examples of NAND memory devices may employ an alternative gate architecture that may include a word line layout that allows for the trapping of charges corresponding to data values ​​within the memory cell based on the properties of the materials used to construct the word lines.

[0023] Figure 1 This description describes an example computing system 100 including a memory subsystem 110 according to some embodiments of the present disclosure. The memory subsystem 110 may include media such as one or more volatile memory devices (e.g., memory device 140), one or more non-volatile memory devices (e.g., memory device 130), or a combination thereof.

[0024] The memory subsystem 110 may be a storage device, a memory module, or a combination of both. Examples of storage devices include solid-state drives (SSDs), flash drives, universal serial bus (USB) flash drives, embedded multimedia controller (eMMC) drives, universal flash memory (UFS) drives, secure digital cards (SD cards), and hard disk drives (HDDs). Examples of memory modules include dual in-line memory modules (DIMMs), small outline DIMMs (SO-DIMMs), and various types of non-volatile dual in-line memory modules (NVDIMMs).

[0025] The computing system 100 may be a computing device, such as a desktop computer, laptop computer, server, web server, mobile device, vehicle (e.g., airplane, drone, train, car or other means of transport), device with Internet of Things (IoT) capabilities, embedded computer (e.g., embedded computer contained in a vehicle, industrial equipment or networked commercial device), or such computing device containing memory and processing devices.

[0026] The computing system 100 may include a host system 120 coupled to one or more memory subsystems 110. In some embodiments, the host system 120 is coupled to different types of memory subsystems 110. Figure 1This describes an example of a host system 120 coupled to a memory subsystem 110. As used herein, “coupled to” or “coupled with” generally refers to a connection between components, which can be an indirect or direct communication connection (e.g., without intervening components), whether wired or wireless, including, for example, electrical connections, optical connections, magnetic connections, etc.

[0027] Host system 120 may include a processor chipset and a software stack executed by the processor chipset. The processor chipset may include one or more cores, one or more caches, a memory controller (e.g., an SSD controller), and a storage protocol controller (e.g., a PCIe controller, a SATA controller). Host system 120 uses memory subsystem 110, for example, to write data to memory subsystem 110 and to read data from memory subsystem 110.

[0028] Host system 120 can be coupled to memory subsystem 110 via a physical host interface. Examples of physical host interfaces include, but are not limited to, Serial Advanced Technology Attachment (SATA) interfaces, Peripheral Component Interconnect High Speed ​​(PCIe) interfaces, Universal Serial Bus (USB) interfaces, Fibre Channel, Serial Attached SCSI (SAS), Small Computer System Interface (SCSI), Dual Data Rate (DDR) memory bus, Dual In-line Memory Module (DIMM) interfaces (e.g., DIMM sockets supporting Dual Data Rate (DDR)), Open NAND Flash Interface (ONFI), Dual Data Rate (DDR), Low Power Dual Data Rate (LPDDR), or any other interface. The physical host interface can be used to transfer data between host system 120 and memory subsystem 110. When memory subsystem 110 is coupled to host system 120 via a PCIe interface, host system 120 can further utilize an NVM Fast (NVMe) interface to access components (e.g., memory device 130). The physical host interface provides an interface for transmitting control, address, data and other signals between the memory subsystem 110 and the host system 120. Figure 1 The memory subsystem 110 is illustrated as an example. Generally, the host system 120 can access multiple memory subsystems via the same communication connection, multiple individual communication connections, and / or combinations of communication connections.

[0029] Memory devices 130 and 140 may comprise any combination of different types of non-volatile memory devices and / or volatile memory devices. Volatile memory devices (e.g., memory device 140) may be, but are not limited to, random access memory (RAM), such as dynamic random access memory (DRAM) and synchronous dynamic random access memory (SDRAM).

[0030] Some examples of non-volatile memory devices (e.g., memory device 130) include NAND type flash memory and in-place write memory, such as three-dimensional crosspoint (“3D crosspoint”) memory devices, which are crosspoint arrays of non-volatile memory cells. The crosspoint array of non-volatile memory can be combined with a stackable cross-grid data access array to perform bit storage based on changes in volume resistance. Furthermore, compared to many flash-based memories, crosspoint non-volatile memory can perform in-place write operations, where non-volatile memory cells can be programmed without pre-erasing them. NAND-type flash memory includes, for example, two-dimensional NAND (2D NAND) and three-dimensional NAND (3D NAND).

[0031] Each of the memory devices 130 and 140 may include one or more arrays of memory cells. One type of memory cell, such as a single-level cell (SLC), may store one bit per cell. Other types of memory cells, such as multi-level cell (MLC), three-level cell (TLC), four-level cell (QLC), and five-level cell (PLC), may store multiple bits per cell. In some embodiments, each of the memory devices 130 may include one or more arrays of memory cells, such as SLC, MLC, TLC, QLC, or any combination thereof. In some embodiments, a particular memory device may include an SLC portion of memory cells, as well as an MLC portion, a TLC portion, a QLC portion, or a PLC portion. The memory cells of the memory device 130 may be grouped into pages, which may refer to logical cells of the memory device used for storing data. In the case of some types of memory (e.g., NAND), pages may be grouped to form blocks.

[0032] While non-volatile memory components, such as three-dimensional cross-point arrays of non-volatile memory cells and NAND-type memories (e.g., 2D NAND, 3D NAND), are described, memory device 130 may be based on any other type of non-volatile memory or storage device, such as read-only memory (ROM), phase-change memory (PCM), auto-select memory, other chalcogenide-based memories, ferroelectric transistor random access memory (FeTRAM), ferroelectric random access memory (FeRAM), magnetic random access memory (MRAM), spin-transfer torque (STT)-MRAM, conductive bridged RAM (CBRAM), resistive random access memory (RRAM), oxide-based RRAM (OxRAM), NOR flash memory, or electrically erasable programmable read-only memory (EEPROM).

[0033] The memory subsystem controller 115 (or simply controller 115) can communicate with the memory device 130 to perform operations, such as reading data, writing data, or erasing data at the memory device 130, and other such operations. The memory subsystem controller 115 may include hardware, such as one or more integrated circuits and / or discrete components, buffer memories, or combinations thereof. The hardware may include digital circuitry with dedicated (i.e., hard-decoded) logic to perform the operations described herein. The memory subsystem controller 115 may be a microcontroller, dedicated logic circuitry (e.g., field-programmable gate array (FPGA), application-specific integrated circuit (ASIC), etc.), or other suitable processor.

[0034] The memory subsystem controller 115 may include a processor 117 (e.g., a processing device) configured to execute instructions stored in local memory 119. In the illustrated example, the local memory 119 of the memory subsystem controller 115 includes embedded memory configured to store instructions for performing various processes, operations, logic flows, and routines for controlling the operation of the memory subsystem 110 (including handling communication between the memory subsystem 110 and the host system 120).

[0035] In some embodiments, local memory 119 may include memory registers storing memory pointers, retrieved data, etc. Local memory 119 may also include read-only memory (ROM) for storing microcode. Although Figure 1 The instance memory subsystem 110 in the present disclosure is described as including a memory subsystem controller 115, but in another embodiment of the present disclosure, the memory subsystem 110 does not include a memory subsystem controller 115, but may rely on external control (e.g., provided by an external host or by a processor 102 or controller separate from the memory subsystem).

[0036] Generally, the memory subsystem controller 115 can receive commands or operations from the host system 120 and can translate these commands or operations into instructions or appropriate commands to implement desired access to memory devices 130 and / or 140. The memory subsystem controller 115 may be responsible for other operations, such as media management operations. Media management operations may include wear leveling operations, garbage collection operations, error detection and error correction code (ECC) operations, encryption operations, caching operations, and resolving the translation between logical addresses (e.g., logical block addresses (LBAs), namespaces) and physical addresses (e.g., physical block addresses, physical media locations, etc.) associated with memory device 130. The memory subsystem controller 115 may also include interface circuitry communicating with the host system 120.

[0037] The memory subsystem 110 may also include additional circuitry or components not described. In some embodiments, the memory subsystem 110 may include cache or buffer (e.g., DRAM) and address circuitry (e.g., row decoder and column decoder) that can receive addresses from the memory subsystem controller 115 and decode the addresses to access memory device 130 and / or memory device 140.

[0038] In some embodiments, memory device 130 includes a local media controller 135 that operates together with memory subsystem controller 115 to perform operations on one or more memory cells of memory device 130. An external controller (e.g., memory subsystem controller 115) may externally manage memory device 130 (e.g., perform media management operations on memory device 130). In some embodiments, memory device 130 is a managed memory device, which is a native memory device combined with a local controller (e.g., local controller 135) for media management within the same memory device package. An example of a managed memory device is a managed NAND (MNAND) device.

[0039] The memory subsystem controller 115 may include DHE 113. Although Figure 1 As not shown, DHE 113 may include various circuits to perform hash operations on data stored in memory devices 130, 140. In some embodiments, DHE 113 may include dedicated circuitry in the form of an ASIC, FPGA, state machine, and / or other logic circuitry, which allows DHE 113 to schedule and / or perform operations to selectively perform hash operations for host 120.

[0040] Memory subsystem 110 may perform hash operations at DHE 113 to offload the hash operation from host 120 (e.g., processor 102 of host 120). Memory subsystem 110 may share the signature generated by the hash operation with host 120. DHE 113 may perform hash operations on blocks of data across an entire page to generate signatures. A signature is a unique identifier of the data (e.g., a data page) generated by performing a hash operation on the data. The signature may be referred to as the hash of the data. DHE 113 may perform hash operations sequentially on the data in the blocks. DHE 113 retains intermediate results of hash operations to be used with the next data block. DHE 113 may be implemented as a hardware fixed-state machine and / or via firmware specifically designed for DHE 113. As used herein, a fixed-state machine includes hardware and / or firmware that may be in one of a finite number of states that do not change. DHE 113 may perform different types of operations that may be loaded / configured at system startup and / or run dynamically via firmware. The source and destination physical / logical memory addresses can be provided by software intent (e.g., a super manager) via processor 102 through a nondeterministic protocol. The super manager can provide the source (e.g., source address) and destination (e.g., destination address) to a specific address (e.g., an address in a region of memory subsystem 110) via dedicated commands or write commands. The resulting nondeterministic complete message, including a signature, can be transmitted to host 120 via the same nondeterministic protocol. DHE 113 can be configured to perform a hash operation on the sequence data via tags provided to the target device when the data is written to a specific memory region.

[0041] Specific regions of memory can be pre-marked to be identified by the DHE 113 as regions for performing hash operations. For example, a specific region can be a multiple of a 4k-bit page size. When a page (e.g., a 4k-bit page of 64×64-bit sequential data) is written from a separate storage / memory device, the memory subsystem can receive data in blocks (e.g., 64-bit blocks). The DHE 113 can identify the received page by address and can perform hash operations sequentially on each block. The DHE 113 can use state capture of intermediate results to finally generate a signature (e.g., a 64-bit signature). The signature can be stored in a separate address region as a list of consecutive signatures (e.g., a list of 64-bit signatures) for sequentially locating pages (e.g., 64k-bit pages).

[0042] DHE 113 can be implemented in conjunction with a virtualized environment where page sharing functionality is invoked and controlled by the super manager and / or during operating system operations attempting to find similar pages. DHE 113 can also be implemented for storing persistent media containing large amounts of data and / or programs. Integrity checks can be performed on the storage subsystem 110 itself, close to the data source, without involving the host 120.

[0043] Figure 2 This description describes an example computing system 200 including a memory subsystem 210 according to some embodiments of the present disclosure. The computing system 200 includes VMs 221-1 and 221-2, a super manager 223, and the memory subsystem 210. VMs 221-1 and 221-1, referred to as VMs 221, also include operating systems (OS) 222-1 and 222-2, referred to as OSs 222. The super manager 223 includes a translation table 224 and a hash table 226. The memory subsystem 210 includes a DHE 213, a memory device 230, and a memory array 225. Although the memory device 230 is labeled 230, the memory device may include volatile and / or non-volatile memory.

[0044] In various cases, the OS 222, VM 221, and super manager 223 can be implemented as software. The memory subsystem 210 is implemented as hardware. The OS 222, VMM 221, and super manager 223 can be implemented by... Figure 1 The processor 102 of the host 102 is implemented.

[0045] OS 222 may request access to an address in VM 221. The address provided by OS 222 to VM 221 may be a system virtual address. As used herein, a system virtual address refers to the address of the virtual software system provided by VM 221. VM 221 may resolve the system virtual address to a guest physical address. As used herein, a guest physical address refers to the address of the virtual physical system provided by the super manager. VM 221 may provide the guest physical address to super manager 223. Super manager 223 may use translation table 224 to resolve the guest physical address to a system physical address. As used herein, a system physical address refers to the address of memory subsystem 110.

[0046] Translation table 224 can be used to resolve client physical addresses to system physical addresses. For example, a first client physical address can be resolved to a first system physical address, and a second client physical address can be resolved to a second system physical address. The super manager 223 can provide the first system physical address and the second physical address, along with a request, to the memory subsystem 210 to generate a signature for data stored in memory cells having the first system physical address and the second physical address. The super manager 223 can provide the first system physical address to the memory subsystem 210 to determine whether the memory cells having the first system physical address and the memory cells having the second system physical address store the same data.

[0047] The memory subsystem 210 may receive a system physical address corresponding to the memory device 230. For example, the memory subsystem 210 may receive a memory array 225 corresponding to the memory device 230 or Figure 1The system physical address of local memory 119. DHE 213 can access the system physical address to perform a hash operation on data stored in memory cells of memory array 225 with the system physical address. The result of the hash operation is a unique signature for the data stored in memory cells of memory array 225 with the system physical address.

[0048] As used in this article, hashing is any number of operations that can be used to map data of any size to a fixed-size value. The value produced using hashing operations (e.g., a fixed-size value) may be referred to as a hash value, hash code, hash, and / or signature (e.g., a hash signature).

[0049] The memory subsystem 210 can return a signature generated using a hash operation to the super manager 223. The memory subsystem 210 can also return the signature to the host of the super manager 223. The signature can be stored in the host's cache and / or accessible via the host's processor for use by the super manager 223.

[0050] The super manager 223 may store a signature and its corresponding address in a hash table 226. If data stored in memory with an address is used to generate a signature, the signature may be associated with and / or may correspond to an address. The super manager 223 may store a first signature provided by memory subsystem 210 and associated with a first system physical address and a second signature provided by memory subsystem 210 and associated with a second system physical address in the hash table 226. The super manager 223 may retrieve the first signature and the second signature from the hash table to compare the first signature and the second signature respectively using the first system physical address and the second system physical address. The first signature may be compared with the second signature to determine whether the first data stored in memory with the first system physical address is the same as the second data stored in memory with the second system physical address.

[0051] In response to determining that the first signature and the second signature are not equal, the super manager 223 can avoid modifying the translation table 224. In response to determining that the first signature and the second signature are equal, the super manager 223 can update the translation table 224 such that the first client physical address and the second client physical address are associated with one of the first system physical address and the second system physical address. The super manager 223 can select one of the first system physical address and the second system physical address and associate the first client physical address and the second client physical address with the selected system physical address. The super manager 223 can also make memory cells with unselected system physical addresses available for storing additional data. The super manager 223 can, for example, provide a command to the memory subsystem 210 to cause the memory subsystem 210 to delete data stored in memory cells with unselected system physical addresses.

[0052] In various situations, the super manager 223 can cause two signatures to be generated simultaneously, and the signatures can be compared without storing them in hash table 226. The super manager 223 can provide multiple system physical addresses to the memory subsystem 210 and cause the memory subsystem 210 to generate signatures for the multiple system physical addresses one at a time. The super manager 223 can store each signature in hash table 226. Each time the super manager 223 receives a new signature, it can store the new signature in hash table 226. The super manager 223 can also retrieve the new signature from hash table 226 and compare the new signature with other signatures stored in table 226 to determine if there is duplicate data stored in memory subsystem 210.

[0053] In various instances, the super manager 223 may request the memory subsystem 210 to perform a hash operation using a write command. A generic write command may not provide an indication of requesting a hash operation. However, a write command to a specified region of memory may provide an indication of requesting a hash operation. For example, during the discovery phase of memory subsystem 210's startup, memory subsystem 210 may notify the super manager (e.g., the host) 223 that a region of memory has been designated for hash operations. Memory subsystem 210 may determine whether the received write command is directed to a memory address corresponding to a region of memory designated for hash operations. If the write command is directed to an address corresponding to a region of memory designated for hash operations, memory subsystem 210 may interpret the write command as a command to perform a hash operation.

[0054] A write command to an address corresponding to a region of memory specified for a hash operation may contain metadata. The metadata of the write command may contain one or more addresses, such as one or more system physical addresses. Therefore, a write command may be associated with two or more addresses. The write command may be associated with a first address of the write command target. Conventionally, the write command will be used to write data to the memory cell with the first address. The write command may also be associated with a second address provided as metadata. The second address can be used to identify the memory cell storing the data used to perform the hash operation. Therefore, the second address may be referred to as the source address. The write command may also be associated with a third or more addresses, which can also be used to identify the memory cell storing the data used to perform the hash operation. The write command may further be associated with a fourth address provided as metadata, which can be used to identify the memory cell where the signature generated by DHE 213 will be stored. The fourth address may be referred to as the destination address.

[0055] Figure 3This is a block diagram of DHE 313 according to some embodiments of the present disclosure. DH3 313 may be implemented in the controller of the memory subsystem or may be implemented independently of the memory subsystem controller. DHE 313 is shown as including address registers 331-1, 331-2, data registers 332-1, 332-2, and signatures 334-1, 334-2. DHE 313 is also shown as including a comparator 333 and hash circuitry 336.

[0056] The DHE 313 may contain more or fewer components than those shown. For example, the DHE 313 may be implemented with a single address register (e.g., address register 331-1), a single data register (e.g., data register 332-1), and / or a single signature register (e.g., signature 334-1) or multiple address registers, data registers, and / or signature registers.

[0057] In response to determining that a write command points to a memory region specified for a hash operation, the memory subsystem can retrieve one or more addresses from metadata and can provide those addresses to DHE 313. DHE 313 can store one or more addresses in address register 331. DHE 313 can cause data to be retrieved from the memory array using one or more addresses. For example, DHE 313 can cause data to be retrieved from a memory cell having an address stored in address register 331-1. In various cases, DHE 313 can cause data to be retrieved from memory not included in the memory array using one or more addresses. For example, DHE 313 can cause data to be retrieved from a local memory address using a local memory address. Figure 1 Data is retrieved from local storage 119.

[0058] The retrieved data may be stored in data register 332. Data can be retrieved from register 332 and provided to hash circuit 336. Hash circuit 336 may include hardware and / or firmware configured to perform a hash operation on the data stored in data register 332. The output of hash circuit 336 may be stored in signature register 334. The output of hash circuit 336 may be referred to as a signature. The signature may be unique for the data stored in data register 332. In an instance where two or more addresses are provided to DHE 313, hash circuit 336 may sequentially generate multiple signatures using the data stored in data register 332. For example, hash circuit 336 may generate a first signature from data stored in data register 332-1 and a second signature from data stored in data register 332-2. DHE 313 may result in the first signature being stored in signature register 334-1 and the second signature being stored in signature register 334-2.

[0059] In response to generating one or more signatures, DHE 313 can provide the signatures to the host. The host can be allowed to read the signature register 334. The signature stored in register 334 can also be provided to the host via a response. The signature can be further stored... Figure 1 119 in local memory and / or in the memory array of the memory subsystem.

[0060] In an instance where DHE 313 is configured to receive metadata for a single address (e.g., a source address) as a write command to a memory region reserved for hash operations, a DHE 313 without comparator 333 can be implemented. In an instance where DHE 313 is configured to receive metadata for multiple addresses (e.g., multiple source addresses) as write commands to a memory region reserved for hash operations, a DHE 313 with comparator 333 can be implemented. Comparator 333 can compare signatures stored in signature register 334. For example, comparator 333 can compare a first signature stored in signature register 334-1 and a second signature stored in signature register 334-2. Comparator 333 can compare signatures to determine if they are equal. If the data used to generate the signature is duplicate data, different signatures can be equal.

[0061] In response to determining that the first signature and the second signature are equal, DHE 313 may provide an indication to the host describing data stored in a memory cell with a first address and data stored in a memory cell with a second address as duplicate data. For example, the indication may be provided by the host and / or may be stored in a memory array. The indication may also be stored in... Figure 1 In the local memory 119.

[0062] In various instances, the host can control the use of signatures and / or trigger their generation. In this way, when hashing operations are offloaded to the memory subsystem, the host can maintain control over the signature. Figure 2 Control over updates to hash table 226 and / or translation table 224. For example, a host may store a signature in hash table 226 and may use the signature stored in hash table 226 to update translation table 224.

[0063] Figure 4 This is a block diagram of a memory array 425 according to some embodiments of the present disclosure. The memory array 425 includes a memory region reserved for hash operations. The memory region may have addresses 441-3. The memory array 425 may also include a plurality of memory cells with addresses. For example, the memory array 425 may include one row of memory cells with a first address 441-1 and another row of memory cells with a second address 441-2.

[0064] Memory cells coupled to word lines (e.g., a row of memory cells) can store data. Memory cells coupled to different word lines (e.g., another row of memory cells) can store different data. A first signature can be generated by performing a first hash operation on the data. A second signature can be generated by performing a second hash operation on the different data. If the data and the different data are equal, then the first signature and the second signature can be the same signature. For example, if the data and the different data are duplicate data, then the first signature and the second signature can be the same signature.

[0065] A write command to the memory region at address 441-3 can be identified as a request to perform a hash operation. The write command may contain metadata. The metadata may contain one or more addresses of memory array 425. For example, the metadata may contain addresses 441-1 and / or address 441-2, as well as other possible addresses.

[0066] DHE can retrieve data stored in a memory cell with address 441-1 and / or different data stored in a memory cell with address 441-2. DHE can use hash circuitry to generate signatures for the data and / or different data.

[0067] Figure 5 This is a block diagram of a translation table 524 according to some embodiments of the present disclosure. Translation table 524 may contain a client physical address 551 and a system physical address 552. Translation table 524 can be used to generate a system physical address 552 from the client physical address 551.

[0068] Translation table 524 may contain addresses 553-1, 553-2, 553-3, and 553-4. Addresses 553-1 and 553-2 may be client physical addresses 551. Addresses 553-3 and 553-4 may be system physical addresses 552. Translation table 524 can associate client physical addresses 551 and system physical addresses 552. For example, translation table 524 can associate addresses 553-1 and 553-2 with addresses 553-3 and 553-4. More precisely, translation table 524 can associate addresses 553-1 and 553-3, as indicated by the solid line connecting address 553-1 to address 553-3. The translation table 524 can also associate addresses 553-2 and 553-4, as indicated by the dotted line connecting addresses 553-2 and 553-4, before generating a signature for the data stored in the memory cells with addresses 553-3 and 553-4.

[0069] In response to the first signature generated for data stored in the memory cell with address 553-3 and the second signature generated for different data stored in the memory cell with address 553-4 being the same signature, the super manager may update the translation table 524 such that addresses 553-1 and 553-2 are both associated with one of addresses 553-3 and 553-4. For example, the super manager may update the translation table 524 such that addresses 553-1 and 553-2 are both associated with address 553-3, as indicated by the solid line connecting addresses 553-1, 553-2 and address 553-3.

[0070] In various situations, the super manager can cause different data to be deleted from the memory cell with address 553-4. Deleting the memory cell with address 553-4 makes the memory cell available for storing additional data.

[0071] Addresses 553-1 and 553-2 can be different addresses. In various cases, addresses 553-1 and 553-2 can be utilized by different VMs and / or the OS within the VMs. For example, the first VM can utilize address 553-1, while the second VM utilizes address 553-2. Memory cells with addresses 553-3 and 553-4 can store duplicate data. In various instances, the duplicate data can be read-only data, such as a library utilized by both the first and second VMs. Utilizing a memory cell with address 553-3 instead of a memory cell with address 553-4 to store duplicate data makes the memory cell with address 553-4 available for storing other data.

[0072] Figure 6 This is a flowchart corresponding to a method 660 for controlling a request provided to a memory subsystem according to some embodiments of the present disclosure. Method 660 may be executed by processing logic, which may include hardware (e.g., processing means, circuitry, dedicated logic, programmable logic, microcode, device hardware, integrated circuits, etc.), software (e.g., instructions that run or execute on a processing means), or a combination thereof. In some embodiments, method 660 is performed by… Figure 1 The front end 121 of the memory subsystem 110 executes. Although shown in a specific sequence or order, the order of processes may be modified unless otherwise specified. Therefore, it should be understood that the illustrated embodiments are merely examples, and the illustrated processes may be executed in different orders, and some processes may be executed in parallel. In addition, one or more processes may be omitted in various embodiments. Therefore, not all processes are required in every embodiment. Other process flows are possible.

[0073] At operation 661, a command for the address of the memory device can be received from the host. The command may include different addresses. These different addresses may be included in the command's metadata. The command may be a write command. However, the command is not limited to write commands, but may include different types of commands, such as read commands, and other types of commands.

[0074] At operation 662, a decision can be made based on the address to determine whether to perform a hash operation. If the address identifies a region designated for performing the hash operation, the decision to perform the hash operation can be made based on the receipt of the command. If the address does not identify the region, a decision can be made not to perform the hash operation. Alternatively, the command can be executed periodically. For example, if the command is a write command to an address where the region is not identified, the write command can be executed. If the command is a read command to an address where the region is not identified, the read command can be executed.

[0075] At operation 663, in response to determining to perform a hash operation, data stored in memory cells with different addresses can be accessed. The DHE of the memory subsystem controller can cause data to be accessed from the memory cell. In various cases, data can be accessed from the memory subsystem's registers instead of from the memory array.

[0076] At operation 664, a hash operation can be performed on the data to generate a signature for the data. The signature can be a hash signature. The signature can be unique for the data. Any change to the data will result in a change to the signature.

[0077] At operation 665, access to a signature can be provided to the host to determine whether the data is duplicate data. The host can compare the signature with different signatures for different data to determine whether the signature is equal to any of the different signatures. The host can store the signature and / or different signatures in hash table 226. Changes to the data may require changes to the signature stored in hash table 226. Accordingly, the host can maintain control over hash table 226. The host can verify whether any command (e.g., a write command) has been provided to any address stored in hash table 226. For example, if a write command to one of the addresses stored in hash table 226 is provided to the memory subsystem, the host can cause a signature to be generated for the data written to the memory cell with the address. In various cases, the host can determine whether to provide a request to perform a hash operation on the data stored in the memory subsystem based on whether the host identifies the data stored in the memory subsystem as potentially duplicate data. For example, the host can perform pattern recognition to determine whether the data is likely to be duplicate data if different addresses are accessed consistently at relatively similar times. This may occur if the VM accesses duplicate data at startup and the VM starts at relatively similar times.

[0078] In various instances, access to a signature can be provided to the host by storing the signature as metadata provided to the target address of the command. As previously described, a write command provided from the host to the memory subsystem may contain metadata. The metadata may contain a source address and a destination address. The source address is the address of the memory cell where the data used to generate the signature is stored. The destination address is the address of the memory cell where the signature is stored. Providing the destination address to the host allows the host to provide a separate read command to the destination address to read the signature. It also provides the host with the ability to obtain the signature when convenient. For example, the host may not need the signature until later. Obtaining the destination address allows the host to decide when to obtain the signature and continue updating the translation table. Although various instances are described as a host performing the action and / or a super manager performing the action, references to the host can be interchanged with references to the super manager if the super manager is implemented by the host. Similarly, references to the host's processor can be interchanged with references to the super manager if the super manager can be implemented by the host's processor.

[0079] The address of the command may correspond to a region of a memory device reserved as an indication for performing a hash operation. A command pointing to an address of a region of the memory device can be interpreted as a command to perform a hash operation. A region of the memory device can serve as an indication because a reference to a region can be interpreted as a request to perform a hash operation. The host knows that the address corresponds to a region of a memory device reserved for performing a hash operation. The memory subsystem may provide the address to the host when the memory device is booted. For example, the memory subsystem may provide the address to the host during a discovery process (e.g., discovery) when the memory device is booted. As used herein, the discovery process of the memory subsystem booting can be described as an interaction between the host and the memory subsystem, whereby the memory subsystem provides the host with information that the host can utilize to interact with the memory subsystem. For example, during discovery, the memory subsystem may provide the host with the address of a region of the memory subsystem reserved for performing a hash operation. The host may then use the address to generate a command for performing a hash operation.

[0080] In various instances, the host's processing device can access the first system physical address of a memory cell in a memory device storing data. The first system physical address may be provided by a super manager. The first system physical address may be associated with a first client address. The association between the first system physical address and the first client address can be described as follows: the first client physical address can be resolved to the first system physical address using, for example, a translation table.

[0081] The processing device may provide a first system physical address to the memory subsystem to perform a hash operation on the data. The first system physical address may be provided as metadata to commands such as write commands. The processing device may access a signature of the data generated using the hash operation. The memory subsystem may provide the signature directly to the processing device, and / or the memory subsystem may store the signature in the memory subsystem so that the processing device can retrieve the signature using a read command.

[0082] The processing device can compare a signature with other signatures to determine whether data and different data are duplicate data. Different data can be stored in different memory locations having a second system physical address associated with a second client physical address. Duplicate data can have the same signature. If data and different data are duplicate data, the signature of the data and the different signature of the different data can be the same signature. If the signatures are equal to each other, the signatures can be the same signature. In response to determining that data and different data are duplicate data, the processing device can update the translation table by associating the first client physical address and the second client physical address with the first system physical address. The processing device can also update the translation table by associating the first client physical address and the second client physical address with the second system physical address. The translation table is used by a super manager, which is implemented by a host including the processing device.

[0083] The processing device may further respond to determining that the data and the distinct data are duplicate data by providing a command to the memory device to delete the distinct data. Deleting the distinct data from the memory cell storing the distinct data makes it possible to use the memory cell to store additional data.

[0084] The processing device can execute a super manager. The super manager is configured to receive a first client physical address and a second client physical address. The first and second client physical addresses can be received from one or more virtual machines (VMs). The super manager can use a translation table to generate a first system physical address from the first client physical address and a second system physical address from the second client physical address. The first client physical address can be received from a first VM, and the second client physical address can be received from a second VM. In various instances, the first and second client physical addresses are received from the same virtual machine. For example, a first operating system (OS) of the VM can provide a first address that the VM translates to the first client physical address, and a second OS of the VM can provide a second address that the VM translates to the second physical address. Therefore, the first client physical address can correspond to a first OS hosted by the same virtual machine, and the second client physical address can correspond to a second OS hosted by the same virtual machine.

[0085] In various instances, the memory subsystem may receive a command from the host for a first address of the memory device. The command may include multiple memory addresses as metadata. For example, the command may include a second address and a third address as metadata. The memory subsystem may determine whether to perform a hash operation based on the first address. If the memory subsystem can determine whether the first address corresponds to a region reserved for performing a hash operation, in response to determining to perform a hash operation using the first address, the memory subsystem may access data stored in a memory cell of the memory device with the second address. The memory subsystem may also access different data stored in different memory cells of the memory device with the third address. The memory subsystem may use the data to perform a hash operation to generate a first signature for the data and use different data to generate a second signature. The memory subsystem may compare the first signature and the second signature. In response to comparing the first signature and the second signature, the memory subsystem may provide an indication of whether the data and the different data are duplicate data.

[0086] The memory subsystem may receive a first address of a memory cell of the memory device via an address bus that couples the host to the memory subsystem. The address bus may transmit address data (e.g., addresses). A second and third address may be received via a command bus that couples the host to the memory subsystem. The command bus may transmit command data (e.g., commands), the command data containing metadata including the second and third addresses.

[0087] In various instances, the first address may correspond to a portion of local memory that is not a memory cell of the memory device. The first address may be a register of the memory device. The first address may also correspond to a register of the memory subsystem. The memory subsystem may be configured to respond to receiving different commands, such as deleting data or different types of data.

[0088] Figure 7 This is a block diagram of an example computer system 700 in which embodiments of this disclosure may operate. For example, Figure 7 An example machine is described as representing computer system 700, within which a set of instructions is executable to cause the machine to perform any one or more of the methods discussed herein. In some embodiments, computer system 700 may correspond to a host system (e.g., Figure 1 The host system 120 includes, is coupled to, or utilizes a memory subsystem (e.g., a memory subsystem). Figure 1 The memory subsystem 110) or the front end that can be used to execute the memory subsystem (e.g., the memory subsystem 110) Figure 1The operation of the front end 121). In alternative embodiments, the machine may connect (e.g., network) to other machines in a LAN, intranet, extranet, and / or the Internet. The machine may operate as a server or client machine in a client-server network environment, as a peer-to-peer machine in a peer-to-peer (or distributed) network environment, or as a server or client machine in a cloud computing infrastructure or environment.

[0089] A machine can be a personal computer (PC), tablet PC, set-top box (STB), personal digital assistant (PDA), cellular telephone, network appliance, server, network router, switch, or bridge, or any machine capable of executing (sequentially or otherwise) a set of instructions specifying actions to be taken by said machine. Furthermore, although a single machine is shown, the term "machine" should also be understood to include any collection of machines that individually or jointly execute a set (or more) of instructions to perform any or more of the methods discussed herein.

[0090] The example computer system 700 includes a processing device 702, a main memory 704 (e.g., read-only memory (ROM), flash memory, dynamic random access memory (DRAM), such as synchronous DRAM (SDRAM) or Rambus DRAM (RDRAM), etc.), a static memory 706 (e.g., flash memory, static random access memory (SRAM), etc.), and a data storage system 718, which communicate with each other via a bus 730.

[0091] Processing device 702 represents one or more general-purpose processing devices, such as microprocessors, central processing units, etc. More specifically, the processing device may be a Complex Instruction Set Computing (CISC) microprocessor, a Reduced Instruction Set Computing (RISC) microprocessor, a Very Long Instruction Word (VLIW) microprocessor, or a processor implementing other instruction sets, or a processor implementing a combination of instruction sets. Processing device 702 may also be one or more special-purpose processing devices, such as application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), digital signal processors (DSPs), network processors, etc. Processing device 702 is configured to execute instructions 726 for performing the operations and steps discussed herein. Computer system 700 may further include a network interface device 708 communicating via network 720.

[0092] The data storage system 718 may include a machine-readable storage medium 724 (also referred to as a computer-readable medium) on which one or more sets of instructions 726 or software embodying any one or more of the methods or functions described herein are stored. The instructions 726 may also reside wholly or at least partially within main memory 704 and / or processing device 702 during execution by computer system 700, the main memory 704 and processing device 702 also constituting machine-readable storage media. The machine-readable storage medium 724, the data storage system 718, and / or main memory 704 may correspond to... Figure 1 The memory subsystem 110.

[0093] In one embodiment, instruction 726 includes implementing a front end corresponding to the memory subsystem (e.g., Figure 1 The front end 121) contains functional instructions. Although machine-readable storage medium 724 is shown as a single medium in the exemplary embodiment, the term "machine-readable storage medium" should be considered to include a single medium or multiple media storing one or more sets of instructions. It should also be considered that the term "machine-readable storage medium" includes any medium capable of storing or encoding a set of instructions that are executable by a machine and cause the machine to perform any one or more of the methods disclosed herein. Accordingly, the term "machine-readable storage medium" should be considered to include, but is not limited to, solid-state memory, optical media, and magnetic media.

[0094] Some parts of the previously described descriptions have been presented based on the algorithms and symbolic representations of operations on data bits within computer memory. These algorithms are described and represented as a way for those skilled in the art of data processing to most effectively communicate the essence of their work to others skilled in the art. An algorithm here is generally considered a self-consistent sequence of operations that produce a desired result. An operation is an operation that requires physical manipulation of physical quantities. These quantities are usually, but not necessarily, in the form of electrical or magnetic signals that can be stored, combined, compared, and otherwise manipulated. Sometimes, primarily for general reasons, it has proven convenient to refer to these signals as bits, values, elements, symbols, characters, terms, numbers, etc.

[0095] However, it should be remembered that all these and similar terms should be associated with appropriate physical quantities and are merely convenient labels for application to those quantities. This disclosure can refer to the actions and processes of a computer system or similar electronic computing device that manipulate and transform data represented as physical (electronic) quantities within the registers and memories of a computer system into other data similarly represented as physical quantities within the computer system's memory or registers or other such information storage systems.

[0096] This disclosure also relates to apparatus for performing the operations described herein. Such apparatus may be specifically constructed for a particular purpose, or it may comprise a general-purpose computer selectively activated or reconfigured by a computer program stored in a computer. Such computer programs may be stored in computer-readable storage media, such as, but not limited to, any type of disk (including floppy disks, optical disks, CD-ROMs, and magneto-optical disks), read-only memory (ROM), random access memory (RAM), EPROM, EEPROM, magnetic cards, or optical cards, or any type of media suitable for storing electronic instructions, each coupled to a computer system bus.

[0097] The algorithms and displays presented herein are not inherently related to any particular computer or other device. Various general-purpose systems may be used with the programs taught herein, or it may prove convenient to construct more specialized devices to execute the methods. Structures for these various systems will be presented as described below. Furthermore, this disclosure is described without reference to any particular programming language. It should be understood that the teachings of this disclosure as described herein can be implemented using various programming languages.

[0098] This disclosure can be provided as a computer program product or software, which may include a machine-readable medium having instructions stored thereon that can be used to program a computer system (or other electronic device) to perform processes according to this disclosure. The machine-readable medium includes any mechanism for storing information in a machine-readable (e.g., computer-readable) form. In some embodiments, the machine-readable (e.g., computer-readable) medium includes machine-readable storage media, such as read-only memory (“ROM”), random access memory (“RAM”), disk storage media, optical storage media, flash memory devices, etc.

[0099] In the foregoing description, embodiments of the present disclosure have been described with reference to specific examples. It will be apparent that various modifications can be made to the present disclosure without departing from the broader spirit and scope of the embodiments set forth in the appended claims. Accordingly, the description and drawings should be viewed in an illustrative rather than restrictive sense.

Claims

1. A method for performing a hash operation, comprising: receiving a command from a host to an address of a memory device, the command comprising a different address; determining whether to perform a hash operation based on the address; in response to determining to perform the hash operation, accessing data stored in a memory cell having the different address; performing the hash operation in a memory sub-system using the data to generate a signature for the data; and providing access to the host to the signature to determine whether the data is duplicate data.

2. The method of claim 1, wherein the signature is unique to the data.

3. The method of claim 1, further comprising providing access to the host to the signature by storing the signature in a target address provided to the command as metadata.

4. The method of claim 1, wherein the address corresponds to a region of the memory device reserved as an indication to perform the hash operation.

5. The method of claim 1, further comprising providing the address to the host at least one of a boot up of the memory device and a discovery at a boot up of the memory device.

6. The method of claim 1, wherein the command comprises the different address as metadata.

7. The method of any one of claims 1-6, further comprising: performing the hash operation on a chunk of the data in sequence to generate the signature for the data; reserving intermediate results of the hash operation performed on the chunk of the data; and performing the hash operation on a next chunk of the chunk of the data with the intermediate results.

8. An apparatus for performing a hash operation, comprising: a processing device configured to: access a first system physical address of a memory cell of a memory device storing data, wherein the first system physical address is provided by a hypervisor, and wherein the first system physical address is associated with a first guest physical address; provide the first system physical address to a memory sub-system to perform a hash operation on the data; access a signature of the data generated using the hash operation; compare the signature to other signatures to determine whether the data and a different data are duplicate data, wherein the different data is stored in a different memory cell having a second system physical address associated with a second guest physical address; in response to determining that the data and the different data are duplicate data, update a translation table by associating the first guest physical address and the second guest physical address with the system physical address.

9. The apparatus of claim 8, wherein the processing device is further configured to provide a command to the memory device to delete the different data in response to determining that the data and the different data are duplicate data.

10. The apparatus of any one of claims 8-9, wherein the translation table is used by the hypervisor implemented by a host comprising the processing device. ​ ​ 11. The apparatus of claim 10, wherein the processing device is configured to execute the hypervisor, and wherein the hypervisor is configured to: receive the first guest physical address and the second guest physical address; generate the first system physical address from the first guest physical address and the second system physical address from the second guest physical address using the translation table.

12. The apparatus of claim 11, wherein the first guest physical address is received from a first virtual machine and the second guest physical address is received from a second virtual machine.

13. The apparatus of claim 11, wherein the first guest physical address and the second guest physical address are received from a same virtual machine, and wherein the first guest physical address corresponds to a first operating system hosted by the same virtual machine and the second guest physical address corresponds to a second operating system hosted by the same virtual machine.

14. An apparatus for performing a hash operation, comprising: a memory array; a processing device coupled to the memory array and configured to: receive a command from a host to a memory device of a first address, the command including a second address and a third address as metadata; determine whether to perform an operation based on the first address; in response to determining to perform the operation using the first address: access data stored in a memory cell of the memory device having the second address; access different data stored in a different memory cell of the memory device having the third address; perform the operation using the data to generate a first signature for the data and using the different data to generate a second signature; in response to comparing the first signature and the second signature, provide an indication of whether the data and the different data are duplicate data.

15. The apparatus of claim 14, wherein the processing device is further configured to receive the first address of a memory cell of the memory device via an address bus coupling the host to the processing device.

16. The apparatus of claim 14, wherein the processing device is further configured to receive the first address of the memory device, wherein the first address does not correspond to a memory cell of the memory device and wherein the first address is to a register of the memory device.

17. The apparatus of claim 14, wherein the command to the first address identifies the operation.

18. The apparatus of any one of claims 14-17, wherein the processing device is further configured to delete one of the data and the different data in response to receiving a different command.

19. The apparatus of any one of claims 14-17, configured to update firmware of the processing device to perform a hash operation using the data to generate the first signature for the data and using the different data to generate the second signature.

20. The apparatus of any of claims 14-17, configured to update firmware of the processing device to use the data to perform a different operation to generate the first signature for the data and to use the different data to generate the second signature.

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