A cut set processing method and system based on BDD equivalence verification
By constructing cut sets and merging or splitting them in BDD equivalence verification, and combining backtracking iteration and learning methods to verify misjudgments, the problem of misjudgments caused by inappropriate cut set selection is solved, thereby improving the accuracy and stability of the verification tool.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- SHENZHEN GOUWEIXIN TECH CO LTD
- Filing Date
- 2022-11-30
- Publication Date
- 2026-06-09
AI Technical Summary
In existing BDD equivalence verification methods, inappropriate cut set selection can easily lead to misjudgments, affecting the accuracy of the verification tool.
The comparison points in the circuit are obtained by matching the names of the comparison points. Cut sets are constructed and their equivalence is verified. Cut sets are merged or cut. Backtracking iteration and learning methods are used to verify false judgments and ensure the equivalence of cut sets.
It effectively prevents misjudgments caused by cut sets, reduces the risk of BDD memory explosion, and improves the accuracy of formal verification tools.
Smart Images
Figure CN115730543B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of integrated circuit equivalence verification, and in particular to a cut set processing method and system based on BDD equivalence verification. Background Technology
[0002] Binary Decision Digrams (BDDs) are commonly used in equivalence verification, but their large memory footprint can easily lead to memory explosion. To address this, cutset techniques were developed. A cutset primarily consists of the original input and internal nodes that are determined to be equivalent. Once the cutset is determined, it's unnecessary to construct a separate BDD from the original input to the original output; instead, a BDD from the determined equivalent nodes to the original output needs to be constructed, thus reducing the size of the BDD and preventing memory explosion.
[0003] However, if the cut set is not chosen appropriately, misjudgment can easily occur. Misjudgment refers to the situation where, after introducing the cut set technique to verify the equivalence of nodes, two nodes that are originally equivalent are judged to be unequal.
[0004] Therefore, in order to ensure the accuracy of formal verification tools, it is essential to address the issue of misjudgment in cut sets. Summary of the Invention
[0005] The purpose of this invention is to address the technical problem of misjudgment caused by cut sets in the equivalence verification process of existing technologies. This invention proposes a cut set processing method and system based on BDD equivalence verification.
[0006] In this embodiment of the invention, a cut set processing method based on BDD equivalence verification is provided, which includes:
[0007] Input two reference circuits and implementation circuits to be verified. Obtain the comparison points in the two circuits by matching the names of the comparison points, and perform equivalence verification on the corresponding comparison points in the two circuits in turn.
[0008] When performing equivalence verification on two comparison points, first construct two cut sets that make the two comparison points to be verified equivalent, and then construct BDD to verify the equivalence of these two cut sets.
[0009] If these two cut sets are equivalent, then these two cut sets are merged with the corresponding previous cut sets in the two circuits to form new cut sets;
[0010] If the two cut sets are not equivalent, backtrack to the previous cut set to verify if there is a misjudgment. If there is a misjudgment, it means that the two cut sets are equivalent. If there is no misjudgment, the current cut set is cut until all subsets of the current cut set pass the equivalence verification. If all subsets fail, the current cut set is not equivalent. If any subset passes the verification, the current cut set and the previous cut set are merged, and the verification of the next cut set is performed.
[0011] In this embodiment of the invention, two cut sets are constructed such that the two comparison points to be verified are equivalent, including:
[0012] Iterate back along the original input direction of the comparison point to be verified, find the merge node and its main input to form a cut set, and determine whether the two cut points are equivalent;
[0013] If they are equivalent, then the cut set construction is complete;
[0014] If they are not equivalent, continue backtracking and iterating towards the original input direction, cut the current cut set, find the next merge node and its main input to form a new cut set, and then determine whether the two cut points are equivalent;
[0015] Repeat the above process until two cut sets are constructed that make the two comparison points equivalent, or until all inputs in the cut sets are the original inputs and the two points are not equivalent. Then, determine that the two circuits to be verified are not equivalent.
[0016] In this embodiment of the invention, if the two cut sets are not equivalent, the process involves backtracking to the previous cut set to verify whether a misjudgment exists, including:
[0017] The input and output of the previous cut set are used to judge the two comparison points to be verified. If the outputs of the two comparison points are equal, the two comparison points are considered to be equivalent and there is a false judgment. Otherwise, the two comparison points are considered not to be equivalent and there is no false judgment.
[0018] In this embodiment of the invention, if the two cut sets are not equivalent, the process iterates back to the previous cut set to further verify whether there is a misjudgment, including:
[0019] Assign the output values of 0 and 1 to the two comparison points to be verified respectively. Select the previous cut set and check whether the assignment is satisfied. If the assignment is not satisfied, the two comparison points are considered to be equivalent, and there is a false judgment. If the assignment is satisfied, the two comparison points are considered to be not equivalent, and there is no false judgment.
[0020] In this embodiment of the invention, the cut set processing method based on BDD equivalence verification further includes:
[0021] After all comparison points have passed the equivalence test,
[0022] The outputs of the final cut set are verified. If the outputs are equivalent, then the two circuits are equivalent; otherwise, the two circuits are not equivalent.
[0023] In this embodiment of the invention, a cut-set processing system based on BDD equivalence verification is also provided, which uses the above-mentioned cut-set processing method based on BDD equivalence verification when performing equivalence verification on two reference circuits and implementation circuits to be verified.
[0024] Compared with existing technologies, the cut set processing method and system based on BDD equivalence verification of the present invention takes two reference circuits and an implementation circuit to be verified as input, obtains the comparison points in the two circuits by name matching of comparison points, and performs equivalence verification on the corresponding comparison points in the two circuits in turn; when performing equivalence verification on two comparison points, firstly, two cut sets that make the two comparison points to be verified equivalent are constructed respectively, and then BDD is constructed to verify the equivalence of these two cut sets; if the two cut sets are equivalent, then these two cut sets are merged with the corresponding previous cut sets in the two circuits respectively, forming If two cut sets are not equivalent, the process iterates back to the previous cut set to verify if there is a misjudgment. If there is a misjudgment, the two cut sets are equivalent. If there is no misjudgment, the current cut set is split until all subsets of the current cut set pass the equivalence verification. If all subsets fail the verification, the current cut set is not equivalent. If any subset passes the verification, the current cut set and the previous cut set are merged, and the verification of the next cut set is performed. This effectively prevents misjudgments caused by cut sets while reducing the risk of BDD memory explosion, thus improving the accuracy of formal verification tools. Attached Figure Description
[0025] Figure 1 This is a flowchart of a cut set processing method based on BDD equivalence verification according to an embodiment of the present invention.
[0026] Figure 2 This is a schematic diagram of a cut set in an embodiment of the present invention.
[0027] Figure 3 This is a schematic diagram of the cut set backtracking iteration in an embodiment of the present invention. Detailed Implementation
[0028] like Figure 1 As shown in the figure, this embodiment of the invention provides a cut set processing method based on BDD equivalence verification, which includes steps S1-S3. These are described below.
[0029] Step S1: Input two reference circuits and implementation circuits to be verified, and obtain the comparison points in the two circuits by matching the names of the comparison points.
[0030] Step S2: Perform equivalence verification on the corresponding comparison points in the two circuits in turn.
[0031] Step S2 further includes steps S21-S24. These will be explained below.
[0032] Step S21: First, construct two cut sets that make the two comparison points to be verified equivalent.
[0033] In this embodiment of the invention, the process of constructing two cut sets that make the two comparison points to be verified equivalent includes:
[0034] Backtracking and iterating in the direction of the original input of the comparison point to be verified, we find the merge node and its main input to form a cut set, and then determine whether the two comparison points are equivalent.
[0035] If they are equivalent, then the cut set construction is complete;
[0036] If they are not equivalent, continue backtracking and iterating towards the original input direction to find the next merge node and its main input, forming a new cut set, and then determine whether the two comparison points are equivalent;
[0037] Repeat the above process until two cut sets are constructed that make the two comparison points equivalent, or until all inputs in the cut sets are the original inputs and the two points are not equivalent. Then, determine that the two circuits to be verified are not equivalent.
[0038] It should be noted that, in the above process, the merging node is a node where the inputs and outputs are equivalent in both circuits.
[0039] Step S22: Construct a BDD to verify the equivalence of the two cut sets.
[0040] If the two cut sets are equivalent, then step S23 is executed to merge the two cut sets with the corresponding previous cut sets in the two circuits to form new cut sets;
[0041] If the two cut sets are not equivalent, then execute step S24 to backtrack to the previous cut set to verify whether there is a misjudgment.
[0042] It should be noted that during the verification of the comparison points of the two circuits, the first comparison point is usually equivalent, thus forming the first cut set. In step S3, after the second comparison point becomes equivalent, the second cut set is formed. Then, the second cut set is merged with the first cut set to form a new cut set. Similarly, after the third cut set becomes equivalent, it is merged with the previously formed cut sets to form a new cut set. This process continues until the last comparison point passes verification, forming the final cut set, or until a certain comparison point fails verification, indicating that the two circuits are not equivalent.
[0043] In step S24, if the two cut sets are not equivalent, backtrack to the previous cut set to verify if there is a misjudgment. If a misjudgment exists, the two cut sets are equivalent. If no misjudgment exists, the current cut set is split until all subsets of the current cut set pass the equivalence verification. If all subsets fail, the current cut set is not equivalent. If any subset passes the verification, the current cut set and the previous cut set are merged, and the verification of the next cut set is performed.
[0044] In this embodiment of the invention, two methods can be used to verify whether there is a misjudgment: one is to use a backtracking iteration method to verify whether there is a misjudgment, and the other is to use a learning method to verify whether there is a misjudgment. These will be described below.
[0045] The backtracking iteration method to verify the misjudgment process includes: using the input and output of the previous cut set to judge the two comparison points to be verified, judging whether the outputs of the two comparison points are equal. If they are equal, the two comparison points are considered to be equivalent and there is a misjudgment; otherwise, the two comparison points are considered not to be equivalent and there is no misjudgment.
[0046] by Figure 2 and Figure 3 The backtracking iteration method will be explained using the circuit shown as an example, as follows:
[0047] like Figure 2 For cut sets 1, a and a' with the same input are equivalent, therefore b and b', c and c' are also equivalent. First, select (b, c) and (b', c') which are close to the original output as the first-level cut sets. o1 and o2 are not equal.
[0048] Iteratively backtracking to find the previous cut set, such as... Figure 3 As shown. We select (x1, a, x2) and (x1, a', x2) as the new cut sets. O1 = (x1 + a) * - (a * x3) = (x1 + a) * (-a + -x3), O2 = (x1 + a') * - (a' * x3) + {-(x1 + a') * (a' * x3)} = (x1 + a) * (-a + -x3) + (-x1 * - a') * (a' * x3) = (x1 + a) * (-a + -x3). Now O1 and O2 are equal, and the misjudgment is eliminated.
[0049] The learning method for verifying misjudgments includes: assigning the outputs of the two comparison points to be verified to 0 and 1 respectively, selecting the previous cut set, and checking whether the assignment is satisfied. If the assignment is not satisfied, the two comparison points are considered to be equivalent, and there is a misjudgment. If the assignment is satisfied, the two comparison points are considered to be not equivalent, and there is no misjudgment.
[0050] by Figure 2 and Figure 3The backtracking iteration method will be explained using the circuit shown as an example, as follows:
[0051] When (b, c) and (b', c') are used as cut sets, such as Figure 2 Let O1 = b * - c, and O2 = (b' * - c') + (-b' * c'). Assume the outputs of O1 and O2 are not equal, then they are (0, 1) or (1, 0) respectively. When the outputs of O1 and O2 are (0, 1), the outputs of b, c, b', and c' should be (0, 1) for O1 and O2 to output (0, 1). Continuing the derivation with b, c, b', and c' as outputs, when c and c' are 1, a, x3, a', and x3 are all (1, 1). Since b and b' are 0, the values of x1, a, and x1, a' can only be (0, 0). This creates an assignment conflict between a and a', therefore the values of b, c, and b', c' cannot be (0, 1). Therefore, the outputs of O1 and O2 cannot be (0, 1). Similarly, when the outputs of O1 and O2 are (1, 0), the values of b and c should be (1, 0) for O1 to output 1. However, when the values of b' and c' are (1, 0), the condition that O2 output 0 cannot be met, resulting in a conflict. The outputs of O1 and O2 cannot be (1, 0). Therefore, O1 and O2 are equal, and the misjudgment is eliminated.
[0052] Step S3: After all comparison points have passed the equivalence verification, verify the output of the final cut set. If the outputs are equivalent, then the two circuits are equivalent; otherwise, the two circuits are not equivalent.
[0053] In this embodiment of the invention, a cut-set processing system based on BDD equivalence verification is also provided. When performing equivalence verification on two reference circuits and implementation circuits to be verified, the aforementioned cut-set processing method based on BDD equivalence verification is employed.
[0054] In summary, the cutset processing method and system based on BDD equivalence verification of the present invention takes two reference circuits and an implementation circuit to be verified as input. It obtains the comparison points in the two circuits by matching the names of the comparison points and sequentially performs equivalence verification on the corresponding comparison points in the two circuits. When performing equivalence verification on two comparison points, it first constructs two cutsets that make the two comparison points to be verified equivalent, and then constructs a BDD equivalence verification for these two cutsets. If the two cutsets are equivalent, they are then merged with the corresponding previous cutsets in the two circuits to form a new cutset. If two cut sets are not equivalent, backtrack to the previous cut set to verify whether there is a misjudgment. If there is a misjudgment, it means that the two cut sets are equivalent. If there is no misjudgment, the current cut set is cut until all subsets of the current cut set pass the equivalence verification. If all subsets fail, the current cut set is not equivalent. If a subset passes the verification, the current cut set and the previous cut set are merged, and the verification of the next cut set is performed. While reducing the risk of BDD memory explosion, it can effectively prevent misjudgments caused by cut sets and improve the accuracy of formal verification tools.
[0055] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention should be included within the protection scope of the present invention.
Claims
1. A cut-set processing method based on BDD equivalence verification, characterized in that, include: Input two reference circuits and implementation circuits to be verified. Obtain the comparison points in the two circuits by matching the names of the comparison points, and perform equivalence verification on the corresponding comparison points in the two circuits in turn. When performing equivalence verification on two comparison points, first construct two cut sets that make the two comparison points to be verified equivalent, and then construct BDD to verify the equivalence of these two cut sets. If these two cut sets are equivalent, then these two cut sets are merged with the corresponding previous cut sets in the two circuits to form new cut sets; If the two cut sets are not equivalent, backtrack to the previous cut set to verify whether there is a misjudgment. If there is a misjudgment, it means that the two cut sets are equivalent. If there is no misjudgment, the current cut set is cut until all subsets of the current cut set pass the equivalence verification. If all subsets fail, the current cut set is not equivalent. If a subset passes the verification, the current cut set and the previous cut set are merged, and the verification of the next cut set is performed. Construct two cut sets that make the two comparison points to be verified equivalent, including: Backtracking and iterating in the direction of the original input of the comparison point to be verified, we find the merge node and its main input to form a cut set, and then determine whether the two comparison points are equivalent. If they are equivalent, then the cut set construction is complete; If they are not equivalent, continue backtracking and iterating towards the original input direction to find the next merge node and its main input, forming a new cut set, and then determine whether the two comparison points are equivalent; Repeat the above process until two cut sets are constructed that make the two comparison points equivalent, or until all inputs in the cut sets are the original inputs and the two points are not equivalent. Then, determine that the two circuits to be verified are not equivalent.
2. The cut set processing method based on BDD equivalence verification as described in claim 1, characterized in that, If the two cut sets are not equivalent, backtrack to the previous cut set to verify whether there is a misjudgment, including: The input and output of the previous cut set are used to judge the two comparison points to be verified. If the outputs of the two comparison points are equal, the two comparison points are considered to be equivalent and there is a false judgment; otherwise, the two comparison points are considered not to be equivalent and there is no false judgment.
3. The cut set processing method based on BDD equivalence verification as described in claim 1, characterized in that, If the two cut sets are not equivalent, backtrack to the previous cut set to further verify whether there is a misjudgment, including: Assign the output values of 0 and 1 to the two comparison points to be verified respectively. Select the previous cut set and check whether the assignment is satisfied. If the assignment is not satisfied, the two comparison points are considered to be equivalent, and there is a misjudgment. If the assignment is satisfied, the two comparison points are considered to be not equivalent, and there is no misjudgment.
4. The cut set processing method based on BDD equivalence verification as described in claim 1, characterized in that, Also includes: After all comparison points have passed the equivalence test, The outputs of the final cut set are verified. If the outputs are equivalent, then the two circuits are equivalent; otherwise, the two circuits are not equivalent.
5. A cut-set processing system based on BDD equivalence verification, characterized in that, When performing equivalence verification on two reference circuits and implementation circuits to be verified, the cut-set processing method based on BDD equivalence verification as described in any one of claims 1-4 is adopted.