A method for automatic interaction of signal simulation and wiring design

Abstract

The application discloses a kind of signal simulation and the method of automatic interaction of wiring design, it is related to simulation and wiring design technical field;To improve efficiency;Based on Python and Cadence Skill procedure implementation, the specific steps of the method that RLC signal simulation is optimized to wiring design are as follows: set RLC constraint requirement of specified circuit in advance, for screening and judging the signal that simulation data exceeds standard;Extract common wiring design optimization strategy and the theoretical formula or empirical formula of R / L / C, for assisting the optimization strategy of automatically determining Fail signal;Write Python program, according to constraint requirement, automatically process simulation result raw data.The application combines Python and Cadence Skill, improves the communication efficiency and accuracy of simulation and circuit design data interaction, and has important significance to improve the auxiliary ability of computer for artificial calculation and design.

Description

Technical Field

[0001] This invention relates to the field of simulation and wiring design technology, and in particular to a method for automatic interaction between signal simulation and wiring design. Background Technology

[0002] As the speed of electronic products increases, signal integrity issues are becoming more and more common. In order to improve the first-time success rate of products and shorten the R&D cycle, the industry usually uses signal integrity simulation to optimize circuit design. However, electromagnetic simulation software and circuit design software are often not unified, data interaction remains unchanged, and a lot of manual calculation and processing is required.

[0003] Currently, the conventional circuit design and simulation steps are as follows:

[0004] ① An initial version of the circuit was designed based on past experience data;

[0005] ② Use simulation software to perform circuit simulation;

[0006] ③ Relying on manual analysis of simulation results, network signals with excessive data are filtered out;

[0007] ④ Rely on manual methods to develop optimization plans for lines that exceed data standards, such as increasing / shortening line length, changing routing methods, and excavating areas;

[0008] ⑤ Based on the optimization plan, the engineer manually selects the corresponding network in the circuit design software and implements the optimization measures;

[0009] ⑥ The simulation engineer re-simulates the adjusted new version of the circuit design to confirm whether the simulation results meet the standards. If they meet the standards, the optimization is successful. If they do not meet the standards, repeat steps 2 to 5 until the simulation results are satisfactory.

[0010] The above method has the following drawbacks:

[0011] ① It requires design first, then simulation, and then feedback and modification of design documents based on simulation results, which results in low work efficiency;

[0012] ② The simulation data needs to be manually converted, calculated and filtered, which may result in calculation errors, omissions in the filtering process, etc.

[0013] ③ Simulation engineers and circuit designers are often two different engineers. Optimization solutions for circuits with out-of-specification data may not be feasible and may require repeated communication and adjustments from both sides, resulting in low efficiency.

[0014] ④ It usually takes a long time to change a design or simulation;

[0015] ⑤ Design change records need to be kept manually, which carries the risk of omissions and errors. Summary of the Invention

[0016] The purpose of this invention is to address the shortcomings of existing technologies by proposing an automatic interactive method for signal simulation and wiring design.

[0017] To achieve the above objectives, the present invention adopts the following technical solution:

[0018] A method for automatic interaction between signal simulation and wiring design, implemented using Python and Cadence Skill, outlines the specific steps for optimizing wiring design through RLC signal simulation:

[0019] S1: Pre-set the RLC constraint requirements for the specified circuit to filter and judge signals whose simulation data exceeds the standard;

[0020] S2: Extract common wiring design optimization strategies and theoretical or empirical formulas for R / L / C to assist in automatically determining optimization strategies for Fail signals;

[0021] S3: Write a Python program to automatically process the raw data of simulation results according to the constraints, and automatically determine the layout optimization strategy according to theoretical formulas or empirical formulas, and output the results as a txt file;

[0022] S4: Import txt file into Cadence;

[0023] S5: Automatically identifies the network name, constraint rules, and specified operations in a txt file through the Skill program, realizes the automatic setting of optimization strategies, and automatically outputs the change record.

[0024] Preferably, in step S2, the extracted content includes the relationship between line length and R / L / C.

[0025] Furthermore, in step S5, the constraint rules include line length constraints and signal delay constraints.

[0026] A further preferred embodiment: In step S3, when outputting the txt file, the txt file is simultaneously backed up in the storage module.

[0027] As a preferred embodiment of the present invention, the storage module is divided into a temporary storage unit and a backup storage unit.

[0028] As a further preferred embodiment of the present invention: when the txt file generated in step S3 is backed up in the storage module, the backup file of the txt file is first stored in a temporary storage unit. After step S5 is completed, the backup file of the txt file is transferred to the backup storage unit, and the storage contents in the temporary storage unit are cleared at the same time.

[0029] As a further aspect of the present invention: in step S5, when outputting the modification record, the modification record document is directly generated in the backup storage unit.

[0030] Based on the aforementioned scheme: the change record document contains change information, time information, etc.

[0031] Based on the aforementioned scheme, the preferred method is applied in the circuit design module of Cadence software.

[0032] The beneficial effects of this invention are as follows:

[0033] 1. This invention combines Python and Cadence Skill, improving the communication efficiency and accuracy of simulation and circuit design data interaction, and is of great significance for enhancing the computer's ability to assist human calculation and design.

[0034] 2. This invention does not limit the simulation software and simulation content, and allows for flexible adjustment of the Python program to recognize result data and constraints in different formats, thus enhancing the flexibility of this solution.

[0035] 3. This invention can automatically output change records through a program, thereby improving work efficiency. Attached Figure Description

[0036] Figure 1 This is a flowchart of an automatic interactive method for signal simulation and wiring design proposed in this invention;

[0037] Figure 2 This is a data display interface diagram of an automatic interactive method for signal simulation and wiring design proposed in this invention. Detailed Implementation

[0038] The technical solution of this patent will be further described in detail below with reference to specific embodiments.

[0039] Example 1:

[0040] A method for automatic interaction between signal simulation and routing design, implemented using Python and Cadence Skill, is applicable to the Cadence software circuit design module, including but not limited to the following three modules: PCB Editor, Package Designer, and System in Package. The specific steps of this method for optimizing routing design through RLC signal simulation are as follows:

[0041] S1: Pre-set the RLC constraint requirements for the specified circuit to filter and judge signals whose simulation data exceeds the standard;

[0042] S2: Extract common wiring design optimization strategies and theoretical or empirical formulas for R / L / C to assist in automatically determining optimization strategies for Fail signals;

[0043] S3: Write a Python program to automatically process the raw data of simulation results according to the constraints, and automatically determine the layout optimization strategy according to theoretical formulas or empirical formulas, and output the results as a txt file;

[0044] S4: Import txt file into Cadence;

[0045] S5: Automatically identifies network names, constraint rules, and specified operations in txt files through the Skill program, enabling automatic setting of optimization strategies and automatic output of change records.

[0046] In step S2, the extracted content includes the relationship between line length and R / L / C.

[0047] In step S5, the constraint rules include line length constraints, signal delay constraints, etc.

[0048] Example 2:

[0049] A method for automatic interaction between signal simulation and wiring design is provided. In this embodiment, the following modification is made to embodiment 1: in step S3, when outputting a txt file, the txt file is simultaneously backed up in the storage module.

[0050] The storage module is divided into a temporary storage unit and a backup storage unit.

[0051] When the txt file generated in step S3 is backed up in the storage module, the backup file of the txt file is first stored in a temporary storage unit. After step S5 is completed, the backup file of the txt file is transferred to the backup storage unit, and the storage contents in the temporary storage unit are cleared.

[0052] In step S5, when outputting the modification record, the modification record document is directly generated in the backup storage unit.

[0053] The change record document contains change information, time information, etc.

[0054] The above description is only a preferred embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any equivalent substitutions or modifications made by those skilled in the art within the scope of the technology disclosed in the present invention, based on the technical solution and inventive concept of the present invention, should be covered within the scope of protection of the present invention.

Claims

1. A method for automatic interaction between signal simulation and wiring design, characterized in that, Based on Python and Cadence Skill, the specific steps of this method to optimize wiring design through resistance, inductance, and capacitance signal simulation are as follows: S1: Pre-set the constraints on the resistance, inductance, and capacitance of the specified circuit to filter and judge signals whose simulation data exceeds the standard; S2: Extract common wiring design optimization strategies and theoretical or empirical formulas for resistors, inductors, and capacitors to assist in automatically determining optimization strategies for Fail signals. S3: Write a Python program to automatically process the raw data of simulation results according to the constraints, and automatically determine the layout optimization strategy according to theoretical formulas or empirical formulas, and output the results as a txt file; S4: Import txt file into Cadence; S5: Automatically identifies the network name, constraint rules, and specified operations in a txt file through the Skill program, realizes the automatic setting of optimization strategies, and automatically outputs the change record.

2. The method for automatic interaction between signal simulation and wiring design according to claim 1, characterized in that, In step S2, the extracted content includes the relationship between line length and resistance, inductance, and capacitance.

3. The method for automatic interaction between signal simulation and wiring design according to claim 2, characterized in that, In step S5, the constraint rules include line length constraints and signal delay constraints.

4. The method for automatic interaction between signal simulation and wiring design according to claim 3, characterized in that, In step S3, when outputting the txt file, the txt file is also backed up in the storage module.

5. The method for automatic interaction between signal simulation and wiring design according to claim 4, characterized in that, The storage module is divided into a temporary storage unit and a backup storage unit.

6. The method for automatic interaction between signal simulation and wiring design according to claim 5, characterized in that, When the txt file generated in step S3 is backed up in the storage module, the backup file of the txt file is first stored in the temporary storage unit. After step S5 is completed, the backup file of the txt file is transferred to the backup storage unit, and the storage contents in the temporary storage unit are cleared.

7. The method for automatic interaction between signal simulation and wiring design according to claim 6, characterized in that, In step S5, when outputting the modification record, the modification record document is directly generated in the backup storage unit.

8. The method for automatic interaction between signal simulation and wiring design according to claim 7, characterized in that, The change log document contains change information and time information.

9. A method for automatic interaction between signal simulation and wiring design according to any one of claims 1-8, characterized in that, This method is applied in the circuit design module of Cadence software.

Images