Pixel Circuit, Driving Method Thereof, and Display Panel

Abstract

An embodiment of the present invention discloses a pixel circuit, a driving method thereof, and a display panel. The pixel circuit includes: a current control module and a time control module. The time control module includes a first input terminal, a second input terminal, a third input terminal, and an output terminal; the first input terminal of the time control module is connected to a time data signal, the second input terminal of the time control module is connected to a first initialization signal, the third input terminal of the time control module is connected to a reference voltage signal, and the output terminal of the time control module is electrically connected to the control terminal of the current control module; the time control module is configured to respond to the time data signal and the first initialization signal, and control the reference voltage signal to be output to the current control module after a preset time, so as to control the current control module to be turned off. Compared with the prior art, the embodiment of the present invention reduces the writing time of the control signal, which is beneficial to realizing high-frequency display and high pixel density of the display panel.

Description

Technical Field

[0001] Embodiments of the present invention relate to the field of display technology, and in particular, to a pixel circuit, a driving method thereof, and a display panel. Background Art

[0002] With the continuous development of display technology, the application scope of display panels is becoming more and more extensive, and people's requirements for display panels are also getting higher and higher. In particular, the display image quality of display panels has always been one of the important indicators for consumers and panel manufacturers to measure the quality of display panels. A display panel includes light-emitting devices and pixel circuits for driving the light-emitting devices. The performance of the pixel circuit determines the light-emitting effect of the light-emitting devices, and thus determines the display effect of the display panel. However, existing pixel circuits have the problem of long write time of control signals, making it difficult to achieve high-frequency display and high pixel density (Pixels Per Inch, PPI) of display panels. Summary of the Invention

[0003] Embodiments of the present invention provide a pixel circuit, a driving method thereof, and a display panel to reduce the write time of control signals and achieve high-frequency display and high pixel density of the display panel.

[0004] To achieve the above technical objectives, the embodiments of the present invention provide the following technical solutions:

[0005] A pixel circuit includes:

[0006] A current control module, the current control module includes a control terminal, and the current control module is used to generate a driving current in response to the potential of its control terminal;

[0007] A time control module, including a first input terminal, a second input terminal, a third input terminal, and an output terminal; the first input terminal of the time control module is connected to a time data signal, the second input terminal of the time control module is connected to a first initialization signal, the third input terminal of the time control module is connected to a reference voltage signal, and the output terminal of the time control module is electrically connected to the control terminal of the current control module; the time control module is used to respond to the time data signal and the first initialization signal, and control the reference voltage signal to be output to the current control module after a preset time to control the current control module to turn off.

[0008] Further, the time control module includes:

[0009] A time initialization unit, including a control terminal, a first terminal, and a second terminal, the control terminal of the time initialization unit is connected to a first time control scan signal, and the first terminal of the time initialization unit is connected to the first initialization signal;

[0010] A voltage switching control unit, including a control terminal, a first terminal, and a second terminal. The control terminal of the voltage switching control unit is electrically connected to the second terminal of the time initialization unit. The first terminal of the voltage switching control unit is connected to the reference voltage signal, and the second terminal of the voltage switching control unit is electrically connected to the control terminal of the current control module;

[0011] A time data writing unit, including a control terminal, a first terminal, and a second terminal. The control terminal of the time data writing unit is connected to the second time control scan signal, and the first terminal of the time data writing unit is connected to the time data signal;

[0012] A coupling unit, including a first terminal and a second terminal. The first terminal of the coupling unit is electrically connected to the second terminal of the time data writing unit, and the second terminal of the coupling unit is electrically connected to the second terminal of the time initialization unit.

[0013] Further, the time initialization unit includes: a first transistor. The gate of the first transistor serves as the control terminal of the time initialization unit, the first pole of the first transistor serves as the first terminal of the time initialization unit, and the second pole of the first transistor serves as the second terminal of the time initialization unit;

[0014] Preferably, the first transistor is an N-type transistor.

[0015] Further, the voltage switching control unit includes: a second transistor. The gate of the second transistor serves as the control terminal of the voltage switching control unit, the first pole of the second transistor serves as the first terminal of the voltage switching control unit, and the second pole of the second transistor serves as the second terminal of the voltage switching control unit;

[0016] Preferably, the second transistor is a P-type transistor.

[0017] Further, the time data writing unit includes: a third transistor. The gate of the third transistor serves as the control terminal of the time data writing unit, the first pole of the third transistor serves as the first terminal of the time data writing unit, and the second pole of the third transistor serves as the second terminal of the time data writing unit;

[0018] Preferably, the third transistor is a P-type transistor.

[0019] Further, the coupling unit includes a first capacitor. The first pole of the first capacitor serves as the first terminal of the coupling unit, and the second pole of the first capacitor serves as the second terminal of the coupling unit.

[0020] Further, the current control module includes:

[0021] A driving unit, including a control terminal, the control terminal of the driving module serves as the control terminal of the current control module, and the driving unit is configured to generate a driving current in response to the potential of its control terminal;

[0022] A current data writing unit, configured to write a current data signal to the control terminal of the driving unit;

[0023] A storage unit, configured to store the potential of the control terminal of the driving unit;

[0024] Preferably, the current data signal and the time data signal share a signal line.

[0025] Correspondingly, the present invention further provides a display panel, including the pixel circuit according to any embodiment of the present invention.

[0026] Correspondingly, the present invention further provides a driving method for a pixel circuit, applicable to the pixel circuit according to any embodiment of the present invention, the driving method includes:

[0027] A time initialization stage, initializing the time control module by using a time data signal and a first initialization signal;

[0028] A time data writing stage, the time data signal undergoes a jump, and the internal node voltage of the time control module undergoes a jump;

[0029] A time light-emitting stage, within the light-emitting stage of the current control module, the first initialization signal undergoes a jump, and the time control module controls the reference voltage signal to be output to the current control module after a preset time according to the voltage jump of the internal node and the first initialization signal, so as to control the current control module to disconnect; wherein, the jump amount of the time data signal is associated with the preset time.

[0030] Further, the waveform of the time data signal changes in a square wave shape;

[0031] The waveform of the first initialization signal changes in a square wave shape;

[0032] The reference voltage signal is a DC voltage signal.

[0033] The pixel circuit provided by the embodiment of the present invention does not require an external driving chip to input a ramp signal. Through the internal logic of the time control module, the time data signal and the voltage amplitude signal of the first initialization signal are converted into a time signal, so that the reference voltage signal is output to the current control module after a preset time, thereby realizing the control of the conduction time of the current control module. Therefore, the embodiment of the present invention does not need to wait for all pixel circuits to complete data writing, and all pixel circuits enter the light-emitting stage simultaneously. The pixel circuits scanned first enter the light-emitting stage first. While they enter the light-emitting stage, the pixel circuits scanned later enter the data writing stage, that is, the embodiment of the present invention can realize the side writing and side light-emitting of different row pixel circuits. Compared with the prior art, the embodiment of the present invention reduces the writing time of control signals, and the driving time of row pixel circuits is shorter, which is beneficial to the high refresh frequency, high brightness display and high pixel density of pixel circuits. In addition, since there is no need to lay signal lines for providing ramp signals, the embodiment of the present invention is beneficial to saving wiring space and the power consumption of signal lines. Description of the Drawings

[0034] Figure 1 FIG. 6 is a schematic structural diagram of an existing pixel circuit;

[0035] Figure 2 FIG. 7 is a schematic structural diagram of a pixel circuit provided by an embodiment of the present invention;

[0036] Figure 3 FIG. 8 is a schematic structural diagram of another pixel circuit provided by an embodiment of the present invention;

[0037] Figure 4 FIG. 9 is a schematic structural diagram of yet another pixel circuit provided by an embodiment of the present invention;

[0038] Figure 5 FIG. 10 is a schematic driving timing diagram of a pixel circuit provided by an embodiment of the present invention;

[0039] Figure 6 FIG. 11 is a schematic structural diagram of yet another pixel circuit provided by an embodiment of the present invention;

[0040] Figure 7 FIG. 12 is a schematic driving timing diagram of another pixel circuit provided by an embodiment of the present invention;

[0041] Figure 8 FIG. 13 is a schematic structural diagram of yet another pixel circuit provided by an embodiment of the present invention;

[0042] Figure 9 FIG. 14 is a schematic driving timing diagram of yet another pixel circuit provided by an embodiment of the present invention;

[0043] Figure 10 FIG. 15 is a schematic flow chart of a driving method of a pixel circuit provided by an embodiment of the present invention. Detailed implementation mode

[0044] The present invention will be further described in detail below with reference to the accompanying drawings and embodiments. It can be understood that the specific embodiments described herein are only used to explain the present invention, rather than limiting the present invention. In addition, it should be noted that, for the sake of convenience of description, only parts related to the present invention rather than all structures are shown in the drawings.

[0045] As described in the background art, the existing pixel circuit has the problems of long control signal writing time and difficulty in achieving high frequency and high pixel density. After research by the inventor, the reasons for this problem are as follows.

[0046] For display devices such as OLEDs or Micro LEDs, there are problems such as large fluctuations in luminous efficiency in the low current state, steep luminance-voltage curves, and sensitivity of emission wavelength to current changes, making it difficult to control the display gray levels, especially in the case of low current density, and the display gray levels cannot be fully developed.

[0047] The prior art provides a digital-analog hybrid drive pixel circuit that uses the combined action of a PWM signal and a ramp signal to control the light emission time of a light-emitting device. Figure 1 It is a schematic structural diagram of an existing pixel circuit. Refer to Figure 1 , this pixel circuit includes a current control module 010, a time control module 020, and a light-emitting module 030. Among them, the current control module 010 is used to generate a drive current in response to the potential of its control terminal to drive the light-emitting module 030 to emit light. The time control module 020 can control the conduction time of the current control module 010 and the light emission time of the light-emitting module 030 by controlling the potential of the control terminal of the current control module 010. The time control module 020 requires various control signals, such as a time control signal S1', a ramp signal Vsweep, a data signal Sig, a light emission control signal Em', etc. Among them, the ramp signal Vsweep is a special signal with a gradually decreasing voltage, which cannot be provided by a shift register and needs to be provided by an external driving chip. And due to the port limitations of the external driving chip, all the pixel circuits on the display panel need to share the ramp signal Vsweep. That is to say, the ramp signal Vsweep cannot be written into the pixel circuit row by row.

[0048] Exemplarily, the time control module 020 includes transistors M1', M2', M3', M4', M5' and a capacitor C1'. Before the light-emitting stage of the current control module 010, a set voltage signal is written to the gate of the transistor M3' under the control of the time control signal S1' and the data signal Sig. During the light-emitting stage of the current control module 010, the ramp signal Vsweep takes effect, and the on-state of the transistor M3' is controlled through the capacitor C1', thereby controlling the on-state of the current control module 010. Since all pixel circuits on the display panel need to share the ramp signal Vsweep, it is necessary to wait until the data writing of all pixel circuits is completed, and then all pixel circuits enter the light-emitting stage simultaneously. That is to say, the pixel circuits that write data first need to wait for the pixel circuits that write data later. For pixel circuits other than the last row of pixel circuits, the data writing stage and the light-emitting stage are separated, which is equivalent to a longer writing time of the control signal, that is, a longer driving time of the row pixel circuit, affecting the refresh frequency of the pixel circuit and making it difficult to achieve high-frequency display and high-brightness display. Moreover, at a fixed refresh frequency, the number of rows of pixel circuits that can be driven in one frame becomes smaller, making it difficult to achieve a high pixel density.

[0049] In view of this, an embodiment of the present invention provides a pixel circuit. Figure 2 It is a schematic structural diagram of a pixel circuit provided by an embodiment of the present invention. Refer to Figure 2 , the pixel circuit includes: a current control module 110 and a time control module 120. The current control module 110 includes a control terminal 111, and the control terminal 111 is defined as the first node N1. The current control module 110 is configured to generate a driving current in response to the potential of its control terminal 111, and the generated driving current can control the light-emitting module 130 to emit light. The light-emitting module 130 may include display devices such as OLED or Micro LED, for example. The time control module 120 includes a first input terminal 121, a second input terminal 122, a third input terminal 123 and an output terminal 124. The first input terminal 121 is connected to the time data signal SPWM, the second input terminal 122 is connected to the first initialization signal Vref1, the third input terminal 123 is connected to the reference voltage signal Vx, and the output terminal 124 is electrically connected to the control terminal 111 of the current control module 110. The time control module 120 is configured to control the reference voltage signal Vx to be output to the current control module 110 after a preset time in response to the time data signal SPWM and the first initialization signal Vref1, so as to control the current control module 110 to turn off.

[0050] Among them, the output terminal 124 of the time control module 120 can be at a high level or a low level, thereby controlling whether a driving current Id is generated by the current control module 110 during the light-emitting stage, so as to control the duty cycle of the light-emitting time of the light-emitting module 130 during the light-emitting stage. Exemplarily, when the first node N1 is at a low level, the current control module 110 is turned on; the reference voltage signal Vx is at a high level. The working principle of the time control module 120 is as follows: In the time initialization stage, the time control module 120 is initialized by using the time data signal SPWM and the first initialization signal Vref1; in the time data writing stage, the time data signal SPWM undergoes a jump, and the voltage of the internal node of the time control module 120 changes accordingly, that is, the time data signal SPWM is used to write data to the time control module 120; in the time light-emitting stage, the time light-emitting stage is within the light-emitting stage of the current control module 110. The internal node that underwent a follow-up jump in the previous stage, combined with the first initialization signal Vref1, can control whether the reference voltage signal Vx is output to the current control module 110. Specifically, before the preset time arrives, the first node N1 is at a low level, and the current control module 110 generates a driving current Id; after the preset time, the reference voltage signal Vx is output to the current control module 110, the first node N1 becomes high level, and the current control module 110 is turned off and no longer generates a driving current. Among them, the jump amount of the time data signal SPWM is associated with the preset time, and the time data signal SPWM is used to control the length of the preset time, so as to control the duty cycle of the light-emitting time of the light-emitting module 130 during the light-emitting stage.

[0051] It can be seen from this that the embodiment of the present invention does not require an external driving chip to input a ramp signal. By converting the voltage amplitude signals of the time data signal SPWM and the first initialization signal Vref1 into time signals through the internal logic of the time control module 120, it is realized that the reference voltage signal Vx is output to the current control module 110 after the preset time, thereby realizing the control of the conduction time of the current control module 110. Therefore, the embodiment of the present invention does not need to wait for all pixel circuits to complete data writing, and all pixel circuits enter the light-emitting stage simultaneously. The pixel circuits scanned first enter the light-emitting stage first. At the same time as they enter the light-emitting stage, the pixel circuits scanned later enter the data writing stage, that is, the embodiment of the present invention can realize side writing and side light-emitting of different row pixel circuits. Compared with the prior art, the embodiment of the present invention reduces the writing time of control signals, and the driving time of row pixel circuits is shorter, which is beneficial to high refresh rate, high brightness display and high pixel density of pixel circuits. And, since there is no need to lay signal lines for providing ramp signals, the embodiment of the present invention is beneficial to saving wiring space and the power consumption of signal lines.

[0052] In the above embodiments, there are various ways to set the time control module 120, which will be specifically described below, but it is not a limitation to the present invention.

[0053] Figure 3 FIG. is a schematic structural diagram of another pixel circuit provided by an embodiment of the present invention. Refer to Figure 3 Based on the above embodiments, optionally, the time control module 120 includes: a time initialization unit 121, a voltage switching control unit 122, a time data writing unit 123, and a coupling unit 124. The time initialization unit 121 includes a control terminal, a first terminal, and a second terminal. The control terminal of the time initialization unit 121 is connected to a first time control scan signal SW1, the first terminal of the time initialization unit 121 is connected to a first initialization signal Vref1, and the second terminal of the time initialization unit 121 is a second node N2. The voltage switching control unit 122 includes a control terminal, a first terminal, and a second terminal. The control terminal of the voltage switching control unit 122 is electrically connected to the second terminal (second node N2) of the time initialization unit 121. The first terminal of the voltage switching control unit 122 is connected to a reference voltage signal Vx, and the second terminal of the voltage switching control unit 122 is electrically connected to the control terminal (first node N1) of the current control module 110. The time data writing unit 123 includes a control terminal, a first terminal, and a second terminal. The control terminal of the time data writing unit 123 is connected to a second time control scan signal SW2, and the first terminal of the time data writing unit 123 is connected to a time data signal SPWM. The coupling unit 124 includes a first terminal and a second terminal. The first terminal of the coupling unit 124 is electrically connected to the second terminal of the time data writing unit 123, and the second terminal of the coupling unit 124 is electrically connected to the second terminal (second node N2) of the time initialization unit 121.

[0054] Specifically, the working principle of the time control module 120 is as follows: In the time initialization stage, the first time control scan signal SW1 controls the time initialization unit 121 to conduct, and the first initialization signal Vref1 is written into the second end (the second node N2) of the coupling unit 124. The second node N2 controls the voltage switching control unit 122 to disconnect. At the same time, the second time control scan signal SW2 controls the time data writing unit 123 to conduct, and the time data signal SPWM is written into the first end of the coupling unit 124. That is, the time control module 120 is initialized by using the time data signal SPWM and the first initialization signal Vref1. In the time data writing stage, the second time control scan signal SW2 continues to control the time data writing unit 123 to conduct, and the time data signal SPWM jumps. Due to the effect of the coupling unit 124, the voltage of the second node N2 jumps. The amount of the jump determines the length of the preset time in the subsequent time light-emitting stage. Exemplarily, the larger the jump amount, the longer the preset time; the smaller the jump amount, the shorter the preset time. That is, the time control module 120 is written with data by using the time data signal SPWM. In the time light-emitting stage, the first initialization signal Vref1 jumps. After the jumped first initialization signal Vref1 is completely written into the second node N2, it can control the voltage switching control unit 122 to conduct. Combining the control of the second node N2 and the first initialization signal Vref1, the time initialization unit 121 conducts, and the first initialization signal Vref1 is gradually written into the second node N2, and the voltage of the second node N2 gradually decreases in a ramp shape. Before the preset time arrives, the voltage of the second node N2 does not reach the turn-on voltage of the voltage switching control unit 122, and the voltage switching control unit 122 disconnects. The first node N1 is at a low level, and the current control module 110 generates a driving current Id. After the preset time, the second node N2 controls the voltage switching control unit 122 to conduct, and the reference voltage signal Vx is output to the current control module 110. The first node N1 becomes high level, and the current control module 110 disconnects and no longer generates a driving current.

[0055] Therefore, in the embodiment of the present invention, the time control module 120 is provided to include a time initialization unit 121, a voltage switching control unit 122, a time data writing unit 123, and a coupling unit 124, so that the time control function of the time control module 120 on the current control module 110 can be realized. Specifically, in the embodiment of the present invention, a ramp signal can be formed inside the time control module 120 without being provided by an external driving chip. Moreover, the jump amount of the data signal SPWM determines the initial value of the ramp signal, thereby controlling the duty cycle of the light-emitting time of the light-emitting module 130 in the light-emitting stage, and realizing adjustable duty cycle.

[0056] Figure 4 It is a schematic structural diagram of another pixel circuit provided by the embodiment of the present invention. Refer to Figure 4, based on the above embodiments, the specific setting methods of the units in the time control module 120 will be described.

[0057] In an embodiment of the present invention, optionally, the time initialization unit 121 includes a first transistor M1. The gate of the first transistor M1 serves as the control end of the time initialization unit 121 and is connected to the first time control scan signal SW1. The first pole of the first transistor M1 serves as the first end of the time initialization unit 121 and is connected to the first initialization signal Vref1. The second pole of the first transistor M1 serves as the second end of the time initialization unit 121 and is electrically connected to the second node N2. In the embodiment of the present invention, it is set that the time initialization unit 121 only includes one transistor, and the circuit structure is simple and easy to implement.

[0058] In an embodiment of the present invention, optionally, the voltage switching control unit 122 includes a second transistor M2. The gate of the second transistor M2 serves as the control end of the voltage switching control unit 122 and is electrically connected to the second node N2. The first pole of the second transistor M2 serves as the first end of the voltage switching control unit 122 and is connected to the reference voltage signal Vx. The second pole of the second transistor M2 serves as the second end of the voltage switching control unit 122 and is electrically connected to the control end (the first node N1) of the current control module 110. In the embodiment of the present invention, it is set that the voltage switching control unit 122 only includes one transistor, and the circuit structure is simple and easy to implement.

[0059] In an embodiment of the present invention, optionally, the time data writing unit 123 includes a third transistor M3. The gate of the third transistor M3 serves as the control end of the time data writing unit 123 and is connected to the second time control scan signal SW2. The first pole of the third transistor M3 serves as the first end of the time data writing unit 123 and is connected to the time data signal SPWM. The second pole of the third transistor M3 serves as the second end of the time data writing unit 123 and is electrically connected to the coupling unit 124. In the embodiment of the present invention, it is set that the time data writing unit 123 only includes one transistor, and the circuit structure unit is easy to implement.

[0060] In an embodiment of the present invention, optionally, the coupling unit 124 includes a first capacitor C1. The first pole of the first capacitor C1 serves as the first end of the coupling unit 124 and is electrically connected to the second end of the time data writing unit 123. The second pole of the first capacitor C1 serves as the second end of the coupling unit 124 and is electrically connected to the second node N2. In the embodiment of the present invention, it is set that the coupling unit 124 only includes one capacitor, and the circuit structure unit is easy to implement.

[0061] Continue to refer to Figure 4, optionally, the core of the time control module 120 includes three transistors and one capacitor, that is, the time control module 120 has a 3T1C structure, and the circuit structure is simple and easy to implement. The following combines the timing diagram to further illustrate Figure 4 the pixel circuit shown. Figure 5 This is a schematic diagram of the driving timing of a pixel circuit provided by an embodiment of the present invention. Combining Figure 4 and Figure 5 , optionally, the first transistor M1 is an N-type transistor, the second transistor M2 is a P-type transistor, and the third transistor M3 is a P-type transistor. The waveform of the time data signal SPWM changes in a square wave shape; the waveform of the first initialization signal Vref1 changes in a square wave shape; the reference voltage signal Vx is a DC voltage signal. The driving process of the pixel circuit is as follows.

[0062] In the time initialization stage T1, the first time control scan signal SW1 is at a high level, the second time control scan signal SW2 is at a low level, the voltage of the first initialization signal Vref1 is V1 (high level), and the time data signal SPWM is at a low level (for example, 0V). The first transistor M1 is turned on in response to the control of the first time control scan signal SW1, and the third transistor M3 is turned on in response to the control of the second time control scan signal SW2. The voltage V1 of the first initialization signal Vref1 is written to the second node N2 to ensure that the second transistor M2 is turned off and maintained. At the same time, the time data signal SPWM is written to the first capacitor C1 as a reference value before the voltage jump. At the same time, the voltage of the first node N1 is controlled by the current control module 110 itself, which is not limited here.

[0063] In the time data writing stage T2, the first time control scan signal SW1 is at a low level, the second time control scan signal SW2 is at a low level, the voltage of the first initialization signal Vref1 is V1 (high level), and the time data signal SPWM jumps upward by △S from 0, and the change amount is △S. The first transistor M1 is turned off in response to the control of the first time control scan signal SW1, and the third transistor M3 is turned on in response to the control of the second time control scan signal SW2. The first pole of the first capacitor C1 jumps upward by △S, and its second pole also jumps upward by △S. The voltage of the second node jumps from V1 to V1 + △S to ensure that the second transistor M2 remains turned off.

[0064] The time light emitting stage T3 includes a first sub-stage T31 and a second sub-stage T32. The time light emitting stage T3 is within the light emitting stage of the current control module 110. Preferably, the time light emitting stage T3 coincides with the light emitting stage of the current control module 110.

[0065] In the first sub-stage T31, the first time control scanning signal SW1 is controlled to be at a high level, the second time control scanning signal SW2 is controlled to be at a high level, the first initialization signal Vref1 jumps downward, and the voltage is V2 (low level). The third transistor M3 is turned off in response to the control of the second time control scanning signal SW2. The first node N1 is at a low level, and the current control module 110 starts to generate a driving current Id under the control of the first node N1, and the light-emitting module 130 starts to emit light. The first transistor M1 is turned on in response to the control of the first time control scanning signal SW1, and the second node N2 starts to discharge through the first transistor M1. The voltage of the second node N2 gradually changes from V1+△S to V2, forming a ramp signal. The preset time mentioned in the foregoing embodiment is the holding time of the first sub-stage T31.

[0066] In the second sub-stage T32, the first time control scanning signal SW1, the second time control scanning signal SW2, and the first initialization signal Vref1 remain unchanged. The third transistor M3 remains turned off, and the first transistor M1 remains turned on. When the voltage of the second node N2 changes to Vx+Vth2, where Vth2 is the threshold voltage of the second transistor M2, the first node N1 is rewritten as the reference voltage signal Vx (high level), and the control current control module 110 stops generating the driving current Id, and the light emission of the light-emitting module 130 ends. Among them, the jump amount △S of the time data signal SPWM determines the holding time of the first sub-stage T31. The larger the jump amount △S, the longer the time required for the voltage of the second node N2 to change to Vx+Vth2, and the longer the holding time of the first sub-stage T31; the smaller the jump amount △S, the shorter the time required for the voltage of the second node N2 to change to Vx+Vth2, and the shorter the holding time of the first sub-stage T31.

[0067] As can be seen from the above analysis, the time control module 120 provided by the present invention utilizes the discharge of its internal key transistor (the first transistor M1) to generate a gradually changing ramp signal inside the pixel circuit, and can convert the voltage amplitude of the time data signal SPWM into a time signal without an external signal. Therefore, the embodiment of the present invention can realize side writing and side light emission of different row pixel circuits, reduce the writing time of the control signal, and the driving time of the row pixel circuit is short, which is beneficial to the high refresh rate, high brightness display and high pixel density of the pixel circuit, and is beneficial to saving the wiring space and the power consumption of the signal line.

[0068] In the above embodiments, taking the case where the first node N1 is at a low level in the first sub-stage T31 as an example, correspondingly, the reference voltage signal Vx is at a high level. For the P-type second transistor M2, the electrode connected to the high level is the source electrode, and the electrode connected to the low level is the drain electrode. Therefore, the first electrode of the second transistor M2 is the source electrode. The conduction condition of the second transistor M2 is that the gate-source voltage difference is equal to Vth2. At this time, the gate voltage of the second transistor M2 is Vx + Vth2. Therefore, the demarcation point between the first sub-stage T31 and the second sub-stage T32 is that the voltage of the second node N2 changes to Vx + Vth2.

[0069] In other embodiments, it is also possible to set the first node N1 to be at a high level in the first sub-stage T31. Correspondingly, the reference voltage signal Vx is at a low level. Then, the second electrode of the second transistor M2 is the source electrode. The conduction condition of the second transistor M2 is that the gate-source voltage difference is equal to Vth2. At this time, the gate voltage of the second transistor M2 is N1 + Vth2. Therefore, the demarcation point between the first sub-stage T31 and the second sub-stage T32 is that the voltage of the second node N2 changes to N1 + Vth2.

[0070] It should be noted that Figure 5 exemplarily shows that there is also a transition stage between the time initialization stage T1 and the time data writing stage T2, which is not a limitation of the present invention. In other embodiments, it is also possible to set that there is no transition region between the time initialization stage T1 and the time data writing stage T2, and it can be set according to needs in actual applications.

[0071] It should also be noted that in the above embodiments, it is exemplarily shown that the first transistor M1 is an N-type transistor, and the second transistor M2 and the third transistor M3 are P-type transistors, which is not a limitation of the present invention. In other embodiments, it is also possible to set that the first transistor M1, the second transistor M2, and the third transistor M3 are all P-type transistors, or all N-type transistors. Preferably, the type of the first transistor M1 is different from the type of the second transistor M2. Still taking the first transistor M1 as an N-type transistor, and the second transistor M2 and the third transistor M3 as P-type transistors as an example, the beneficial effects of the preferred solution are described.

[0072] Combined with Figure 4 and Figure 5, during the time emission stage T3, the first initialization signal Vref1 is at a low level and the second node N2 is at a high level. For an N-type transistor, the electrode connected to the low level is the source electrode, and the electrode connected to the high level is the drain electrode. Then, the source electrode of the first transistor M1 is the first initialization signal Vref1, the drain electrode is the second node N2, and the gate electrode is the second time control scan signal SW2. Among them, both the first initialization signal Vref1 and the second time control scan signal SW2 are fixed values, and the voltage of the second node N2 changes. Therefore, the gate-source voltage difference Vgs of the first transistor M1 is the voltage of the second time control scan signal SW2 minus the voltage V2 of the first initialization signal Vref1, and the gate-source voltage difference Vgs is also a fixed value. The drain-source voltage difference Vds of the first transistor M1 is the voltage of the second node N2 minus the voltage V2 of the first initialization signal Vref1. According to the characteristics of the transistor, when the drain-source voltage difference Vds > Vgs - Vth1, where Vth1 is the threshold voltage of the first transistor M1, the first transistor M1 is in the saturation region, and its current I = k(Vgs - Vth1) 2 , where k is a constant. Since the gate-source voltage difference Vgs is a fixed value, the current I of the first transistor M1 is also a fixed value.

[0073] It can be seen that by setting the first transistor M1 as an N-type transistor and the second transistor M2 and the third transistor M3 as P-type transistors, the second node N2 can discharge to V2 with a constant current I, that is, the relationship between the potential of the second node N2 and time is linear, as shown in Figure 5 the potential change of the second node N2 shown. Therefore, the embodiment of the present invention realizes the controllable discharge of the first transistor M1, which is beneficial to more accurately calculate the time when the second node N2 reaches Vx + Vth2 or N1 + Vth2, and is beneficial to the accurate control of the light emission time of the light emission module 130.

[0074] In the above embodiments, the setting method of the time control module 120 is described. The time control module 120 provided by the embodiment of the present invention can be applied to any current control module 110. The basic composition of the current control module 110 includes a driving unit, a current data writing unit, and a storage unit. Among them, the driving unit includes a control end, and the control end of the driving module is used as the control end of the current control module 110. The driving unit is used to generate a driving current in response to the potential of its control end. The current data writing unit is used to write a current data signal into the control end of the driving unit. The storage unit is used to store the potential of the control end of the driving unit. There are various setting methods for the current control module 110. Several setting methods of the current control module 110 are described below, but it is not a limitation to the present invention.

[0075] Figure 6 This is a schematic structural diagram of another pixel circuit provided by the embodiment of the present invention. Refer toFigure 6 , in an embodiment of the present invention, optionally, the driving unit 111 includes a fourth transistor M4. The gate of the fourth transistor M4 serves as the control terminal of the current control module 110 and is electrically connected to the first node N1. The first pole of the fourth transistor M4 is connected to the first power supply signal VDD, the second pole of the fourth transistor M4 is electrically connected to the first pole of the light-emitting module 130, and the second pole of the light-emitting module 130 is connected to the second power supply signal VSS. The current data writing unit 112 includes a fifth transistor M5. The gate of the fifth transistor M5 is connected to the first scan signal S1, the first pole of the fifth transistor M5 is connected to the current data signal DATA, and the second pole of the fifth transistor M5 is electrically connected to the first node N1. The storage unit 113 includes a second capacitor C2. The first pole of the second capacitor C2 is connected to the first power supply signal VDD, and the second pole of the second capacitor C2 is electrically connected to the first node N1. The current control module 110 has a 2T1C structure. Exemplarily, both the fourth transistor M4 and the fifth transistor M5 are P-type transistors.

[0076] Figure 7 It is a schematic diagram of the driving timing of another pixel circuit provided by the embodiment of the present invention. Combining Figure 6 and Figure 7 , the time light-emitting stage T3 coincides with the light-emitting stage T4 of the current control module 110. In the time light-emitting stage T3, the first scan signal S1 is at a certain level to control the fifth transistor M5 to conduct. The fifth transistor M5 writes the current data signal DATA into the first node N1, and the first node N1 controls the fourth transistor M4 to conduct, generating a driving current. Due to the control of the time control module 120, in the second sub-stage T32, the voltage of the first node N1 is written as the reference voltage signal Vx (high level), thereby controlling the fourth transistor M4 to turn off and no longer generating a driving current.

[0077] It can be seen that the time control module 120 provided by the embodiment of the present invention is applicable to the current control module 110 with a 2T1C structure. The current control module 110 and the time control module 120 cooperate to achieve side writing and side light-emitting of different row pixel circuits, reduce the writing time of control signals, and the driving time of the row pixel circuits is short, which is beneficial to high refresh rate, high brightness display and high pixel density of the pixel circuit, and is also beneficial to saving wiring space and power consumption of signal lines.

[0078] Combining Figure 6 and Figure 7, based on the above embodiments, optionally, the current data signal DATA and the time data signal SPWM share a signal line, that is, they share a data line. The data line provides the time data signal SPWM to the pixel circuit during the time data writing stage T2, and provides the current data signal DATA to the pixel circuit during the time light emitting stage T3. With such a setting, without affecting the normal operation of the pixel circuit, the number of signal lines is reduced, which is beneficial to saving the wiring space.

[0079] Figure 8 This is a schematic structural diagram of another pixel circuit provided by an embodiment of the present invention. Refer to Figure 8 , in an embodiment of the present invention, optionally, the driving unit 111 includes a fourth transistor M4. The gate of the fourth transistor M4 serves as the control end of the current control module 110 and is electrically connected to the first node N1. The current data writing unit 112 includes a sixth transistor M6 and a seventh transistor M7. The gate of the sixth transistor M6 receives the third scan signal S3. The first pole of the sixth transistor M6 receives the current data signal DATA. The second pole of the sixth transistor M6 is electrically connected to the first pole of the fourth transistor M4. The gate of the seventh transistor M7 receives the third scan signal S3. The first pole of the seventh transistor M7 is electrically connected to the second pole of the fourth transistor M4. The second pole of the seventh transistor M7 is electrically connected to the first node N1. The storage unit 113 includes a second capacitor C2. The first pole of the second capacitor C2 receives the first power signal VDD. The second pole of the second capacitor C2 is electrically connected to the first node N1.

[0080] The current control module 110 further includes a light-emitting control unit 114, a first initialization unit 115, and a second initialization unit 116. The light-emitting control unit 114 includes an eighth transistor M8 and a ninth transistor M9. The gate of the eighth transistor M8 is connected to the light-emitting control signal EM, the first pole of the eighth transistor M8 is connected to the first power supply signal VDD, and the second pole of the eighth transistor M8 is electrically connected to the first pole of the fourth transistor M4. The gate of the ninth transistor M9 is connected to the light-emitting control signal EM, the first pole of the ninth transistor M9 is connected to the second pole of the fourth transistor M4, and the second pole of the ninth transistor M9 is connected to the first pole of the light-emitting module 130. The first initialization unit 115 includes a tenth transistor M10. The gate of the tenth transistor M10 is connected to the second scan signal S2, the first pole of the tenth transistor M10 is connected to the second initialization signal Vref2, and the second pole of the tenth transistor M10 is connected to the second pole of the ninth transistor M9. The second initialization unit 116 includes an eleventh transistor M11. The gate of the eleventh transistor M11 is connected to the second scan signal S2, the first pole of the eleventh transistor M11 is connected to the second initialization signal Vref2, and the second pole of the eleventh transistor M11 is connected to the first node N1. The current control module 110 has a 7T1C structure. Exemplarily, each transistor in the current control module 110 is a P-type transistor.

[0081] Figure 9 It is a schematic diagram of the driving timing of another pixel circuit provided by the embodiment of the present invention. Combining Figure 6 and Figure 7, the initialization stage T1 of the time coincides with the initialization stage T5 of the current control module 110, the time data writing stage T2 coincides with the data writing stage T6 of the current control module 110, and the time light emitting stage T3 coincides with the light emitting stage T7 of the current control module 110. In the time initialization stage T1, the second scan signal S2 is at a low level, controlling the tenth transistor M10 and the eleventh transistor M11 to conduct, and initializing the light emitting module 130 and the first node. At the same time, the time data signal SPWM and the first initialization signal Vref1 initialize the time control module 120. In the time data writing stage T2, the third scan signal S3 is at a low level, controlling the sixth transistor M6 and the seventh transistor M7 to conduct, and the current data signal DATA is written into the first node N1, raising the voltage of the first node N1 to DATA + Vth4, where Vth4 is the threshold voltage of the fourth transistor M4. At the same time, the time data signal SPWM writes data into the time control module 120. In the time light emitting stage T3, the light emitting control signal EM is at a low level, controlling the eighth transistor M8 and the ninth transistor M9 to conduct, and the fourth transistor M4 generates a driving current. Due to the control of the time control module 120, in the second sub-stage T32, the voltage of the first node N1 is rewritten as the reference voltage signal Vx (high level), thereby controlling the fourth transistor M4 to turn off and no longer generate a driving current.

[0082] It can be seen that the time control module 120 provided by the embodiment of the present invention is applicable to the current control module 110 with a 7T1C structure. The current control module 110 and the time control module 120 cooperate to achieve side writing and side light emission of different row pixel circuits, reduce the writing time of control signals, and the driving time of the row pixel circuit is short, which is beneficial to the high refresh rate, high brightness display and high pixel density of the pixel circuit, and is beneficial to saving wiring space and the power consumption of signal lines.

[0083] Combined Figure 8 and Figure 9 , on the basis of the above embodiments, optionally, the current data signal DATA and the time data signal SPWM share a signal line, that is, a shared data line. Correspondingly, the time data writing stage T2 includes a first sub-writing stage and a second sub-writing stage. The data line provides the time data signal SPWM to the pixel circuit in the first sub-writing stage and provides the current data signal DATA to the pixel circuit in the second sub-writing stage. With this setting, the number of signal lines is reduced without affecting the normal operation of the pixel circuit, which is beneficial to saving wiring space.

[0084] In the above embodiments, the size of the current data signal DATA may be fixed or adjustable, and may be set as required in practical applications. If the size of the current data signal DATA is fixed, the pixel circuit is a digital drive pixel circuit; if the size of the current data signal DATA is adjustable, the pixel circuit is an analog-digital hybrid drive pixel circuit.

[0085] It should be noted that, in the above-mentioned embodiments, the time light-emitting stage T3 and the light-emitting stage T7 of the current control module 110 are overlapped by way of example, which is not a limitation of the present invention. In other embodiments, the time light-emitting stage T3 and the light-emitting stage T7 of the current control module 110 may also be overlapped, which may be set as needed in practical applications.

[0086] The embodiment of the present invention further provides a display panel, including the pixel circuit provided by any embodiment of the present invention, and having corresponding effects. Exemplarily, the display panel can be a display panel of the type of OLED or Micro LED; the pixel circuit can be arranged in an array in the display panel.

[0087] An embodiment of the present invention further provides a driving method for a pixel circuit, which is applicable to the pixel circuit provided by any embodiment of the present invention and has corresponding beneficial effects. Figure 10 FIG. 1 is a flow chart of a driving method of a pixel circuit provided by an embodiment of the present invention. Figures 8 - 10 , the driving method of the pixel circuit includes:

[0088] S110 , a time initialization stage, wherein the time control module 120 is initialized using the time data signal SPWM and the first initialization signal Vref1 .

[0089] S120 , in the time data writing stage, the time data signal SPWM jumps, and the internal node voltage of the time control module 120 jumps.

[0090] S130, the time light-emitting stage, is located in the light-emitting stage of the current control module 110, the first initialization signal Vref1 jumps, and the time control module 120 controls the reference voltage signal Vx to be output to the current control module 110 after a preset time according to the voltage jump of the internal node and the first initialization signal Vref1, so as to control the current control module 110 to disconnect; wherein, the jump amount of the time data signal SPWM is associated with the preset time.

[0091] Optionally, the waveform of the time data signal SPWM changes in a square wave shape; the waveform of the first initialization signal Vref1 changes in a square wave shape; and the reference voltage signal Vx is a DC voltage signal.

[0092] In the embodiment of the present invention, without an external driving chip inputting a ramp signal, by controlling the waveform changes of the time data signal SPWM and the first initialization signal Vref1, and cooperating with the internal logic of the time control module 120 to convert the voltage amplitude signals of the time data signal SPWM and the first initialization signal Vref1 into time signals, it is realized that the reference voltage signal Vx is output to the current control module 110 after a preset time, thereby realizing the control of the conduction time of the current control module 110. Therefore, in the embodiment of the present invention, it is not necessary to wait for the data writing of all pixel circuits to be completed, and all pixel circuits enter the light-emitting stage simultaneously. The pixel circuits scanned first enter the light-emitting stage T7 first. At the same time when they enter the light-emitting stage T7, the pixel circuits scanned later enter the data writing stage T6, that is, the embodiment of the present invention can realize the side writing and side light-emitting of pixel circuits in different rows. Compared with the prior art, the embodiment of the present invention reduces the writing time of control signals, and the driving time of row pixel circuits is shorter, which is beneficial to the high refresh rate, high brightness display and high pixel density of pixel circuits. Moreover, since there is no need to arrange signal lines for providing ramp signals, the embodiment of the present invention is beneficial to saving wiring space and the power consumption of signal lines.

[0093] Note that the above is only the preferred embodiment of the present invention and the technical principles applied. Those skilled in the art will understand that the present invention is not limited to the specific embodiments described here. Various obvious changes, re-adjustments and substitutions can be made by those skilled in the art without departing from the protection scope of the present invention. Therefore, although the present invention has been described in detail through the above embodiments, the present invention is not limited to the above embodiments. Without departing from the concept of the present invention, it can also include more other equivalent embodiments, and the scope of the present invention is determined by the scope of the appended claims.

Claims

1. A pixel circuit, characterized in that, it includes: a current control module, the current control module includes a control terminal, and the current control module is used to generate a driving current in response to the potential of its control terminal; a time control module, including a first input terminal, a second input terminal, a third input terminal and an output terminal; the first input terminal of the time control module is connected to a time data signal, the second input terminal of the time control module is connected to a first initialization signal, the third input terminal of the time control module is connected to a reference voltage signal, and the output terminal of the time control module is electrically connected to the control terminal of the current control module; the time control module is used to respond to the time data signal and the first initialization signal, and control the reference voltage signal to be output to the current control module after a preset time to control the current control module to disconnect; the time control module includes: a time initialization unit, including a control terminal, a first terminal and a second terminal, the control terminal of the time initialization unit is connected to a first time control scan signal, and the first terminal of the time initialization unit is connected to the first initialization signal; a voltage switching control unit, including a control terminal, a first terminal and a second terminal, the control terminal of the voltage switching control unit is electrically connected to the second terminal of the time initialization unit, the first terminal of the voltage switching control unit is connected to the reference voltage signal, and the second terminal of the voltage switching control unit is electrically connected to the control terminal of the current control module; a time data writing unit, including a control terminal, a first terminal and a second terminal, the control terminal of the time data writing unit is connected to a second time control scan signal, and the first terminal of the time data writing unit is connected to the time data signal; a coupling unit, including a first terminal and a second terminal, the first terminal of the coupling unit is electrically connected to the second terminal of the time data writing unit, and the second terminal of the coupling unit is electrically connected to the second terminal of the time initialization unit.

2. The pixel circuit according to claim 1, characterized in that, the time initialization unit includes: a first transistor, the gate of the first transistor serves as the control terminal of the time initialization unit, the first pole of the first transistor serves as the first terminal of the time initialization unit, and the second pole of the first transistor serves as the second terminal of the time initialization unit.

3. The pixel circuit according to claim 2, characterized in that, the first transistor is an N-type transistor.

4. The pixel circuit according to claim 2, characterized in that, the voltage switching control unit includes: a second transistor, the gate of the second transistor serves as the control terminal of the voltage switching control unit, the first pole of the second transistor serves as the first terminal of the voltage switching control unit, and the second pole of the second transistor serves as the second terminal of the voltage switching control unit.

5. The pixel circuit according to claim 4, characterized in that, the second transistor is a P-type transistor.

6. The pixel circuit according to claim 1, characterized in that, The time data writing unit includes: a third transistor, where the gate of the third transistor serves as the control end of the time data writing unit, the first pole of the third transistor serves as the first end of the time data writing unit, and the second pole of the third transistor serves as the second end of the time data writing unit.

7. The pixel circuit according to claim 6, wherein, the third transistor is a P-type transistor.

8. The pixel circuit according to claim 1, wherein, the coupling unit includes a first capacitor, where the first pole of the first capacitor serves as the first end of the coupling unit, and the second pole of the first capacitor serves as the second end of the coupling unit.

9. The pixel circuit according to claim 1, wherein, the current control module includes: a driving unit, including a control end, where the control end of the driving unit serves as the control end of the current control module, and the driving unit is configured to generate a driving current in response to the potential of its control end; a current data writing unit, configured to write a current data signal to the control end of the driving unit; a storage unit, configured to store the potential of the control end of the driving unit.

10. The pixel circuit according to claim 9, wherein, the current data signal and the time data signal share a signal line.

11. A display panel, wherein, it includes the pixel circuit according to any one of claims 1-10.

12. A driving method for a pixel circuit, wherein, the pixel circuit includes a current control module and a time control module; the time control module includes: a time initialization unit, including a control end, a first end, and a second end, where the control end of the time initialization unit is connected to a first time control scan signal, and the first end of the time initialization unit is connected to a first initialization signal; a voltage switching control unit, including a control end, a first end, and a second end, where the control end of the voltage switching control unit is electrically connected to the second end of the time initialization unit, the first end of the voltage switching control unit is connected to a reference voltage signal, and the second end of the voltage switching control unit is electrically connected to the control end of the current control module; a time data writing unit, including a control end, a first end, and a second end, where the control end of the time data writing unit is connected to a second time control scan signal, and the first end of the time data writing unit is connected to a time data signal; a coupling unit, including a first end and a second end, where the first end of the coupling unit is electrically connected to the second end of the time data writing unit, and the second end of the coupling unit is electrically connected to the second end of the time initialization unit; the driving method includes: a time initialization stage, initializing the time control module using a time data signal and a first initialization signal; a time data writing stage, where the time data signal undergoes a jump, and the voltage at the second end of the time initialization unit undergoes a jump; During the time-luminescence stage, which is within the luminescence stage of the current control module, a jump occurs in the first initialization signal. The time control module controls the reference voltage signal to be output to the current control module after a preset time based on the voltage jump at the second terminal of the time initialization unit and the first initialization signal, so as to control the current control module to disconnect; wherein, the jump amount of the time data signal is associated with the preset time.

13. The driving method of the pixel circuit according to claim 12, characterized in that, the waveform of the time data signal changes in a square wave shape; the waveform of the first initialization signal changes in a square wave shape; the reference voltage signal is a DC voltage signal.

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