A display panel

Abstract

The present application relates to the field of display control technology, and discloses a display panel, including: a display area, wherein the display area includes pixel units arranged in an array and a plurality of gate lines extending along a first direction, wherein each row of pixel units is electrically connected to the signal input ends of at least two gate lines, a first gate driving circuit and a second gate driving circuit are respectively located on both sides of the display area, and the signal input ends of at least two gate lines electrically connected to the pixel units in the same row are located on the same side of the display area, so that the signal input ends of at least two gate lines on the same side are used to power switches of three color channels R, G and B in the pixel units in the same row, thereby ensuring balanced power supply to each pixel unit, thereby reducing the left green and right red, vertical stripes and other problems caused by inconsistent voltage differences.

Description

Technical Field

[0001] The present application relates to the field of display control technology and provides a display panel. Background Art

[0002] Currently, DualGate technology has been widely used in display panels. It can not only save integrated circuit (IC) costs, but also reduce the number of ICs in high pixel density (Pixels Per Inch, PPI) products and improve module bonding problems. During the implementation process, due to the influence of gate line delay, the voltage difference of pixels is inconsistent, resulting in the problem of green on the left and red on the right. Summary of the invention

[0003] A display panel provided in an embodiment of the present application is used to improve the situation in which the left side is blue and the right side is red, vertical stripes are defective, etc. in a display area.

[0004] The specific technical solutions provided by this application are as follows:

[0005] In a first aspect, an embodiment of the present application provides a display panel, comprising: a display area;

[0006] The display area includes pixel units arranged in an array and a plurality of gate lines extending along a first direction;

[0007] Each row of pixel units is electrically connected to the signal input terminals of at least two gate lines;

[0008] A first gate driving circuit and a second gate driving circuit respectively located at two sides of the display area;

[0009] The signal input ends of at least two gate lines electrically connected to the pixel units in the same row are located at the same side of the display area.

[0010] Optionally, the signal input ends of at least two gate lines electrically connected to the odd-numbered rows of pixel units are located at one side of the display area;

[0011] The signal input ends of at least two gate lines electrically connected to the even-numbered rows of pixel units are located at the other side of the display area.

[0012] Optionally, any two pixel units electrically connected to the same gate line are electrically connected to different data lines, wherein the data lines extend along the second direction, and the first direction intersects the second direction.

[0013] Optionally, the data lines of the pixel units in the Nth column are electrically connected to the data lines of the pixel units in the N+6th column, where N is a natural number.

[0014] Optionally, the same grid includes two pixel units, one of which is electrically connected to one of the two gate lines, and the other pixel unit is electrically connected to the other of the two gate lines, and the grid is determined by two adjacent gate lines and two adjacent data lines.

[0015] Optionally, if the same grid includes a pixel unit, the first k pixel units in the same row of pixel units are electrically connected to one of the two gate lines, and the last k pixel units in the same row of pixel units are electrically connected to the other of the two gate lines, alternating in sequence, where k is a natural number.

[0016] Optionally, it also includes: the first gate driving circuit includes a plurality of cascaded first shift registers, the second gate driving circuit includes a plurality of cascaded second shift registers, and each first shift register shares a first signal input terminal, and each second shift register shares a second signal input terminal.

[0017] Optionally, the height of one pixel unit corresponds to one first shift register or one second shift register.

[0018] Optionally, a connection line between the first shift register or the second shift register and the corresponding gate line extends along the gate line direction.

[0019] Optionally, the first gate driving circuit is connected to the 1st to Mth clock signals, where M is a natural number;

[0020] The second gate driving circuit is connected to the (M+1)th to (2M)th clock signals, wherein any two of every M clock signals are the same square wave signals.

[0021] Other features and advantages of the present application will be described in the following description, and partly become apparent from the description, or be understood by practicing the present application. The purpose and other advantages of the present application can be realized and obtained by the structures specifically pointed out in the written description, claims, and drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] The drawings described herein are used to provide a further understanding of the present application and constitute a part of the present application. The illustrative embodiments of the present application and their descriptions are used to explain the present application and do not constitute an improper limitation on the present application. In the drawings:

[0023] Figure 1 A schematic diagram of a driving architecture of a pixel unit in the related art;

[0024] Figure 2 is a schematic diagram of a driving architecture of a second pixel unit in the related art;

[0025] Figure 3 is a schematic diagram of a driving architecture of a third pixel unit in the related art;

[0026] Figure 4 is a schematic diagram of a driving architecture of a fourth pixel unit in the related art;

[0027] Figure 5 It is a schematic diagram of connecting pixel units in the same row to different side gate lines in the related art;

[0028] Figure 6 This is a schematic diagram of connecting pixel units in the same row to gate lines on the same side in an embodiment of the present application;

[0029] Figure 7 This is a schematic diagram of pixel units in different columns multiplexing the same data line in an embodiment of the present application;

[0030] Figure 8 This is another schematic diagram of connecting pixel units in the same row to gate lines on the same side in an embodiment of the present application;

[0031] Fig. 9 This is a schematic diagram of wiring the first shift register and the second shift register on both sides of the display panel in an embodiment of the present application. DETAILED DESCRIPTION

[0032] In order to make the purpose, technical solution and advantages of the embodiments of the present application clearer, the technical solution of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the technical solution of the present application, rather than all of the embodiments. Based on the embodiments recorded in the application documents, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the technical solution of the present application.

[0033] The terms "first", "second", etc. in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the numbers used in this way can be interchanged where appropriate, so that the embodiments of the present invention described herein can be implemented using sequences other than those illustrated or described herein.

[0034] The preferred implementation modes of the present application are described in detail below with reference to the accompanying drawings.

[0035] During implementation, see Figure 1 , Figure 2 and Figure 3 The pixel structure shown in the figure often results in high power consumption, uneven brightness, and bad shaking head lines. In order to improve the above situation, the common pixel structure corresponding to DualGate technology is as follows Figure 4As shown, if this pixel structure adopts Figure 5 The single drive design shown in the figure has an inconsistent voltage difference of pixels due to the influence of gate line delay, resulting in the problem of green on the left and red on the right. Figure 5 From the above example, the R pixel on the left is driven by the proximal end of one gate line, and the G pixel is driven by the distal end of another gate line. In this way, the R pixel ΔVp is large, the G pixel ΔVp is small (brighter), and the display effect is green; the G pixel on the right is driven by the proximal end of one gate line, and the R pixel is driven by the distal end of another gate line. The G pixel ΔVp is large, the R pixel ΔVp is small, and the display effect is red.

[0036] in addition, Figure 5 A level transmission architecture can be adopted, that is, the pull-up module of G5 is opened by G1, G6 is opened by G2, G7 is opened by G3, G8 is opened by G4, and so on; this case not only supports the Gn+4GOA level transmission architecture, but also Gn+8 and Gn+12.

[0037] See also Figure 6 As shown, a display panel in an embodiment of the present application includes: a display area.

[0038] The display area includes pixel units arranged in an array and a plurality of gate lines extending along a first direction.

[0039] It should be noted that the above-mentioned display area is a plurality of pixel units in the display panel that actually have display capabilities, and the plurality of pixel units are arranged in an array, each of which includes three color channels of R, G and B, and the pixel units in each row and each column in the array jointly display the image in the display panel.

[0040] In addition to the pixel units arranged in an array, the display area also includes a plurality of gate lines extending along a first direction. Preferably, the first direction is a horizontal direction, that is, the gate lines are parallel to each row of pixel units in the array.

[0041] Each row of pixel units is electrically connected to the signal input terminals of at least two gate lines, and correspondingly, also includes a first gate driving circuit and a second gate driving circuit respectively located at two sides of the display area.

[0042] In the embodiment of the present application, each row of pixel units is electrically connected to the signal input end of at least two gate lines. Usually, the three color channels R, G and B in each pixel unit are electrically connected to different gate lines. Since each color channel includes a switch tube, the switch tube is electrically connected to the gate line, and the opening and closing of the light switch tube is controlled by the electrical signal on the gate line. Preferably, the three color channels R, G and B in each pixel unit are electrically connected to the signal input end of at least two gate lines.

[0043] During the implementation process, the above-mentioned first gate driving circuit is connected to the signal input terminal of one gate line among the at least two gate lines, and is used to generate a first driving signal, and transmit the first driving signal to the corresponding signal input terminal. The above-mentioned second gate driving circuit is connected to the signal input terminal of another gate line among the at least two gate lines, and is used to generate a second driving signal, and transmit the second driving signal to the corresponding signal input terminal.

[0044] The signal input ends of at least two gate lines electrically connected to the pixel units in the same row are located at the same side of the display area.

[0045] Taking into account that the input end of the gate line is usually on one side of the display area, and the electrical signal in the gate line will be delayed and attenuated during the transmission process, based on this, in order to balance the current in each pixel unit, in an embodiment of the present application, the signal input ends of at least two gate lines electrically connected to the same row of pixel units are located on the same side of the display area.

[0046] Furthermore, the signal input ends of at least two gate lines electrically connected to the odd-numbered pixel units are located on one side of the display area, and the signal input ends of at least two gate lines electrically connected to the even-numbered pixel units are located on the other side of the display area.

[0047] That is to say, the signal input ends of at least two gate lines electrically connecting two adjacent rows of pixel units are located on different sides of the display area. In this way, the current balance of the pixel units in each row can be ensured, effectively avoiding the situation where the left side is green and the right side is red due to voltage difference, and the display uniformity of the entire display panel can be ensured.

[0048] Any two pixel units electrically connected to the same gate line are electrically connected to different data lines, wherein the data lines extend along the second direction, and the first direction intersects the second direction.

[0049] The display area also includes data lines for providing display values ​​for the three color channels R, G and B in each pixel unit, that is, the gate lines control the turning off of the color channels, and the data lines control the specific values ​​displayed by the color channels. In the embodiment of the present application, in the same row of pixel units, any two pixel units electrically connected to the same gate line are electrically connected to different data lines, and preferably, the above-mentioned any two pixel units are two adjacent pixel units or four adjacent pixel units.

[0050] In the above array, the data lines extend along the second direction, and the first direction intersects the second direction.

[0051] Preferably, the data lines are arranged in parallel with the columns in the array, and the first direction crosses the second direction. Preferably, the second direction is a vertical direction.

[0052] The data lines of the pixel units in the Nth column and the pixel units in the N+6th column are electrically connected, wherein N is a natural number.

[0053] In order to ensure the display effect of each column of pixel units and reduce the wiring of data lines to a certain extent, refer to Figure 7 As shown, in the embodiment of the present application, the data lines of the pixel units in the Nth column are electrically connected to the pixel units in the N+6th column, where N is a natural number.

[0054] That is, the data line of the pixel units in the first column is the same as the data line of the pixel units in the seventh column, the data line of the pixel units in the second column is the same as the data line of the pixel units in the eighth column, and so on.

[0055] See also Figure 6 As shown, the same grid includes two pixel units, one of which is electrically connected to one of the two gate lines, and the other pixel unit is electrically connected to the other of the two gate lines. The grid is determined by two adjacent gate lines and two adjacent data lines.

[0056] Since the multiple gate lines and the multiple data lines in the display area divide all the pixel units, two adjacent gate lines and two adjacent data lines determine a grid. It should be noted that the grid includes two pixel units. In order to achieve a better display effect, one of the pixel units is electrically connected to one of the two gate lines (for example, the gate line above the row of pixel units), and the other pixel unit is electrically connected to the other of the two gate lines (for example, the gate line below the row of pixel units).

[0057] See also Figure 7 and Figure 8 As shown, if the same grid includes a pixel unit, the first k pixel units in the same row of pixel units are electrically connected to one of the two gate lines, and the last k pixel units in the same row of pixel units are electrically connected to the other of the two gate lines.

[0058] In another embodiment, based on the electrical connection of the data lines of the pixel units in the Nth column and the pixel units in the N+6th column, there may be a situation where one pixel unit is included in the same grid. In this case, the first k pixel units in the same row of pixel units may be electrically connected to one of the two gate lines (for example, the gate line above the pixel units in the row), and the last k pixel units in the same row of pixel units may be electrically connected to the other of the two gate lines (for example, the gate line below the pixel units in the row).

[0059] Furthermore, during the wiring process, the height of one pixel unit corresponds to one first shift register or one second shift register.

[0060] In the related art, for example, in some products, a shift dual-drive Dualgate design is adopted, and the height of the pixel unit in the shift wiring space in the first direction is 36.5um-50um. In the present application, since the pixel units in the same row are all driven by a single side, the pixel units in the shift wiring space are 73um-100um, that is, the height of the pixel units corresponding to the first shift register and the second shift register in the first direction is 73um-100um.

[0061] In addition, in order to ensure the signal input of each of the above-mentioned gate lines, in an embodiment of the present application, the first gate driving circuit includes a plurality of cascaded first shift registers, the second gate driving circuit includes a plurality of cascaded second shift registers, and each first shift register shares a first signal input terminal, and each second shift register shares a second signal input terminal.

[0062] During implementation, the first gate driving circuit located on the same side of the display area includes a plurality of cascaded first shift registers, each of which is used to drive pixel units located in different rows. Similarly, the second gate driving circuit located on the other side of the display area includes a plurality of cascaded second shift registers, each of which is used to drive pixel units located in different rows.

[0063] Furthermore, in order to facilitate the provision of driving signals, the above-mentioned first shift registers share a first signal input terminal, that is, the driving signals are provided to each first shift register through the first signal input terminal, and the second shift registers share a second signal input terminal, that is, the driving signals are provided to each second shift register through the second signal input terminal.

[0064] See also Fig. 9 As shown, the connection line between the first shift register or the second shift register and the corresponding gate line extends along the gate line direction.

[0065] It should be noted that, for the convenience of wiring, the connection line between the first shift register and the corresponding gate line extends along the gate line direction. The connection line between the second shift register and the corresponding gate line also extends along the gate line direction. Usually, after the above-mentioned connection lines are extended, the first shift register and the second shift register can be evenly distributed on both sides of the display area.

[0066] In addition, the first gate drive circuit is connected to the 1st to Mth clock signals, where M is a natural number, and the second gate drive circuit is connected to the M+1th to 2Mth clock signals, where any two every M clock signals are the same square wave signal.

[0067] Usually, the signal used to power the gate line is a square wave signal, etc., which is pre-stored in a register. In order to reduce the input of the excitation source signal, the first gate drive circuit is connected to the 1st to Mth clock signals, and the second gate drive circuit is connected to the M+1th to 2Mth clock signals. Any two clock signals every M are the same square wave signal, where M is a natural number.

[0068] First of all, it should be explained that due to the fast signal transmission rate, the impact of sharing the same square wave signal can be ignored, so the number of square wave signal inputs can be reduced to a certain extent. During the implementation process, every M arbitrary two clock signals are the same square wave signal, that is, the 1st clock signal and the M+1th clock signal are the same square wave signal, the 2nd clock signal and the M+2th clock signal are the same square wave signal, and so on, the Mth clock signal and the 2Mth clock signal are the same square wave signal.

[0069] It should be noted that, generally, the above-mentioned same square wave signal refers to a square wave signal with the same duty cycle, that is, the duty cycles of the first square wave signal and the second square wave signal corresponding to different driving circuits are the same, and so on.

[0070] In summary, in an embodiment of the present application, a display panel is provided, comprising: a display area, wherein the display area comprises pixel units arranged in an array and a plurality of gate lines extending along a first direction, wherein each row of pixel units is electrically connected to the signal input ends of at least two gate lines, a first gate driving circuit and a second gate driving circuit are respectively located on both sides of the display area, and the signal input ends of at least two gate lines electrically connected to the same row of pixel units are located on the same side of the display area, so that the signal input ends of at least two gate lines on the same side are used to power the switches of the three color channels R, G and B in the same row of pixel units, thereby ensuring balanced power supply to each pixel unit, thereby reducing the left green and right red, vertical stripes and other defects caused by inconsistent voltage differences.

[0071] Those skilled in the art will appreciate that the embodiments of the present application may be provided as methods, systems, or computer program product systems. Therefore, the present application may adopt the form of a complete hardware embodiment, a complete software embodiment, or an embodiment in combination with software and hardware. Moreover, the present application may adopt the form of a computer program product system implemented in one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) that include computer-usable program code.

[0072] The present application is described with reference to the flowcharts and / or block diagrams of the methods, devices (systems), and computer program product systems according to the present application. It should be understood that each process and / or box in the flowchart and / or block diagram, as well as the combination of the processes and / or boxes in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to produce a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0073] These computer program instructions may also be stored in a computer-readable memory capable of directing a computer or other programmable data processing device to operate in a specific manner, so that the instructions stored in the computer-readable memory produce an article of manufacture comprising an instruction device, which implements the process Figure 1 A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.

[0074] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operating steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing instructions for implementing the process. Figure 1 A process or multiple processes and / or boxes Figure 1 The steps for the functions specified in one or more boxes.

[0075] Obviously, those skilled in the art can make various changes and modifications to the present application without departing from the spirit and scope of the present application. Thus, if these modifications and variations of the present application fall within the scope of the claims of the present application and their equivalents, the present application is also intended to include these modifications and variations.

Claims

1. A display panel, characterized in that: include: Display area; The display area includes pixel units arranged in an array and a plurality of gate lines extending along a first direction; Each row of the pixel units is electrically connected to at least two of the gate lines; A first gate driving circuit and a second gate driving circuit respectively located at two sides of the display area; The signal input ends of at least two gate lines electrically connected to the pixel units in the same row are located at the same side of the display area.

2. The display panel according to claim 1, wherein: The signal input ends of at least two of the gate lines electrically connected to the odd-numbered rows of pixel units are located at one side of the display area; The signal input ends of at least two of the gate lines electrically connected to the pixel units in even-numbered rows are located at the other side of the display area.

3. The display panel according to claim 1, wherein: Any two pixel units electrically connected to the same gate line are electrically connected to different data lines, wherein the data lines extend along a second direction, and the first direction intersects the second direction.

4. The display panel according to claim 3, wherein: The pixel units in the Nth column are electrically connected to the data lines of the pixel units in the N+6th column, wherein N is a natural number.

5. The display panel according to claim 1, wherein: The same grid includes two pixel units, one of which is electrically connected to one of the two gate lines, and the other pixel unit is electrically connected to the other of the two gate lines. The grid is determined by two adjacent gate lines and two adjacent data lines.

6. The display panel according to claim 1, wherein: The same grid includes one pixel unit, then the first k pixel units in the same row are electrically connected to one of the two gate lines, and the last k pixel units in the same row are electrically connected to the other of the two gate lines, alternating in sequence, and the grid is determined by two adjacent gate lines and two adjacent data lines.

7. The display panel according to any one of claims 1 to 6, characterized in that: Also includes: The first gate driving circuit includes a plurality of cascaded first shift registers, and the second gate driving circuit includes a plurality of cascaded second shift registers. The first shift registers share a first signal input terminal, and the second shift registers share a second signal input terminal.

8. The display panel according to claim 6, wherein: The height of one pixel unit corresponds to one first shift register or one second shift register.

9. The display panel according to claim 8, wherein: The connection line between the first shift register or the second shift register and the corresponding gate line extends along the gate line direction.

10. The display panel according to claim 6, wherein: The first gate driving circuit is connected to the 1st to Mth clock signals, wherein M is a natural number; The second gate driving circuit is connected to the (M+1)th to (2M)th clock signals, wherein any two of every M clock signals are the same square wave signal.

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