Display panel and display device

Abstract

This invention discloses a display panel and a display device. The display panel has a first display area and a second display area, and includes: a first sub-pixel, a second sub-pixel, a scanning circuit, a first pixel circuit, and a second pixel circuit. The first sub-pixel is located in the first display area, and the second sub-pixel is located in the second display area. The scanning circuit is located in the first display area, and the first pixel circuit and the second pixel circuit are located in the second display area. The first pixel circuit drives the corresponding first sub-pixel, and the second pixel circuit drives the corresponding second sub-pixel. The arrangement order of each first pixel circuit in the second display area is consistent with the arrangement order of the first sub-pixels corresponding to each first pixel circuit in the first display area. The technical solution of this invention helps to reduce the area of ​​the non-display area, thereby achieving a narrow bezel design.

Description

Technical Field

[0001] This invention relates to the field of display technology, and more particularly to a display panel and a display device. Background Technology

[0002] With the continuous development of display technology, people have increasingly higher requirements for the performance of display panels. Display panels consist of display areas and non-display areas. The non-display areas are usually designed with scanning circuits and packaging areas, which makes the non-display areas relatively large, resulting in larger bezels on the display panels and hindering the improvement of screen-to-body ratio. Summary of the Invention

[0003] This invention provides a display panel and a display device that help reduce the area of ​​the non-display area, thereby achieving a narrow bezel design.

[0004] In a first aspect, embodiments of the present invention provide a display panel having a first display area and a second display area, the display panel comprising:

[0005] A first sub-pixel and a second sub-pixel, wherein the first sub-pixel is located in the first display area and the second sub-pixel is located in the second display area;

[0006] The scanning circuit is located in the first display area;

[0007] A first pixel circuit and a second pixel circuit are located in the second display area. The first pixel circuit is used to drive the corresponding first sub-pixel, and the second pixel circuit is used to drive the corresponding second sub-pixel. The arrangement order of each first pixel circuit in the second display area is consistent with the arrangement order of the first sub-pixels corresponding to each first pixel circuit in the first display area.

[0008] Optionally, m second sub-pixels constitute a sub-pixel unit, and at least some of the second pixel circuits corresponding to the m second sub-pixels in the sub-pixel unit and a first pixel circuit constitute a pixel driving unit, and the first pixel circuits corresponding to each first sub-pixel are located in different pixel driving units, where m≥1;

[0009] Preferably, the first sub-pixel and the second sub-pixel are arranged in the same row and in an array. The m second sub-pixels in the sub-pixel unit are located in the same row. The first pixel circuit corresponding to the i-th first sub-pixel in each row is located in the pixel driving unit corresponding to the i-th sub-pixel unit in that row, i≤n, where n is the total number of first sub-pixels in each row and n≥1.

[0010] Preferably, the first pixel circuit is located between two adjacent second pixel circuits.

[0011] Optionally, the display panel further includes a first data line that corresponds one-to-one with each column of the first sub-pixels and a second data line that corresponds one-to-one with each column of the second sub-pixels, wherein both the first data line and the second data line are located in the second display area;

[0012] The j-th first data line is connected to the first pixel circuit corresponding to the first sub-pixel in the j-th column, and is used to transmit data voltage to the first pixel circuit corresponding to the first sub-pixel in the j-th column; the k-th second data line is connected to the second pixel circuit corresponding to the second sub-pixel in the k-th column, and is used to transmit data voltage to the second pixel circuit corresponding to the second sub-pixel in the k-th column; the arrangement order of each first data line and each second data line in the second display area is consistent with the arrangement order of each first pixel circuit and each second pixel circuit connected to it in the second display area;

[0013] Where j≤a, a is the total number of columns of the first sub-pixel, and a≥1; k≤b, b is the total number of columns of the second sub-pixel, and b≥1.

[0014] Optionally, the display panel has a non-display area, and the display panel further includes a first data connection line corresponding to a first data line, b second data connection lines corresponding to b second data lines, and a plurality of bonding connection parts, wherein the first data connection line, the second data connection line, and the bonding connection parts are all located in the non-display area;

[0015] The j-th first data connection line is connected between the j-th first data line and the corresponding bonding connection part, and the k-th second data connection line is connected between the k-th second data line and the corresponding bonding connection part;

[0016] The arrangement of the first data connection line and the second data connection line satisfies either the first condition or the second condition; the first condition is that the arrangement order of the first data connection line a and the second data connection line b is consistent with the arrangement order of the first sub-pixel in column a and the second sub-pixel in column b in the second display area; the second condition is that the arrangement order of each first data connection line and the second data connection line is consistent with the arrangement order of each first data line and the second data line connected to it in the second display area.

[0017] Optionally, the non-display area includes a first non-display area and a second non-display area. Along the extension direction of the first data line or the second data line, the first non-display area and the second non-display area are arranged sequentially on one side of the second display area, and the first non-display area is a fan-out area.

[0018] Both the first data connection line and the second data connection line are located in the first non-display area, or both the first data connection line and the second data connection line are located in the second non-display area.

[0019] Optionally, the display panel includes a substrate and an anode layer, wherein the anodes of the first sub-pixel and the second sub-pixel are disposed in the anode layer, and the scanning circuit, the first pixel circuit and the second pixel circuit are all located between the substrate and the anode layer, wherein the first pixel circuit is connected to the anode of the corresponding first sub-pixel, and the second pixel circuit is connected to the anode of the corresponding second sub-pixel;

[0020] The vertical projection of each of the scanning circuits on the substrate and the vertical projection of the anode of each of the first sub-pixels on the substrate are located in the same area of ​​the first display area.

[0021] Optionally, the vertical projections of the first pixel circuit and the second pixel circuit in each pixel driving unit onto the substrate, and the vertical projections of the anodes of the m second sub-pixels corresponding to that pixel driving unit onto the substrate, are located in the same area of ​​the second display area.

[0022] Optionally, the display panel further includes a shielding electrode located between the anode layer and the scanning circuit, for shielding the signal interference between the anode and the scanning circuit.

[0023] Secondly, embodiments of the present invention provide a display device, including the display panel described in the first aspect.

[0024] Optionally, the arrangement of the first data connection line and the second data connection line satisfies the second condition; the bonding connection part includes a first bonding connection part that is connected to a first data connection line in a one-to-one correspondence and a second bonding connection part that is connected to b second data connection lines in a one-to-one correspondence; the arrangement order of each first bonding connection part and the second bonding connection part is consistent with the arrangement order of each first data connection line and the second data connection line to which it is connected.

[0025] The display device further includes a flexible connector, which includes a first lines corresponding to a first bonding connection portions and b second lines corresponding to b second bonding connection portions; the j-th first line connects to the j-th first bonding connection portion, and the k-th second line connects to the k-th second bonding connection portion; the arrangement order of the a first lines and b second lines on the flexible connector is consistent with the arrangement order of the corresponding a column of first sub-pixels and b column of second sub-pixels in the second display area; or...

[0026] The display device further includes a driver chip, which includes a first data voltage terminals corresponding to a first bonding connection portions and b second data voltage terminals corresponding to b second bonding connection portions. The j-th first data voltage terminal is connected to the j-th first bonding connection portion, and the k-th second data voltage terminal is connected to the k-th second bonding connection portion. The arrangement order of the a first data voltage terminals and the b second data voltage terminals on the driver chip is consistent with the arrangement order of the corresponding a column of first sub-pixels and b column of second sub-pixels in the second display area. Alternatively, the arrangement order of the a first data voltage terminals and the b second data voltage terminals on the driver chip is consistent with the arrangement order of each first bonding connection portion and second bonding connection portion to which they are connected, and the driver chip is configured to: output the data voltage of the first sub-pixel corresponding to the first pixel circuit connected to it through the first data voltage terminal, and output the data voltage of the second sub-pixel corresponding to the second pixel circuit connected to it through the second data voltage terminal.

[0027] The display panel and display device provided in this invention, by placing the first pixel circuit corresponding to the first sub-pixel in the first display area and the second pixel circuit corresponding to the second sub-pixel in the second display area in the second display area, eliminate the need for the first pixel circuit to occupy space in the first display area, thus freeing up space for the scanning circuit. This allows the scanning circuit to provide scanning signals to both the first and second pixel circuits without placing the scanning circuit in a non-display area, preventing it from occupying space in that area and reducing its size, thereby achieving a narrow bezel design. Furthermore, by placing the first pixel circuit between two adjacent second pixel circuits, and ensuring that the arrangement order of each first pixel circuit in the second display area matches the arrangement order of the corresponding first sub-pixels, it is convenient to supply data voltage to the corresponding first pixel circuit according to the arrangement order of the first sub-pixels, enabling sequential driving of each first sub-pixel according to its arrangement order, which simplifies the driving method of the first sub-pixels.

[0028] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of the present invention, nor is it intended to limit the scope of the invention. Other features of the invention will become readily apparent from the following description. Attached Figure Description

[0029] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0030] Figure 1 This is a schematic diagram of the structure of a display panel provided in an embodiment of the present invention;

[0031] Figure 2 yes Figure 1 An enlarged view of region B in the middle;

[0032] Figure 3 yes Figure 1 Another magnified view of region B in the middle;

[0033] Figure 4 yes Figure 1 The sectional view obtained by cutting the display panel along section line CC';

[0034] Figure 5 yes Figure 1 Another magnified view of region B in the middle;

[0035] Figure 6 yes Figure 1 An enlarged view of region M1 in the middle;

[0036] Figure 7 yes Figure 1 Another enlarged view of region M1;

[0037] Figure 8 yes Figure 1 Another enlarged view of region M1;

[0038] Figure 9 yes Figure 1 Another enlarged view of region M1;

[0039] Figure 10 yes Figure 1 The sectional view obtained by cutting the display panel along section line LL';

[0040] Figure 11 This is a schematic diagram of the structure of a display device provided in an embodiment of the present invention;

[0041] Figure 12 yes Figure 11 An enlarged view of the M2 region;

[0042] Figure 13 This is a schematic diagram of another display device provided in an embodiment of the present invention. Detailed Implementation

[0043] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.

[0044] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0045] As described in the background section, existing display panels have a large non-display area, resulting in a large bezel size, which is not conducive to improving the screen-to-body ratio. To address the above problems, embodiments of the present invention provide a display panel. Figure 1 This is a schematic diagram of the structure of a display panel provided in an embodiment of the present invention; Figure 2 yes Figure 1 An enlarged view of region B in the middle; Figure 3 yes Figure 1 Another enlarged view of region B in the middle. Among them, Figure 2 The arrangement of the first and second sub-pixels in region B is shown. Figure 3 The layout of the scanning circuit, the first pixel circuit, and the second pixel circuit in region B is shown.

[0046] Combination Figures 1 to 3The display panel has a display area and a non-display area (NAA). The display area includes a first display area AA1 and a second display area AA2. Specifically, the display panel includes: a first sub-pixel 110, a second sub-pixel 120, a scanning circuit 210, a first pixel circuit 310, and a second pixel circuit 320. The first sub-pixel 110 is located in the first display area AA1, and the second sub-pixel 120 is located in the second display area AA2. The scanning circuit 210 is located in the first display area AA1, and the first pixel circuit 310 and the second pixel circuit 320 are located in the second display area AA2. The first pixel circuit 310 drives the corresponding first sub-pixel 110, and the second pixel circuit 320 drives the corresponding second sub-pixel 120. The arrangement order of each first pixel circuit 310 in the second display area AA2 is consistent with the arrangement order of the corresponding first sub-pixels 110 in the first display area AA1.

[0047] Specifically, the display panel provided in this embodiment of the invention can be an Organic Light-Emitting Diode (OLED) display panel or a Micro-LED display panel, etc. The non-display area NAA of this display panel is located around the first display area AA1 and the second display area AA2, and the first display area AA1 is located on at least one side of the second display area AA2. Figure 1 The diagram shows a first display area AA1 located on the left and right sides of a second display area AA2. Both the first sub-pixel 110 and the second sub-pixel 120 can be light-emitting devices, such as organic light-emitting diodes (OLEDs) or micro-LEDs.

[0048] The first pixel circuit 310 is electrically connected to the corresponding first sub-pixel 110 to drive the corresponding first sub-pixel 110 to emit light. The second pixel circuit 320 is electrically connected to the corresponding second sub-pixel 120 to drive the corresponding second sub-pixel 120 to emit light. The structures of the first pixel circuit 310 and the second pixel circuit 320 can be the same. For example, both the first pixel circuit 310 and the second pixel circuit 320 include thin-film transistors and storage capacitors. The thin-film transistors include driving transistors and switching transistors. The scanning circuit 210 can connect the switching transistors in the first pixel circuit 310 and the second pixel circuit 320 through scan lines to provide a scan signal in the form of a pulse signal to the gate of the switching transistor through the scan lines. When there is a scan signal input to the gate of the switching transistor, the switching transistor is turned on, and a data voltage is transmitted to the driving transistor through the switching transistor and stored through the storage capacitor. This allows the driving transistor to provide a driving current to the corresponding first sub-pixel 110 or second sub-pixel 120 according to the data voltage stored in the storage capacitor, thereby driving the first sub-pixel 110 or the second sub-pixel 120 to emit light with a corresponding brightness.

[0049] By setting the second pixel circuit 320 corresponding to the second sub-pixel 120 in the second display area AA2 in the second display area AA2, and setting the first pixel circuit 310 corresponding to the first sub-pixel 110 in the first display area AA1 in the second display area AA2, the first pixel circuit 310 does not need to occupy the space of the first display area AA1, leaving space in the first display area AA1 for the scanning circuit 210. In this way, scanning signals can be provided to the first pixel circuit 310 and the second pixel circuit 320 through the scanning circuit 210, and the scanning circuit 210 does not need to be placed in the non-display area NAA, thus avoiding the scanning circuit 210 occupying the space of the non-display area NAA, which helps to reduce the area of ​​the non-display area NAA, thereby achieving a narrow bezel design.

[0050] The first pixel circuit 310 can be disposed in any area of ​​the second display area AA2. For example, the first pixel circuits 310 can be concentrated in the same area of ​​the second display area AA2, or dispersed in different areas of the second display area AA2, or a portion of the first pixel circuits 310 can be concentrated in the same area of ​​the second display area AA2, while the other portion can be dispersed in other areas of the second display area AA2. Preferably, each first pixel circuit 310 can be disposed in the area between two adjacent second pixel circuits 320. Figure 3This illustration shows different first pixel circuits 310 disposed between second pixel circuits 320 in different regions. In other embodiments, multiple first pixel circuits 310 may be disposed between two adjacent second pixel circuits 320. The arrangement order of each first pixel circuit 310 in the second display area AA2 is consistent with the arrangement order of the first sub-pixels 110 corresponding to each first pixel circuit 310 in the first display area AA1. This means that in each row of sub-pixels, each first sub-pixel 110 is arranged sequentially, and in the row of pixel circuits corresponding to that row of sub-pixels, the first pixel circuits 310 corresponding to each first sub-pixel 110 are arranged sequentially. Moreover, the arrangement order of each first pixel circuit 310 in the row of pixel circuits is the same as the arrangement order of the first sub-pixels 110 corresponding to each first pixel circuit 310 in the row of sub-pixels. For example, for the first sub-pixels 110 in the same row, the first pixel circuits 310 corresponding to each first sub-pixel 110 can be arranged according to their arrangement order. 10. Sequentially arranged between adjacent second pixel circuits 320 in the same row of second pixel circuits 320; and / or, in each column of sub-pixels, each first sub-pixel 110 is arranged sequentially, and in the column of pixel circuits corresponding to the column of sub-pixels, each first pixel circuit 310 corresponding to the first sub-pixel 110 is arranged sequentially, and the arrangement order of each first pixel circuit 310 in the column of pixel circuits is the same as the arrangement order of each first sub-pixel 110 corresponding to the first pixel circuit 310 in the column of sub-pixels. For example, for the first sub-pixels 110 in the same column, the first pixel circuits 310 corresponding to each first sub-pixel 110 can be sequentially arranged between adjacent second pixel circuits 320 in the same column of second pixel circuits 320 according to the arrangement order of each first sub-pixel 110. By setting the arrangement order of each first pixel circuit 310 in the second display area AA2 to be consistent with the arrangement order of the first sub-pixels 110 corresponding to each first pixel circuit 310 in the first display area AA1, it is convenient to supply data voltage to the corresponding first pixel circuit 310 according to the arrangement order of each first sub-pixel 110, so as to drive each first sub-pixel 110 one by one according to the arrangement order, which helps to simplify the driving method of the first sub-pixel 110.

[0051] In summary, the technical solution of this invention, by setting the first pixel circuit corresponding to the first sub-pixel in the first display area and the second pixel circuit corresponding to the second sub-pixel in the second display area in the second display area, eliminates the need for the first pixel circuit to occupy space in the first display area, thus freeing up space for the scanning circuit. This allows the scanning circuit to provide scanning signals to both the first and second pixel circuits without placing the scanning circuit in the non-display area, preventing it from occupying space and reducing the area of ​​the non-display area, thereby achieving a narrow bezel design. Furthermore, by positioning the first pixel circuit between two adjacent second pixel circuits, and ensuring that the arrangement order of each first pixel circuit in the second display area matches the arrangement order of the corresponding first sub-pixels, it is convenient to supply data voltage to the corresponding first pixel circuit according to the arrangement order of the first sub-pixels, enabling sequential driving of each first sub-pixel and simplifying the driving method of the first sub-pixels.

[0052] Figure 4 yes Figure 1 The sectional view is obtained by cutting the display panel along section line CC'. Combined with... Figures 1 to 4 In one embodiment, m second sub-pixels 120 constitute a sub-pixel unit 10. At least some of the m second sub-pixels 120 in the sub-pixel unit 10 correspond to a second pixel circuit 320 and a first pixel circuit 310, which constitute a pixel driving unit 30. The first pixel circuit 310 corresponding to each first sub-pixel 110 is located in different pixel driving units 30, where m≥1.

[0053] For example, let's take m=4 as an example. Every four second sub-pixels 120 can form a sub-pixel unit 10. The second pixel circuit 320 corresponding to the four second sub-pixels 120 and a first pixel circuit 310 in the sub-pixel unit 10 can form a pixel driving unit 30. In this way, the first pixel circuit 310 corresponding to each first sub-pixel 110 can be respectively set in different pixel driving units 30, so that the area between two adjacent second pixel circuits 320 in each pixel driving unit 30 can be used to set the first pixel circuit 310. Preferably, the first pixel circuit 310 can be set in the middle of the four second pixel circuits 320, that is, in the middle of the second and third second pixel circuits 320.

[0054] Furthermore, the first sub-pixel 110 and the second sub-pixel 120 can be arranged in the same row, and the first sub-pixel 110 and the second sub-pixel 120 are arranged in an array. The m second sub-pixels 120 in the sub-pixel unit 10 are located in the same row. The first pixel circuit 310 corresponding to the i-th first sub-pixel 110 in each row is located in the pixel driving unit 30 corresponding to the i-th sub-pixel unit 10 in that row, i≤n, where n is the total number of first sub-pixels 110 in each row, and n≥1.

[0055] The following explanation will still take m=4 as an example. For the first sub-pixel 110 and the second sub-pixel 120 in each row, every 4 second sub-pixels 120 can form a sub-pixel unit 10. The first pixel circuit 310 and the second pixel circuit 320 in the same pixel driving unit 30 are located in the same row, and the first pixel circuit 310 and the second pixel circuit 320 in the pixel driving unit 30 corresponding to the sub-pixel unit 10 in the same row are arranged in the same row. Figure 4 The diagram illustrates the case where there are a total of 8 first sub-pixels 110 in each row. When n=8, the first pixel circuit 310a corresponding to the first first sub-pixel 110a in each row can be set in the pixel driving unit 30 corresponding to the first sub-pixel unit 10 in that row; the first pixel circuit 310b corresponding to the second first sub-pixel 110b in each row can be set in the pixel driving unit 30 corresponding to the second sub-pixel unit 10 in that row; the first pixel circuit 310c corresponding to the third first sub-pixel 110c in each row can be set in the pixel driving unit 30 corresponding to the third sub-pixel unit 10 in that row; and the first pixel circuit 310d corresponding to the fourth first sub-pixel 110d in each row can be set in the pixel driving unit 30 corresponding to the first sub-pixel unit 10 in that row. The setting method for the first pixel circuits 310 corresponding to the 5th to 8th first sub-pixels 110 in each row can be deduced similarly and will not be described in detail here. This allows the first pixel circuits 310 corresponding to each first sub-pixel 110 to be sequentially arranged in each pixel driving unit 30 according to the arrangement order of each first sub-pixel 110 in each row. This ensures that the arrangement order of each first pixel circuit 310 is consistent with the arrangement order of the first sub-pixels 110 corresponding to each first pixel circuit 310 in the first display area AA1. This facilitates the supply of data voltage to the corresponding first pixel circuit 310 according to the arrangement order of each first sub-pixel 110, so as to drive each first sub-pixel 110 one by one according to the arrangement order, which helps to simplify the driving method of the first sub-pixels 110.

[0056] Furthermore, the arrangement order of each second pixel circuit 320 in the second display area AA2 can be set to be consistent with the arrangement order of the second sub-pixels 120 corresponding to each second pixel circuit 320 in the second display area AA2. For example, when m=4, the first second pixel circuit 320 in each pixel driving unit 30 can correspond to the first second sub-pixel 120 in the sub-pixel unit 10, the second second pixel circuit 320 can correspond to the second second sub-pixel 120 in the sub-pixel unit 10, the third second pixel circuit 320 can correspond to the third second sub-pixel 120 in the sub-pixel unit 10, and the fourth second pixel circuit 320 can correspond to the fourth second sub-pixel 120 in the sub-pixel unit 10. Moreover, the first pixel circuit 310 in the pixel driving unit 30 can be set between the second second pixel circuit 320 and the third second pixel circuit 320.

[0057] Figure 5 yes Figure 1 Another magnified view of region B in the middle. Combined with... Figure 2 and Figure 5 Based on the above embodiments, optionally, the display panel further includes a first data line D corresponding to each column of first sub-pixels 110 and a second data line E corresponding to each column of second sub-pixels 120. Both the first data line D and the second data line E are located in the second display area AA2. The j-th first data line D is connected to the first pixel circuit 310 corresponding to the j-th column of first sub-pixels 110, and is used to transmit data voltage to the first pixel circuit 310 corresponding to the j-th column of first sub-pixels 110. The k-th second data line E is connected to the second pixel circuit 320 corresponding to the k-th column of second sub-pixels 120, and is used to transmit data voltage to the second pixel circuit 320 corresponding to the k-th column of second sub-pixels 120. The arrangement order of each first data line D and the second data line E in the second display area AA2 is consistent with the arrangement order of each first pixel circuit 310 and second pixel circuit 320 to which they are connected in the second display area AA2. Where j≤a, a is the total number of columns of the first sub-pixel 110, and a≥1; k≤b, b is the total number of columns of the second sub-pixel 120, and b≥1.

[0058] In one embodiment, column a first sub-pixels 110 are arranged sequentially in the first display area AA1, and column b second sub-pixels 120 are arranged sequentially in the second display area AA2. From the first display area AA1 to the second display area AA2, column a first sub-pixels 110 and column b second sub-pixels 120 are arranged sequentially. The column b second pixel circuits 320 corresponding to the column b second sub-pixels 120 are arranged sequentially in the second display area AA2. One column of first sub-pixels 110 is interspersed within every m columns of second pixel circuits 320, and column a first pixel circuits 310 corresponding to column a first sub-pixels 110 are interspersed sequentially within each column of second pixel circuits 320. Correspondingly, b second data lines E connected to the column b second pixel circuits 320 are arranged sequentially in the second display area AA2. One first data line D is interspersed within every m second data lines E, and a first data line D is interspersed sequentially within each second data line E.

[0059] For example, when m=4 and a=8, the first data line D1 in the second display area AA2 is connected to the first pixel circuit 310 corresponding to the first sub-pixel 110 in the first column of the first display area AA1, the second data line D2 is connected to the first pixel circuit 310 corresponding to the first sub-pixel 110 in the second column of the first display area AA1, the third data line D3 is connected to the first pixel circuit 310 corresponding to the first sub-pixel 110 in the third column of the first display area AA1, and the fourth data line D4 is connected to the first pixel circuit 310 corresponding to the first sub-pixel 110 in the fourth column of the first display area AA1. The first second data line E1 in the second display area AA2 is connected to the second pixel circuit 320 corresponding to the second sub-pixel 120 in the first column of the second display area AA2. The second second data line E2 is connected to the second pixel circuit 320 corresponding to the second sub-pixel 120 in the second column of the second display area AA2, and so on. The sixteenth second data line E is connected to the second pixel circuit 320 corresponding to the second sub-pixel 120 in the sixteenth column of the second display area AA2. The first to sixteenth second data lines E1-E16 are arranged sequentially in the second display area AA2. One first data line D is inserted between every four second data lines E, and the first to fourth first data lines D1-D4 are inserted between the first to sixteenth second data lines E1-E16. Preferably, the first pixel circuit 310 in each pixel driving unit 30 can be disposed in the middle of the four second pixel circuits 320, that is, in the middle of the second and third second pixel circuits 320. Correspondingly, a first data line D can be disposed between the second and third of the four second data lines E.

[0060] It should be noted that, Figure 5Only the first data lines D1-D4 (1st to 4th) and the second data lines E1-E16 (1st to 16th) in the second display area AA2 are shown. The specific settings of the first data lines D (5th to 8th) and the remaining second data lines E can be understood by referring to the above text and will not be repeated here.

[0061] Figure 6 yes Figure 1 A magnified view of region M1 in the middle. Combined with... Figure 2 , Figure 5 and Figure 6 Based on the above embodiments, optionally, the display panel further includes a first data connection line F corresponding to a first data line D, b second data connection lines G corresponding to b second data lines E, and a plurality of bonding connection parts P. The first data connection lines F, second data connection lines G, and bonding connection parts P are all located in the non-display area NAA. The j-th first data connection line F is connected between the j-th first data line D and the corresponding bonding connection part P, and the k-th second data connection line G is connected between the k-th second data line E and the corresponding bonding connection part P.

[0062] Specifically, the bonding connection P is used to supply data voltage to transmit data voltage to the first data line D via the first data connection line F, or to the second data line E via the second data connection line G. The first first data connection line F1 is connected between the first first data line D1 and the corresponding bonding connection P; the second first data connection line F2 is connected between the second first data line D2 and the corresponding bonding connection P, and so on, with the a-th first data connection line Fa connected between the a-th first data line D1 and the corresponding bonding connection P. The first second data connection line G1 is connected between the first second data line E1 and the corresponding bonding connection P; the second second data connection line G2 is connected between the second second data line E2 and the corresponding bonding connection P, and so on, with the b-th second data connection line Gb connected between the b-th second data line Eb and the corresponding bonding connection P.

[0063] In one embodiment, the arrangement of the first data connection line F and the second data connection line G can satisfy a first condition. The first condition is that the arrangement order of the first data connection line F (a) and the second data connection line G (b) is consistent with the arrangement order of their corresponding first sub-pixel 110 (a) and second sub-pixel 120 (b) in the second display area AA2.

[0064] Specifically, the first sub-pixel 110 corresponding to the j-th first data connection line F is the first sub-pixel 110 corresponding to the first pixel circuit 310 connected to the first data line D connected to the j-th first data connection line F, and the second sub-pixel 120 corresponding to the k-th second data connection line G is the second sub-pixel 120 corresponding to the second pixel circuit 320 connected to the second data connection line G connected to the k-th second data connection line G. Optionally, when the first display area AA1 is located on one side of the second display area AA2, and the first sub-pixel 110 is provided in the first display area AA1, the first sub-pixels 110 in columns 1 to 1a in the first display area AA1 are arranged sequentially, and the second sub-pixels 120 in columns 1 to 1b in the second display area AA2 are arranged sequentially, and from the first display area AA1 to the second display area AA2, the first sub-pixels 110 in column a are arranged before the second sub-pixels 120 in column b. Accordingly, the first data connection lines F1-Fa, from the first to the ath, are arranged sequentially in the non-display area NAA, and the second data connection lines G1-Gb, from the first to the bth, are arranged sequentially in the non-display area NAA, with the first data connection lines F1-Fa preceding the second data connection lines G1-Gb. This ensures that the arrangement order of the ath first data connection lines F and the bth second data connection lines G is consistent with the arrangement order of their corresponding ath column first sub-pixels 110 and bth column second sub-pixels 120 in the second display area AA2. This arrangement facilitates the supply of data voltage to the bonding connection portion P connected to each of the first data connection lines F and the second data connection lines G according to the arrangement order of each first sub-pixel 110 and the second sub-pixel 120, thereby driving each of the first sub-pixels 110 and the second sub-pixels 120 individually and simplifying the pixel driving method of the display panel.

[0065] Figure 7 yes Figure 1 Another magnified view of region M1. Combined with... Figure 2 , Figure 5 and Figure 7Optionally, when the first display area AA1 is located on both sides of the second display area AA2, and each column of first sub-pixels 110 is respectively set in the first display area AA1 on both sides, the first sub-pixels 110 from the 1st column to the cth column are arranged sequentially in the first display area AA1 on one side of the second display area AA2, the second sub-pixels 120 from the 1st column to the bth column are arranged sequentially in the second display area AA2, and the first sub-pixels 110 from the c+1th column to the ath column are arranged sequentially in the first display area AA1 on the other side of the second display area AA2, where c = a / 2, a is an even number and a ≥ 2. Accordingly, the first data connection lines F1-Fc from the 1st to the cth are arranged sequentially in the non-display area NAA, the second data connection lines G1-Gb from the 1st to the bth are arranged sequentially in the non-display area NAA, and the first data connection lines Fc+1-Fa from the (c+1)th to the ath are arranged sequentially in the non-display area NAA. The first data connection lines F1-Fc are positioned before the second data connection line G1, and the first data connection lines Fc+1-Fa are positioned after the second data connection line Gb, so that the arrangement order of the ath first data connection line F and the bth second data connection line G is consistent with the arrangement order of their corresponding ath column first sub-pixel 110 and bth column second sub-pixel 120 in the second display area AA2. This embodiment also helps to simplify the pixel driving method of the display panel, for the same reasons as before.

[0066] Combination Figure 1 and Figure 6 or in combination Figure 1 and Figure 7 The non-display area NAA includes a first non-display area NAA1 and a second non-display area NAA2. Along the extension direction of the first data line D or the second data line E, the first non-display area NAA1 and the second non-display area NAA2 are sequentially arranged on one side of the second display area AA2. The first non-display area NAA1 is a fan-out area. Optionally, in one embodiment, both the first data connection line F and the second data connection line G are located in the first non-display area NAA1. Specifically, the non-display area NAA may further include a third non-display area NAA3, located on the side of the second non-display area NAA2 away from the first non-display area NAA1. The third non-display area NAA3 can be a bonding area. Both the first data connection line F and the second data connection line G can be fan-out lines. The second non-display area NAA2 may also include a first trace H. When both the first data connection line F and the second data connection line G are located in the first non-display area NAA1, each first data connection line F and each second data connection line G can be connected to the bonding connection part P through the first trace H.

[0067] Figure 8 yes Figure 1 Another magnified view of region M1. Figure 8The diagram illustrates the arrangement of the first data connection line F and the second data connection line G when the first display area AA1 is located on one side of the second display area AA2 and the first sub-pixel 110 is provided in the first display area AA1. Figure 9 yes Figure 1 Another magnified view of region M1. Figure 9 This illustrates the arrangement of the first data connection line F and the second data connection line G when the first display area AA1 is located on both sides of the second display area AA2, and each column of first sub-pixels 110 is respectively disposed on both sides of the first display area AA1. Combined with... Figure 1 and Figure 8 or in combination Figure 1 and Figure 9 Optionally, in another embodiment, both the first data connection line F and the second data connection line G are located in the second non-display area NAA2. When both the first data connection line F and the second data connection line G are located in the second non-display area NAA2, the first non-display area NAA1 may further include a first trace H, each first data connection line F is connected to the corresponding first data line D through the first trace H, and each second data connection line G is connected to the corresponding second data line E through the first trace H.

[0068] Figure 10 yes Figure 1 The sectional view is obtained by cutting the display panel along section line LL'. Combined with... Figure 4 and Figure 10 The display panel includes a substrate 410 and an anode layer 421. The anode layer 421 contains anodes 4211 for a first sub-pixel 110 and a second sub-pixel 120. A scanning circuit 210, a first pixel circuit 310, and a second pixel circuit 320 are all located between the substrate 410 and the anode layer 421. The first pixel circuit 310 is connected to the corresponding anode 4211 of the first sub-pixel 110, and the second pixel circuit 320 is connected to the corresponding anode 4211 of the second sub-pixel 120. The vertical projection of each scanning circuit 210 onto the substrate 410 and the vertical projection of each anode 4211 of the first sub-pixel 110 onto the substrate 410 are located within the same area of ​​the first display area AA1.

[0069] Specifically, the substrate 410 can provide buffering, protection, or support for the display panel. The display panel also includes a light-emitting functional layer 422 and a cathode 423 located on the side of the anode layer 421 away from the substrate 410. The anode layer 421, the light-emitting functional layer 422, and the cathode 423 form the respective first sub-pixels 110 and second sub-pixels 120 in the display panel. Since the first pixel circuit 310 corresponding to the first sub-pixel 110 is located in the second display area AA2, each scanning circuit 210 can be located in the area between the substrate 410 and the anode layer 421 in the first display area AA1. This ensures that the vertical projection of each scanning circuit 210 onto the substrate 410 is located in the same area as the vertical projection of the anode 4211 of each first sub-pixel 110 onto the substrate 410, thus avoiding the scanning circuit 210 occupying the space of the non-display area NAA, which helps to reduce the area of ​​the non-display area NAA and achieve a narrow bezel design.

[0070] Furthermore, the vertical projections of the first pixel circuit 310 and the second pixel circuit 320 in each pixel driving unit 30 onto the substrate 410, and the vertical projections of the anodes 4211 of the m second sub-pixels 120 corresponding to that pixel driving unit 30 onto the substrate 410, are located within the same area of ​​the second display area AA2. For example, when m = 4, the vertical projections of one first pixel circuit 310 and four second pixel circuits 320 in each pixel driving unit 30 onto the substrate 410, and the vertical projections of the anodes 4211 of the four second sub-pixels 120 corresponding to that pixel driving unit 30 onto the substrate 410, are located within the same area of ​​the second display area AA2. In other words, along the direction perpendicular to the substrate 410, each sub-pixel unit 10 and its corresponding pixel driving unit 30 are in the same position in the display panel. This allows the first pixel circuit 310 to be placed between adjacent second pixel circuits 320 in each pixel driving unit 30. At the same time, it ensures that the second sub-pixel 120 in each sub-pixel unit 10 and its corresponding second pixel circuit 320 are all placed in the same area, so that the second pixel circuit 320 connects to the corresponding second sub-pixel 120.

[0071] Furthermore, the display panel may also include a shielding electrode 450, which is located between the anode layer 421 and the scanning circuit 210, and is used to shield the signal interference between the anode 4211 and the scanning circuit 210, so as to avoid the signal in the scanning circuit 210 affecting the anode potential of the first sub-pixel 110, thereby affecting the display effect.

[0072] Figure 10The diagram shows a first transistor TFT1 and a first capacitor C1 located in the second display area AA2, and a second transistor TFT2 and a second capacitor C2 located in the first display area AA1. The first transistor TFT1 may be a transistor connected to the anode 4211 of the second sub-pixel 120 in the second pixel circuit 320. The first capacitor C1 may be a capacitor in the second pixel circuit 320. The second transistor TFT2 may be a transistor in the scanning circuit 210, and the second capacitor C2 may be a capacitor in the scanning circuit 210. The first transistor TFT1 includes an active layer 431, a gate 432, a first electrode 433, and a second electrode 434. One of the first electrode 433 and the second electrode 434 is the source, and the other is the drain. The first capacitor C1 includes a first electrode plate 441 and a second electrode plate 442. The gate 432 of the first transistor TFT1 and the first electrode plate 441 of the first capacitor C1 are located in the first metal layer M1, the second electrode plate 442 of the first capacitor C1 is located in the second metal layer M2, and the first electrode 433 and the second electrode 434 of the first transistor TFT1 are located in the third metal layer M3. The display panel also includes a fourth metal layer M4 located between the anode layer 421 and the third metal layer M3. The shielding electrode 450 can be disposed in the fourth metal layer M4 of the first display area AA1, and the vertical projection of the shielding electrode 450 on the substrate 410 can overlap with the vertical projection of the anode 4211 of the first sub-pixel 110 on the substrate 410 to shield the signal influence between the anode 4211 and the scanning circuit 210.

[0073] This invention also provides a display device, including the display panel in any of the above embodiments, and thus possesses the corresponding functional structure and beneficial effects of the display panel, which will not be elaborated further here. The display device can be a mobile phone, or any electronic product with display functionality, including but not limited to the following categories: televisions, laptops, desktop monitors, tablets, digital cameras, smart bracelets, smart glasses, in-vehicle displays, medical devices, industrial control equipment, touch interactive terminals, etc. This invention does not impose any special limitations on these categories.

[0074] Figure 11 This is a schematic diagram of the structure of a display device provided in an embodiment of the present invention. Figure 12 yes Figure 11 A magnified view of the M2 region. Combined with... Figure 11 and Figure 12 Optionally, in another embodiment, the arrangement of the first data connection line F and the second data connection line G can satisfy the second condition. The second condition is that the arrangement order of each first data connection line F and the second data connection line G is consistent with the arrangement order of each first data line D and the second data line E connected to them in the second display area AA2.

[0075] For example, when the first display area AA1 is located on both sides of the second display area AA2, and each column of first sub-pixels is respectively disposed in the first display areas AA1 on both sides, the first sub-pixels from column 1 to column c are arranged sequentially in the first display area AA1 on one side of the second display area AA2, the second sub-pixels from column 1 to column b are arranged sequentially in the second display area AA2, and the first sub-pixels from column c+1 to column a are arranged sequentially in the first display area AA1 on the other side of the second display area AA2. The arrangement order of each first data line D and second data line E in the second display area AA2 is consistent with the arrangement order of each first pixel circuit and second pixel circuit connected to it in the second display area AA2. Therefore, the arrangement order of each first data connection line F and second data connection line G is also consistent with the arrangement order of each first pixel circuit and second pixel circuit connected to each first data line D and second data line E in the second display area AA2. The advantage of this arrangement is that it simplifies the connection method of the first data line D and the corresponding first data connection line F, thereby simplifying the wiring layout in the non-display area NAA.

[0076] Combination Figure 11 and Figure 12 Furthermore, when the arrangement of the first data connection line F and the second data connection line G meets the second condition, the bonding connection part P can be configured to include a first bonding connection part P1 corresponding to a first data connection line F and a second bonding connection part P2 corresponding to b second data connection lines G. The arrangement order of each first bonding connection part P1 and the second bonding connection part P2 is consistent with the arrangement order of each first data connection line F and the second data connection line G to which they are connected. The display device also includes a flexible connector 510, which includes a first line corresponding to a first bonding connection part P1 and b second lines corresponding to b second bonding connection parts P2; the j-th first line connects to the j-th first bonding connection part P1, and the k-th second line connects to the k-th second bonding connection part P2. The arrangement order of line a and line b on the flexible connector 510 is consistent with the arrangement order of the corresponding first sub-pixel 110 in column a and second sub-pixel 120 in the second display area AA2.

[0077] Specifically, the flexible connector 510 can be a flexible printed circuit (FPC). In this embodiment, the display device can be a display device employing chip-on-film (COF) packaging technology, for example, a driver chip in the display device (…). Figure 11(Not shown) can be disposed on the flexible connector 510 to bond with the display panel through the flexible connector 510, and to provide data voltage to the first bonding connection part P1 through the first line in the flexible connector 510, and to provide data voltage to the second bonding connection part P2 through the second line in the flexible connector 510.

[0078] The arrangement order of each first data line D and second data line E in the second display area AA2 is consistent with the arrangement order of each first pixel circuit and second pixel circuit connected to it in the second display area AA2. Similarly, the arrangement order of each first data connection line F and second data connection line G is consistent with the arrangement order of each first data line D and second data line E connected to it in the second display area AA2. Furthermore, the arrangement order of each first bonding connection P1 and second bonding connection P2 is consistent with the arrangement order of each first data connection line F and second data connection line G connected to it. Based on this, the arrangement order of a first line and b second line on the flexible connector 510 is consistent with the arrangement order of their corresponding a column of first sub-pixels and b column of second sub-pixels in the second display area AA2.

[0079] The first bonding connection P1 can be connected to the first pixel circuit in sequence through the first trace H, the first data connection line F, and the first data line D. The second bonding connection P2 can be connected to the second pixel circuit in sequence through the first trace H, the second data connection line G, and the second data line E. Then, the first sub-pixel corresponding to each first line can be the first sub-pixel corresponding to the first pixel circuit connected to the first bonding connection P1 connected to that first line. The second sub-pixel corresponding to each second line can be the second sub-pixel corresponding to the second pixel circuit connected to the second bonding connection P2 connected to that second line. By setting the arrangement order of the first line (a) and the second line (b) on the flexible connector 510 to be consistent with the arrangement order of the corresponding first sub-pixels (a) and second sub-pixels (b) in the second display area AA2, it is convenient to supply data voltage to each first line and second line in each flexible connector 510 according to the arrangement order of each first sub-pixel and second sub-pixel. This allows data voltage to be transmitted to the first pixel circuit through the first line, the first bonding connection part P1, the first trace H, the first data connection line F, and the first data line D, and to the second pixel circuit through the second line, the second bonding connection part P2, the first trace H, the second data connection line G, and the second data line E. The data voltage is driven one by one according to the arrangement order of each first sub-pixel and second sub-pixel, which helps to simplify the pixel driving method of the display panel.

[0080] Figure 13 This is a schematic diagram of another display device provided in an embodiment of the present invention. Figure 11 and Figure 13The structure of region M2 can be the same. (Combined) Figure 12 and Figure 13 In another embodiment, the display device further includes a driver chip 520, which includes a first data voltage terminals corresponding to a first bonding connection portions P1 and b second data voltage terminals corresponding to b second bonding connection portions P2. The j-th first data voltage terminal is connected to the j-th first bonding connection portion P1, and the k-th second data voltage terminal is connected to the k-th second bonding connection portion P2. The arrangement order of the a first data voltage terminals and the b second data voltage terminals on the driver chip 520 is consistent with the arrangement order of their corresponding a column of first sub-pixels 110 and b column of second sub-pixels 120 in the second display area AA2.

[0081] Specifically, the display device in this embodiment can be a display device that uses a packaging technology that places the driver chip 520 on the display panel (Chip On Glass, COG). For example, the driver chip 520 is directly placed in the non-display area NAA of the display panel, and is bonded to the first bonding connection part P1 through the first data voltage terminal, and to the second bonding connection part P2 through the second data voltage terminal.

[0082] The first sub-pixel corresponding to each first data voltage terminal can be the first sub-pixel corresponding to the first pixel circuit connected to the first bonding connection P1 connected to the first data voltage terminal, and the second sub-pixel corresponding to each second data voltage terminal can be the second sub-pixel corresponding to the second pixel circuit connected to the second bonding connection P2 connected to the second data voltage terminal. By setting the arrangement order of the a first data voltage terminals and b second data voltage terminals on the driver chip 520 to be consistent with the arrangement order of the corresponding a column first sub-pixel 110 and b column second sub-pixel 120 in the second display area AA2, the driver chip 520 can output data voltage through the corresponding first data voltage terminals and second data voltage terminals according to the arrangement order of each first sub-pixel and second sub-pixel. This allows the driver chip 520 to transmit data voltage to the first pixel circuit through the first data voltage terminal, the first bonding connection part P1, the first trace H, the first data connection line F, and the first data line D, and to transmit data voltage to the second pixel circuit through the second data voltage terminal, the second bonding connection part P2, the first trace H, the second data connection line G, and the second data line E. By driving each first sub-pixel and second sub-pixel one by one according to their arrangement order, the driver chip 520 can simplify the pixel driving method of the display panel.

[0083] In other embodiments, the arrangement order of each first data voltage terminal and the second data voltage terminal on the driver chip 520 can be set to be consistent with the arrangement order of each first bonding connection P1 and the second bonding connection P2 to which they are connected. This allows each first data voltage terminal and the second data voltage terminal to be connected to each first bonding connection P1 and the second bonding connection P2 in sequence, thereby simplifying the connection method between the driver chip 520 and the display panel. Based on this, the driver chip 520 can be configured to: output the data voltage of the first sub-pixel corresponding to the first pixel circuit to which it is connected through each first data voltage terminal, and control each second data voltage terminal to output the data voltage of the second sub-pixel corresponding to the second pixel circuit to which it is connected. This simplifies the connection method between the driver chip 520 and the display panel while ensuring that the first pixel circuit corresponding to each first sub-pixel and the second pixel circuit corresponding to each second sub-pixel receive the correct data voltage, thereby driving each first sub-pixel and the second sub-pixel to emit light.

[0084] It should be understood that the various forms of processes shown above can be used, with steps reordered, added, or deleted. For example, the steps described in this invention can be executed in parallel, sequentially, or in different orders, as long as the desired result of the technical solution of this invention can be achieved, and this is not limited herein.

[0085] The specific embodiments described above do not constitute a limitation on the scope of protection of this invention. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this invention should be included within the scope of protection of this invention.

Claims

1. A display panel, characterized by, The display panel has a first display area and a second display area, and comprises: a first sub-pixel and a second sub-pixel, the first sub-pixel being located in the first display area, and the second sub-pixel being located in the second display area; a scanning circuit located in the first display area; a first pixel circuit and a second pixel circuit located in the second display area, the first pixel circuit being used for driving a corresponding first sub-pixel, and the second pixel circuit being used for driving a corresponding second sub-pixel, and an arrangement sequence of each first pixel circuit in the second display area being consistent with an arrangement sequence of the first sub-pixel corresponding to each first pixel circuit in the first display area.

2. The display panel of claim 1, wherein, m second sub-pixels constitute a sub-pixel unit, and a second pixel circuit corresponding to the m second sub-pixels in at least part of the sub-pixel units and a first pixel circuit constitute a pixel driving unit, the first pixel circuit corresponding to each first sub-pixel is located in a different pixel driving unit, and m≥1.

3. The display panel of claim 2, wherein, The first sub-pixel and the second sub-pixel are arranged in the same row, and the first sub-pixel and the second sub-pixel are arranged in an array, the m second sub-pixels in the sub-pixel unit are located in the same row, the first pixel circuit corresponding to the i-th first sub-pixel in each row is located in the pixel driving unit corresponding to the i-th sub-pixel unit in the row, i≤n, n is the total number of the first sub-pixels in each row, and n≥1.

4. The display panel of claim 2, wherein, The first pixel circuit is located between two adjacent second pixel circuits.

5. The display panel of claim 1, wherein, The display panel further comprises a first data line corresponding to each column of first sub-pixels and a second data line corresponding to each column of second sub-pixels, and the first data line and the second data line are located in the second display area; The jth first data line is connected to the first pixel circuit corresponding to the jth column of first sub-pixels, and is used for transmitting a data voltage to the first pixel circuit corresponding to the jth column of first sub-pixels; the kth second data line is connected to the second pixel circuit corresponding to the kth column of second sub-pixels, and is used for transmitting a data voltage to the second pixel circuit corresponding to the kth column of second sub-pixels; and an arrangement sequence of each first data line and second data line in the second display area is consistent with an arrangement sequence of each first pixel circuit and second pixel circuit in the second display area; wherein, j≤a, a is the total number of columns of first sub-pixels, and a≥1; k≤b, b is the total number of columns of second sub-pixels, and b≥1.

6. The display panel of claim 5, wherein, The display panel has a non-display area, and further comprises a first data connection line corresponding to each of the a first data lines, a second data connection line corresponding to each of the b second data lines, and a plurality of bonding connection portions, and the first data connection line, the second data connection line and the bonding connection portion are located in the non-display area. The first data connection line is connected between the first data line and the corresponding bonding connection part, and the second data connection line is connected between the second data line and the corresponding bonding connection part; The arrangement mode of the first data connection line and the second data connection line satisfies a first condition or a second condition; the first condition is that the arrangement order of a first data connection line and a second data connection line is consistent with the arrangement order of a first sub-pixel and a second sub-pixel in the second display area; and the second condition is that the arrangement order of each first data connection line and each second data connection line is consistent with the arrangement order of each first data line and each second data line in the second display area.

7. The display panel of claim 6, wherein, The non-display area includes a first non-display area and a second non-display area, and the first non-display area and the second non-display area are arranged in sequence on one side of the second display area along the extension direction of the first data line or the second data line; and the first non-display area is a fan-out area. The first data connection line and the second data connection line are located in the first non-display area, or the first data connection line and the second data connection line are located in the second non-display area.

8. The display panel of any one of claims 1-7, wherein, The display panel includes a substrate and an anode layer, the anode layer is provided with anodes of the first sub-pixels and the second sub-pixels, the scanning circuit, the first pixel circuit and the second pixel circuit are located between the substrate and the anode layer, the first pixel circuit is connected to the anode of the corresponding first sub-pixel, and the second pixel circuit is connected to the anode of the corresponding second sub-pixel. The vertical projection of each scanning circuit on the substrate and the vertical projection of the anode of each first sub-pixel on the substrate are located in the same region of the first display area.

9. The display panel of claim 8, wherein, The vertical projection of the first pixel circuit and the second pixel circuit in each pixel driving unit on the substrate and the vertical projection of the anodes of the m second sub-pixels corresponding to the pixel driving unit on the substrate are located in the same region of the second display area.

10. The display panel of claim 8, wherein, The display panel further includes a shielding electrode located between the anode layer and the scanning circuit, for shielding the signal influence between the anode and the scanning circuit.

11. A display device comprising: The display panel includes the display panel of any one of claims 1-10.

12. The display device of claim 11, wherein, The arrangement mode of the first data connection line and the second data connection line satisfies the second condition; the bonding connection part includes a first bonding connection part corresponding to each first data connection line and a second bonding connection part corresponding to each second data connection line; and the arrangement order of each first bonding connection part and each second bonding connection part is consistent with the arrangement order of each first data connection line and each second data connection line connected thereto. The display device further comprises a flexible connecting member, the flexible connecting member comprises a first line corresponding to each of the a first bonding connection and a second line corresponding to each of the b second bonding connection; the jth first line is connected to the jth first bonding connection, and the kth second line is connected to the kth second bonding connection; the arrangement order of the a first lines and the b second lines on the flexible connecting member is consistent with the arrangement order of the a columns of the first sub-pixels and the b columns of the second sub-pixels in the second display area; or, The display device further comprises a driving chip, the driving chip comprises a first data voltage terminal corresponding to each of the a first bonding connection and a second data voltage terminal corresponding to each of the b second bonding connection; the jth first data voltage terminal is connected to the jth first bonding connection, and the kth second data voltage terminal is connected to the kth second bonding connection; the arrangement order of the a first data voltage terminals and the b second data voltage terminals on the driving chip is consistent with the arrangement order of the a columns of the first sub-pixels and the b columns of the second sub-pixels in the second display area; Or, the arrangement order of the a first data voltage terminals and the b second data voltage terminals on the driving chip is consistent with the arrangement order of the first bonding connection and the second bonding connection connected thereto, and the driving chip is configured to output the data voltage of the first sub-pixel corresponding to the first pixel circuit connected thereto through the first data voltage terminal, and output the data voltage of the second sub-pixel corresponding to the second pixel circuit connected thereto through the second data voltage terminal.

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