Anisotropic display substrate and display device

Abstract

The application provides a special-shaped display substrate and a display device, and relates to the technical field of display, and aims to solve the problems that when the layout of the gate driving circuit of a special-shaped display product is performed, all the gate driving circuits are manually placed and adjusted step by step, time consumption is long, the efficiency is low, and the production progress and capacity are not conducive. The special-shaped layout area of the special-shaped display substrate comprises a plurality of gate driving circuits, the plurality of gate driving circuits comprise at least two Nth gate driving circuits located in an Nth area and at least two (N+1)th gate driving circuits located in an (N+1)th area, the connection line between the target parts of the at least two Nth gate driving circuits and the first direction have a first included angle, and the distance a is staggered between the two adjacent Nth gate driving circuits along the second direction; the connection line between the target parts of the at least two (N+1)th gate driving circuits and the first direction have a second included angle, and the distance b is staggered between the two adjacent (N+1)th gate driving circuits along the second direction.

Description

Technical Field

[0001] This invention relates to the field of display technology, and more particularly to a non-circular display substrate and a display device. Background Technology

[0002] With the continuous development of display technology, GOA (Gate on Array) technology has been widely used. This GOA technology integrates the gate driving circuit on the substrate of the display product, so that the display product can achieve a narrow bezel design.

[0003] Display products generally include rectangular display products. When laying out the bezels of such display products, four gate drive circuit units are usually designed first, and then these four gate drive circuits are arrayed to obtain an entire row of gate drive circuits located in the bezel area.

[0004] For irregularly shaped display products, because the left and right boundaries of the bezel area used to lay out the gate drive circuits are irregular, it is impossible to use software to array the gate drive circuits. The gate drive circuits must be placed manually, level by level, and the traces on both sides must be adjusted. This method is still applicable to low-resolution irregularly shaped display products, but for high-resolution display products, manually placing and adjusting all the gate drive circuits level by level is time-consuming, inefficient, and detrimental to production schedules and capacity. Summary of the Invention

[0005] The purpose of this invention is to provide a non-standard display substrate and display device to solve the problem that when laying out the gate drive circuits of non-standard display products, manually placing and adjusting all the gate drive circuits step by step is time-consuming, inefficient, and detrimental to production progress and capacity.

[0006] To achieve the above objectives, the present invention provides the following technical solution:

[0007] A first aspect of the present invention provides an irregularly shaped display substrate, comprising: a display area and a non-display area surrounding the display area; the non-display area includes an irregularly shaped layout area, the irregularly shaped layout area includes a multi-level gate driving circuit arranged in sequence, and the irregularly shaped layout area further includes an Nth region and an N+1th region arranged in sequence, where N is greater than or equal to 1;

[0008] The multi-level gate driving circuit includes at least two Nth gate driving circuits located in the Nth region and arranged sequentially. The line connecting the target portions of the at least two Nth gate driving circuits has a first angle with the first direction. Adjacent Nth gate driving circuits are staggered by a distance a along the second direction. The second direction intersects the first direction.

[0009] The multi-level gate driving circuit further includes at least two N+1 gate driving circuits located in the N+1 region and arranged sequentially. The line connecting the target portions of the at least two N+1 gate driving circuits has a second angle with the first direction. The second angle is different from the first angle. Adjacent N+1 gate driving circuits are offset by a distance b along the second direction, and a and b are not equal.

[0010] Optionally, the irregular layout region further includes a connection region, at least a portion of which is located between the Nth region and the N+1th region, and the connection region includes at least one connection gate driving circuit.

[0011] The connection gate driving circuit and the adjacent Nth gate driving circuit are offset by a distance c along the second direction, where c may be equal to or different from a.

[0012] And / or,

[0013] The connection gate driving circuit and the adjacent (N+1)th gate driving circuit are offset by a distance d along the second direction, where d is equal to or not equal to b.

[0014] Optionally, the distance a is proportional to the first included angle, and the distance b is proportional to the second included angle.

[0015] Optionally, the Nth gate driving circuit includes an Nth output transistor, and in two adjacent Nth gate driving circuits, the gates of the Nth output transistor are offset by a distance a along the second direction;

[0016] The (N+1)th gate driving circuit includes an (N+1)th output transistor. In two adjacent (N+1)th gate driving circuits, the gates of the (N+1)th output transistor are offset by a distance b along the second direction.

[0017] Optionally, the display area includes a circular display area, the irregular layout area includes an arc-shaped layout area, and the display area is provided with arc-shaped layout areas on both sides opposite to each other along the second direction. The arc-shaped layout area includes the Nth region, the connecting region, and the N+1th region.

[0018] Optionally, the arc-shaped layout area includes a first region to the (N+X)th region, where X is greater than or equal to 2;

[0019] The arc-shaped layout area is divided into three regions: the first region includes the first region to the Mth region; the second region includes the M+1th region to the M+Cth region; and the third region includes the M+C+1th region to the N+Xth region, where 1≤M<N+X, M+1≤M+C<N+X, and M+C+1≤N+X.

[0020] In the first region, the angle between the connection between the target portions of the gate drive circuit in each region and the first direction is between 60° and 80°.

[0021] In the second region, the connection between the target portions of the gate drive circuit in each region has an angle between 10° and 25° with the first direction;

[0022] In the third region, the connection between the target portions of the gate drive circuit in each region has an angle between 60° and 80° with the first direction.

[0023] Optionally, in the first portion region, from the first region to the Mth region, the distance between the gate drive circuits in each region along the second direction gradually decreases;

[0024] In the third region, from the M+C+1 region to the N+X region, the distance between the gate drive circuits in each region along the second direction gradually increases.

[0025] Optionally, in the first portion region, the distance between the gate drive circuits in each region along the second direction is between 150 micrometers and 300 micrometers.

[0026] In the second region, the distance between the gate drive circuits in each region along the second direction is between 30 micrometers and 60 micrometers;

[0027] In the third region, the distance between the gate drive circuits in each region and the distance along the second direction is between 150 micrometers and 300 micrometers.

[0028] Optionally, the arc-shaped layout area includes: Y clock signal lines and the multi-stage gate driving circuit; each stage of the gate driving circuit includes a gate driving signal output terminal, a clock signal input terminal, an input signal terminal and a reset terminal;

[0029] The clock signal input terminal of the Y×(B-1)+F level gate drive circuit is coupled to the Fth clock signal line, where Y is an integer greater than or equal to 2, F is a positive integer less than or equal to Y, and B is an integer greater than or equal to 1.

[0030] Optionally, in the multi-stage gate drive circuit: the gate drive signal output terminal of the A-th stage gate drive circuit is coupled to the input signal terminal of the A+E-th stage gate drive circuit and the reset terminal of the AE-th stage gate drive circuit, respectively, where A is an integer greater than or equal to 3 and E is a positive integer less than A.

[0031] The multi-stage gate driving circuit is divided into multiple groups of gate driving circuits arranged in sequence, each group of gate driving circuits including at least two adjacent gate driving circuits; the Nth region includes at least one group of gate driving circuits, which includes the Nth gate driving circuit; the N+1th region includes at least one group of gate driving circuits, which includes the N+1th gate driving circuit.

[0032] Optionally, the Nth region includes multiple Nth sub-regions, and each Nth sub-region includes a corresponding Nth gate drive circuit and signal line; the layout structure of the Nth sub-region where the Nth gate drive circuit connected to the same clock signal line is located is completely identical;

[0033] The N+1th region includes multiple N+1th sub-regions, and each N+1th sub-region includes a corresponding N+1th gate drive circuit and signal line; the layout structure of the N+1th sub-region where the N+1th gate drive circuit connected to the same clock signal line is completely identical.

[0034] Optionally, the layout of the different clock signal lines may differ in each of the Nth sub-regions where the Nth gate drive circuit connecting different clock signal lines is located;

[0035] In each of the N+1 sub-regions where the gate drive circuits connecting different clock signal lines are located, the layout of the different clock signal lines is different.

[0036] Optionally, the layout structure of the gate driving circuits at each stage is exactly the same, but the layout of the signal lines in the Nth sub-region and the N+1 sub-region is not exactly the same.

[0037] Optionally, the Nth gate driving circuit, the connection region, and the (N+1)th gate driving circuit each include:

[0038] The input sub-circuit is used to input carry signals to the pull-up node;

[0039] The output sub-circuit is used to input a clock signal to the drive signal output terminal;

[0040] The first pull-up node reset sub-circuit is used to input a first reset signal to the pull-up node;

[0041] The second pull-up node reset sub-circuit is used to input a second reset signal to the pull-up node;

[0042] The pull-down node reset sub-circuit is used to input the second reset signal to the pull-down node;

[0043] An output reset sub-circuit is used to input the second reset signal to the drive signal output terminal;

[0044] The storage sub-circuit is coupled to the pull-up node and the drive signal output terminal, respectively.

[0045] Based on the above-described irregularly shaped display substrate, a second aspect of the present invention provides a display device including the aforementioned irregularly shaped display substrate.

[0046] In the technical solution provided by the present invention, by setting the connection between the target portions of the at least two Nth gate driving circuits in the Nth region to have a first angle with the first direction, and setting the adjacent two Nth gate driving circuits to be offset by a distance a along the second direction; and setting the connection between the target portions of the at least two N+1th gate driving circuits in the N+1 region to have a second angle with the first direction, the second angle being different from the first angle, and the adjacent two N+1th gate driving circuits to be offset by a distance b along the second direction, where a and b are not equal; the layout structure in the Nth region and the N+1 region can be well matched with the shape of the irregular layout region.

[0047] Furthermore, in the technical solution provided by this invention, the Nth region includes at least two Nth gate driving circuits, the connection between the target portions of the at least two Nth gate driving circuits has a first angle with the first direction, and adjacent Nth gate driving circuits are staggered by a distance 'a' along the second direction; this ensures that each Nth gate driving circuit has the same layout, and at least some of the signal lines around each Nth gate driving circuit have the same layout. Thus, when laying out the Nth region, the same at least two Nth gate driving circuits can be directly copied in the Nth region, and only the signal lines with different layouts around each Nth gate driving circuit need to be adjusted.

[0048] In the technical solution provided by this invention, the N+1 region includes at least two N+1 gate driving circuits. The connection between the target portions of the at least two N+1 gate driving circuits forms a second angle with a first direction, and adjacent N+1 gate driving circuits are staggered by a distance b along the second direction. This ensures that each N+1 gate driving circuit has the same layout, and at least a portion of the signal lines surrounding each N+1 gate driving circuit have the same layout. Therefore, when laying out the N+1 region, the same at least two N+1 gate driving circuits can be directly copied within the N+1 region, and only the signal lines with different layouts around each N+1 gate driving circuit need to be adjusted.

[0049] Therefore, in the technical solution provided by the present invention, when laying out the gate driving circuit in the irregular layout area, the layout is carried out by dividing the area, eliminating the need for step-by-step placement and adjustment of a large number of signal lines, which effectively improves the layout efficiency of the gate driving circuit, reduces the layout time, and improves the production progress and capacity. Attached Figure Description

[0050] The accompanying drawings, which are included to provide a further understanding of the invention and form part of this invention, illustrate exemplary embodiments of the invention and are used to explain the invention, but do not constitute an undue limitation of the invention. In the drawings:

[0051] Figure 1 This is a schematic diagram of the structure of the irregularly shaped display substrate provided in an embodiment of the present invention;

[0052] Figure 2 A schematic diagram of the first layout of the Nth region and the N+1th region provided in an embodiment of the present invention;

[0053] Figure 3 A schematic diagram of the second layout of the Nth and N+1th regions provided in an embodiment of the present invention;

[0054] Figure 4 A schematic diagram of the layout of the gate driving circuit and its surrounding signals provided in an embodiment of the present invention;

[0055] Figure 5 A schematic diagram of the cascaded multi-stage gate drive circuit provided in an embodiment of the present invention;

[0056] Figure 6 A schematic diagram of the layout of the first clock signal line coupled to the gate drive circuit in the Nth region provided in an embodiment of the present invention;

[0057] Figure 7 A schematic diagram of the layout of the second clock signal line coupled to the gate drive circuit in the Nth region provided in an embodiment of the present invention;

[0058] Figure 8 A schematic diagram of the layout of the third clock signal line coupled to the gate drive circuit in the Nth region provided in an embodiment of the present invention;

[0059] Figure 9 A schematic diagram of the layout of the fourth clock signal line coupled to the gate drive circuit in the Nth region provided in an embodiment of the present invention;

[0060] Figure 10 This is a schematic diagram of the layout of the first clock signal line coupled to the gate drive circuit in the N+1 region provided in an embodiment of the present invention.

[0061] Figure 11This is a schematic diagram of the layout of the second clock signal line coupled to the gate drive circuit in the N+1 region provided in an embodiment of the present invention.

[0062] Figure 12 This is a schematic diagram of the layout of the third clock signal line coupled to the gate drive circuit in the N+1 region provided in an embodiment of the present invention;

[0063] Figure 13 This is a schematic diagram of the layout of the fourth clock signal line coupled to the gate drive circuit in the N+1 region provided in an embodiment of the present invention.

[0064] Figure 14 A circuit diagram of the gate drive circuit of the 4T1C structure provided in an embodiment of the present invention;

[0065] Figure 15 The timing diagram of the gate drive circuit of the 4T1C structure provided in the embodiment of the present invention;

[0066] Figure 16 A schematic diagram of the operation of the gate drive circuit of the 4T1C structure provided in the embodiment of the present invention during the input period;

[0067] Figure 17 A schematic diagram of the operation of the gate drive circuit of the 4T1C structure provided in the embodiment of the present invention during the output period;

[0068] Figure 18 A schematic diagram of the operation of the gate drive circuit of the 4T1C structure provided in the embodiment of the present invention during the reset period;

[0069] Figure 19 The circuit diagram of the gate drive circuit of the 11T1C structure provided in the embodiment of the present invention. Detailed Implementation

[0070] To further illustrate the irregularly shaped display substrate and display device provided in the embodiments of the present invention, a detailed description is provided below with reference to the accompanying drawings.

[0071] Please see Figures 1 to 4 This invention provides an irregularly shaped display substrate, including: a display area 10 and a non-display area surrounding the display area 10. The non-display area includes an irregularly shaped layout area 21, which includes a multi-level gate driving circuit arranged in sequence. The irregularly shaped layout area 21 also includes an Nth region 30 and an N+1th region 40 arranged in sequence, where N is greater than or equal to 1.

[0072] The multi-level gate driving circuit includes at least two Nth gate driving circuits located in the Nth region 30 and arranged sequentially. The line connecting the target portions of the at least two Nth gate driving circuits has a first angle θ1 with the first direction. Adjacent Nth gate driving circuits are staggered by a distance a along the second direction. The second direction intersects the first direction.

[0073] The multi-level gate driving circuit further includes at least two N+1 gate driving circuits located in the N+1 region 40 and arranged sequentially. The line connecting the target portions of the at least two N+1 gate driving circuits has a second angle θ2 with the first direction. The second angle is different from the first angle. The two adjacent N+1 gate driving circuits are offset by a distance b along the second direction. a and b are not equal.

[0074] For example, the irregular layout area 21 located on one side of the display area 10 includes N+X regions. In the same region, among the at least two gate driving circuits arranged in sequence, the line connecting the target portions of the two gate driving circuits located at both ends has a certain angle with the first direction.

[0075] For example, a region includes eight gate driving circuits arranged sequentially. The line connecting the target portion of the first gate driving circuit and the target portion of the eighth gate driving circuit forms an angle with a first direction. Notably, the target portions of the second to seventh gate driving circuits are all located on this line.

[0076] For example, the target portion can be a specific location within a particular structure. For instance, the center portion of the gate of each output transistor (i.e., the third transistor M3 mentioned later). Since the gate area of ​​the output transistor is relatively large, it is easy to identify and measure using the gate of the output transistor as a reference, thus reducing testing errors.

[0077] It needs to be explained that, Figure 1 The diagram also illustrates the driver chip IC, the flexible circuit board FPC, and the fan-out area 22. Figure 3 In this context, 301-CLK1 represents the gate drive circuit in the Nth sub-region being coupled to the first clock signal line. Figure 3 In this context, 301-CLK2 represents the gate drive circuit in the Nth sub-region being coupled to the second clock signal line. Figure 3 In this context, 301-CLK3 represents the gate drive circuit in the Nth sub-region being coupled to the third clock signal line. Figure 3 In this context, 301-CLK4 represents the gate drive circuit in the Nth sub-region being coupled to the fourth clock signal line. Figure 3In this context, 401-CLK1 represents the gate drive circuit in the N+1th sub-region being coupled to the first clock signal line. Figure 3 In this context, 401-CLK2 represents the gate drive circuit in the N+1th sub-region being coupled to the second clock signal line. Figure 3 In this context, 401-CLK3 represents the gate drive circuit in the N+1th sub-region being coupled to the third clock signal line. Figure 3 In this context, 401-CLK4 represents the gate drive circuit in the N+1th sub-region being coupled to the fourth clock signal line. Figure 3 50-CLK2 in the diagram represents the gate drive circuit in the connection area being coupled to the second clock signal line.

[0078] For example, the multi-stage gate drive circuits are cascaded, and each stage of the gate drive circuit is used to provide a gate drive signal for the corresponding scan line.

[0079] For example, the irregular layout area 21 includes a region with a certain curvature at its boundary.

[0080] For example, the Nth gate driving circuit and the N+1th gate driving circuit include the same circuit structure, such as both including 4T1C (4 transistors and 1 capacitor), 8T1C (8 transistors and 1 capacitor), 10T1C (10 transistors and 1 capacitor), 11T1C (11 transistors and 1 capacitor), 17T1C (17 transistors and 1 capacitor) or 21T1C (21 transistors and 1 capacitor) models.

[0081] For example, the circuit structure layout in the Nth gate driving circuit and the N+1th gate driving circuit is the same, but the signal line layout in the Nth gate driving circuit and the N+1th gate driving circuit is not exactly the same.

[0082] It should be noted that having the same layout for two gate drive circuits means that the dimensions and shapes of all components in the two gate drive circuits are the same, and the relative positions of the components are the same. Similarly, having the same layout for the signal lines surrounding the two gate drive circuits means that the dimensions and shapes of the signal lines are the same, and the position of the signal lines relative to the gate drive circuits is the same.

[0083] The fact that the signal line layouts in the Nth gate driving circuit and the (N+1)th gate driving circuit are not completely the same means that the layouts of some signal lines in the Nth gate driving circuit and the (N+1)th gate driving circuit are different (such as clock signal lines), while the layouts of other signal lines are the same (such as other signal lines besides clock signal lines).

[0084] For example, taking the gate drive circuit including an 11T1C structure as an example, in the Nth sub-region 301 and the N+1th sub-region 401, the signal lines include: a first frame start signal line for inputting a first frame start signal STV1; a second frame start signal line for inputting a second frame start signal STV2; an input control signal line for inputting an input control signal Input; a carry signal line for inputting a carry signal VDS; a first pull-down control line for inputting a first pull-down control signal GCH; a clock signal line for inputting a clock signal CLK; a first reset control line for inputting a first reset control signal Reset; a second reset control line for inputting a second reset control signal STV0; a third reset control line for inputting a third reset control signal GCL; a first reset signal line for inputting a first reset signal VSD; and a second reset signal line for inputting a second reset signal VGL.

[0085] For example, the target portion of the Nth gate driving circuit and the target portion of the (N+1)th gate driving circuit are the same reference portion. For example, they are both portions included in a transistor with a specific function, or they are both portions included in a capacitor.

[0086] For example, two adjacent Nth gate drive circuits are offset by a distance a along a second direction, and the target portions of the at least two Nth gate drive circuits can be connected to form a straight line, which has a first angle with the first direction.

[0087] For example, two adjacent N+1th gate drive circuits are offset by a distance b along a second direction, and the target portions of the at least two N+1th gate drive circuits can be connected to form a straight line, which has a second angle with the first direction.

[0088] For example, the display area of ​​the irregularly shaped display substrate includes data lines and gate lines, the data lines including at least a portion extending along the first direction, and the gate lines including at least a portion extending along the second direction. For example, the first direction is perpendicular to the second direction.

[0089] According to the specific structure of the irregular display substrate described above, in the irregular display substrate provided in this embodiment of the invention, the irregular layout area 21 includes an Nth region 30 and an N+1th region 40 arranged sequentially. Adjacent Nth gate driving circuits in the Nth region 30 are offset by a distance a along a second direction; the connecting line between the target portions of each Nth gate driving circuit has a first angle with the first direction; adjacent N+1th gate driving circuits in the N+1th region 40 are offset by a distance b along the second direction; the connecting line between the target portions of each N+1th gate driving circuit has a second angle with the first direction.

[0090] In the irregular display substrate provided in this embodiment of the invention, by setting the connection between the target portions of the at least two Nth gate driving circuits in the Nth region 30 to have a first angle with the first direction, and setting the adjacent two Nth gate driving circuits to be offset by a distance a along the second direction; and setting the connection between the target portions of the at least two N+1th gate driving circuits in the N+1th region 40 to have a second angle with the first direction, the second angle being different from the first angle, and setting the adjacent two N+1th gate driving circuits to be offset by a distance b along the second direction, where a and b are not equal; the layout structure in the Nth region 30 and the N+1th region 40 can be well matched with the shape of the irregular layout area 21.

[0091] Furthermore, in the irregularly shaped display substrate provided in this embodiment of the invention, by setting the Nth region 30 to include at least two Nth gate driving circuits, the connection between the target portions of the at least two Nth gate driving circuits has a first angle with the first direction, and adjacent Nth gate driving circuits are staggered by a distance 'a' along the second direction; this makes the layout of each Nth gate driving circuit the same, and the layout of at least a portion of the signal lines around each Nth gate driving circuit the same. Thus, when laying out the Nth region 30, the same at least two Nth gate driving circuits can be directly copied in the Nth region 30, and only the signal lines with different layouts around each Nth gate driving circuit need to be adjusted.

[0092] More specifically, taking the irregularly shaped layout area 21 located on one side of the display area 10, which includes Y clock signal lines, as an example. In a region (such as the Nth region), Y gate driving circuits are grouped together, and this region includes k groups. The Y gate driving circuits in a group are coupled one-to-one with the Y clock signal lines. In this region, the layout of each group of gate driving circuits is the same and can be directly copied. During layout, it is only necessary to stagger the gate driving circuits between adjacent groups by a preset distance (a distance a in the Nth region). This can improve the efficiency of wiring the gate driving circuits.

[0093] For example, Y equals 4, and the first region includes eight gate driving circuits arranged in sequence. Among the eight gate driving circuits, the first gate driving circuit is connected to the first clock signal line, the second gate driving circuit is connected to the second clock signal line, the third gate driving circuit is connected to the third clock signal line, the fourth gate driving circuit is connected to the fourth clock signal line, the fifth gate driving circuit is connected to the first clock signal line, the sixth gate driving circuit is connected to the second clock signal line, the seventh gate driving circuit is connected to the third clock signal line, and the eighth gate driving circuit is connected to the fourth clock signal line.

[0094] In the eight gate driving circuits, the first and second gate driving circuits are offset by a distance 'a' along the second direction. After the first to fourth gate driving circuits are arranged, the fifth to eighth gate driving circuits can directly replicate the arrangement of the first to fourth gate driving circuits, with the fifth gate driving circuit offset by a distance 'a' relative to the fourth gate driving circuit. It is noteworthy that since both the fifth and first gate driving circuits are connected to the first clock signal line, the layout of the first clock signal line connected to the fifth and first gate driving circuits is the same. Similarly, the layout of the second clock signal line connected to the second and sixth gate driving circuits is the same. The layout of the third clock signal line connected to the third and seventh gate driving circuits is the same. The layout of the fourth clock signal line connected to the fourth and eighth gate driving circuits is the same. The layouts of the first to fourth clock signal lines are different, and the specific layout needs to be set individually according to the edge of the irregular layout area.

[0095] Similarly, in the irregular display substrate provided in this embodiment of the invention, by setting the N+1 region 40 to include at least two N+1 gate driving circuits, the connection between the target portions of the at least two N+1 gate driving circuits has a second angle with the first direction, and adjacent two N+1 gate driving circuits are staggered by a distance b along the second direction; this makes the layout of each N+1 gate driving circuit the same, and at least some of the signal lines around each N+1 gate driving circuit have the same layout. Thus, when laying out the N+1 region 40, the same at least two N+1 gate driving circuits can be directly copied in the N+1 region 40, and only the signal lines around each N+1 gate driving circuit with different layouts need to be adjusted.

[0096] Therefore, in the irregular display substrate provided in this embodiment of the invention, when laying out the gate driving circuit in the irregular layout area 21, the layout is carried out in a regional manner, eliminating the need for step-by-step placement and adjustment of a large number of signal lines, which effectively improves the layout efficiency of the gate driving circuit, reduces the layout time, and improves the production progress and capacity.

[0097] The irregularly shaped display substrate provided in this embodiment of the invention adopts a GOA design, which is beneficial for narrowing the bezel of the irregularly shaped display substrate.

[0098] In addition, when the irregularly shaped display substrate provided in the embodiments of the present invention is applied to a small-sized display device, since the signal lines in the small-sized display device are short, there is almost no probability of ESD (electrostatic discharge). Therefore, the irregularly shaped display substrate provided in the embodiments of the present invention can be designed without electrostatic rings, which can provide more layout space for the gate driving circuit and is conducive to better realizing the narrow bezel design.

[0099] like Figures 1 to 4 As shown, in some embodiments, the irregular layout region 21 further includes a connection region 50, at least a portion of which is located between the Nth region 30 and the N+1th region 40, and the connection region 50 includes at least one connection gate driving circuit.

[0100] The connection gate driving circuit and the adjacent Nth gate driving circuit are offset by a distance c along the second direction, where c may be equal to or different from a.

[0101] And / or,

[0102] The connection gate driving circuit and the adjacent (N+1)th gate driving circuit are offset by a distance d along the second direction, where d is equal to or not equal to b.

[0103] For example, the connection gate driving circuit has the same circuit structure as the Nth gate driving circuit and the N+1th gate driving circuit.

[0104] For example, the layout of the connecting gate driving circuit is the same as that of the Nth gate driving circuit and the N+1th gate driving circuit, but the layout of the signal lines in the connecting gate driving circuit is not exactly the same as that of the Nth gate driving circuit and the N+1th gate driving circuit.

[0105] For example, the connecting gate driving circuit is the same as the Nth gate driving circuit and the N+1th gate driving circuit, and can be coupled to the corresponding scan line in the display area to provide a gate driving signal for the coupled scan line.

[0106] For example, the gate drive circuit of the connection region is used to connect two adjacent regions. The two adjacent regions are arranged according to their respective slopes. The clock signal lines coupled to the gate drive circuit of the connection region can be laid out differently from the clock signal lines of the other regions it connects to, so as to adjust the appropriate trace layout position according to the layout of the adjacent regions.

[0107] In the irregular display substrate provided in the above embodiment, by setting the connection region 50 between the Nth region 30 and the N+1th region 40, and setting the connection gate driving circuit and the adjacent Nth gate driving circuit to be offset by a distance c along the second direction, and the connection gate driving circuit and the adjacent N+1th gate driving circuit to be offset by a distance d along the second direction, the connection gate driving circuit in the connection region 50 can play the role of adjusting the offset distance. This not only ensures the offset distance between the adjacent Nth gate driving circuit and the adjacent N+1th gate driving circuit, but also allows the layout position between the Nth gate driving circuit and the N+1th gate driving circuit to achieve a smoother transition through the connection gate driving circuit, and can better match the boundary of the irregular layout region 21.

[0108] like Figure 3 As shown, in some embodiments, the distance a is set to be proportional to the first included angle, and the distance b is set to be proportional to the second included angle.

[0109] The above configuration allows the layout of the Nth gate driving circuit and the (N+1)th gate driving circuit to better match the layout space of the irregular layout region 21, and the layout boundaries of the Nth gate driving circuit and the (N+1)th gate driving circuit to better match the boundary of the irregular layout region 21, thereby more effectively improving the utilization rate of the layout space of the irregular layout region 21.

[0110] In some embodiments, the Nth gate driving circuit includes an Nth output transistor, and in two adjacent Nth gate driving circuits, the gates of the Nth output transistor are offset by a distance a along a second direction;

[0111] The (N+1)th gate driving circuit includes an (N+1)th output transistor. In two adjacent (N+1)th gate driving circuits, the gates of the (N+1)th output transistor are offset by a distance b along the second direction.

[0112] For example, the Nth output transistor and the N+1th output transistor have the same structure and the same layout.

[0113] For example, with reference to the boundary of the display area away from the gate of the Nth output transistor, the offset distance between the gates of adjacent Nth output transistors along the second direction is calculated. For example, with reference to the boundary of the display area near the gate of the Nth output transistor, the offset distance between the gates of adjacent Nth output transistors along the second direction is calculated.

[0114] For example, with reference to the boundary of the display area away from the gate of the (N+1)th output transistor, the offset distance between the gates of adjacent (N+1)th output transistors along the second direction is calculated. For example, with reference to the boundary of the display area near the gate of the (N+1)th output transistor, the offset distance between the gates of adjacent (N+1)th output transistors along the second direction is calculated.

[0115] It should be noted that, in addition to the gates of adjacent Nth output transistors being offset by a distance 'a' along the second direction, in adjacent Nth gate drive circuits, identical other components are also offset by a distance 'a' along the second direction. Similarly, in addition to the gates of adjacent N+1th output transistors being offset by a distance 'b' along the second direction, in adjacent N+1th gate drive circuits, identical other components are also offset by a distance 'b' along the second direction.

[0116] like Figures 1 to 4 As shown, in some embodiments, the display area includes a circular display area, the irregular layout area 21 includes an arc-shaped layout area, and the display area is provided with arc-shaped layout areas on both sides opposite to each other along the second direction. The arc-shaped layout area includes the Nth region 30, the connecting region 50, and the N+1th region 40.

[0117] For example, two arc-shaped layout areas located on both sides of the display area are symmetrically arranged, and the axis of symmetry of the two arc-shaped layout areas passes through the center of the circular display area and extends along the first direction.

[0118] For example, each arc-shaped layout region includes the multi-stage gate drive circuit.

[0119] For example, in the irregularly shaped display substrate, scanning signals can be provided to the scan lines from opposite sides of the display area along the second direction.

[0120] For example, each scan line can simultaneously receive scan signals on both opposite sides of the display area along the second direction.

[0121] For example, odd-numbered scan lines can receive scan signals provided by the gate driving circuit on the left side of the display area along the second direction. Even-numbered scan lines can receive scan signals provided by the gate driving circuit on the right side of the display area along the second direction.

[0122] The above configuration method is also conducive to further improving the layout efficiency of the irregular layout area 21.

[0123] In some embodiments, the arc-shaped layout area includes a first region to the (N+X)th region, where X is greater than or equal to 2.

[0124] The arc-shaped layout area is divided into three regions: the first region includes the first region to the Mth region; the second region includes the M+1th region to the M+Cth region; and the third region includes the M+C+1th region to the N+Xth region, where 1≤M<N+X, M+1≤M+C<N+X, and M+C+1≤N+X.

[0125] In the first region, the connection between the target portions of the gate drive circuit in each region has an angle between 60° and 80° with the first direction, and may include endpoint values;

[0126] In the second region, the connection between the target portions of the gate drive circuit in each region has an angle between 10° and 25° with the first direction, and may include endpoint values;

[0127] In the third region, the connection between the target portions of the gate drive circuit in each region has an angle between 60° and 80° with the first direction, and may include endpoint values.

[0128] For example, the arc-shaped layout area includes a first region to a N+Xth region arranged sequentially along the arc-shaped extension direction. The arc-shaped layout area is divided into three parts, wherein the second part is located between the first part and the third part.

[0129] For example, in regions M through M, the angle between the line connecting the target portions of the gate driving circuits within each region and the first direction is between 60° and 80°. In regions M+1 through M+C, the angle between the line connecting the target portions of the gate driving circuits within each region and the first direction is between 10° and 25°. In regions M+C+1 through N+X, the angle between the line connecting the target portions of the gate driving circuits within each region and the first direction is between 60° and 80°.

[0130] For example, N+X equals 9, M equals 3, and M+C equals 6.

[0131] For example, in at least two of the regions from the first region to the N+Xth region, the gate drive circuits form the same angle with the first direction.

[0132] The above configuration allows the multi-stage gate drive circuit to better match the layout space of the arc-shaped layout area, thus enabling the multi-stage gate drive circuit to be well-placed within the arc-shaped layout area.

[0133] In some embodiments, in the first portion region, from the first region to the Mth region, the distance between the gate drive circuits in each region along the second direction gradually decreases;

[0134] In the third region, from the M+C+1 region to the N+X region, the distance between the gate drive circuits in each region along the second direction gradually increases.

[0135] For example, in at least two regions from the first region to the N+Xth region, the gate drive circuits are offset by an equal distance along the second direction.

[0136] For example, N+X equals 9. The distance offset along the second direction between adjacent gate drive circuits in the ninth region includes 170 micrometers. The distance offset along the second direction between adjacent gate drive circuits in the eighth region includes 110 micrometers. The distance offset along the second direction between adjacent gate drive circuits in the seventh region includes 80 micrometers. The distance offset along the second direction between adjacent gate drive circuits in the sixth region includes 45 micrometers. The distance offset along the second direction between adjacent gate drive circuits in the fifth region includes 0 micrometers. The distance offset along the second direction between adjacent gate drive circuits in the fourth region includes 45 micrometers. The distance offset along the second direction between adjacent gate drive circuits in the third region includes 90 micrometers. The distance offset along the second direction between adjacent gate drive circuits in the second region includes 160 micrometers. The distance offset along the second direction between adjacent gate drive circuits in the first region includes 300 micrometers.

[0137] The above configuration allows the multi-stage gate drive circuit to better match the layout space of the arc-shaped layout area, thus enabling the multi-stage gate drive circuit to be well-placed within the arc-shaped layout area.

[0138] In some embodiments, in the first portion region, the distance between the gate drive circuits in each region offset along the second direction is between 150 micrometers and 300 micrometers, and may include endpoint values;

[0139] In the second region, the distance between the gate drive circuits in each region along the second direction is between 30 micrometers and 60 micrometers, and may include endpoint values;

[0140] In the third region, the distance between the gate drive circuits in each region and the distance offset along the second direction is between 150 micrometers and 300 micrometers, and may include endpoint values.

[0141] For example, in regions M through M, the distance between the gate drive circuits in each region and offset along the second direction is between 30 micrometers and 60 micrometers. In regions M+1 through M+C, the distance between the gate drive circuits in each region and offset along the second direction is between 30 micrometers and 60 micrometers. In regions M+C+1 through N+X, the distance between the gate drive circuits in each region and offset along the second direction is between 150 micrometers and 300 micrometers.

[0142] The above configuration allows the multi-stage gate drive circuit to better match the layout space of the arc-shaped layout area, thus enabling the multi-stage gate drive circuit to be well-placed within the arc-shaped layout area.

[0143] In some embodiments, the arc-shaped layout area includes: Y clock signal lines and the multi-stage gate driving circuit; each stage of the gate driving circuit includes a gate driving signal output terminal, a clock signal input terminal, an input signal terminal, and a reset terminal;

[0144] The clock signal input terminal of the Y×(B-1)+F level gate drive circuit is coupled to the Fth clock signal line, where Y is an integer greater than or equal to 2, F is a positive integer less than or equal to Y, and B is an integer greater than or equal to 1.

[0145] In some embodiments, in the multi-stage gate driving circuit: the gate driving signal output terminal of the A-th stage gate driving circuit is coupled to the input signal terminal of the A+E-th stage gate driving circuit and the reset terminal of the AE-th stage gate driving circuit, respectively, where A is an integer greater than or equal to 3 and E is a positive integer less than A.

[0146] The multi-stage gate driving circuit is divided into multiple groups of gate driving circuits arranged in sequence, each group of gate driving circuits including at least two adjacent gate driving circuits; the Nth region 30 includes at least one group of gate driving circuits, which includes the Nth gate driving circuit; the N+1th region 40 includes at least one group of gate driving circuits, which includes the N+1th gate driving circuit.

[0147] For example, the clock signal input terminal of the Y×(B-1)+F level gate drive circuit is coupled to the Fth clock signal line to receive the Fth clock signal provided by the Fth clock signal line.

[0148] For example, Y equals 4, and F takes the values ​​1, 2, 3, and 4.

[0149] For example, in the multi-stage gate driving circuit: the input signal terminal of the first-stage gate driving circuit is coupled to the first frame start signal line included in the arc-shaped layout area; the input signal terminal of the second-stage gate driving circuit is coupled to the second frame start signal line included in the arc-shaped layout area.

[0150] For example, the gate drive signal output terminal of the A-level gate drive circuit is coupled to the input signal terminal of the A+E-level gate drive circuit, and the gate drive signal output from the A-level gate drive circuit serves as the input signal of the A+E-level gate drive circuit. The gate drive signal output terminal of the A-level gate drive circuit is coupled to the reset terminal of the AE-level gate drive circuit, and the gate drive signal output from the A-level gate drive circuit serves as the reset signal of the AE-level gate drive circuit.

[0151] like Figure 5 As shown, Figure 5 The diagram illustrates that odd-numbered scan lines receive gate drive signals (i.e., scan signals) provided by the gate drive circuit in the irregular layout area on the right, while even-numbered scan lines receive gate drive signals provided by the gate drive circuit in the irregular layout area on the left.

[0152] Gate-1 to Gate480 represent scan lines. Dummy-1 to Dummy-4 represent virtual scan lines.

[0153] Figure 5 The Gate-1 to Gate480 and Dummy-1 to Dummy-4 marked in the Chinese block represent the scan lines coupled to the corresponding numbers, used to provide gate drive signals for the scan lines marked accordingly.

[0154] The irregular layout area on the left includes the first frame start signal line STV1 and the second frame start signal line STV2. The irregular layout area on the right includes the third frame start signal line STV3 and the fourth frame start signal line STV4. The irregular layout area on the right also includes the fifth clock signal line CLK5, the sixth clock signal line CLK6, the seventh clock signal line CLK7, and the eighth clock signal line CLK8.

[0155] For example, the multi-stage gate driving circuit is divided into multiple groups of gate driving circuits arranged in sequence, and each stage of gate driving circuit belongs to only one group of gate driving circuits.

[0156] For example, the Nth region 30 includes at least one group of gate driving circuits, and the gate driving circuit included in the at least one group of gate driving circuits is the Nth gate driving circuit; the N+1th region 40 includes at least one group of gate driving circuits, and the gate driving circuit included in the at least one group of gate driving circuits is the N+1th gate driving circuit.

[0157] By cascading the multi-stage gate driving circuits in the manner described above, not only is the working performance of the multi-stage gate driving circuits guaranteed, but the layout space occupied by the multi-stage gate driving circuits is also reduced, which is beneficial for narrowing the bezel of irregularly shaped display substrates.

[0158] In some embodiments, the gate driving circuit includes a gate driving signal output terminal, an input terminal, and a reset terminal; the AH-level gate driving circuit is used to provide an input signal to the A-level gate driving circuit through its gate driving signal output terminal, and the A+H+1-level gate driving circuit is used to provide a reset signal to the A-level gate driving circuit through its gate driving signal output terminal.

[0159] For example, consider a non-standard layout area on one side of the display area with four clock signal lines. The first gate drive circuit provides an input signal to the third-stage gate drive circuit through its gate drive signal output terminal. The sixth gate drive circuit provides a reset signal to the third-stage gate drive circuit through its gate drive signal output terminal.

[0160] It should be noted that the reset can be set according to actual needs and is not limited. For example, the fourth gate drive circuit can reset the first gate drive circuit, or the fifth gate drive circuit can reset the first gate drive circuit.

[0161] like Figure 3 As shown, in some embodiments, the Nth region 30 includes a plurality of Nth sub-regions 301, and the Nth sub-region 301 includes the corresponding Nth gate drive circuit and signal line; the layout structure of the Nth sub-region 301 where the Nth gate drive circuit connected to the same clock signal line is located is the same;

[0162] The N+1th region 40 includes multiple N+1th sub-regions 401, each of which includes a corresponding N+1th gate drive circuit and signal line; the layout structure of the N+1th sub-region 401 containing the N+1th gate drive circuit connected to the same clock signal line is the same.

[0163] like Figure 6 As shown, for example, the first clock signal line CLK1 includes three connecting lines. The first connecting line extends along the first direction, the third connecting line extends along the second direction, the first direction and the second direction are perpendicular, and the second connecting line is coupled to both the first connecting line and the third connecting line. In the same region (such as the Nth region), within each sub-region including the first clock signal line, the first clock signal line is arranged in this manner.

[0164] like Figure 8As shown, for example, the third clock signal line CLK3 is laid out differently from the first clock signal line CLK1 to accommodate the layout requirements of the irregular layout area.

[0165] For example, the width of the Nth sub-region 301 along the first direction is approximately the same as the width of the layout area occupied by a sub-pixel in the display area. The width of the (N+1)th sub-region 401 along the first direction is also approximately the same as the width of the layout area occupied by a sub-pixel in the display area. It should be noted that theoretically, the width of the Nth sub-region 301 and the (N+1)th sub-region 401 along the first direction are set to be the same as the width of the layout area occupied by a sub-pixel in the display area. However, due to process errors in the fabrication of irregularly shaped display substrates, the actual width during fabrication may differ from the theoretically set width. Considering this process error, the aforementioned widths are limited to approximately the same.

[0166] For example, the Nth region 30 includes a plurality of Nth sub-regions 301 arranged in sequence, each Nth sub-region 301 corresponding to the Nth gate driving circuit, and each Nth sub-region 301 includes the corresponding Nth gate driving circuit and the signal line coupled to the Nth gate driving circuit.

[0167] like Figure 4 , Figure 5 and Figure 19 As shown, exemplarily, the type and number of signal lines in the Nth sub-region 301 and the N+1th sub-region 401 are related to the specific structure of the gate driving circuit. Taking the gate driving circuit including an 11T1C structure as an example, the signal lines in the Nth sub-region 301 and the N+1th sub-region 401 include: a first frame start signal line for inputting the first frame start signal STV1; a second frame start signal line for inputting the second frame start signal STV2; an input control signal line for inputting the input control signal Input; a carry signal line for inputting the carry signal VDS; a first pull-down control line for inputting the first pull-down control signal GCH; a clock signal line for inputting the clock signal CLK; a first reset control line for inputting the first reset control signal Reset; a second reset control line for inputting the second reset control signal STV0; a third reset control line for inputting the third reset control signal GCL; a first reset signal line for inputting the first reset signal VSD; and a second reset signal line for inputting the second reset signal VGL.

[0168] For example, the input control signal line is used to connect the input signal terminal of the gate drive circuit in the current sub-region and the gate drive signal output terminal of the previous E-stage gate drive circuit. The first reset control line is used to connect the reset terminal of the gate drive circuit in the current sub-region and the gate drive signal output terminal of the subsequent E-stage gate drive circuit.

[0169] The above configuration allows for the direct replication of the Nth sub-region 301 containing the Nth gate drive circuit connected to the same clock signal line, and the direct replication of the N+1th sub-region 401 containing the N+1th gate drive circuit connected to the same clock signal line. This avoids the time-consuming and inefficient layout issues caused by manually placing and adjusting all gate drive circuits step by step. It effectively improves the production progress and capacity of irregularly shaped display substrates.

[0170] In some embodiments, such as Figures 6 to 9 As shown, in each of the Nth sub-regions 301 where the Nth gate drive circuit is located, the layout of the different clock signal lines is different;

[0171] like Figures 10 to 13 As shown, in each of the N+1 sub-regions 401 where the N+1 gate drive circuits connecting different clock signal lines are located, the layout of the different clock signal lines is different.

[0172] It should be noted that the different layouts of the different clock signal lines refer to the different shapes and sizes of the clock signal lines, and / or the different positions of the clock signal lines relative to the gate drive circuit.

[0173] like Figures 6 to 13 As shown, in some embodiments, the layout structure of the gate drive circuits at each stage is exactly the same, but the layout of the signal lines in the Nth sub-region 301 and the N+1 sub-region is not exactly the same.

[0174] It should be noted that different signal line layouts refer to different signal line shapes and sizes, and / or different signal line positions relative to the gate drive circuit.

[0175] The above configuration allows the layout structure in the Nth region 30 and the N+1th region 40 to match the shape of the irregular layout area 21 very well.

[0176] When laying out the gate drive circuit in the irregular layout area 21, the above-mentioned settings can be used to lay out the circuit in a segmented manner. Only a small number of signal lines (such as clock signal lines) need to be adjusted, without the need for step-by-step placement and adjustment of a large number of signal lines. This effectively improves the layout efficiency of the gate drive circuit, reduces the layout time, and increases production progress and capacity.

[0177] In some embodiments, the Nth gate driving circuit, the connection region 50, and the (N+1)th gate driving circuit each include:

[0178] The input sub-circuit is used to pull up the PU node to input the carry signal;

[0179] The output sub-circuit is used to input a clock signal to the drive signal output terminal;

[0180] The first pull-up node reset sub-circuit is used to input a first reset signal to the pull-up node PU;

[0181] The second pull-up node reset sub-circuit is used to input a second reset signal to the pull-up node PU;

[0182] The pull-down node reset sub-circuit is used to pull down the second reset signal input to the pull-down node PD;

[0183] An output reset sub-circuit is used to input the second reset signal to the drive signal output terminal;

[0184] The storage sub-circuit is coupled to the pull-up node PU and the drive signal output terminal, respectively.

[0185] like Figure 19 As shown, exemplarily, the input sub-circuit includes a first transistor M1. The output sub-circuit includes a third transistor M3. The first pull-up node reset sub-circuit includes a second transistor M2. The second pull-up node reset sub-circuit includes a fourth transistor M4 and a tenth transistor M10. The pull-down node reset sub-circuit includes a fifth transistor M5, a sixth transistor M6, an eighth transistor M8, and a ninth transistor M9. The output reset sub-circuit includes a seventh transistor M7 and an eleventh transistor M11. The storage sub-circuit includes a storage capacitor C.

[0186] The gate of the first transistor M1 is coupled to the input control line, the first terminal of the first transistor M1 is coupled to the carry signal line, and the second terminal of the first transistor M1 is coupled to the pull-up node PU.

[0187] The gate of the second transistor M2 is coupled to the first reset control line, the first terminal of the second transistor M2 is coupled to the pull-up node PU, and the second terminal of the second transistor M2 is coupled to the first reset signal line.

[0188] The gate of the third transistor M3 is coupled to the pull-up node PU, the first terminal of the third transistor M3 is coupled to the clock signal line, and the second terminal of the third transistor M3 is coupled to the gate drive signal output terminal.

[0189] The gate of the fourth transistor M4 is coupled to the second reset control line, the first terminal of the fourth transistor M4 is coupled to the pull-up node PU, and the second terminal of the fourth transistor M4 is coupled to the second reset signal line.

[0190] The gate of the fifth transistor M5 is coupled to the second terminal of the ninth transistor M9, the first terminal of the fifth transistor M5 is coupled to the first pull-down control line, and the second terminal of the fifth transistor M5 is coupled to the pull-down node PD.

[0191] The gate of the sixth transistor M6 is coupled to the pull-up node PU, the first terminal of the sixth transistor M6 is coupled to the pull-down node PD, and the second terminal of the sixth transistor M6 is coupled to the second reset signal line.

[0192] The gate of the seventh transistor M7 is coupled to the third reset control line, the first terminal of the third transistor M3 is coupled to the gate drive signal output terminal, and the second terminal of the seventh transistor M7 is coupled to the second reset signal line.

[0193] The gate of the eighth transistor M8 is coupled to the pull-up node PU, the first terminal of the eighth transistor M8 is coupled to the second terminal of the ninth transistor M9, and the second terminal of the eighth transistor M8 is coupled to the second reset signal line.

[0194] The gate and first electrode of the ninth transistor M9 are both coupled to the first pull-down control line.

[0195] The gate of the tenth transistor M10 is coupled to the pull-down node PD, the first terminal of the tenth transistor M10 is coupled to the pull-up node PU, and the second terminal of the tenth transistor M10 is coupled to the second reset signal line.

[0196] The gate of the eleventh transistor M11 is coupled to the pull-down node PD, the first terminal of the eleventh transistor M11 is coupled to the gate drive signal output terminal, and the second terminal of the eleventh transistor M11 is coupled to the second reset signal line.

[0197] The gate drive circuit provided in the above embodiments can realize forward and reverse scanning functions, effectively reduce noise, and solve the problem of horizontal stripes at the end of high-temperature reliable scanning.

[0198] See Figure 14Taking a gate drive circuit with a 4T1C structure as an example, the gate drive circuit includes: an input sub-circuit, an output sub-circuit, a pull-up node reset sub-circuit, an output reset sub-circuit, and a storage sub-circuit. The input sub-circuit includes a first transistor M1, the output sub-circuit includes a third transistor M3, the pull-up node reset sub-circuit includes a second transistor M2, and the output reset sub-circuit includes a seventh transistor M7. The storage sub-circuit includes a storage capacitor C, with its first terminal coupled to the pull-up node PU and its second terminal coupled to the gate drive signal output terminal.

[0199] The gate and first terminal of the first transistor M1 both receive the input control signal Input, and the second terminal of the first transistor M1 is coupled to the pull-up node PU. The gate of the second transistor M2 receives the first reset control signal Reset, the first terminal of the second transistor M2 is coupled to the pull-up node PU, and the second terminal of the second transistor M2 is connected to the negative power supply signal VSS. The gate of the third transistor M3 is coupled to the pull-up node PU, the first terminal of the third transistor M3 receives the clock signal CLK, and the second terminal of the third transistor M3 is coupled to the gate drive signal output terminal Output. The gate of the seventh transistor M7 receives the first reset control signal Reset, the first terminal of the seventh transistor M7 is coupled to the gate drive signal output terminal Output, and the second terminal of the seventh transistor M7 is connected to the negative power supply signal VSS.

[0200] M1 is used as a carry signal input to raise the potential of the pull-up node PU, thus enabling M3; M2 is used to reset the pull-up node PU after the current row output is completed; M3 is used to control the gate drive signal output terminal Output to output the clock signal CLK line by line, so as to provide the scanning signal for the corresponding scan line in the display area; M4 is used to reset the gate drive signal output terminal Output after the current row output is completed.

[0201] like Figures 15 to 18 As shown, the working principle is as follows: First, M1 is turned on: Input is at a high level, PU is at a high level; M3 is turned on: CLK is at a low level, Output is at a low level; then M1 is turned off; M3 is turned on again: CLK is at a high level, Output is at a high level; finally, M2 and M4 are turned on, PU and Output are connected to VSS; M3 is turned off; Output is at a low level.

[0202] The 4T1C can realize the basic functions of the gate drive circuit and has a simple structure.

[0203] This invention also provides a display device, including the irregularly shaped display substrate provided in the above embodiments.

[0204] For example, the display device includes a small-sized round watch.

[0205] For example, the display device includes a liquid crystal display device.

[0206] For example, the display device can be any product or component with display function, such as a television, monitor, digital photo frame, mobile phone, or tablet computer. The display device may also include flexible circuit boards, printed circuit boards, and backplanes.

[0207] In the irregular display substrate provided in the above embodiment, the irregular layout area 21 includes an Nth region 30 and an N+1th region 40 arranged sequentially. Adjacent Nth gate driving circuits in the Nth region 30 are offset by a distance a along a second direction; the connecting line between the target portions of each Nth gate driving circuit has a first angle with the first direction; adjacent N+1th gate driving circuits in the N+1th region 40 are offset by a distance b along the second direction; the connecting line between the target portions of each N+1th gate driving circuit has a second angle with the first direction.

[0208] In the irregular display substrate provided in the above embodiments, by setting the connection between the target portions of the at least two Nth gate driving circuits in the Nth region 30 to have a first angle with the first direction, and setting the adjacent two Nth gate driving circuits to be offset by a distance a along the second direction; and setting the connection between the target portions of the at least two N+1th gate driving circuits in the N+1th region 40 to have a second angle with the first direction, the second angle being different from the first angle, and setting the adjacent two N+1th gate driving circuits to be offset by a distance b along the second direction, where a and b are not equal; the layout structure in the Nth region 30 and the N+1th region 40 can be well matched with the shape of the irregular layout area 21.

[0209] Furthermore, in the irregularly shaped display substrate provided in the above embodiments, by setting the Nth region 30 to include at least two Nth gate driving circuits, the connection between the target portions of the at least two Nth gate driving circuits has a first angle with the first direction, and adjacent Nth gate driving circuits are staggered by a distance 'a' along the second direction; this makes the layout of each Nth gate driving circuit the same, and the layout of at least a portion of the signal lines around each Nth gate driving circuit the same. Thus, when laying out the Nth region 30, the same at least two Nth gate driving circuits can be directly copied in the Nth region 30, and only the signal lines with different layouts around each Nth gate driving circuit need to be adjusted.

[0210] Similarly, in the irregular display substrate provided in the above embodiments, by setting the N+1 region 40 to include at least two N+1 gate driving circuits, the connection between the target portions of the at least two N+1 gate driving circuits has a second angle with the first direction, and adjacent N+1 gate driving circuits are staggered by a distance b along the second direction; this makes the layout of each N+1 gate driving circuit the same, and the layout of at least some signal lines around each N+1 gate driving circuit the same. Thus, when laying out the N+1 region 40, the same at least two N+1 gate driving circuits can be directly copied in the N+1 region 40, and only the signal lines around each N+1 gate driving circuit with different layouts need to be adjusted.

[0211] Therefore, in the irregular display substrate provided in the above embodiments, when laying out the gate driving circuit in the irregular layout area, the layout is carried out in a regional manner, eliminating the need for step-by-step placement and adjustment of a large number of signal lines. This effectively improves the layout efficiency of the gate driving circuit, reduces the layout time, and increases production progress and capacity.

[0212] Therefore, the display device provided in the embodiments of the present invention, when including the above-mentioned irregular display substrate, also has the above-mentioned beneficial effects, which will not be repeated here.

[0213] It should be noted that the various embodiments in this specification are described in a progressive manner, and the same or similar parts between the various embodiments can be referred to mutually. Each embodiment focuses on describing the differences from other embodiments. In particular, the method embodiments are basically similar to the product embodiments, so the description is relatively simple, and the relevant parts can be referred to the description of the product embodiments.

[0214] Unless otherwise defined, the technical or scientific terms used in this disclosure shall have the ordinary meaning understood by one of ordinary skill in the art to which this invention pertains. The terms “first,” “second,” and similar terms used in this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Terms such as “comprising” or “including” mean that the element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects. Terms such as “connection,” “coupled,” or “linked” are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. Terms such as “upper,” “lower,” “left,” and “right” are used only to indicate relative positional relationships; these relative positional relationships may change accordingly when the absolute position of the described object changes.

[0215] It is understandable that when a component such as a layer, film, region, or substrate is referred to as being "above" or "below" another component, the component may be "directly" located "above" or "below" the other component, or there may be intermediate components present.

[0216] In the description of the above embodiments, specific features, structures, materials, or characteristics may be combined in any suitable manner in one or more embodiments or examples.

[0217] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A non-circular display substrate, characterized in that, include: A display area and a non-display area surrounding the display area; the non-display area includes an irregularly shaped layout area, the irregularly shaped layout area includes a multi-level gate driving circuit arranged in sequence, and the irregularly shaped layout area also includes an Nth region and an N+1th region arranged in sequence, where N is greater than or equal to 1; The multi-level gate driving circuit includes at least two gate driving circuits located in the Nth region and arranged sequentially. The connection between the target portions of the at least two gate driving circuits has a first angle with the first direction. Adjacent gate driving circuits are staggered by a distance a along the second direction. The second direction intersects the first direction. In the Nth region, each gate driving circuit has the same layout, and at least some of the signal lines around each gate driving circuit have the same layout. The multi-level gate driving circuit further includes at least two gate driving circuits located in the N+1th region and arranged sequentially. The connection between the target portions of the at least two gate driving circuits has a second angle with the first direction. The second angle is different from the first angle. Adjacent gate driving circuits are staggered by a distance b along the second direction, where a and b are not equal. In the N+1th region, each gate driving circuit has the same layout, and at least some of the signal lines around each gate driving circuit have the same layout. The layout of the circuit structure in the gate driving circuit of the Nth region and the gate driving circuit of the N+1th region is the same. In the Nth region, Y gate drive circuits are grouped together. This region includes k groups. The Y gate drive circuits in a group of gate drive circuits are coupled one-to-one with Y clock signal lines. The Nth region includes eight gate driving circuits arranged in sequence. Among the eight gate driving circuits, the first gate driving circuit is connected to the first clock signal line, the second gate driving circuit is connected to the second clock signal line, the third gate driving circuit is connected to the third clock signal line, the fourth gate driving circuit is connected to the fourth clock signal line, the fifth gate driving circuit is connected to the first clock signal line, the sixth gate driving circuit is connected to the second clock signal line, the seventh gate driving circuit is connected to the third clock signal line, and the eighth gate driving circuit is connected to the fourth clock signal line. The first gate driving circuit and the second gate driving circuit are offset by a distance a along the second direction; The layout of the first clock signal line connected to the fifth gate driving circuit and the first gate driving circuit is the same; the layout of the second clock signal line connected to the second gate driving circuit and the sixth gate driving circuit is the same; the layout of the third clock signal line connected to the third gate driving circuit and the seventh gate driving circuit is the same; the layout of the fourth clock signal line connected to the fourth gate driving circuit and the eighth gate driving circuit is the same; the layout of the first clock signal line to the fourth clock signal line is different for each of them.

2. The irregularly shaped display substrate according to claim 1, characterized in that, The irregular layout region further includes a connection region, at least a portion of which is located between the Nth region and the N+1th region, and the connection region includes at least one connection gate driving circuit. The connection gate driving circuit and the adjacent Nth gate driving circuit are offset by a distance c along the second direction, where c may be equal to or different from a. And / or, The connection gate driving circuit and the adjacent (N+1)th gate driving circuit are offset by a distance d along the second direction, where d is equal to or not equal to b.

3. The irregularly shaped display substrate according to claim 1, characterized in that, The distance a is proportional to the first included angle, and the distance b is proportional to the second included angle.

4. The irregularly shaped display substrate according to claim 1, characterized in that, The gate driving circuit of the Nth region includes an Nth output transistor. In two adjacent Nth gate driving circuits, the gates of the Nth output transistors are offset by a distance a along the second direction. The gate driving circuit of the N+1th region includes an N+1th output transistor. In two adjacent N+1th gate driving circuits, the gates of the N+1th output transistors are offset by a distance b along the second direction.

5. The irregularly shaped display substrate according to claim 2, characterized in that, The display area includes a circular display area, the irregular layout area includes an arc-shaped layout area, and the display area is provided with arc-shaped layout areas on both sides opposite to each other along the second direction. The arc-shaped layout area includes the Nth region, the connecting region, and the N+1th region.

6. The irregularly shaped display substrate according to claim 5, characterized in that, The arc-shaped layout area includes the first region to the N+Xth region, where X is greater than or equal to 2; The arc-shaped layout area is divided into three regions: the first region includes the first region to the Mth region; the second region includes the M+1th region to the M+Cth region; and the third region includes the M+C+1th region to the N+Xth region, where 1≤M<N+X, M+1≤M+C<N+X, and M+C+1≤N+X. In the first region, the angle between the connection between the target portions of the gate drive circuit in each region and the first direction is between 60° and 80°. In the second region, the connection between the target portions of the gate drive circuit in each region has an angle between 10° and 25° with the first direction; In the third region, the connection between the target portions of the gate drive circuit in each region has an angle between 60° and 80° with the first direction.

7. The irregularly shaped display substrate according to claim 6, characterized in that, In the first part of the region, from the first region to the Mth region, the distance between the gate drive circuits in each region along the second direction gradually decreases; In the third region, from the M+C+1 region to the N+X region, the distance between the gate drive circuits in each region along the second direction gradually increases.

8. The irregularly shaped display substrate according to claim 6, characterized in that, In the first region, the distance between the gate drive circuits in each region along the second direction is between 150 micrometers and 300 micrometers; In the second region, the distance between the gate drive circuits in each region along the second direction is between 30 micrometers and 60 micrometers; In the third region, the distance between the gate drive circuits in each region and the distance along the second direction is between 150 micrometers and 300 micrometers.

9. The irregularly shaped display substrate according to claim 5, characterized in that, The arc-shaped layout area includes: Y clock signal lines and the multi-stage gate drive circuit; each stage of the gate drive circuit includes a gate drive signal output terminal, a clock signal input terminal, an input signal terminal, and a reset terminal; The clock signal input terminal of the Y×(B-1)+F level gate drive circuit is coupled to the Fth clock signal line, where Y is an integer greater than or equal to 2, F is a positive integer less than or equal to Y, and B is an integer greater than or equal to 1.

10. The irregularly shaped display substrate according to claim 9, characterized in that, In the multi-stage gate drive circuit: the gate drive signal output terminal of the A-th stage gate drive circuit is coupled to the input signal terminal of the A+E-th stage gate drive circuit and the reset terminal of the AE-th stage gate drive circuit, respectively. A is an integer greater than or equal to 3, and E is a positive integer less than A. The multi-stage gate driving circuit is divided into multiple groups of gate driving circuits arranged in sequence, each group of gate driving circuits including at least two adjacent gate driving circuits; the Nth region includes at least one group of gate driving circuits, which includes the Nth gate driving circuit; the N+1th region includes at least one group of gate driving circuits, which includes the N+1th gate driving circuit.

11. The irregularly shaped display substrate according to claim 9, characterized in that, The Nth region includes multiple Nth sub-regions, and each Nth sub-region includes a corresponding Nth gate drive circuit and signal line; the layout structure of the Nth sub-region where the Nth gate drive circuit connected to the same clock signal line is located is the same. The N+1th region includes multiple N+1th sub-regions, and each N+1th sub-region includes a corresponding N+1th gate drive circuit and signal line; the layout structure of the N+1th sub-region where the N+1th gate drive circuit connected to the same clock signal line is the same.

12. The irregularly shaped display substrate according to claim 11, characterized in that, In each of the Nth sub-regions where the Nth gate drive circuit connecting different clock signal lines is located, the layout of the different clock signal lines is different. In each of the N+1 sub-regions where the gate drive circuits connecting different clock signal lines are located, the layout of the different clock signal lines is different.

13. The irregularly shaped display substrate according to claim 11, characterized in that, The layout structure of the gate drive circuits at each stage is exactly the same, but the layout of the signal lines in the Nth sub-region and the N+1 sub-region is not exactly the same.

14. The irregularly shaped display substrate according to claim 2, characterized in that, The Nth gate driving circuit, the connection region and the (N+1)th gate driving circuit both include: The input sub-circuit is used to input carry signals to the pull-up node; The output sub-circuit is used to input a clock signal to the drive signal output terminal; The first pull-up node reset sub-circuit is used to input a first reset signal to the pull-up node; The second pull-up node reset sub-circuit is used to input a second reset signal to the pull-up node; The pull-down node reset sub-circuit is used to input the second reset signal to the pull-down node; An output reset sub-circuit is used to input the second reset signal to the drive signal output terminal; The storage sub-circuit is coupled to the pull-up node and the drive signal output terminal, respectively.

15. A display device, characterized in that, Includes the irregularly shaped display substrate as described in any one of claims 1 to 14.

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