Integrated command to calibrate read voltage levels

Abstract

This disclosure relates to an integrated command to calibrate read voltage levels. Processing logic in a memory device receives a command to perform a set of read operations having read voltage levels corresponding to a program distribution associated with the memory device. A set of memory bit counts is determined, where each memory bit count corresponds to a respective bin of a set of bins associated with the plurality of read voltage levels of the set of read operations. A valley center bin having a smallest memory bit count of the set of memory bit counts is determined. The processing logic determines that the smallest memory bit count of the valley center bin satisfies a condition, and identifies an adjusted read voltage level associated with the valley center bin in response to satisfying the condition.

Description

TECHNICAL FIELD

[0001] Embodiments of the present disclosure generally relate to memory sub-systems and, more particularly, to execution of integrated commands to calibrate read voltage levels in a memory sub-system. BACKGROUND

[0002] A memory sub-system can include one or more memory devices that store data. The memory devices can be, for example, non-volatile memory devices and volatile memory devices. Generally, a host system can utilize a memory sub-system to store data at the memory devices and retrieve data from the memory devices. SUMMARY

[0003] One aspect of the present disclosure provides a memory device comprising: a memory array comprising a set of memory cells; and processing logic, operatively coupled with the memory array, to perform operations comprising: receiving, from a memory sub-system controller, a command to perform a set of read operations at a plurality of read voltage levels corresponding to a program distribution associated with the memory device; determining, in response to the command, a set of memory bit counts, wherein each memory bit count corresponds to a respective bin of a set of bins associated with the plurality of read voltage levels of the set of read operations; identifying, in response to the command, a valley center bin having a smallest memory bit count of the set of memory bit counts; determining, in response to the command, that the smallest memory bit count of the valley center bin satisfies a condition; and identifying, in response to the command, an adjusted read voltage level associated with the valley center bin in response to satisfying the condition.

[0004] Another aspect of the present disclosure provides a memory device comprising: a memory array comprising a set of memory cells; and processing logic, operatively coupled with the memory array, to perform operations comprising: receiving a calibration scan command; causing, in response to the calibration scan command, a set of read operations to be performed on the memory device at a plurality of read voltage levels; identifying, in response to the calibration scan command, a set of bit counts, wherein each bit count of the set of bit counts corresponds to a respective bin of a set of bins associated with the plurality of read voltage levels; and identifying, based on the bit count corresponding to each bin of the set of bins, a bin having a lowest bit count.

[0005] Another aspect of the disclosure provides a method comprising: receiving, from a memory sub-system controller, a command to perform a set of read operations at a plurality of read voltage levels corresponding to a program distribution associated with a memory device; determining a set of memory bit counts, wherein each memory bit count corresponds to a respective bin of a set of bins associated with the plurality of read voltage levels of the set of read operations; identifying a valley center bin having a smallest memory bit count of the set of memory bit counts; determining that the smallest memory bit count of the valley center bin satisfies a condition; and identifying an adjusted read voltage level associated with the valley center bin in response to the condition being satisfied. BRIEF DESCRIPTION OF DRAWINGS

[0006] The disclosure will be more fully understood from the following embodiments taken in conjunction with the accompanying drawings, from which the nature of the disclosure will be apparent.

[0007] Figure 1A An example computing system including a memory sub-system in accordance with one or more embodiments of the disclosure is described.

[0008] Figure 1B A block diagram of a memory device in communication with a memory sub-system controller of a memory sub-system in accordance with one or more embodiments of the disclosure.

[0009] Figures 2A to 2C A schematic diagram of a portion of a memory cell array in a memory of the type as can be used in reference Figure 1B described in accordance with one or more embodiments of the disclosure.

[0010] Figure 3 A schematic block diagram of a portion of a memory cell array in a memory of the type as can be used in reference Figure 1B described in accordance with one or more embodiments of the disclosure.

[0011] Figure 4 An example program distribution to be calibrated in accordance with an integrated calibration command in accordance with an embodiment of the disclosure is described.

[0012] Figure 5 An example program distribution to be calibrated in accordance with an integrated calibration command in accordance with an embodiment of the disclosure is described.

[0013] Figure 6 A flowchart of an example method of executing an integrated calibration command to determine an adjusted read voltage level corresponding to a valley portion relative to a default read voltage level in accordance with one or more embodiments of the disclosure.

[0014] Figure 7 A block diagram of an example computer system in which embodiments of the disclosure can operate. DETAILED DESCRIPTION

[0015] Aspects of the present disclosure relate to the execution of integrated commands to calibrate read voltage levels in a memory sub-system. The memory sub-system can be a storage device, a memory module, or a hybrid of a storage device and a memory module. Examples of storage devices and memory modules are described below in connection with FIG. 1. Generally, a host system can utilize a memory sub-system that includes one or more components such as a memory device that stores data. The host system can provide data to be stored at the memory sub-system and can request data to be retrieved from the memory sub-system.

[0016] The memory sub-system can include high-density non-volatile memory devices in which data needs to be retained when no power supply is provided to the memory device. One example of a non-volatile memory device is a NAND (Not AND) memory device. Other examples of non-volatile memory devices are described below in connection with FIG. 1. A non-volatile memory device is a package of one or more dies. Each die can be composed of one or more planes. For some types of non-volatile memory devices (e.g., NAND devices), each plane is composed of a set of physical blocks. Each block is composed of a set of pages. Each page is composed of a set of memory cells (“cells”). A cell is an electronic circuit that stores information. Depending on the cell type, a cell can store one or more bits of binary information and has various logic states related to the number of bits being stored. The logic states can be represented by binary values such as “0” and “1” or a combination of such values.

[0017] The memory device can be composed of bits arranged in a two-dimensional or three-dimensional grid. Memory cells are etched onto a silicon wafer in the form of an array of columns (also referred to below as bit lines) and rows (also referred to below as word lines). A word line can refer to one or more rows of memory cells of a memory device used with one or more bit lines to generate an address for each of the memory cells. The intersection of a bit line and a word line constitutes an address of a memory cell. In the following, a block refers to a unit of a memory device to store data and can include a group of memory cells, a group of word lines, a word line, or an individual memory cell.

[0018] The memory device includes a plurality of memory cells, each of which can store one or more bits of information depending on the memory cell type. A memory cell can be programmed (written to) by applying a certain voltage to the memory cell, which causes the memory cell to retain a charge, thus allowing modulation of the voltage distribution generated by the memory cell. Moreover, precisely controlling the amount of charge stored by a memory cell allows establishing multiple threshold voltage levels corresponding to different logic levels, effectively allowing a single memory cell to store multiple bits of information: with 2 nA memory cell capable of operating at n different threshold voltage levels can store n bits of information. "Threshold voltage" will refer herein to a voltage level defining a boundary between two adjacent voltage distributions corresponding to two logic levels. Read operations can thus be performed by comparing a measured voltage exhibited by a memory cell to one or more reference voltage levels in order to distinguish between two logic levels for single-level cells and multiple logic levels for multi-level cells.

[0019] A memory sub-system can include a plurality of memory components that can store data from a host system according to a plurality of program distributions. To establish and maintain a desired program distribution associated with a respective program level, a data integrity scan is performed.

[0020] In various systems, calibration is performed to determine an optimal or desired read threshold voltage corresponding to each of a program distribution and an integrity or health of bits stored in a memory cell, as represented by a read window budget (RWB) valley margin tolerance associated with the program distribution. Calibration techniques can sample a margin between program distributions, also referred to as read threshold valleys or valley, to determine whether to maintain a desired valley margin or relative width between adjacent program distributions. The valley margin can be related to the RWB, where the RWB for a valley can refer to an absolute measurement in volts (e.g., millivolts (mV)) between two adjacent program distributions.

[0021] To monitor the integrity of a system, a memory sub-system can perform a data integrity check (also referred to herein as a "scan") to verify that data stored at a data block remains at a sufficient level of reliability. During a data integrity check, a set of read and / or write operations are invoked and one or more reliability statistics are determined for data stored at a data block. One example of a reliability statistic is raw bit error rate (RBER). RBER can be defined as a ratio of a number of erroneous bits to a number of all data bits stored in a data block.

[0022] In some systems, a data integrity scan is performed to determine one or more reliability statistics associated with a program distribution. For example, an initial scan can be performed to measure the RBER of a system. If the initial scan returns an RBER above an acceptable error threshold level, a controller can perform a series of operations to calibrate read threshold voltage levels to establish a desired program distribution. In some systems, when a read operation is performed, an automatic read calibration (ARC) algorithm is performed using measured data from a high frequency data integrity scan to center a valley of read threshold positions. For example, an ARC read operation is performed to identify a location of an optimal or ideal read level within a valley associated with a program or voltage level distribution. In this regard, a discrete command is issued and a corresponding operation of the ARC process is performed to identify a read voltage level corresponding to a center of the valley.

[0023] Additionally, upon identifying the ideal or optimal read level within the valley, further commands and operations are commanded and operated in subsequent phases to scan or check reliability statistics based on the identified read level. These further operations can identify a width of the valley margin threshold for comparison to an acceptable valley margin threshold. In this further phase of the typical calibration process, the size or margin of each valley is measured by issuing a sequence of read commands to determine the corresponding RWB. If these operations result in a determination that the read margin is not acceptable (e.g., the data is not reliable), the data is refreshed.

[0024] Each scan involves the execution of the series of commands identified above and multiple operations on the memory device itself, which consumes bandwidth of the memory device and data transfer on the communication interface and bus (e.g., ONFI interface). Thus, the typical calibration process includes the execution of multiple phases that include the issuance of multiple discrete commands and the execution of multiple corresponding operations on the memory device, which results in a large amount of data transfer and bandwidth consumption on the communication interface and bus.

[0025] Accordingly, the above-described method disadvantageously requires the execution of multiple read operations during the execution of the ARC and RWB measurements. Further, the multi-phase process with multiple commands results in duplication of read operations during the ARC processing phase and the RWB measurement phase. Additionally, the multi-phase calibration process includes the issuance of multiple discrete commands that increase command overhead and result in the execution of multiple operations, including duplicate operations. These multiple commands and operations create a large amount of data transfer and additional stress on the memory device, which consumes bandwidth on the communication interface.

[0026] Aspects of the present disclosure address the above and other deficiencies by a process that includes a single integrated command that enables and executes a read level calibration process. According to this method, a single command (also referred to herein as an “integrated calibration command”) can be implemented to generate a calibration indication or hint that is capable of identifying an optimal or adjusted read voltage level associated with one or more programming distributions of a memory device. In this regard, the previously used separate commands associated with the ARC processing phase and the RBER measurement phase are eliminated. According to embodiments, the integrated calibration command of the present disclosure causes the execution of multiple read operations at respective read voltage levels. The read voltage levels of the set of read operations include a default read voltage level (Vread0) within a range of voltages, one or more read voltage levels at a lower offset (e.g., Vread -1 -2 and so forth) relative to the default read voltage level (referred to herein as a “set of lower offset levels”) and one or more read voltage levels at a higher offset level (e.g., Vread1, Vread2, and so forth) relative to the default read voltage level (referred to herein as a “set of higher offset levels”). ​

[0027] According to embodiments, a set of bins is identified between each respective pair of read voltage levels. Each bin corresponds to a range of voltages between two adjacent read voltage thresholds. For example, a first bin corresponds to a first range of voltages between Vread -2 and Vread -1 , a second bin corresponds to a second range of voltages between Vread -1 and Vread0, and so on. A memory bit count is determined for each of the respective bins. The memory bit count represents the number of cells programmed to a voltage within the range. A comparison of the memory bit counts corresponding to the bins is performed to identify a bin having a minimum bit count. In embodiments, the minimum bit count corresponds to the bin having the fewest number of cells programmed to a voltage within the range compared to all other bins. In embodiments, the bin having the minimum bit count is identified as a valley center bin (e.g., corresponding to a region or portion corresponding to an estimated valley center of the programming distribution). In embodiments, a representation of the memory bit counts is generated. For example, the representation can include a data structure including the memory bit counts corresponding to each bin or a histogram representing the memory bit counts in each bin.

[0028] In embodiments, the memory bit count of the identified valley center bin is compared to a valley margin threshold to determine whether a condition is satisfied (also referred to as a "valley check" operation). In embodiments, the condition is satisfied when the memory bit count of the identified valley center bin is less than the valley margin threshold. In embodiments, the performance of the valley check operation and the satisfaction of the condition indicates that the identified valley center has sufficient valley margin. In embodiments, if the identified valley center fails the valley check operation, then it is determined that the data is unreliable and a refresh operation can be performed.

[0029] In another embodiment, an aggregate memory bit count corresponding to the identified valley center bin and one or more adjacent bins is determined. For example, a first memory bit count associated with the identified valley center bin (e.g., bin 2) can be added to a second memory bit count associated with a first additional bin to the left of the valley center bin (e.g., bin 1) and a third memory bit count associated with a second additional bin to the right of the valley center bin (e.g., bin 3). In embodiments, the aggregate memory bit count is compared to a valley margin threshold to determine whether a condition is satisfied. In this embodiment, the condition is satisfied when the aggregate memory bit count is less than the valley margin threshold, thereby indicating that the valley center bin has sufficient valley margin.

[0030] In an embodiment, an indication of the identified valley center by the trough check operation is provided by the local media controller to the memory sub-system controller. In an embodiment, using the identified valley center with an acceptable valley tolerance, the memory sub-system controller identifies an optimal or adjusted read voltage level associated with the valley center. In an embodiment, the memory sub-system controller sets the adjusted read voltage level as a new or updated read voltage level for a subsequent calibration scan. In another embodiment, the local media controller can determine the adjusted read voltage level corresponding to the identified valley center and provide information identifying the adjusted read voltage level to the memory sub-system controller.

[0031] Advantageously, an integrated command can be issued to enable identification of a valley center and further determine whether a valley tolerance associated with the valley center is sufficient. An indication or hint of the identified valley center having a sufficient valley tolerance (e.g., a valley center by a trough check operation) is used to determine an adjusted read voltage level for establishing a desired programming distribution of a memory device.

[0032] Figure 1A An example computing system 100 including a memory sub-system 110 according to some embodiments of the present disclosure is illustrated. The memory sub-system 110 can include media such as one or more volatile memory devices (e.g., memory devices 140), one or more non-volatile memory devices (e.g., memory devices 130), or a combination of these.

[0033] The memory sub-system 110 can be a storage device, a memory module, or a hybrid of a storage device and a memory module. Examples of storage devices include solid-state drives (SSDs), flash drives, universal serial bus (USB) flash drives, embedded Multi-Media Controllers (eMMC) drives, Universal Flash Storage (UFS) drives, Secure Digital (SD) cards, and hard disk drives (HDDs). Examples of memory modules include dual in-line memory modules (DIMMs), small outline DIMMs (SO-DIMMs), and various types of non-volatile dual in-line memory modules (NVDIMMs).

[0034] The computing system 100 can be a computing device such as a desktop computer, a laptop computer, a network server, a mobile device, a vehicle (e.g., an airplane, a drone, a train, a car, or other transportation vehicle), an Internet of Things (IoT) enabled device, an embedded computer (e.g., an embedded computer included in a vehicle, industrial equipment, or a networked commercial device), or such computing device including a memory and a processing device.

[0035] The computing system 100 can include a host system 120 coupled to one or more memory sub-systems 110. In some embodiments, the host system 120 is coupled to different types of memory sub-systems 110. Figure 1A An example of a host system 120 coupled to one memory sub-system 110 is illustrated. As used herein, “coupled to” or “coupled with” generally refers to a connection between components that can be an indirect communicative connection or direct communicative connection (e.g., without intervening components), whether wired or wireless, including connections such as electrical, optical, magnetic, etc.

[0036] The host system 120 can include a processor chipset and a software stack executed by the processor chipset. The processor chipset can include one or more cores, one or more cache memories, memory controllers (e.g., NVDIMM controllers), and storage protocol controllers (e.g., PCIe controllers, SATA controllers). The host system 120 uses the memory sub-system 110, for example, to write data to and read data from the memory sub-system 110.

[0037] The host system 120 can be coupled to the memory sub-system 110 via a physical host interface. Examples of a physical host interface include, but are not limited to, a serial advanced technology attachment (SATA) interface, a peripheral component interconnect express (PCIe) interface, a universal serial bus (USB) interface, a Fibre Channel, Serial Attached SCSI (SAS), a double data rate (DDR) memory bus, a small computer system interface (SCSI), a dual in-line memory module (DIMM) interface (e.g., a DIMM socket interface supporting double data rate (DDR)), etc. The physical host interface can be used to transfer data between the host system 120 and the memory sub-system 110. When the memory sub-system 110 is coupled with the host system 120 by a physical host interface (e.g., a PCIe bus), the host system 120 can further utilize an NVM Express (NVMe) interface to access access components (e.g., memory devices 130). The physical host interface can provide an interface for passing control, address, data, and other signals between the memory sub-system 110 and the host system 120. Figure 1A A memory sub-system 110 is illustrated as an example. In general, a host system 120 can access multiple memory sub-systems via the same communication connection, multiple separate communication connections, and / or a combination of communication connections.

[0038] The memory devices 130, 140 can include any combination of different types of non-volatile memory devices and / or volatile memory devices. Volatile memory devices (e.g., memory devices 140) can be, but are not limited to, random access memories (RAMs), such as dynamic random access memories (DRAMs) and synchronous dynamic random access memories (SDRAMs).

[0039] Some examples of non-volatile memory devices (e.g., memory devices 130) include negative- and (NAND) type flash memory and in-place write memory, such as a three-dimensional cross-point (“3D cross-point”) memory device, which is a cross-point array of non-volatile memory cells. The cross-point array of non-volatile memory can perform bit storage based on changes in bulk resistance in conjunction with a stackable cross-grided data access array. Additionally, in contrast to many flash-based memories, cross-point non-volatile memory can perform in-place write operations, where a non-volatile memory cell can be programmed without first erasing the non-volatile memory cell. NAND type flash memory includes, for example, two-dimensional NAND (2D NAND) and three-dimensional NAND (3D NAND).

[0040] Each of the memory devices 130 can include one or more arrays of memory cells. One type of memory cell, such as a single-level cell (SLC), can store one bit per cell. Other types of memory cells, such as a multi-level cell (MLC), a triple-level cell (TLC), a quad-level cell (QLC), and a penta-level cell (PLC), can store multiple bits per cell. In some embodiments, each of the memory devices 130 can include one or more arrays of memory cells, such as SLC, MLC, TLC, QLC, or any combination of these. In some embodiments, a particular memory device can include SLC, MLC, TLC, QLC, or PLC portions of memory cells. The memory cells of the memory devices 130 can be grouped into pages, which can refer to logical units of the memory device used to store data. In the case of some types of memory (e.g., NAND), pages can be grouped to form blocks. In one embodiment, the term “MLC memory” can be used to refer to any type of memory cell that stores more than one bit per cell (e.g., 2 bits, 3 bits, 4 bits, or 5 bits per cell).

[0041] Although non-volatile memory components such as 3D cross-point non-volatile memory cell arrays and NAND-type flash memory (e.g., 2D NAND, 3D NAND) are described, the memory devices 130 can be based on any other type of non-volatile memory such as read-only memory (ROM), phase change memory (PCM), self-selecting memory, other chalcogenide-based memory, ferroelectric transistor random access memory (FeTRAM), ferroelectric random access memory (FeRAM), magnetic random access memory (MRAM), spin-transfer torque (STT)-MRAM, conductive-bridge RAM (CBRAM), resistive random access memory (RRAM), oxide-based RRAM (OxRAM), or non-volatile (NOR) flash memory and electrically erasable programmable read-only memory (EEPROM).

[0042] The memory sub-system controller 115 (also referred to as“controller 115”) can communicate with the memory devices 130 to perform operations such as reading data, writing data, or erasing data at the memory devices 130, and other such operations. The memory sub-system controller 115 can include hardware such as one or more integrated circuits and / or discrete components, a buffer memory, or a combination thereof. The hardware can include digital circuitry with dedicated (i.e., hard-coded) logic to perform the operations described herein. The memory sub-system controller 115 can be a microcontroller, a special- purpose logic circuitry (e.g., a field-programmable gate array (FPGA), an application-specific integrated circuit (ASIC), etc.), or other suitable processor.

[0043] The memory sub-system controller 115 can be a processing device that includes one or more processors (e.g., processor 117) configured to execute instructions stored in local memory 119. In the illustrated example, the local memory 119 of the memory sub-system controller 115 includes embedded memory configured to store instructions for performing various processes, operations, logic flows, and routines that control the operation of the memory sub-system 110, including handling communications between the memory sub-system 110 and the host system 120.

[0044] In some embodiments, the local memory 119 can include memory registers that store memory pointers, fetched data, etc. The local memory 119 can also include read-only memory (ROM) for storing microcode. Although Figure 1A The example memory sub-system 110 in FIG. 1 has been illustrated as including the memory sub-system controller 115, but in another embodiment of the disclosure, the memory sub-system 110 does not include the memory sub-system controller 115 and can instead rely on external control (e.g., provided by an external host or by a processor or controller separate from the memory sub-system).

[0045] In general, memory sub-system controller 115 can receive commands or operations from host system 120 and can convert the commands or operations into instructions or appropriate commands to effectuate desired accesses to memory devices 130. Memory sub-system controller 115 can be responsible for other operations such as wear leveling operations, garbage collection operations, error detection and error-correcting code (ECC) operations, encryption operations, caching operations, and address translations between logical addresses (e.g., logical block addresses (LBAs), namespaces) and physical addresses (e.g., physical block addresses) associated with memory devices 130. Memory sub-system controller 115 can further include host interface circuitry to communicate with host system 120 via a physical host interface. The host interface circuitry can convert commands received from the host system into command instructions to access the memory devices 130 as well as convert responses associated with the memory devices 130 into information for the host system 120.

[0046] Memory sub-system 110 can also include additional circuitry or components not illustrated. In some embodiments, memory sub-system 110 can include a cache or buffer (e.g., DRAM) and address circuitry (e.g., row and column decoders) that can receive an address from memory sub-system controller 115 and decode the address to access memory devices 130.

[0047] In some embodiments, memory devices 130 include a local media controller 135 that operates in conjunction with memory sub-system controller 115 to perform operations on one or more memory cells of memory devices 130. An external controller (e.g., memory sub-system controller 115) can externally manage memory devices 130 (e.g., perform media management operations on memory devices 130). In some embodiments, memory sub-system 110 is a managed memory sub-system that includes raw memory devices 130 with control logic (e.g., local media controller 135) on a die and a controller (e.g., memory sub-system controller 115) for media management within the same memory device package. An example of a managed memory device is a managed NAND (MNAND) device.

[0048] In one embodiment, the memory sub-system 110 includes a memory interface component 113. The memory interface component 113 is responsible for handling interactions of the memory sub-system controller 115 with memory devices of the memory sub-system 110, such as memory devices 130. For example, the memory interface component 113 can send memory access commands, such as program commands, read commands, or other commands, corresponding to requests received from the host system 120 to the memory devices 130. Additionally, the memory interface component 113 can receive data from the memory devices 130, such as data retrieved in response to a read command or confirmation of successful execution of a program command. For example, the memory sub-system controller 115 can include a processor 117 (processing device) configured to execute instructions stored in local memory 119 for performing the operations described herein.

[0049] In embodiments, the memory sub-system 110 includes at least portions of a calibration manager 134 that can be used to perform operations related to an integrated calibration command to identify a valley center, evaluate a valley tolerance of the identified valley center, and determine an established optimal or adjusted read voltage level corresponding to a program distribution associated with the memory devices 130. In one embodiment, processing logic associated with the calibration manager can be included in both the memory sub-system controller 115 (i.e., calibration manager 134) and a local media controller 135 of the memory devices 130 (i.e., calibration manager 136). In embodiments, the calibration manager 134 is configured to issue an integrated calibration command to cause a plurality of read operations to be performed at a set of different read voltage levels within a voltage range. In embodiments, the set of read operations are performed at fixed voltage offsets or intervals within the voltage range, which includes a default or center read voltage level, one or more lower offset read voltage levels (e.g., the default read voltage level minus one or more offsets), and one or more higher offset read voltage levels (e.g., the default read voltage level plus one or more offsets), as illustrated in more detail in the example shown in Figure 4 and 5 In embodiments, the calibration manager 136 identifies a number of bins or buckets between each adjacent pair of read voltage levels (e.g., where each bin corresponds to a voltage range between two adjacent read voltage levels). In embodiments, a count of memory bits within each bin is determined. In embodiments, the calibration manager 136 identifies the bin with the lowest relative number of memory bits as the valley center bin.

[0050] In one embodiment, the calibration manager 136 performs a valley tolerance check associated with the identified valley center bin. In another embodiment, the calibration manager 136 compares the number of bits in the identified valley center bin with a valley tolerance threshold representing the minimum number of bits required to define a valley value with sufficient tolerance, to select an adjusted read voltage for verifying the reliability of data during calibration. In another embodiment, the valley tolerance check may be based on a comparison of the aggregated memory bit count of the identified valley center bin with the bit counts of one or more neighboring bins. If the aggregated count of the number of bits in the valley center bin or a combination of bins is below the valley tolerance threshold level, then the valley center bin is identified as an optimal valley center through the valley tolerance check.

[0051] In an embodiment, calibration managers 134, 136 may determine an adjusted readout voltage level corresponding to the identified valley center bin. In an embodiment, the adjusted readout voltage level may be a voltage within a voltage range defining the bin (e.g., a voltage within a range between two readout voltage gates defining the identified valley center bin). In an embodiment, the adjusted readout voltage level may be determined by calculating the average of two readout voltage levels associated with the valley center bin. In an embodiment, the adjusted readout level may be used for subsequent calibration scans.

[0052] In one embodiment, the memory subsystem controller 130 includes at least a portion of a calibration manager 136 configured to perform operations and functions associated with integrated calibration commands and related processing. In some embodiments, the local media controller 135 includes at least a portion of the calibration manager 136 and is configured to perform portions of the functionality described herein. In some embodiments, calibration managers 134, 136 are implemented on the memory subsystem 110 and memory device 130 using firmware, hardware components, or a combination thereof. Further details regarding the operation of calibration managers 134, 136 are described below.

[0053] Figure 1B A first device in the form of a presenting memory device 130 according to an embodiment and a presenting memory subsystem (e.g., Figure 1A A simplified block diagram of a second device communicating with a memory subsystem controller 115 in the form of a memory subsystem 110. Some examples of electronic systems include personal computers, personal digital assistants (PDAs), digital cameras, digital media players, digital recorders, games, electrical equipment, vehicles, wireless devices, mobile phones, etc. The memory subsystem controller 115 (e.g., a controller external to the memory device 130) may be a memory controller or other external host device.

[0054] The memory device 130 includes an array 150 of memory cells logically arranged in rows and columns. The memory cells in a logical row are typically connected to the same access line (e.g., word line), while the memory cells in a logical column are typically selectively connected to the same data line (e.g., bit line). A single access line can be associated with more than one logical row of memory cells, and a single data line can be associated with more than one logical column. The memory cells of at least a portion of the array 250 (not shown in the middle) are capable of being programmed to one of at least two target data states. Figure 1B

[0055] Row decode circuitry 208 and column decode circuitry 210 are provided to decode address signals. Address signals are received and decoded by the row and column decode circuitry 208, 210 to access the array 150 of memory cells. The memory device 130 also includes input / output (I / O) control circuitry 212 to manage the input of commands, addresses and data to the memory device 130 and the output of data and status information from the memory device 130. Address registers 214 are in communication with the I / O control circuitry 212 and the row and column decode circuitry 208, 210 to latch the address signals prior to decoding. Command registers 224 are in communication with the I / O control circuitry 212 and the local media controller 135 to latch incoming commands.

[0056] The controller (e.g., the local media controller 135 internal to the memory device 130) controls access to the array 150 of memory cells in response to commands and generates status information for the external memory sub-system controller 115, i.e., the local media controller 135 is configured to perform access operations (e.g., read, program, and / or erase operations) to the array 150 of memory cells. The local media controller 135 is in communication with the row and column decode circuitry 208, 210 to control the row and column decode circuitry 208, 210 in response to addresses. In one embodiment, the local media controller 135 includes at least portions of a calibration manager 136 that can implement operations associated with integrated calibration commands issued by portions of the calibration manager 134 of the memory sub-system controller 115, as described herein.

[0057] ​The local media controller 135 also communicates with a cache register 218. The cache register 218 latches incoming or outgoing data as directed by the local media controller 135 to temporarily store the data while the memory cell array 150 is busy writing or reading other data, respectively. During a program operation (e.g., a write operation), data can be transferred from the cache register 218 to a data register 220 for transfer to the memory cell array 150; new data can then be latched from the I / O control circuitry 212 in the cache register 218. During a read operation, data can be transferred from the cache register 218 to the I / O control circuitry 212 for output to the memory sub-system controller 115; new data can then be transferred from the data register 220 to the cache register 218. The cache register 218 and / or the data register 220 can form a page buffer (e.g., can form part of) of the memory device 130. The page buffer can further include sensing means (not shown in Figure 1B

[0058] The memory device 130 receives control signals at the memory sub-system controller 115 from the local media controller 135 via a control link 232. For example, the control signals can include a chip enable signal CE#, a command latch enable signal CLE, an address latch enable signal ALE, a write enable signal WE#, a read enable signal RE#, and a write protect signal WP#. Additional or alternative control signals (not shown) can further be received via the control link 232, depending on the nature of the memory device 130. In one embodiment, the memory device 130 receives command signals (which represent commands), address signals (which represent addresses), and data signals (which represent data) from the memory sub-system controller 115 over a multiplexed input / output (I / O) bus 234, and outputs data to the memory sub-system controller 115 over the I / O bus 234.

[0059] ​For example, commands can be received at I / O control circuitry system 212 via input / output (I / O) pins [7:0] of input / output (I / O) bus 234, and then written to command register 224. Addresses can be received at I / O control circuitry system 212 via input / output (I / O) pins [7:0] of input / output (I / O) bus 234, and then written to address register 214. Data can be received at I / O control circuitry system 212 via input / output (I / O) pins [7:0] for 8-bit devices or input / output (I / O) pins [15:0] for 16-bit devices, and then written to cache register 218. Data can then be written to data register 220 for programming memory cell array 150.

[0060] In this embodiment, the cache register 218 may be omitted, and data may be written directly to the data register 220. Data may also be output via input / output (I / O) pins [7:0] for 8-bit devices or input / output (I / O) pins [15:0] for 16-bit devices. While references may be made to I / O pins, they may include any conductive nodes, such as commonly used conductive pads or conductive bumps, that enable electrical connection to the memory device 130 via an external device (e.g., the memory subsystem controller 115).

[0061] Those skilled in the art will understand that additional circuitry and signals can be provided, and the system has been simplified. Figure 1B The memory device 130. It should be understood that, reference Figure 1B The functionality of the various block components described need not be separated from the different components or component portions of the integrated circuit device. For example, a single component or component portion of the integrated circuit device may be adapted to perform... Figure 1B The functionality of more than one block component. Alternatively, one or more components or component portions of an integrated circuit device can be combined to perform... Figure 1B The functionality of a single block component. Furthermore, while specific I / O pins are described according to popular conventions for the reception and output of various signals, it should be noted that combinations of other I / O pins (or other I / O node structures) or other numbers of I / O pins (or other I / O node structures) may be used in various embodiments.

[0062] Figures 2A to 2C For example, it can be used as part of the memory cell array 104 according to the embodiment in reference. Figure 1B A schematic diagram of a portion of a memory cell array 200A, such as a NAND memory array, used in the described type of memory. The memory array 200A includes, for example, word lines 2020 to 202. N Access lines and, for example, bit lines 2040 to 204M The data line. Word line 202 can be coupled to a many-to-one relationship. Figure 2A Global access lines (e.g., global word lines) not shown in the diagram. In some embodiments, the memory array 200A may be formed over a semiconductor, for example, conductively doped to have a conductivity type, such as p-type conductivity, for example, to form a p-well, or n-type conductivity, for example, to form an n-well.

[0063] The memory array 200A can be arranged in rows (each row corresponds to word lines 202) and columns (each column corresponds to bit lines 204). Each column can contain a string of memory cells connected in series (e.g., non-volatile memory cells), such as NAND strings 2060 to 206. M One of them. Each NAND string 206 may be connected (e.g., selectively connected) to a common source (SRC) 216 and may contain memory cells 2080 to 208. N Memory cell 208 may represent a non-volatile memory cell used for storing data. The memory cells 208 of each NAND string 206 may be connected in series between select gate 210 (e.g., a field-effect transistor) and select gate 212 (e.g., a field-effect transistor), the select gates being, for example, select gates 2100 to 210. M One of them (for example, it may be a source-select transistor, commonly referred to as a select-gate-source), and the select gate is, for example, select gate 2120 to 212. M One of them (for example, it could be a drain-select transistor, often referred to as a select-gate drain). Select gate 2100 to 210 M They can be commonly connected to select line 214, such as source select line (SGS), and select gates 2120 to 212. M They can be connected together to select line 215, such as drain select line (SGD). Although depicted as conventional field-effect transistors, select gates 210 and 212 can utilize a structure similar to (e.g., identical to) memory cell 208. Select gates 210 and 212 can represent a plurality of select gates connected in series, each selected gate configured in series to receive the same or independent control signals.

[0064] The source of each select gate 210 can be connected to a common source 216. The drain of each select gate 210 can be connected to a memory cell 2080 in the corresponding NAND string 206. For example, the drain of select gate 2100 can be connected to a memory cell 2080 in the corresponding NAND string 2060. Therefore, each select gate 210 can be configured to selectively connect the corresponding NAND string 206 to the common source 216. The control gate of each select gate 210 can be connected to a select line 214.

[0065] The drain of each select gate 212 can be connected to a bit line 204 for the corresponding NAND string 206. For example, the drain of select gate 2120may be connected to bit line 2040for the corresponding NAND string 2060. The source of each select gate 212 can be connected to a memory cell 208 in the corresponding NAND string 206 N . For example, the source of select gate 2120may be connected to memory cell 208 N of the corresponding NAND string 2060. Thus, each select gate 212 can be configured to selectively connect the corresponding NAND string 206 to the corresponding bit line 204. The control gate of each select gate 212 can be connected to a select line 215.

[0066] Figure 2A The memory array 200A in Figure 1A can be a quasi-two-dimensional memory array and can have a substantially planar structure, e.g., where the common sources 216, NAND strings 206, and bit lines 204 extend on a substantially parallel plane. Alternatively, Figure 2A The memory array 200A in Figure 1A can be a three-dimensional memory array, e.g., where the NAND strings 206 can extend substantially perpendicular to a plane containing the common sources 216 and a plane containing the bit lines 204 can extend substantially parallel to the plane containing the common sources 216.

[0067] A typical construction of a memory cell 208 includes a data storage structure 234 (e.g., a floating gate, charge trap, etc.) that can determine a data state of the memory cell (e.g., by a change in threshold voltage) and a control gate 236, as shown in Figure 1A. The data storage structure 234 can include both conductive structures and dielectric structures, while the control gate 236 is typically formed of one or more conductive materials. In some cases, the memory cell 208 can further have a defined source / drain (e.g., source) 230 and a defined source / drain (e.g., drain) 232. The memory cell 208 has its control gate 236 connected to (and in some cases formed by) a word line 202. Figure 2A

[0068] A column of memory cells 208 can be a NAND string 206 or a number of NAND strings 206 that are selectively connected to a given bit line 204. A row of memory cells 208 can be memory cells 208 that are commonly connected to a given word line 202. A row of memory cells 208 can include, but need not include, all of the memory cells 208 that are commonly connected to a given word line 202. Rows of memory cells 208 can generally be divided into one or more groups of physical pages of memory cells 208, and a physical page of memory cells 208 generally includes every other memory cell 208 that is commonly connected to a given word line 202. For example, the memory cells 208 N ​and selectively connected to even bit lines 204 (e.g., bit lines 2040, 2042, 2044, etc.) can be one physical page of memory cells 208 (e.g., even memory cells), while those commonly connected to word lines 202 N and selectively connected to odd bit lines 204 (e.g., bit lines 2041, 2043, 2045, etc.) can be another physical page of memory cells 208 (e.g., odd memory cells).

[0069] Although not explicitly depicted in Figure 2A , it is apparent from the figures that bit lines 204 of memory cell array 200A can be numbered consecutively from bit line 2040 to bit line 204 M . Other groupings of memory cells 208 commonly connected to a given word line 202 can also define physical pages of memory cells 208. For certain memory devices, all memory cells commonly connected to a given word line can be considered a physical page of memory cells. Portions of a physical page of memory cells (which can still be an entire row in some embodiments), such as an upper or lower page of memory cells, that are read during a single read operation or programmed during a single program operation can be considered a logical page of memory cells. A block of memory cells can include those memory cells configured to be erased together, such as all memory cells connected to word lines 2020-202 N . Unless explicitly distinguished, references to a page of memory cells herein refer to memory cells of a logical page of memory cells. Although examples are discussed in connection with NAND flash, the embodiments and concepts described herein are not limited to a particular array architecture or structure, and can include other structures (e.g., SONOS, phase change, ferroelectric, etc.) and other architectures (e.g., AND array, NOR array, etc.). Figure 2A

[0070] Figure 2B Another schematic diagram of a portion of a memory cell array 200B, such as can be used in a memory of the type described in reference to Figure 1B . Like-numbered elements in Figure 2B correspond to the description provided in reference to Figure 2A . Figure 2B ​Additional details are provided of one example of a three-dimensional NAND memory array structure. Three-dimensional NAND memory array 200B can incorporate vertical structures that can include semiconductor pillars, where portions of the pillars can act as channel regions of memory cells of NAND strings 206. NAND strings 206 can each be selectively connected to bit lines 2040to 204 M through select transistors 212 (e.g., which can be drain select transistors, commonly referred to as select gate drains) and to a common source 216 through select transistors 210 (e.g., which can be source select transistors, commonly referred to as select gate sources). Multiple NAND strings 206 can be selectively connected to the same bit line 204. Subsets of NAND strings 206 can be connected to their respective bit lines 204 through biasing select lines 2150to 215 K to selectively activate particular select transistors 212 each between a NAND string 206 and a bit line 204. Select transistors 210 can be activated through biasing select lines 214. Each word line 202 can be connected to multiple rows of memory cells of memory array 200B. Rows of memory cells commonly connected to each other through a particular word line 202 can be commonly referred to as a tier.

[0071] Figure 2C Another schematic diagram of portions of a memory cell array 200C that can be used, for example, in a memory of the type described in reference to Figure 1B Memory Cell Array 200C Figure 2C The same numbered elements in FIG. 15 correspond to the description provided as to Figure 2A Memory Cell Array 200C can incorporate series-connected memory cell strings (e.g., NAND strings) 206, access (e.g., word) lines 202, data (e.g., bit) lines 204, select lines 214 (e.g., source select lines), select lines 215 (e.g., drain select lines), and sources 216 as depicted in Figure 2A

[0072] Figure 2C Depictions of grouping NAND strings 206 into memory cell blocks 250, such as memory cell blocks 2500to 250 L Memory cell blocks 250 can be groupings of memory cells 208 that can be erased together in a single erase operation, sometimes referred to as erase blocks. Each memory cell block 250 can represent those NAND strings 206 that are commonly associated with a single select line 215, such as select line 2150. Sources 216 of memory cell block 2500may be the same sources 216 as sources 216 of memory cell block 250 L For example, each memory cell block 2500to 250​L The source 216 can be selectively commonly connected to the access lines 202. The access lines 202 and the select lines 214 and 215 of one memory cell block 250 are respectively commonly connected to the memory cell blocks 2500 to 250 L The access lines 202 and the select lines 214 and 215 of any other memory cell block can not have a direct connection.

[0073] The bit lines 2040 to 204 M may be connected (e.g., selectively connected) to a buffer portion 240, which can be part of a page buffer 152 of the memory device 130. The buffer portion 240 can correspond to a memory plane (e.g., a set of memory cell blocks 2500 to 250 L The buffer portion 240 can include sensing circuitry (which can include a sense amplifier) for sensing data values indicated on the respective bit lines 204.

[0074] Figure 3 is a schematic block diagram of a portion of a memory cell array 300 as can be used in a memory of the type described with reference to Figure 1B The memory cell array 300 is depicted as having four memory planes 350 (e.g., memory planes 3500 to 3503), each in communication with a respective buffer portion 240, which can collectively form a page buffer 352. While four memory planes 350 are depicted, other numbers of memory planes 350 can collectively be in communication with the page buffer 352. Each memory plane 350 is depicted as including L+1 memory cell blocks 250 (e.g., memory cell blocks 2500 to 250 L ).

[0075] Figure 4 Example program distributions 401, 402 (program distribution N and program distribution N+1) to be calibrated according to an integrated calibration command are illustrated in accordance with embodiments of the disclosure. In embodiments, the integrated calibration command is issued by processing logic of a memory subsystem (e.g., the calibration manager 134 of the memory subsystem controller 115 of Figure 1A and Figure 1B In embodiments, the integrated calibration command is received by processing logic of a local media controller (e.g., the calibration manager 136 of the local media controller 135 of Figure 1A and Figure 1B In the illustrated example, the set of read operations includes a default read voltage (Vread0) and an additional set of read operations at various offsets or intervals within a voltage range relative to the default read voltage. In the illustrated example, the integrated calibration command causes a plurality of read operations or a set of read voltage

[0076] In embodiments, the additional set of read operations includes a first set of one or more read voltage strobes at one or more read voltage levels lower than the first read voltage level (e.g., Vref -1 , Vref -2 …Vref -N ; where N is any suitable integer) and a second set of one or more read voltage strobes at one or more read voltage levels higher than the first read voltage level (e.g., Vref1, Vref2…Vref M ; where M is any suitable, integer). In embodiments, one or more of N and M can have a value of 1, 2, etc.

[0077] In Figure 4 instances, the set of read operations includes a first set of one or more lower offset read strobes (e.g., Vread -2 , Vread -1 ) and a second set of one or more higher offset read strobes (e.g., Vread1 and Vread2). For example, a predefined interval or offset value (e.g., 0.3V, 0.5V, etc.) can be set and used to define the read voltage levels of Vread -2 , Vread -1 , Vread1 and Vread2 such that each read voltage level is separated by the predefined interval or offset value. In an instance, at an offset value of 0.3V, Vread0 can be set to 1.5V, Vread -1 can be set to 1.2V, Vread -2 can be set to 0.9V, Vread1 can be set to 1.8V, and Vread2 can be set to 2.1V to establish a read voltage range of 0.9V to 2.1V.

[0078] In embodiments, a set of buckets or bins 410 associated with the set of read voltage strobes is identified. In embodiments, each bin is defined by one or more portions of the programming distribution corresponding to a voltage range between two adjacent read voltage strobes. In the instance shown in Figure 4 , a first bin (Bin 1) is established between Vread -2 and Vread -1 , a second bin (Bin 2) is established between Vread -1 and Vread0, a third bin (Bin 3) is established between Vread0 and Vread1, and a fourth bin (Bin 4) is established between Vread1 and Vread2.

[0079] In embodiments, as Figure 4As explained, in response to a read operation caused by an integrated calibration command, a bit count is determined for each item in the identified compartment 410. For example, as described by... Figure 4 The example histogram illustrates how the memory bit count corresponding to each bin is determined. As shown, bin 1 has a first bit count, bin 2 has a second bit count, bin 3 has a third bit count, and bin 4 has a fourth bit count. In embodiments, the bit count information associated with each bin can be represented in any suitable format or data structure (e.g., tabular format, histogram format, etc.). In embodiments, the bit count report for each bin (e.g., in histogram format) can be sent to the memory subsystem controller for further processing, as described herein.

[0080] In an embodiment, the processing logic (e.g., Figure 1A The calibration manager 134, 136 of the local media controller 135 or memory subsystem controller 115 determines which memory set 410 has the lowest or minimum bit count (i.e., the memory set 410 with the fewest number of programming cells or voltage range). The memory set with the lowest bit count is identified as the valley center memory set indicating the valley portion relative to the default read voltage level (Vread0). Figure 4 In the example shown, bin 2 is identified as the valley center bin because it has the lowest number of bits among bins 410 (e.g., bins 1, 2, 3, and 4). In this embodiment, the identified valley center bin indicates the location or position of the optimal or adjusted read voltage level for calibration purposes. In this embodiment, multiple read operations are performed before determining reliability metrics (e.g., RBER or RWB), determining the bit counts of the various bins 410, and identifying the valley center bin in response to an integrated calibration command.

[0081] In the embodiment, the identified valley value center warehouse (e.g., Figure 4 The valley center warehouse (2) is used to determine whether it corresponds to a sufficient valley tolerance. In an embodiment, the bit count of the valley center warehouse is compared with a valley tolerance threshold to determine whether condition 420 is met. In an embodiment, if the memory bit count of the valley center warehouse is less than the valley tolerance threshold, then condition 420 is met (i.e., the valley check passes). In an embodiment, the valley tolerance check is used to determine whether the valley center warehouse represents an acceptable valley tolerance to be identified as the optimal valley for identifying the adjusted read voltage level.

[0082] In an embodiment, if condition 420 is met and the bit count of the valley center bin is below the valley tolerance threshold, then the adjusted read voltage level associated with the valley center bin can be identified. Figure 4 In the example shown, the read voltage level can be adjusted to the voltage associated with bay 2, such as Vread. -1a voltage within a range of Vread0. In an embodiment, the adjusted read voltage level can be a voltage associated with Vread -1 an average value or average voltage associated with the range of Vread0. In an embodiment, the adjusted read voltage level can be Vread -1 a midpoint or center voltage value within the range of Vread0. In an embodiment, the result of the valley value margin check can be generated by processing logic of a calibration manager of the local media controller and provided to the memory sub-system controller for identifying the adjusted read voltage level in the event of a pass of the valley check.

[0083] In an embodiment, processing logic of a calibration manager of the local media controller can determine an adjusted read voltage level associated with an identified valley center bin that passed the valley check, providing an indication of the adjusted read voltage level to the memory sub-system controller. In an embodiment, if the valley check fails (i.e., the bit count of the identified valley center bin is greater than or equal to the valley margin threshold), then the data is determined to be unreliable and the data is to be refreshed.

[0084] Figure 5 Example program distributions 501, 502 (program distribution N and program distribution N+1) to be calibrated according to an integrated calibration command are illustrated in accordance with another embodiment of the disclosure. Similar to the process illustrated in Figure 4 the integrated calibration command is issued to cause a plurality of read operations to be generated using a set of read voltage levels 505 within a voltage range. As shown, the set of read operations uses read strobes 505 having read voltage levels Vread -2 , Vread -1 , Vread0, Vread1, and Vread2. As described above, a set of bins 510 (bin 1, bin 2, bin 3, and bin 4) corresponding to one or more program distributions between each adjacent pair of read voltage levels are identified. In the example shown in Figure 5 , a first bin (bin 1) is established between Vread -2 and Vread -1 , a second bin (bin 2) is established between Vread -1 and Vread0, a third bin (bin 3) is established between Vread0 and Vread1, and a fourth bin (bin 4) is established between Vread1 and Vread2.

[0085] In response to the integrated calibration command, processing logic of the local media controller (e.g., the calibration manager 134 of FIG. 1) determines a bit count for each of the bins in the set of bins 510. The respective bit counts corresponding to the set of bins 510 are compared to one another to identify a bin having a lowest relative bit count, which is identified as a valley center bin.

[0086] A valley center bin (e.g., bin 2 in Figure 5 According to embodiments, the processing logic performs a valley check 515 based on the valley center bin and an aggregate number of bits of one or more neighboring bins. In this embodiment, the respective bit counts of the one or more additional bins are added to the bit count of the valley center bin to determine an aggregate bit count 515. In embodiments, the valley check is performed at 520 using the aggregate bit count to determine whether sufficient valley margin is detected. In embodiments, the aggregate bit count (e.g., a sum of the bit count of bin 1, the bit count of bin 2 (the valley center bin), the bit count of bin 3) is compared to a valley margin threshold to determine whether the condition 520 is satisfied. In embodiments, the condition 520 is satisfied (i.e., the valley check passes) if the aggregate bit count is less than the valley margin threshold. In this example, a first neighboring bin corresponding to a lower voltage range relative to the valley center bin and a second neighboring bin corresponding to a higher voltage range relative to the valley center bin are selected. It should be noted that any suitable number of neighboring bins can be used to determine the aggregate bit count. In embodiments, an asymmetric set of neighboring bins (e.g., where the number of bins to the left of the valley center bin is not equal to the number of bins to the right of the valley center bin) is selected for determining the aggregate bit count.

[0087] In embodiments, as Figure 5 shown, if the valley check passes (i.e., the aggregate memory bit count is less than the valley margin threshold), an adjusted read voltage level associated with the valley center bin is identified and used for further calibration processing. As Figure 5 shown, if the valley center bin fails the valley check (i.e., the aggregate memory bit count is greater than or equal to the valley margin threshold), it is deemed that the data is unreliable and a refresh operation is performed. Advantageously, the valley check associated with the identified valley center bin determines can be used to provide an indication or hint regarding the estimated valley location and associated read voltage level to the memory subsystem controller for calibration processes without placing a large amount of traffic on the communication interface (e.g., ONFI related traffic).

[0088] Figure 6 A flow diagram of an example method for performing an integrated calibration command to generate an indication of a valley center location of an adjusted read voltage level for calibration according to a programming distribution associated with a memory device according to one or more embodiments of the disclosure. The method 600 can be performed by processing logic that can comprise hardware (e.g., processing device, circuitry, dedicated logic, programmable logic, microcode, hardware of a device, integrated circuit, etc.), software (e.g., instructions run or executed on a processing device), or a combination thereof. In some embodiments, the method 600 is performed by Figure 1A and 1Bby the calibration manager 134. Although shown in a particular sequence or order, unless otherwise specified, the order of the processes can be modified. Thus, the illustrated embodiments should be understood only as examples, and the illustrated processes can be performed in a different order, and some processes can be performed in parallel. Additionally, one or more processes can be omitted in various embodiments. Thus, not all processes are required in every embodiment. Other process flows are possible.

[0089] At operation 610, a command is issued. For example, processing logic (e.g., calibration manager 134) can issue an integrated calibration command to cause a set of read operations to be performed at a plurality of read voltage levels corresponding to a programming distribution associated with a memory device. In an embodiment, the set of read operations includes applying a plurality of read voltage gating at a set of read voltage levels. In an embodiment, the set of read voltage levels includes a default or initial read voltage level (Vread0), a set of one or more lower offset read voltage levels (e.g., Vread -1 or Vread -1 to Vread -N ), and a set of one or more higher offset read voltage levels (e.g., Vread1 or Vread1 to Vread M ). In an embodiment, the set of one or more lower offset read voltage levels includes read levels that are lower voltages relative to the default read voltage level (Vread0). For example, Vread -1 may equal Vread0 - V offset ; Vread -2 may equal Vread0 - (2 x V offset ), and so on, where V offset is a predetermined or preset offset voltage value (e.g., 0.1V, 0.2V, 0.3V, etc.). In an embodiment, the set of one or more higher offset read voltage levels includes read levels that are higher voltages relative to the default read voltage level (Vread0). For example, Vread1 may offset equal Vread0 + V offset ; Vread2 may equal Vread0 + (2 x V -1 ), and so on.

[0090] At operation 620, memory bit counts are determined. For example, processing logic can determine a set of memory bit counts, where each memory bit count corresponds to a respective bin in a set of bins between a respective pair of read voltage levels in the plurality of read voltage levels. In an embodiment, a bin is defined as a portion of one or more programming distributions between each adjacent pair of read voltage levels of a read operation. For example, for a set of read voltage levels including Vread0, Vread -1 , Vread -2a set of read operations of read levels of Vreadl and Vread2, between Vread -2 and Vread -1 identifies a first bin, between Vread -1 and Vread0 identifies a second bin, between Vread0 and Vreadl identifies a third bin, and between Vreadl and Vread2 identifies a fourth bin. In embodiments, a count of memory bits within each respective bin is determined.

[0091] At operation 630, a valley center is derived. For example, processing logic can identify a valley center bin having a smallest memory bit count of a set of memory bit counts. In embodiments, the set of memory bit counts are compared to determine which bin has the lowest relative bit count. The bin having the lowest bit count is identified as the valley center bin representing an estimated positioning or location of the valley portion relative to a default read voltage level (Vread0). In embodiments, a representation (e.g., histogram, table, etc.) of the bit counts associated with the set of bins can be generated and provided by the local media controller to the memory sub-system controller for further processing.

[0092] At operation 640, a determination is made. For example, processing logic can perform a valley check operation to determine whether the smallest memory bit count of the valley center bin satisfies a condition. In embodiments, the condition is satisfied when the smallest memory bit count of the valley center bin is less than a valley margin threshold. In embodiments, the valley check operation is used to determine whether the identified valley center bin has a sufficient level of valley margin to provide a reliable data metric (e.g., RWB or RBER reliability).

[0093] In another embodiment, as shown in Figure 5 , the valley check operation can be performed using an aggregate memory bit count associated with the valley center bin and one or more neighboring bins. For example, a first memory bit count of the valley center bin (e.g., bin 2 in Figure 5 ) can be added to a second memory bit count of a neighboring lower offset bin (e.g., bin 1 in Figure 5 ) and a third memory bit count of a neighboring higher offset bin (e.g., bin 3 in Figure 5 ) to produce an aggregate memory bit count. The aggregate memory bit count can then be compared to a valley margin threshold to determine whether the condition is satisfied (e.g., pass or fail the valley check).

[0094] At operation 650, a read voltage level is identified. For example, processing logic can identify an adjusted read voltage level associated with the valley center bin in response to the condition being satisfied. In embodiments, the adjusted read voltage level is a voltage within a voltage range associated with the valley center bin. For example, as shown in Figure 4The adjusted voltage level can be Vread0 -1 and Vread0. In an embodiment, the adjusted voltage level can be a midpoint or average of the voltages in the range associated with the valley center bin (e.g., a midpoint between Vread0 and Vread -1 In an embodiment, the adjusted read voltage level can be identified by processing logic of the memory sub-system controller based on memory count and valley check information provided by the local media controller. In an embodiment, the adjusted read voltage level can be identified by processing logic of the local media controller, which in turn provides information identifying the adjusted rad voltage level to the memory sub-system controller to be used as a new or updated default read voltage level in subsequent scan operations.

[0095] Advantageously, process 600 implements an integrated (single) command that sets an adjusted read voltage level for calibration of a memory device using a minimized latency of data integrity scan commands compared to a typical calibration process. According to an embodiment, operations 610, 620, 630, 640, and 650 are performed in response to the integrated calibration command. In this regard, to more efficient calibration processing, the number of commands issued to the memory device is minimized. Further, the reduced latency can be leveraged to expand the read voltage search window, which can further reduce calibration scan inefficiencies. The reduced latency further allows for an accelerated calibration scan rate without impacting performance or quality of service metrics.

[0096] Figure 7 An example machine of a computer system 700, within which a set of instructions for causing the machine to perform any one or more of the methodologies discussed herein can be executed, is illustrated in FIG. 7. In some embodiments, the computer system 700 can correspond to a host system (e.g., the host system 120 of FIG. 1) that includes, is coupled to, or utilizes a memory sub-system (e.g., the memory sub-system 110 of FIG. 1) or can be used to perform operations of a controller (e.g., execute an operating system to perform operations corresponding to the calibration manager 134 of FIG. 1). In alternative embodiments, the machine can be connected (e.g., networked) to other machines in a LAN, an intranet, an extranet, and / or the Internet. The machine can operate in the capacity of a peer machine or a server or a client machine in client-server network environments. The machine can be a personal computer (PC), a tablet PC, a set-top box (STB), a

[0097] The machine can be a personal computer (PC), a tablet PC, a set-top box (STB), a personal digital assistant (PDA), a cellular telephone, a web appliance, a server, a network router, a switch or bridge, or any machine capable of executing a set of instructions (sequential or otherwise) that specify actions to be taken by that machine. Further, while a single machine is illustrated, the term "machine" shall also be taken to include any collection of machines that individually or jointly execute a set (or multiple sets) of instructions to perform any one or more of the methodologies discussed herein.

[0098] The example computer system 700 includes a processing device 702, a main memory 704 (e.g., read-only memory (ROM), flash memory, dynamic random access memory (DRAM) such as synchronous DRAM (SDRAM) or Rambus DRAM (RDRAM), etc.), a static memory 706 (e.g., flash memory, static random access memory (SRAM), etc.), and a data storage system 718, which communicate with each other via a bus 730.

[0099] Processing device 702 represents one or more general -purpose processing devices such as a microprocessor, central processing unit, or the like. More particularly, the processing device can be complex instruction set computing (CISC) microprocessor, reduced instruction set computing (RISC) microprocessor, very long instruction word (VLIW) microprocessor, or processor implementing other instruction sets, or processors implementing a combination of instruction sets. Processing device 702 can also be one or more special-purpose processing devices such as an application specific integrated circuit (ASIC), a field programmable gate array (FPGA), a digital signal processor (DSP), network processor, or the like. The processing device 702 is configured to execute instructions 726 for performing the operations and steps discussed herein. The computer system 700 can further include a network interface device 708 to communicate over the network 720.

[0100] The data storage system 718 can include a machine-readable storage medium 724 (also known as a computer-readable medium, e.g., a non-transitory computer-readable medium) on which is stored one or more sets of instructions 726 or software embodying any one or more of the methodologies or functions described herein. The instructions 726 can also reside, completely or at least partially, within the main memory 704 and / or within the processing device 702 during execution thereof by the computer system 700, the main memory 704 and the processing device 702 also constituting machine-readable storage media. The machine-readable storage medium 724, data storage system 718, and / or main memory 704 can correspond to the memory sub-system 110 of FIG. 1.

[0101] In one embodiment, the instructions 726 include instructions to implement functionality corresponding to the calibration manager 134 of FIG. 1. Although the machine- readable medium 724 is illustrated in an example embodiment to be a single medium, the term "machine-readable medium" should be taken to include a single medium or multiple media that store one or more sets of instructions. The term "machine-readable medium" shall also be taken to include any medium that is capable of storing or encoding a set of instructions for execution by the machine and that cause the machine to perform any one or more of the methodologies of the present disclosure. The term "machine-readable medium" shall accordingly be taken to include, but not be limited to, solid-state memories, optical media, and magnetic media.

[0102] Some portions of the preceding detailed descriptions have been presented in terms of algorithms and symbolic representations of operations on data bits within a computer memory. These

[0103] It should be borne in mind, however, that all of these and similar terms are to be associated with the appropriate physical quantities and are merely convenient labels applied to these quantities. The present disclosure can refer to the action and processes of a computer system, or similar electronic computing device, that manipulates and transforms data represented as physical (electronic) quantities within the computer system's registers and memories into other data similarly represented as physical quantities within the computer system memories or registers or other such information storage systems.

[0104] The present disclosure also relates to an apparatus for performing the operations herein. This apparatus can be specially constructed for the intended purposes, or it can include a general purpose computer selectively activated or reconfigured by a computer program stored in the computer. Such a computer program can be stored in a computer readable storage medium, such as, but not limited to, any type of disk including floppy disks, optical disks, CD-ROMs, and magnetic-optical disks, read-only memories (ROMs), random access memories (RAMs), EPROMs, EEPROMs, magnetic or optical cards, or any type of media suitable for storing electronic instructions, each coupled to a computer system bus.

[0105] The algorithms and displays presented herein are not inherently related to any particular computer or other apparatus. Various general purpose systems can be used with programs in accordance with the teachings herein, or it can prove convenient to construct more specialized apparatus to perform the methods of the present disclosure. The structure for a variety of these systems will appear as described in the description below. In addition, the present disclosure is not described with reference to any particular programming language. It will be appreciated that a variety of programming languages can be used to implement the teachings of the present disclosure as described herein.

[0106] The present disclosure can be provided as a computer program product, or software, that can include a machine-readable medium having stored thereon instructions that can be used to program a computer system (or other electronic devices) to perform a process according to the present disclosure. A machine-readable medium includes any mechanism for storing information in a form accessible by a machine (e.g., a computer). In some embodiments, a machine- readable (e.g., computer-readable) medium includes a machine (e.g., a computer) readable storage medium such as read only memory ("ROM"), random access memory ("RAM"), magnetic disk storage media, optical storage media, flash memory components, etc.

[0107] In the foregoing specification, embodiments of the present disclosure have been described with reference to specific examples thereof. It will be evident that various modifications can be made thereto without departing from the broader spirit and scope of embodiments of the present disclosure as set forth in the following claims. The present disclosure is not to be limited to the specific examples thereof.

Claims

1. A memory device comprising: A memory array, which comprises a set of memory cells; and Processing logic, operatively coupled to the memory array, performs operations including: Receive commands from the memory subsystem controller to perform a set of read operations at multiple read voltage levels corresponding to the programming distribution associated with the memory device; In response to the command, a set of memory bit counts is determined, wherein each memory bit count corresponds to a corresponding bin in a set of bins associated with the plurality of read voltage levels of the set of read operations; In response to the command, identify the valley center warehouse with the smallest memory bit count in the set of memory bit counts; In response to the command, it is determined that the minimum memory bit count of the valley value center warehouse meets a condition, wherein the condition is met when the minimum memory bit count of the valley value center warehouse is less than the valley value tolerance threshold. and In response to the command, and in response to the fulfillment of the condition, the adjusted read voltage level associated with the valley value center warehouse is identified.

2. The memory device of claim 1, wherein the operation further comprises: The aggregated memory bit count is determined based on the minimum memory bit count of the valley value center warehouse and one or more additional memory bit counts associated with one or more additional warehouses.

3. The memory device of claim 2, wherein the operation further comprises comparing the aggregated memory bit count with a valley tolerance threshold to determine whether the condition is met.

4. The memory device of claim 1, wherein each of the memory locations corresponds to a portion of one or more programming distributions between adjacent read voltage level pairs of the plurality of read voltage levels.

5. The memory device of claim 1, the operation further comprising sending information identifying the adjusted read voltage level to the memory subsystem controller, wherein the memory subsystem controller applies the adjusted read voltage level in a subsequent calibration scan associated with the memory device.

6. The memory device of claim 1, wherein the plurality of read voltage levels includes a default read voltage level, one or more lower offset read voltage levels, and one or more higher offset read voltage levels.

7. A method comprising: Receive commands from the memory subsystem controller to perform a set of read operations at multiple read voltage levels corresponding to the programming distribution associated with the memory device; Determine a set of memory bit counts, wherein each memory bit count corresponds to a corresponding bin in a set of bins associated with the plurality of read voltage levels of the set of read operations; Identify the valley center warehouse with the smallest memory bit count in the set of memory bit counts; The minimum memory bit count of the valley value center warehouse is determined to meet the condition, wherein the condition is met when the minimum memory bit count of the valley value center warehouse is less than the valley value tolerance threshold. and In response to the fulfillment of the stated conditions, an adjusted read voltage level associated with the valley center warehouse is identified.

8. The method of claim 7, further comprising determining an aggregated memory bit count based on the minimum memory bit count of the valley center warehouse and one or more additional memory bit counts associated with one or more additional warehouses.

9. The method of claim 8, further comprising comparing the aggregated memory bit count with a valley tolerance threshold to determine whether the condition is met.

10. The method of claim 7, wherein each of the collection bins corresponds to a portion of one or more programmed distributions between adjacent pairs of read voltage levels in the plurality of read voltage levels.

11. The method of claim 7, further comprising sending information identifying the adjusted read voltage level to the memory subsystem controller, wherein the memory subsystem controller applies the adjusted read voltage level in a subsequent calibration scan associated with the memory device.

12. A non-volatile computer-readable medium comprising instructions that, when executed by a processing means, cause the processing means to perform an operation comprising the following steps: A memory array, which comprises a set of memory cells; and Processing logic, operatively coupled to the memory array, performs operations including: Receive commands from the memory subsystem controller to perform a set of read operations at multiple read voltage levels corresponding to the programming distribution associated with the memory device; In response to the command, a set of memory bit counts is determined, wherein each memory bit count corresponds to a corresponding bin in a set of bins associated with the plurality of read voltage levels of the set of read operations; In response to the command, identify the valley center warehouse with the smallest memory bit count in the set of memory bit counts; In response to the command, it is determined that the minimum memory bit count of the valley value center warehouse meets a condition, wherein the condition is met when the minimum memory bit count of the valley value center warehouse is less than the valley value tolerance threshold. and In response to the command, and in response to the fulfillment of the condition, the adjusted read voltage level associated with the valley value center warehouse is identified.

13. The non-volatile computer-readable medium of claim 12, wherein the operation further comprises: The aggregated memory bit count is determined based on the minimum memory bit count of the valley value center warehouse and one or more additional memory bit counts associated with one or more additional warehouses.

14. The non-volatile computer-readable medium of claim 13, the operation further comprising comparing the aggregated memory bit count with a valley tolerance threshold to determine whether the condition is met.

15. The non-volatile computer-readable medium of claim 12, wherein each of the bins in the bin set corresponds to a portion of one or more programmed distributions between adjacent pairs of read voltage levels in the plurality of read voltage levels.

16. The non-volatile computer-readable medium of claim 12, the operation further comprising sending information identifying the adjusted read voltage level to the memory subsystem controller, wherein the memory subsystem controller applies the adjusted read voltage level in a subsequent calibration scan associated with the memory device.

17. The non-volatile computer-readable medium of claim 12, wherein the plurality of read voltage levels includes a default read voltage level, one or more lower offset read voltage levels, and one or more higher offset read voltage levels.

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