Multiplane switching of non-volatile memory

Abstract

This disclosure relates to multi-plane switching of non-volatile memory. One method includes transferring data out of a first buffer of a first plane coupled to a plurality of planes of a memory component, wherein the data was previously transferred from the first plane to the first buffer in response to an access request sensing data stored in the plurality of planes of the memory component. The method further includes, after transferring the data out of the first buffer and independently of a command from a processing device, transferring data out of a second buffer of a second plane coupled to the plurality of planes of the memory component, wherein the data transferred out of the second buffer was previously transferred from the second plane to the second buffer in response to the access request.

Description

Technical Field

[0001] Embodiments of this disclosure generally relate to memory subsystems, and more specifically, to multiplane switching of nonvolatile memory. Background Technology

[0002] The memory subsystem may include one or more memory devices for storing data. The memory devices may be, for example, non-volatile memory devices and volatile memory devices. Generally, a host system may utilize the memory subsystem to store data at the memory devices and retrieve data from the memory devices. Summary of the Invention

[0003] In one aspect, this disclosure provides a method for performing multi-plane sensing operations, comprising: transferring data from a first buffer of a first plane coupled to a plurality of planes of a memory component, wherein the data was previously transferred from the first plane to the first buffer in response to an access request for sensing data stored in the plurality of planes of the memory component; and, after transferring the data from the first buffer and independently of a command from a processing device, transferring data from a second buffer of a second plane coupled to the plurality of planes of the memory component, wherein the data transferred from the second buffer was previously transferred from the second plane to the second buffer in response to the access request.

[0004] In another aspect, this disclosure further provides a system for performing multi-plane sensing operations, comprising: a memory component having a plurality of planes; and a processing means operatively coupled to the memory component such that the memory component: transfers data out of a first buffer, wherein the data was previously transferred from a page of a first plane in the plurality of planes to the first buffer in response to an access request for sensing data stored in the plurality of planes; and transfers data out of the first buffer in response to a portion of the data corresponding to the last column address of the page, independently of a command from the processing means, transfers data out of a second buffer, wherein the data transferred out of the second buffer was previously transferred from a page of a second plane in the plurality of planes to the second buffer in response to the access request.

[0005] In another aspect, this disclosure further provides a non-transitory computer-readable storage medium including instructions for performing a multiplane sensing operation, the instructions, when executed by a processing means, causing the processing means to: enable a configuration associated with performing a multiplane read operation on a memory component such that the memory component reads data from a plurality of planes of the memory component according to the enabled configuration to perform the multiplane read operation; wherein the enabled configuration causes the memory component, in response to receiving an access request to perform the multiplane read operation, to: transfer data out of a first cache register coupled to a first plane of the plurality of planes, wherein the data was previously transferred from the first plane to the first cache register in response to the access request; and after the data is transferred out of the first cache register, to transfer data out of a second cache register independently of a command to transfer data out of a second cache register coupled to a second plane of the plurality of planes. Attached Figure Description

[0006] This disclosure will be more fully understood in light of the detailed description provided below and the accompanying drawings of various embodiments thereof.

[0007] Figure 1 This describes an example computing system including a memory subsystem according to some embodiments of the present disclosure.

[0008] Figure 2 This document describes example timing diagrams associated with performing multi-plane read operations according to some embodiments of the present disclosure.

[0009] Figure 3 A block diagram illustrating a memory array and registers coupled to the memory array according to some embodiments of the present disclosure.

[0010] Figure 4 This is a flowchart corresponding to a method for multiplane sensing of a non-volatile memory according to some embodiments of the present disclosure.

[0011] Figure 5 This is a block diagram of an example computer system in which embodiments of the present disclosure can be operated. Detailed Implementation

[0012] This disclosure relates to multiplane switching of non-volatile memory, and more specifically, to a memory subsystem comprising multiplane operating components such that memory components transfer data out of cache registers coupled to the respective planes, as part of the execution of multiplane sensing (e.g., read) operations. The memory subsystem may be a storage system, a storage device, a memory module, or a combination thereof. An example of a memory subsystem is a storage system such as a solid-state drive (SSD). The following is combined with… Figure 1 And other diagrams illustrating examples of storage devices and memory modules. Generally, a host system may utilize a memory subsystem that contains one or more components (such as memory devices) for storing data. The host system can provide data to be stored in the memory subsystem and can request retrieval of data from the memory subsystem.

[0013] The memory device can be a non-volatile memory device. An example of a non-volatile memory device is a NAND flash memory device (also known as flash memory). The following section combines... Figure 1 Other examples of non-volatile memory devices are described below. A non-volatile memory device is a package of one or more dies. A memory die may be referred to herein as a “logic cell” or “LUN”. A memory die may further comprise one or more planes. For some types of non-volatile memory devices (e.g., NAND devices), each plane consists of a set of physical blocks. Each block consists of a set of pages. Each page consists of a set of memory cells (“cells”). A cell is an electronic circuit for storing information. Hereinafter, a block refers to a cell of a memory device used to store data and may contain groups of memory cells, groups of word lines, word lines, or individual memory cells. For some memory devices, a block (also referred to herein as a “memory block”) is the smallest erasable area. Pages cannot be erased individually; only the entire block can be erased.

[0014] Each plane of a non-volatile memory device may be coupled to a corresponding buffer (e.g., a page buffer), which may further include a set of data registers and cache registers. The buffer can be used to temporarily store data transferred from the non-volatile memory device. Some types of read operations that can be performed on a non-volatile memory device (e.g., multi-plane read operations) involve sensing data stored in multiple planes (e.g., pages of multiple planes). During a read operation, data transferred to a buffer (e.g., a cache register) may be sequentially transferred out of the cache register (e.g., to an external memory subsystem controller). In previous methods, this data transfer from the cache register was always controlled by the memory subsystem controller. For example, in these methods, whenever a corresponding portion of data is transferred out of the corresponding cache register to initiate the transfer of another portion of data out of a subsequent cache register, the memory subsystem controller must issue a special command (e.g., a change read column command and / or a change read column enhancement command). This operation by the memory subsystem controller inevitably consumes the memory subsystem controller's resources and causes latency associated with issuing and / or executing dedicated commands, which can worsen as the number of planes associated with multi-plane read operations increases.

[0015] The aspects of this disclosure address the above and other drawbacks by providing a multi-plane sensing (e.g., read) operation scheme for NAND memory devices, which enables the NAND memory device to perform multi-plane read operations without receiving dedicated commands from the memory subsystem controller. For example, embodiments of this disclosure allow the NAND memory device to automatically initiate the transfer of data out of subsequent cache registers without being prompted by dedicated commands, which eliminates the latency associated with the controller issuing and / or executing dedicated commands during multi-plane read operations.

[0016] Figure 1 This description describes an example computing system 100 including a memory subsystem 110 according to some embodiments of the present disclosure. The memory subsystem 110 may include media, such as one or more volatile memory devices (e.g., memory device 140), one or more non-volatile memory devices (e.g., memory device 130), or a combination thereof.

[0017] The memory subsystem 110 may be a storage device, a memory module, or a combination of both. Examples of storage devices include solid-state drives (SSDs), flash drives, universal serial bus (USB) flash drives, embedded multimedia controller (eMMC) drives, universal flash memory (UFS) drives, secure digital cards (SD cards), and hard disk drives (HDDs). Examples of memory modules include dual in-line memory modules (DIMMs), small form factor DIMMs (SO-DIMMs), and various types of non-volatile dual in-line memory modules (NVDIMMs).

[0018] The computing system 100 may be a computing device, such as a desktop computer, laptop computer, web server, mobile device, vehicle (e.g., airplane, drone, train, car or other means of transport), device with Internet of Things (IoT) functionality, embedded computer (e.g., embedded computer contained in a vehicle, industrial equipment or networked business device), or such computing device containing memory and processing devices.

[0019] The computing system 100 may include a host system 120 coupled to one or more memory subsystems 110. In some embodiments, the host system 120 is coupled to different types of memory subsystems 110. Figure 1 This describes an example of a host system 120 coupled to a memory subsystem 110. As used herein, “coupled to” or “coupled with” generally refers to a connection between components, which can be an indirect or direct communication connection (e.g., without intervening components), whether wired or wireless, and includes connections such as electrical, optical, magnetic, etc.

[0020] Host system 120 may include a processor chipset and a software stack executed by the processor chipset. The processor chipset may include one or more cores, one or more cache memories, a memory controller (e.g., an SSD controller), and a storage protocol controller (e.g., a PCIe controller, a SATA controller). Host system 120 uses memory subsystem 110, for example, to write data to memory subsystem 110 and to read data from memory subsystem 110.

[0021] Host system 120 can be coupled to memory subsystem 110 via a physical host interface. Examples of physical host interfaces include, but are not limited to, Serial Advanced Technology Attachment (SATA) interfaces, Peripheral Component Interconnect High Speed ​​(PCIe) interfaces, Universal Serial Bus (USB) interfaces, Fibre Channel, Serial Attached SCSI (SAS), Small Computer System Interface (SCSI), Dual Data Rate (DDR) memory bus, Dual In-line Memory Module (DIMM) interfaces (e.g., DIMM sockets supporting Dual Data Rate (DDR)), Open NAND Flash Interface (ONFI), Dual Data Rate (DDR), Low Power Dual Data Rate (LPDDR), or any other interface. The physical host interface can be used to transmit data between host system 120 and memory subsystem 110. When memory subsystem 110 is coupled to host system 120 via a PCIe interface, host system 120 can further utilize an NVM High Speed ​​(NVMe) interface to access components (e.g., memory device 130). The physical host interface provides an interface for transmitting control, address, data and other signals between the memory subsystem 110 and the host system 120. Figure 1 The memory subsystem 110 is described as an example. Generally, the host system 120 can access multiple memory subsystems via the same communication connection, multiple separate communication connections, and / or a combination of communication connections.

[0022] Memory devices 130 and 140 may comprise any combination of different types of non-volatile memory devices and / or volatile memory devices. Volatile memory devices (e.g., memory device 140) may be, but are not limited to, random access memory (RAM), such as dynamic random access memory (DRAM) and synchronous dynamic random access memory (SDRAM).

[0023] Examples of non-volatile memory devices (e.g., memory device 130) include NAND flash memory. Each of memory devices 130 may include one or more arrays of memory cells. Memory cells may include single-level cells (SLC) that can store one bit per cell, multi-level cells (MLC) that can store two bits per cell, three-level cells (TLC) that can store three bits per cell, four-level cells (QCC) that can store four bits per cell, and / or five-level cells (PLC) that can store five bits per cell, etc. As used herein, the term multi-level cell is used to refer to a cell configured to store more than one bit per cell (e.g., MLC, TLC, QLC, PLC, etc.). In some embodiments, a particular memory component may include SLC and MLC portions, TLC portions, QLC portions, and / or PLC portions of memory cells. Each of the memory cells may store one or more data bits for use by the host system 120. Furthermore, the memory cells of the memory device 130 may be grouped into memory pages or memory blocks, which may refer to cells of a memory component used to store data.

[0024] Although a non-volatile memory component, such as NAND type memory, is described, memory device 130 may be based on any other type of non-volatile memory or storage device, such as read-only memory (ROM), phase-change memory (PCM), select memory, other chalcogenide-based memory, ferroelectric transistor random access memory (FeTRAM), ferroelectric random access memory (FeRAM), magnetic random access memory (MRAM), spin-transfer torque (STT)-MRAM, conductive bridged RAM (CBRAM), resistive random access memory (RRAM), oxide-based RRAM (OxRAM), NOR flash memory, and electrically erasable programmable read-only memory (EEPROM).

[0025] Although not described herein, array 114 may be further coupled to a sensing circuitry (e.g., one or more sensing amplifiers and / or computing components) that can read and latch data pages (e.g., rows) from array 114. Memory device 130 further includes a buffer 116 coupled to the sensing circuitry and / or array 114. Buffer 116 may include registers (e.g., ... Figure 3 The data register 336 and / or cache register 338, which are further described in the text, can temporarily store data to be written to array 114 and / or sensed from said array.

[0026] The memory subsystem controller 115 (or simply controller 115) can communicate with the memory device 130 to perform operations, such as reading data, writing data, or erasing data at the memory device 130, and other such operations. The memory subsystem controller 115 may include hardware, such as one or more integrated circuits and / or discrete components, buffer memories, or combinations thereof. The hardware may include digital circuitry with dedicated (i.e., hard-decoded) logic to perform the operations described herein. The memory subsystem controller 115 may be a microcontroller, a dedicated logic circuit system (e.g., a field-programmable gate array (FPGA), an application-specific integrated circuit (ASIC), etc.), or other suitable processor.

[0027] The memory subsystem controller 115 may include a processor 117 (e.g., a processing device) configured to execute instructions stored in local memory 119. In the illustrated example, the local memory 119 of the memory subsystem controller 115 includes embedded memory configured to store instructions for executing various processes, operations, logical flows, and routines that control the operation of the memory subsystem 110, including handling communication between the memory subsystem 110 and the host system 120.

[0028] In some embodiments, local memory 119 may include memory registers that store memory pointers, retrieved data, etc. Local memory 119 may also include read-only memory (ROM) for storing microcode. Although Figure 1 The instance memory subsystem 110 in the present disclosure is described as including a memory subsystem controller 115, but in another embodiment of the present disclosure, the memory subsystem 110 does not include a memory subsystem controller 115, but may rely on external control (e.g., provided by an external host or by a processor or controller separate from the memory subsystem).

[0029] Generally, the memory subsystem controller 115 can receive commands or operations from the host system 120 and can translate these commands or operations into instructions or appropriate commands to enable desired access to memory devices 130 and / or 140. The memory subsystem controller 115 may be responsible for other operations, such as wear leveling, garbage collection, error detection and error correction (ECC) operations, encryption, caching, and address translation between logical addresses (e.g., logical block addresses (LBAs), namespaces) and physical addresses (e.g., physical block addresses, physical media addresses, etc.) associated with memory device 130. The memory subsystem controller 115 may further include a host interface circuitry for communicating with the host system 120 via a physical host interface. The host interface circuitry can translate commands received from the host system into command instructions to access memory devices 130 and / or 140 and translate responses associated with memory devices 130 and / or 140 into information for the host system 120.

[0030] The memory subsystem 110 may also include additional circuitry or components not described. In some embodiments, the memory subsystem 110 may include a cache or buffer (e.g., DRAM) and an address circuitry (e.g., a row decoder and a column decoder) that can receive an address from the memory subsystem controller 115 and decode the address to access memory device 130 and / or memory device 140.

[0031] In some embodiments, memory device 130 includes a local media controller 135 that operates in conjunction with memory subsystem controller 115 to perform operations on one or more memory cells of array 114 of memory device 130. An external controller (e.g., memory subsystem controller 115) may externally manage memory device 130 (e.g., perform media management operations on memory device 130). In some embodiments, memory device 130 is a managed memory device, which is a raw memory device combined with a local controller (e.g., local controller 135) for media management within the same memory device package. An example of a managed memory device is a managed NAND (MNAND) device.

[0032] The memory subsystem 110 may further include multiplane operation components 112 and 113, respectively, in the memory subsystem controller 115 and the local media controller 135, which may cause the memory device 130 to transfer data out of buffers 116 (e.g., cache registers of buffer 116) coupled to the respective planes of the array 114 as part of the execution of a multiplane sensing (e.g., read) operation. In some embodiments, the memory subsystem controller 115 includes at least a portion of the multiplane operation component 112. For example, the memory subsystem controller 115 may include a processor 117 (processing means) configured to execute instructions stored in local memory 119 for performing the operations described herein. In some embodiments, the multiplane operation component 112 is part of the host system 110, an application, or an operating system.

[0033] Multiplane operation component 112 can specify the manner in which multiplane read operations are performed on memory device 130. For example, multiplane operation component 112 of memory subsystem controller 115 can enable configuration to cause memory device 130 (e.g., multiplane operation component 113 of local media controller 135 of memory device) to perform operations (e.g., multiplane read operations) according to the manner specified by the enabled configuration. As described herein, when performed on memory device 130, a multiplane read operation causes data stored in pages of planes of array 114 to be read (e.g., transferred out) from memory device 130 to memory subsystem controller 115. In some embodiments, multiplane operation component 112 can issue a set feature command to memory device 130 to cause memory device 130 to perform a configuration operation (e.g., alternatively referred to as a feature address operation), which causes memory device 130 to perform multiplane read operations according to the configuration. Although embodiments are not limited thereto, multiplane operation component 112 can provide configuration to and / or issue set feature commands to each corresponding memory die of memory device 130.

[0034] The configuration can define (e.g., specify) the corresponding cache register to be transferred out (e.g., Figure 3 The column address range of the size (e.g., the page size of the plane) of the data in the corresponding cache register 338 described herein. For example, the column address range specified by the configuration may further specify edge values ​​(e.g., a first edge value and a second edge value greater than the first edge value), such as column addresses (e.g., a first column address and a last column address), so that when the multi-plane operation component 113 determines that data corresponding to the second edge value (e.g., the last edge value) is transferred out of the corresponding cache register, the multi-plane operation component 113 may switch to a subsequent cache register (e.g., subsequent cache register 338) to begin transferring data out of the subsequent cache register.

[0035] Once the configuration is enabled and provided to the local media controller 135 (e.g., the multi-plane operation component 113 of the local media controller), the multi-plane operation component 113 can cause the local media controller 135 to perform multi-plane read operations according to the received configuration, independent of commands from the controller 115, for example without receiving one or more change read column commands and / or change read column enhancement commands. As described herein, for example, the multi-plane operation component 113 can sequentially transfer data from a location (e.g., a data portion) corresponding to the first column address of a plane (e.g., a page of a plane) to a location (e.g., a data portion) corresponding to the last column address of a plane (e.g., a page of a plane) as specified by the enabled configuration. When the multi-plane operation component 113 determines that data corresponding to the last column address specified by the configuration has been transferred out of the cache register of the buffer 116 (e.g., Figure 3 When the cache register 338 described herein is accessed, the multiplane operation component 113 can automatically initiate the transfer of data out of the buffer 116 to subsequent cache registers (e.g., ...). Figure 3 The cache register 338 described herein), without changing the read column command and / or changing the read column enhancement command bootstrap. Once the multiplane operation component 113 determines the last cache register of the data transfer out buffer 116 (e.g., Figure 3 With the cache register 338 described herein, the multiplane operation component 113 can stop transmitting data out of the buffer 116 and complete the execution of the multiplane read operation.

[0036] Although not in Figure 1 As described herein, the multiplane operation component 113 may further include a counter (e.g., a column address counter) which can be used to determine whether data corresponding to an edge (e.g., last) column address specified by the configuration has been transferred out. For example, the multiplane operation component 113 may sequentially update (e.g., increment and / or decrement) the counter from an initial value (e.g., corresponding to a first column address specified by the configuration) whenever data corresponding to the corresponding column address has been transferred out of the corresponding cache register of buffer 116, and when the updated value of the counter corresponds to the last column address specified by the configuration, the multiplane operation component 113 may switch to the subsequent cache register to begin transferring data out of the subsequent cache register. Therefore, embodiments of this disclosure eliminate the latency associated with executing change read column commands and / or change read column enhancement commands during multiplane read operations.

[0037] Figure 2 This illustration shows instance timing diagram 218 associated with performing a multi-plane read operation according to some embodiments of the present disclosure. For example, Figure 2This diagram illustrates the timing diagram associated with performing a multiplane read operation without receiving a change read column command and / or a change read column enhancement command, which in previous methods were originally obtained from an external controller (e.g., Figure 1 The memory subsystem controller 115 described herein is externally deployed as part of the execution of multi-plane read operations.

[0038] For example, in this prior method, a page read command can be issued to transfer data from one plane of the memory array, and the data can be further transferred out of a cache register coupled to that plane. Once the data has been transferred out of the cache register, several additional commands can be issued to switch to a subsequent cache register and initiate the transfer of data out of that cache register. These commands can be executed sequentially and can be collectively referred to as change read column enhancement commands. After executing the change read column enhancement command, the data can be transferred out of the subsequent cache register. The time period between executing the change read column enhancement command and transferring the data out of the subsequent cache register can correspond to the latency associated with the switching between cache registers during the execution of a multi-plane read operation.

[0039] In comparison, such as Figure 2 As described in the document, the memory subsystem (e.g., Figure 1 The memory subsystem 110 described herein experiences only a delay of time period 231 corresponding to the time of column setting change when switching between planes (as part of performing a multi-plane read operation according to this disclosure). For example, once in Figure 2 At time 233, data is transferred out of a cache register, so that it can be stored after time period 231 expires (for example, at time 233). Figure 2 At time 235, data will be immediately transferred out of the subsequent cache registers without executing commands that change the read column enhancement command sequence.

[0040] Figure 3 A block diagram illustrating a memory array 314 and registers coupled to the memory array 314 according to some embodiments of the present disclosure. The memory array 314 may be similar to... Figure 1 The memory array 114 described herein.

[0041] A memory die may contain several planes. For example, memory die 337-1 contains planes 320-1 and 320-2, and memory die 337-2 contains planes 320-3 and 320-4, as shown below. Figure 3 As explained in the text, a plane can contain several blocks. For example, plane 320-4 contains several blocks 332-1, 332-2, ..., 332-B, as... Figure 3As explained in the document, blocks of memory cells can be erased together in a single erase operation.

[0042] A block can further contain several pages. For example, block 332-1 can contain pages 334-1, 334-2, ..., 334-P, such as... Figure 3 As described herein, pages of a memory cell can be written to or read together in a single write or read operation. Embodiments are not limited to those separately contained in a memory device (e.g., Figure 1 The memory device 130 described herein, and the specific number of dies, planes, blocks and / or pages in the memory, planes and / or blocks.

[0043] Each plane can be coupled to a corresponding set of cache registers and data registers. For example... Figure 3 As illustrated herein, for example, plane 320-1 is coupled to data register 336-1 and cache register 338-1; plane 320-2 is coupled to data register 336-2 and cache register 338-2; plane 320-3 is coupled to data register 336-3 and cache register 338-3; and plane 320-4 is coupled to data register 336-4 and cache register 338-4. As used herein, a set of cache registers and data registers may be collectively referred to as buffers (e.g., Figure 1 Buffer 116 as described in [the document]. Although not in [the document] Figure 3 As explained, however, cache register 338 may be coupled to several data buses (e.g., DQ bus), through which data can be received at cache register 338 and / or data can be transferred out of cache register 338.

[0044] Each plane 320-1 to 320-4 can communicate bidirectionally with data registers 336-1 to 336-4, and each data register 336-1 to 336-4 can communicate bidirectionally with cache registers 338-1 to 338-4. For example, during a write operation, data received at the corresponding cache register 338 can be transferred to the corresponding data register 336, and then to the corresponding memory plane 320. For example, during a read operation (e.g., a multi-plane read operation), data can first be transferred from memory plane 320 to the corresponding data register 336, and then to the corresponding cache register 338.

[0045] When a multi-plane read operation is performed on memory array 314, data pages in each plane 320 can be transferred to the corresponding data register 336, and further transferred to the corresponding cache register 338. As part of the execution of the multi-plane operation, data transferred to and stored in cache register 338 can be sequentially transferred out of cache register 338. For example, once data is transferred out of cache register 338-1, data can be transferred out of cache register 338-2; once data is transferred out of cache register 338-2, data can be transferred out of cache register 338-3; and once data is transferred out of cache register 338-3, data can be transferred out of cache register 338-4.

[0046] As described herein, when configuration is enabled via the memory subsystem controller and the configuration is provided externally from the memory subsystem controller, it can be independent of the memory subsystem controller (e.g., Figure 1 The switching of sequentially transferring data out of cache register 338 is controlled by commands from the memory subsystem controller 115 (described herein). For example, once data has been transferred out of cache register 338-1, the multiplane operation component 113 can automatically switch to transferring data out of cache register 338-2, without needing to switch from the memory subsystem controller (e.g., ...) in the previous method. Figure 1 Commands (e.g., change read column command and / or change read column enhancement command) issued by the memory subsystem controller 115 as described herein are guided. Therefore, compared to previous methods where three of these dedicated commands (e.g., change read column command or change read column enhancement command) are used to issue commands to transfer data out of each of the four cache registers 338-1 to 338-4, embodiments of this disclosure can perform multi-plane read operations without experiencing the delays associated with issuing and / or executing dedicated commands.

[0047] Figure 4 This is a flowchart corresponding to a method 440 for multi-plane switching of non-volatile memory according to some embodiments of the present disclosure. Method 440 may be executed by processing logic, which may include hardware (e.g., processing device, circuit system, specialized logic, programmable logic, microcode, device hardware, integrated circuit, etc.), software (e.g., instructions that run or execute on the processing device), or a combination thereof. In some embodiments, method 440 is performed by… Figure 1The multi-plane operation component 113 performs the operation. Although shown in a specific order or sequence, the order of the processes may be modified unless otherwise specified. Therefore, it should be understood that the illustrated embodiments are merely examples, and the illustrated processes may be performed in different orders, and some processes may be performed in parallel. In addition, one or more processes may be omitted in various embodiments. Therefore, not all processes are required in each embodiment. Other process flows are also possible.

[0048] At operation 442, data can be transferred out to multiple planes coupled to the memory component (e.g., Figure 3 The first plane in planes 320-1 to 320-4 described herein (e.g., Figure 1 The first buffer (e.g., plane 320-1) described in the document Figure 1 The buffer 116 described herein is in Figure 3 (See cache register 338-1 as described in the document). Before being transferred out of the first buffer, data is transferred from the first plane to the first buffer in response to an access request for data stored in multiple planes of the memory component (e.g., an access request to perform a multi-plane read operation).

[0049] At operation 444, after data is transmitted out of the first buffer and independently of data from the processing device (e.g., ...), Figure 1 Commands (e.g., change read column command and / or change read column enhancement command) of the memory subsystem controller 115 described herein can transfer data out of a second plane among the multiple planes coupled to the memory component (e.g., Figure 3 The second buffer (e.g., plane 320-1) described in the document Figure 1 The buffer 116 described herein is in Figure 3 (Referring to cache register 338-2). For example, data can be transferred out of the second buffer without receiving commands from the processing device. As an example, data can be transferred out of the second buffer without having a column address cycle or row address cycle associated with executing a command from the processing device.

[0050] In some embodiments, when it is determined that a portion of the data transmitted from the first buffer corresponds to the last column address of the first plane, the data may be transmitted from a second buffer corresponding to the first column address of the second plane in response to said determination. In some embodiments, after the data is transmitted from the first buffer, the column setting time may be changed (e.g., Figure 2 Once the time period 231 described in the document expires, the data will be immediately transmitted out of the second buffer.

[0051] Figure 5 This is a block diagram of an example computer system 580 in which embodiments of the present disclosure are operable. For example, Figure 5 This describes an instance machine of computer system 580, within which a set of instructions is executable to cause the machine to perform any or more of the methods discussed herein. In some embodiments, computer system 580 may correspond to a host system (e.g., Figure 1 The host system 120 includes, is coupled to, or utilizes a memory subsystem (e.g., Figure 1 The memory subsystem 110) or can be used to perform controller operations (e.g., execute the operating system to perform operations corresponding to...). Figure 1 (Operation of multi-plane operating components 112 and / or 113). In alternative embodiments, the machine may be connected (e.g., networked) to other machines in a LAN, intranet, extranet, and / or the Internet. The machine may operate as a peer machine in a peer-to-peer (or distributed) network environment or as a server or client machine in a cloud computing infrastructure or environment, operating at the capacity of a server or client machine in a client-server network environment.

[0052] The machine may be a personal computer (PC), tablet PC, set-top box (STB), personal digital assistant (PDA), cellular phone, network device, server, network router, switch, or bridge, or any machine capable of (sequentially or otherwise) executing a set of instructions specifying actions to be taken by the machine. Furthermore, although a single machine is described, the term "machine" should be understood to include any collection of machines that individually or collectively execute one or more sets of instructions to perform any one or more of the methods discussed herein.

[0053] The example computer system 580 includes a processing device 582, a main memory 586 (e.g., read-only memory (ROM), flash memory, dynamic random access memory (DRAM), such as synchronous DRAM (SDRAM) or Rambus DRAM (RDRAM), etc.), a static memory 594 (e.g., flash memory, static random access memory (SRAM), etc.), and a data storage system 590, which communicate with each other via a bus 592.

[0054] Processing device 582 represents one or more general-purpose processing devices, such as microprocessors, central processing units, etc. More specifically, the processing device may be a Complex Instruction Set Computing (CISC) microprocessor, a Reduced Instruction Set Computing (RISC) microprocessor, a Very Long Instruction Word (VLIW) microprocessor, or a processor implementing other instruction sets, or a combination of instruction sets. Processing device 582 may also be one or more special-purpose processing devices, such as application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), digital signal processors (DSPs), network processors, etc. Processing device 582 is configured to execute instructions 584 for performing the operations and steps discussed herein. Computer system 580 may further include a network interface device 596 for communication via network 588.

[0055] Data storage system 590 may include machine-readable storage medium 596 (also referred to as computer-readable medium) on which one or more sets of instructions 584 or software embodying any one or more of the methods or functions described herein are stored. The instructions 584 may also reside wholly or at least partially within main memory 586 and / or processing device 582 during execution by computer system 580, the main memory 586 and processing device 582 also constituting machine-readable storage medium. Machine-readable storage medium 596, data storage system 590 and / or main memory 586 may correspond to... Figure 1 The memory subsystem 110.

[0056] In one embodiment, instruction 584 includes instructions for implementing components corresponding to the superblock construction (e.g., Figure 1 The multi-plane operating components 112 and / or 113) contain functional instructions. Although the machine-readable storage medium 596 is shown as a single medium in the exemplary embodiment, the term "machine-readable storage medium" should be considered to include a single medium or multiple media storing one or more sets of instructions. The term "machine-readable storage medium" should also be considered to include any medium capable of storing or encoding a set of instructions executable by a machine and causing the machine to perform any one or more of the methods of this disclosure. Therefore, the term "machine-readable storage medium" should be considered to include, but is not limited to, solid-state memory, optical media, and magnetic media.

[0057] Some parts of the previously described algorithms and symbolic representations of operations on data bits within computer memory have been presented. These algorithmic descriptions and representations are the means by which those skilled in the art of data processing most effectively communicate the essence of their work to others skilled in the art. In this document, and generally in general, an algorithm is conceived as a self-consistent sequence of operations that produce a desired result. An operation is an operation that requires physical manipulation of a physical quantity. Typically (but not always), these quantities take the form of electrical or magnetic signals that can be stored, combined, compared, and otherwise manipulated. It has been shown that it is sometimes convenient to refer to these signals as bits, values, elements, symbols, characters, items, numbers, etc., primarily for common use.

[0058] However, it should be remembered that all these and similar terms will be associated with appropriate physical quantities and are merely convenient notations for application to those quantities. This disclosure can refer to the actions and processes of a computer system or similar electronic computing device that manipulate and transform data represented as physical (electronic) quantities in the registers and memories of a computer system into other data similarly represented as physical quantities in the computer system's memory or registers or other such information storage systems.

[0059] This disclosure also relates to apparatus for performing the operations described herein. Such apparatus may be specifically constructed for the desired purpose, or may comprise a general-purpose computer selectively activated or reconfigured by a computer program stored in a computer. This computer program may be stored in a computer-readable storage medium, such as, but not limited to, any type of disk, including floppy disks, optical disks, CD-ROMs and magneto-optical disks, read-only memory (ROM), random access memory (RAM), EPROM, EEPROM, magnetic cards or optical cards, or any type of media suitable for storing electronic instructions and each coupled to a computer system bus.

[0060] The algorithms and displays presented herein are not inherently related to any particular computer or other device. Various general-purpose systems can be used with the programs taught herein, or it may prove convenient to construct more specialized devices to perform the methods described herein. The structures of various such systems will be presented as set forth in the description below. Furthermore, this disclosure is described without reference to any particular programming language. It should be understood that the teachings of this disclosure as described herein can be implemented using various programming languages.

[0061] This disclosure may be provided as a computer program product or software, which may include a machine-readable medium having instructions stored thereon that can be used to program a computer system (or other electronic device) to perform processes according to this disclosure. The machine-readable medium includes any mechanism for storing information in a machine-readable (e.g., computer-readable) form. In some embodiments, the machine-readable (e.g., computer-readable) medium includes machine-readable (e.g., computer-readable) storage media, such as read-only memory (“ROM”), random access memory (“RAM”), disk storage media, optical storage media, flash memory devices, etc.

[0062] In the foregoing description, embodiments of this disclosure have been described with reference to specific example embodiments thereof. It will be apparent that various modifications may be made to this disclosure without departing from the broader spirit and scope of the embodiments set forth in the appended claims. Therefore, the description and drawings should be viewed in an illustrative rather than restrictive sense.

Claims

1. A method for performing multi-plane sensing operations, comprising: The self-processing device receives a setting feature command that enables a configuration associated with performing a multi-plane read operation on a memory component, wherein the configuration defines a column address range corresponding to the size of data transferred from each plane of the multi-plane read operation to a corresponding cache register of the memory component, wherein the range has a first edge value and a second edge value greater than the first edge value; In response to receiving an access request from the processing device, the multi-plane read operation is performed on the memory component: Data is transmitted from a first buffer of a first plane of a plurality of planes coupled to a memory component, wherein the data was previously transmitted from the first plane to the first buffer in response to an access request for data stored in the plurality of planes of the memory component. In response to a portion of the data corresponding to the column address of the first plane being transferred out of the cache register coupled to the first plane, the column address counter is sequentially updated from the first edge value to the second edge value; as well as In response to the updated column address counter indicating the second edge value and independently of the access request received from the processing device, data is transferred out of a second buffer of a second plane among the plurality of planes coupled to the memory component, wherein the data transferred out of the second buffer was previously transferred from the second plane to the second buffer in response to the access request sensing of the data.

2. The method according to claim 1, further comprising: In response to the updated column address counter indicating the second edge value, it is determined that a portion of the data transmitted out of the first buffer corresponds to the last column address of the first plane; as well as In response to the determination, data is transmitted out of the second buffer corresponding to the first column address of the second plane.

3. The method of claim 1, wherein transmitting the data out of the second buffer independently of the access request from the processing device includes transmitting the data out of the second buffer without receiving a command from the processing device.

4. The method according to any one of claims 1 to 3, wherein transferring the data out of the second buffer independently of the access request received from the processing device includes transferring the data out of the second buffer without having a column address cycle or row address cycle associated with executing a command from the processing device.

5. The method according to any one of claims 1 to 3, further comprising, after transmitting the data out of the first buffer, immediately transmitting the data out of the second buffer after the change column setting time expires.

6. A system for performing multi-plane sensing operations, comprising: Memory components having multiple planes; as well as Processing device, which is operatively coupled to the memory component, to: Setting characteristic commands are issued to the memory component to enable and provide configuration, the configuration defining a column address range corresponding to the size of the data, which is transferred from each of the plurality of planes to the corresponding cache register of the memory component; and The access request is provided to the memory component to perform a multi-plane read operation and cause the memory component to: Data is transmitted out of the first buffer, wherein the data was previously transmitted from a page of the first plane in the plurality of planes to the first buffer in response to an access request for data stored in the plurality of planes; In response to a portion of the data corresponding to a column address of the first plane being transferred out of a cache register coupled to the first plane, the column address counter is sequentially updated from a first edge value of the column address range to a second edge value of the column address range; as well as In response to the updated column address counter indicating the second edge value, data is transferred out of the second buffer independently of the access request from the processing device, wherein the data transferred out of the second buffer was previously transferred from a page of the second plane of the plurality of planes to the second buffer in response to the access request sensing the data.

7. The system of claim 6, wherein the first buffer and the second buffer include cache registers respectively coupled to the first plane and the second plane.

8. The system of claim 6, wherein the processing means causes the memory component to transfer the data out of the second buffer without receiving a command from the processing means.

9. The system according to any one of claims 6 to 8, wherein the processing means causes the memory component to immediately transmit the data out of the second buffer after the change column setting time expires, following the transmission of the portion of the data corresponding to the last column address of the page from the first buffer.

10. The system according to any one of claims 6 to 8, wherein the data is sequentially transmitted out of the first buffer from a portion of the data corresponding to the first column address of the page to a portion of the data corresponding to the last column address of the page.

11. The system according to any one of claims 6 to 8, wherein the processing means causes the memory component to transfer the data out of the first buffer or the second buffer without having a column address cycle or row address cycle associated with executing a command from the processing means.

12. A non-transitory computer-readable storage medium comprising instructions for performing multi-plane sensing operations, the instructions causing the processing device, when executed by a processing device, to: By providing a setting feature command to the memory component, a configuration associated with performing a multi-plane read operation on the memory component is enabled such that the memory component reads data from multiple planes of the memory component according to the enabled configuration to perform the multi-plane read operation, wherein the enabled configuration defines a range of column addresses corresponding to the size of the data, the data being transferred from each of the multiple planes to the corresponding cache register of the memory component; The enabled configuration causes the memory component to respond to receiving an access request to perform the multi-plane read operation as follows: Data is transferred out of a first cache register of a first plane coupled to one of the plurality of planes, wherein the data was previously transferred from the first plane to the first cache register in response to the access request; In response to a portion of the data corresponding to a column address of the first plane being transferred out of the first cache register coupled to the first plane, the column address counter is sequentially updated from a first edge value of the column address range to a second edge value of the column address range; as well as In response to the updated column address counter indicating the second edge value, data is transferred out of the second cache register independently of the command to transfer data out of the second cache register coupled to the second plane in the plurality of planes.

13. The non-transitory computer-readable storage medium of claim 12, wherein the multi-plane read operation includes the operation of reading data in a corresponding page of each plane of the memory component.

14. The non-transitory computer-readable storage medium of claim 13, wherein the enabled configuration defines a range of column addresses corresponding to the size of the respective page of each plane of the memory component.

15. The non-transitory computer-readable storage medium of claim 12, wherein the memory component comprises a plurality of dies, each comprising a plurality of planes, and the processing means further issues a corresponding setting feature command to each of the plurality of dies.

16. The non-transitory computer-readable storage medium of claim 12, wherein the enabled configuration causes the memory component to perform the multi-plane read operation without further receiving a change read column enhancement command from the processing device.

17. The non-transitory computer-readable storage medium of claim 12, wherein the enabled configuration causes the memory component to perform the multiplane read operation without further receiving a change read column command from the processing device.

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