Semiconductor memory device

Abstract

The present application provides a semiconductor memory device, which can shorten the processing time of error detection and correction. The flash memory (100) of the present application has a NAND chip (200) and an ECC chip (300). The NAND chip (200) has a dedicated input / output terminal (220) for transmitting data between the NAND chip (200) and the ECC chip (300), and the ECC chip (300) has a dedicated input / output terminal (320) for transmitting data between the NAND chip (200) and the ECC chip (300). When the readout operation is performed in the NAND chip (200), the NAND chip (200) transmits the readout data containing the parity data to the ECC chip (300) via the dedicated input / output terminal (220), and the ECC chip (300) performs error detection and correction of the readout data based on the parity data, and transmits the corrected data to the controller (400) via the input / output terminal (330).

Description

TECHNICAL FIELD

[0001] The present application relates to a semiconductor memory device such as a NAND type flash memory, and particularly relates to error detection and correction. BACKGROUND

[0002] In a NAND type flash memory, repeated programming or erasing of data sometimes causes deterioration of a tunnel insulating film and the like, resulting in a decrease in charge retention characteristics, or threshold variation due to charge trapped in the tunnel insulating film, leading to bit errors. As a countermeasure against such bit errors, an error detection and correction circuit (hereinafter referred to as an ECC circuit) is used in the flash memory. SUMMARY

[0003] Figure 1 A diagram showing the structure of a conventional off-chip ECC-equipped flash memory. A flash memory 10 is configured to include a NAND chip 20 including a memory array of a NAND type or a peripheral circuit thereof, and the NAND chip 20 is connected to a controller chip 30 on which an ECC function 40 is mounted. The NAND chip 20 and the controller chip 30 are respectively housed in different packages, and each package is mounted on a printed board, for example.

[0004] The NAND chip 20 and the controller chip 30 are mounted with a serial peripheral interface (SPI) that can transmit data in synchronization with a clock signal, and input / output terminals of #CS, CLK, DI, DO, #WP, and #HOLD are provided in each of the chips. The controller chip 30 sends a command, an address, and data to the NAND chip 20 via the input / output terminals of the SPI.

[0005] The ECC function 40 includes an encoder that encodes data and generates parity data, and a decoder that decodes data based on the parity data. The ECC function 40 performs error detection and correction of a plurality of bits (for example, 2 bits, 4 bits, 8 bits, and the like) by a BCH (Bose Chaudhuri Hocquenghem) code, for example, and in this case, the BCH decoder includes a syndrome calculation section that evaluates a syndrome of data, a Euclidean algorithm calculation section that calculates an error location polynomial (ELP), an error location search section that calculates a root of the error location polynomial and searches for an error location, and an error correction section that corrects an error based on the searched error location.

[0006] The page buffer / sense circuit of the NAND chip 20 includes two latches, one of which includes two buffers, one of which holds data of a plurality of sectors (e.g., 2 sectors, 4 sectors, etc.). Data transfer between the NAND chip 20 and the controller chip 30 is performed in units of buffers. Also, the ECC function 40 generates parity data, or performs error detection, correction, in units of sectors. One sector encoded by the ECC function 40 includes main data and parity data.

[0007] When the controller chip 30 causes the NAND chip 20 to perform a program operation, the controller chip 30 causes the ECC function 40 to generate parity data from data to be programmed, and transfers the generated parity data and main data to the NAND chip 20 via the DO terminal of the SPI. The NAND chip 20 holds the received main data and parity data in the latches, and programs the data held in the latches to the selected page of the memory array.

[0008] On the other hand, data read out from the memory array in the NAND chip 20 is transferred to the controller chip 30 via the DO terminal of the SPI. The ECC function 40 detects errors based on the parity data, and corrects the main data or the parity data according to the result of the detection.

[0009] Figure 2 A timing chart showing the operation of each part of the ECC function of the controller chip 30 is shown in FIG. 6. The NAND chip 20 performs a read operation according to a read command transferred from the controller chip 30, and outputs the read data to the controller chip 30. At time tO, the NAND IF of the controller chip 30 starts receiving main data and parity data Pt of sector SO from the NAND chip 20, and at time tl, starts receiving main data and parity data Pt of sector SI, and at time t2, time t3, starts receiving main data and parity data Pt of sector S2, sector S3. The ECC function 40 performs syndrome calculation of the main data of sector SO, calculation of the error position polynomial, search for the error position, in the form of pipeline processing, at the same time as the data reception of sector SI, and corrects errors in the main data of sector SO based on the searched error position. Then, the CPU IF of the controller chip 30 transfers the error-corrected data of sector SO to the host device. The ECC processing for sector SI, sector S2, sector S3 is also performed in the same manner, and the error-corrected data of each sector is output in the reception of the sector.

[0010] When transmitting read data from NAND chip 20 to controller chip 30, the parity calculation must be performed after transmitting the parity data of the sector. Therefore, the following problems exist: if the bit width of the SPI DO terminal is narrow, data transmission takes longer, the idle state of controller chip 30 during this period becomes longer, and the pipeline processing performance cannot be fully utilized.

[0011] The semiconductor memory device of the present invention includes: a NAND chip, comprising a NAND-type memory array and control components for controlling operations related to the memory array; and an ECC chip, including error detection and correction functions, wherein the NAND chip includes a first dedicated terminal for performing ECC-related data transmission, and the ECC chip includes a second dedicated terminal connected to the first dedicated terminal.

[0012] According to the present invention, by providing a first dedicated terminal and a second dedicated terminal for transmitting ECC-related data in the NAND chip and the ECC chip respectively, the data transmission time can be reduced, and the idle state of the ECC processing in the ECC chip that is running at the same time can be reduced, thereby shortening the processing time for error detection and correction. Attached Figure Description

[0013] Figure 1 A diagram illustrating a general structure of a conventional flash memory;

[0014] Figure 2 A diagram illustrating the timing of ECC function operations in previous flash memory applications;

[0015] Figure 3 A diagram illustrating a schematic structure of a flash memory according to an embodiment of the present invention;

[0016] Figure 4 This is a block diagram illustrating the internal structure of the NAND chip and ECC chip according to an embodiment of the present invention;

[0017] Figure 5 This is a timing diagram illustrating the ECC operation of the flash memory in an embodiment of the present invention;

[0018] Figure 6 (A) and Figure 6 (B) is a diagram showing the timing of data transmission between the master data and parity data in sector S0. Figure 6 (A) represents the comparative example. Figure 6 (B) indicates this embodiment;

[0019] Figure 7 (A) and Figure 7 (B) is a timing diagram representing data input and parity data generation. Figure 7(A) of FIG. 1 indicates a conventional example, Figure 7 (B) of FIG. 1 indicates an embodiment of the present application;

[0020] Figure 8 FIG. 1 is a diagram showing a structure of a flash memory of an ECC chip of an embodiment of the present application;

[0021] Figure 9 FIG. 2 is a diagram showing a structure of a flash memory in which a plurality of NAND chips of an embodiment of the present application are stacked;

[0022] Figure 10 FIG. 3 is a diagram showing a timing chart of a continuous readout operation of a flash memory of an embodiment of the present application;

[0023] Figure 11 FIG. 4 is a diagram showing a timing chart when an interruption occurs in the continuous readout operation;

[0024] Figure 12 (A) of FIG. 1 and Figure 12 (B) of FIG. 1 is a timing chart showing a copyback operation of a flash memory of an embodiment of the present application, in which data is corrected;

[0025] Figure 13 FIG. 5 is a diagram showing a timing chart of each part of an ECC chip at the time of the copyback operation of an embodiment of the present application.

[0026] Explanation of symbols

[0027] 10, 100, 100A: flash memory

[0028] 20, 200, 200A: NAND chip

[0029] 30, 400: controller chip

[0030] 40: ECC function

[0031] 210, 310, 330, 410: input / output terminal for SPI

[0032] 220, 320: input / output terminal for ECC

[0033] 230: page buffer / sense circuit

[0034] 240: interface circuit (ECC IF)

[0035] 250, 350: interface circuit (CTL IF)

[0036] 260, 370: ECC control section

[0037] 270, 380: controller

[0038] 280: address control section

[0039] 300: ECC chip

[0040] 340: Interface circuit (NAND IF)

[0041] 360: ECC core

[0042] ADD0 to ADD3: Correction address

[0043] C0, C1: Buffer

[0044] CK, CLK: Clock signal

[0045] D0 to D3, DA0 to DA3: Correction data

[0046] L1, L2: Latch

[0047] OSC: Oscillator

[0048] P0, P1: Page

[0049] Pt: Parity data

[0050] S0 to S7: Sector

[0051] SEL1 to SEL5: Selector

[0052] t0 to t9, ta, tb, tc: Time DETAILED DESCRIPTION

[0053] Figure 3 A diagram showing the outline structure of a flash memory of an embodiment of the present application. The flash memory 100 of the present embodiment is configured to include a NAND chip 200 and an ECC chip 300 electrically connected to the NAND chip 200.

[0054] Although not shown here, the NAND chip 200 typically includes a memory array of the NAND type and a peripheral circuit. The peripheral circuit includes a row decoder, a column decoder, a page buffer / sense circuit, an interface circuit, a controller, an internal voltage generation circuit, and the like, and the controller controls readout, programming, erasure, and the like, in accordance with an input command. The memory array includes a plurality of blocks, and a plurality of NAND strings are formed in each block. The NAND strings can be formed two-dimensionally on the surface of a substrate or three-dimensionally on the surface of a substrate. The memory cells can be of the single-level cell (SLC) type storing one bit (binary data), or of a type storing a plurality of bits.

[0055] The NAND chip 200 includes input and output terminals 210 (#CS, CLK, DI, DO, #WP, #HOLD) for SPI and input and output terminals 220 (VALID, CK, DATA) for ECC as an interface with the ECC chip 300. The "#" indicates low active. The #CS is a terminal that receives a chip selection signal for enabling or disabling the chip, the CLK is a terminal that receives a serial clock signal, the DI is a terminal that inputs serial data, the DO is a terminal that outputs serial data, the #WP is a terminal that receives a signal for protecting a status register from being written, and the #HOLD is a terminal that receives a signal for holding the chip. The NAND chip 200 receives a command, an address, and data in synchronization with the serial clock signal CLK or outputs data in synchronization with the serial clock signal CLK via the input and output terminals 210 for SPI.

[0056] As the input and output terminals 220 for ECC, the VALID is a terminal that inputs and outputs a VALID signal indicating whether or not data transfer between the NAND chip 200 and the ECC chip 300 is active, the CK is a terminal that outputs a clock signal CK used for data transfer and ECC processing, and the DATA is a terminal that inputs and outputs data between the NAND chip 200 and the ECC chip 300. Note that the bit width m (data transfer width) of the DO terminal / DI terminal for SPI is, for example, x1, x4, or x8, but the bit width n of the DATA terminal for ECC is configured to be larger than the bit width m of the DO terminal / DI terminal for SPI (n > m), for example, x32. Therefore, if the frequency of the clock signal CK is the same as that of the clock signal CLK, the data transfer time between the NAND chip 200 and the ECC chip 300 is n / m times faster than the data transfer time based on SPI.

[0057] Further, although not illustrated here, the NAND chip 200 can include an interface for ONFi in addition to the input and output terminals 210 for SPI. The interface for ONFi includes external control terminals such as a command latch enable (CLE), an address latch enable (ALE), a write enable (#WE), and input and output terminals such as I / O.

[0058] The ECC chip 300 includes input and output terminals 310 (#CS, CLK, DI, DO, #WP, #HOLD) for SPI and input and output terminals 320 (VALID, CK, DATA) for ECC as an interface with the NAND chip 200. The input and output terminals 310 for SPI of the ECC chip 300 are electrically coupled to the corresponding terminals of the input and output terminals 210 for SPI of the NAND chip 200, respectively, and the input and output terminals 320 for ECC are electrically coupled to the corresponding terminals of the input and output terminals 220 for ECC of the NAND chip 200, respectively.

[0059] The ECC chip 300 further includes input and output terminals 330 (#CS, CLK, DI, DO, #WP, #HOLD) for SPI as an interface with the controller chip 400. The input and output terminals 330 are electrically coupled to the corresponding terminals of the input and output terminals 410 for SPI of the controller chip 400. Each of the terminals of the input and output terminals 310 (#CS, CLK, DI, DO, #WP, #HOLD) is electrically coupled to the corresponding terminal of the input and output terminals 330 (#CS, CLK, DI, DO, #WP, #HOLD) by internal wiring or the like, respectively. That is, the input and output terminals 310 and the input and output terminals 330 are physically arranged apart for the connection of the NAND chip 200 and the controller chip 400, but in terms of electrical properties, the input and output terminals 310 and the input and output terminals 330 are common to the NAND chip 200 and the controller chip 400, and such connection is equivalent to the connection of the input and output terminals 210 for SPI of the NAND chip 200 to the input and output terminals 410 for SPI of the controller chip 400.

[0060] Figure 4 A block diagram showing the internal structure of the NAND chip 200 and the ECC chip 300. Note, however, that the structure related to the ECC operation is shown in the NAND chip 200, and not all structures are shown.

[0061] The NAND chip 200 includes: a page buffer / sensing circuit 230 including a latch LI, a latch L2; an oscillator OSC generating a clock signal CK; an interface circuit (hereinafter referred to as an ECC_IF) 240 controlling data transfer with the ECC chip 300 via the ECC-dedicated input / output terminal 220; an interface circuit (hereinafter referred to as a CTL_IF) 250 controlling data transfer with the controller chip 400 via the SPI-dedicated input / output terminal 210; an ECC control section 260; a controller 270 receiving a command and an address input from the input / output terminal 210, including a decoder interpreting the command or an address counter performing hold and count of the address, and controlling each section based on the decoding result of the command; and an address control section 280 controlling the column address of the page buffer / sensing circuit 230.

[0062] The latch LI and the latch L2 each include a buffer CO and a buffer CI, and the latch LI and the latch L2 can perform bidirectional data transfer in units of the buffer CO and the buffer CI. The latch LI and the latch L2 each hold one page of data (e.g., 4 KB), and the buffer CO and the buffer CI each hold one-half page of data (e.g., 2 KB). For example, in a case where one page includes eight sectors, the buffer CO holds data of four sectors S0 to S3 (e.g., one sector is 512 bytes), and the buffer CI holds data of four sectors S4 to S7.

[0063] The oscillator OSC generates the clock signal CK, which is a frequency most suitable for the data transfer time and the processing time of each section of the ECC operation. The data transfer between the NAND chip 200 and the ECC chip 300 using the DATA terminal is performed in synchronization with the clock signal CK, and the ECC processing by the ECC core 360 of the ECC chip 300 is performed in synchronization with the clock signal CK. The frequency of the clock signal CK is independent of the frequency of the clock signal CLK of the SPI, and can be set to be higher than the frequency of the clock signal CLK.

[0064] The ECC_IF 240 receives the clock signal CK generated by the oscillator OSC, and supplies the clock signal to the CK terminal of the ECC chip 300. The ECC_IF 240 outputs the read data held in the latch L2 from the DATA terminal to the DATA terminal of the ECC chip 300 at a timing synchronized with the clock signal CK at the time of the read operation, and receives the parity data generated by the ECC chip 300 from the DATA terminal at a timing synchronized with the clock signal CK at the time of the program operation.

[0065] The ECC control section 260 supplies the VALID signal to the ECC_IF 240 at the time of readout operation. The VALID signal defines a period in which data transfer between the ECC exclusive input / output terminal 220 and the input / output terminal 320 becomes valid. The ECC_IF 240 transfers data from the DATA terminal of the NAND chip 200 to the DATA terminal of the ECC chip in the period defined by the VALID signal, for example, in the period in which the VALID signal is at the high level. Further, the ECC_IF 240 outputs the VALID signal from the VALID terminal to the VALID terminal of the ECC chip 300 so that the NAND_IF 340 of the ECC chip 300 can receive data from the NAND chip 200.

[0066] The CTL_IF 250 controls input / output of data via the input / output terminal 210. The CTL_IF 250 receives a command, an address, and data output from the controller chip 400, supplies the command and the address to the controller 270, and holds the data in the latch L2 or the latch LI.

[0067] The controller 270 decodes the input command and controls readout, programming, erasure, and the like based on the decoding result. Further, the controller 270 supplies a control flag for identifying readout or programming to the ECC control section 260 or a status signal indicating whether the NAND chip 200 is busy or in standby state to the CTL_IF 250 based on the decoding result. The controller 270 includes an address counter that counts a column address input from the CTL_IF 250 and supplies the address of the address counter to the address control section 280.

[0068] The ECC control section 260 includes logic for controlling ECC processing and an address counter that performs holding and counting of addresses for ECC processing. The ECC control section 260 is configured in the same manner as the ECC control section 370 of the ECC chip 300, that is, the ECC control section 260 is synchronized with the ECC control section 370 so that it can identify what kind of ECC operation is performed by the ECC chip 300. Further, the control flag is used for switching of the encoder or the decoder performed by the ECC core 360.

[0069] The address control section 280 receives a column address output from the controller 270 and an ECC exclusive column address output from the ECC control section 260 and supplies a column address selected in accordance with the operation of the NAND chip 200 to the page buffer / sense circuit 230. The position of data read out from the latch L2 or the position of data written in the latch L2 is controlled by the column address.

[0070] The ECC chip 300 includes random access memories RAM0, RAM1; an interface circuit (hereinafter referred to as NAND_IF) 340 that controls data transfer with the NAND chip 200 via the ECC-dedicated input / output terminal 320; an interface circuit (hereinafter referred to as CTL_IF) 350 that controls input and output of data with the NAND chip 200 and the controller chip 400 via the SPI-dedicated input / output terminal 330 and the input / output terminal 310; an ECC core 360 that performs error detection and correction; an ECC control section 370 that includes logic for controlling the ECC core 360 and an address counter that performs holding and counting of addresses for ECC processing; and a controller 380 that receives commands, addresses, and data input from the input / output terminal 310 and the input / output terminal 330.

[0071] Note here that in the ECC chip 300, the controller 380 is mounted to recognize what action is performed by the NAND chip 200, and the controller 380 receives input commands and addresses, includes a decoder that interprets the commands or an address counter that performs holding and counting of addresses, similarly to the controller 270 of the NAND chip 200. Also, the SPI-dedicated input / output terminal 330 is electrically connected to the corresponding terminal of the SPI-dedicated input / output terminal 310, and commands, addresses, and data from the controller 400 are supplied to both the ECC chip 300 and the NAND chip 200.

[0072] The RAM0 and the RAM1 hold 1 / 2 page data, respectively, for example, the RAM0 holds data of sectors S0 to S3, and the RAM1 holds data of sectors S4 to S7. When a read operation is performed in the NAND chip 200, the NAND_IF 340 receives one page data from the NAND chip 200 in units of sectors via the ECC-dedicated input / output terminal 220 and the input / output terminal 320 during a period in which the VALID signal is high active. The received data is stored in the RAM0 or the RAM1 selected by the selector SEL1 as data 0 (Data0) (for example, sectors S0 to S3) or data 1 (Data1) (for example, sectors S4 to S7).

[0073] The ECC control section 370 selects the address of the RAMO or the RAMl by the selector SEL3 when performing error detection and correction of read data in the ECC core 360, and supplies the data read from the selected RAMO or RAMl to the ECC core 360. The ECC core 360 performs syndrome calculation, Euclidean division calculation, and error position search in pipeline processing for the data read from the RAMO or the RAMl under the control of the ECC control section 370, and inverts the error bit of the data read from the RAMO or the RAMl selected by the selector SEL4 in order to correct the error based on the searched error position, and outputs the corrected data to the controller chip 400 via the input / output terminal 330 through the CTL_IF 350.

[0074] Also, when performing a program operation, the command, address, and data from the controller chip 400 are input to the ECC chip 300 in addition to the NAND chip 200. The controller 380 recognizes the program operation based on the decoding result of the command, and saves the input data in the RAMO and the RAMl. The ECC control section 370 recognizes the program operation by the control flag from the controller 380, causes the encoder of the ECC core 360 to operate, and supplies the VALID signal to the NAND_IF 340. The VALID signal is also supplied to the VALID terminal of the NAND chip 200.

[0075] The ECC core 360 reads the input data held in the RAMO or the RAMl under the control of the ECC control section 370, encodes the read data in units of sectors, and generates the parity data for each sector. The generated parity data is transmitted from the DATA terminal via the NAND_IF 340 to the DATA terminal of the NAND chip 200. The NAND chip 200 holds the data received from the controller chip 400 in the latch L2, holds the parity data for each sector received from the ECC chip 300 via the ECC_IF 240 in the latch L2 in accordance with the column address designated by the ECC control section 260, and transmits the data held in the latch L2 to the latch LI. Then, the controller 270 programs the data held in the latch LI to the memory array.

[0076] Next, the ECC operation of the flash memory 100 of the present embodiment will be described in detail. Figure 5Fig. 6 shows a timing chart for decoding read data by the ECC core 360. When the NAND chip 200 performs a read operation in accordance with a read command, at time tO, the ECC IF 240 of the NAND chip 200 sends the main data and the parity data Pt of the sector SO held in the latch L2 from the DATA terminal in synchronization with the clock signal CK, and the NAND IF 340 of the ECC chip 300 starts receiving the main data and the parity data Pt of the sector SO from the DATA terminal. At time tl, the reception of the main data and the parity data Pt of the sector SO ends. With respect to the transmission time from time tO to time tl, since the data width of the DATA terminal dedicated to ECC and the frequency of the clock signal CK are optimized for ECC processing, the time can be shorter than the time for transmitting data via the input / output terminal 210 for SPI. Similarly, at time t2, the transmission of the main data and the parity data Pt of the sector Sl ends, at time t3, the transmission of the main data and the parity data Pt of the sector S2 ends, and at time t4, the transmission of the main data and the parity data Pt of the sector S3 ends.

[0077] The data of the sectors SO to S3 received from the NAND chip 200 are sequentially stored in the RAMO. At the same time as storing the data of the sector SO in the RAMO, the ECC core 360 starts calculating the syndrome of the sector SO. In some embodiments, the bit width of the DATA terminal or the frequency of the clock signal CK is set in such a manner that the calculation of the syndrome of the sector SO ends at time tl. After calculating the syndrome, the ECC core 360 performs the error position polynomial calculation and error position search of the sector SO in the reception of the sector Sl.

[0078] At time t5, the ECC core 360 reads the main data of the sector SO from the RAMO selected by the selector SEL4 and the selector SEL5 in synchronization with the clock signal CLK, inverts the bit error of the main data of the sector SO by ExOR, and outputs the error-corrected main data of the sector SO from the DO terminal of the input / output terminal 330 to the controller chip 400 in synchronization with the clock signal CLK for SPI. The ECC core 360 performs error correction of the sectors Sl, S2, and S3 at times t6, t7, and t8, and sequentially outputs the error-corrected main data of the sectors Sl, S2, and S3 to the controller chip 400 via the input / output terminal 330. The CPU IF of the controller chip 400 transmits the main data of the sectors SO, Sl, S2, and S3 received at times t6, t7, t8, and t9 to the host device. Although the ECC operation related to the sectors S4 to S7 is not shown, the processing of the sectors S4 to S7 is performed similarly after the processing of the sectors SO to S3.

[0079] Figure 6(A) and Figure 6 (B) is a diagram showing the timing of data transmission of the master data and parity data of sector S0. Figure 6 (A) is a comparative example. At time t0, the main data of sector S0 is transmitted. At time t1, the parity data of sector S0 is transmitted. At time t2 after the parity data is transmitted, the main data of the next sector S1 is transmitted. At time t3, the parity data of sector S1 is transmitted.

[0080] When performing parity calculations simultaneously with data transmission between the chip and the chip, the timing of these calculations needs to be aligned. Although parity data is stored in a spare area, its size is 16×N bytes (N is a natural number), and not the entire area is used for parity data. In this embodiment, it is not as... Figure 6 Instead of transmitting the entire spare area as parity data as shown in (B), only the parity data of the spare area is transmitted. Therefore, the transmission of parity data for sector S0 can be completed before time t2. The completion of the corrector calculation introduces a latency relative to the transmission of parity data; data transmission for sector S1 begins at the moment the corrector calculation for sector S0 is completed. To transmit only the necessary data when necessary, both the NAND chip 200 and the ECC chip 300 are equipped with an ECC control unit 260 and an ECC control unit 370 containing an address counter for ECC, sharing the ECC-related operations of both the NAND chip 200 and the ECC chip 300.

[0081] Figure 7 (A) and Figure 7 (B) is a diagram showing the timing of parity check data generation performed by the ECC core. Figure 7 (A) is Figure 1 Following the usual procedure, at time t0, controller chip 30 receives data from sector S0 from the host device, and then receives data from sectors S1, S2, and S3 from the host device at certain time intervals. At time t1, controller chip 30 begins generating parity data via ECC function 40. At time t2, it sends the main data and parity data Pt of sector S0 to NAND chip 20 via the SPI input / output terminals. At time t3, it receives data from the next sector S1. At time t4, it begins generating parity data for sector S1. At time t5, the generation of parity data for sector S1 ends, and it begins sending the main data and parity data for sector S1. If NAND chip 20 receives a page of main data and parity data from sectors S0 to S7 from controller chip 30, it programs this data into the select page of the memory array.

[0082] In this embodiment, asFigure 7 As shown in (B), the controller chip 400 receives the data of the sector SO from the host device at time tO, and then receives the data of the sector SI, the sector S2, and the sector S3 from the host device at certain time intervals. At time tl, the CTL_IF of the controller chip 400 transmits the host data of the sector SO to the ECC chip 300 via the input / output terminal 410 for SPI. At this time, the input / output terminal 210 of the NAND chip 200 is connected to the input / output terminal 410 of the controller chip 400 via the input / output terminal 310 and the input / output terminal 330 of the ECC chip, and thus the data of the sector SO is introduced into the NAND chip 200, and the introduced data of the sector SO is held in the latch L2.

[0083] The controller chip 400 receives the data of the sector SI from the host device at time t2, and transmits the host data of the sector SI to the ECC chip 300 at time t3. If the ECC chip 300 completes the reception of the host data of the sector SO, the ECC core 360 generates the parity data based on the host data of the sector SO, and the NAND_IF 340 transmits the generated parity data of the sector SO from the DATA terminal for ECC to the NAND chip 200 at time t4. The transmission of the parity data from time t4 to time t5 is performed via the input / output terminal 220 and the input / output terminal 320 for ECC, and thus is faster than the transmission via SPI. In this way, the NAND chip 200 sequentially receives the parity data of each sector, holds the received parity data in the latch L2, transmits the data of the latch L2 to the latch LI, and then programs the host data and the parity data of each sector held in the latch LI to the selected page of the memory array. By shortening the transmission time of the parity data between the ECC chip 300 and the NAND chip, the timing of performing the programming can be accelerated.

[0084] Figure 8 A diagram showing the structure of the flash memory 100 when the ECC chip 300 is not mounted in the embodiment. The flash memory 100 houses only the NAND chip 200 in the package, and the input / output terminal 210 for SPI of the NAND chip 200 is connected to the input / output terminal 410 for SPI of the controller chip 400. When the ECC function is not needed, the cost of the flash memory can be reduced by cutting the ECC chip.

[0085] Figure 9 A diagram showing the structure of the flash memory of the modification of the embodiment, and the structure of the flash memory is the same as that of the embodiment shown in FIG. 6. Figure 3The same structure is assigned the same reference numeral. In this example, the flash memory 100A includes a plurality of NAND chips 200A stacked. The input and output terminals 210 for the SPI and the input and output terminals 220 for the ECC are electrically connected among the plurality of NAND chips 200A. For example, the input and output terminals 210 and the input and output terminals 220 among the stacked chips are commonly connected by a conductive member that penetrates the silicon substrate of the stacked NAND chips. The input and output terminals 210 and the input and output terminals 220 of the uppermost NAND chip 200A of the stacked chips are respectively electrically connected to the input and output terminals 310 and the input and output terminals 320 of the ECC chip 300 by wiring or the like.

[0086] Although the input and output terminals 210 and the input and output terminals 220 of the NAND chips 200A are commonly connected to each other, each NAND chip 200A can determine which chip is selected. For example, the address counter of the controller 270 of each NAND chip 200A can monitor the address space of the overall memory array including all the NAND chips 200A, i.e., the number of bits of the address counter can represent the address space of the overall memory array, and the controller 270 determines which chip is selected by identifying the memory array corresponding to the address input by the user.

[0087] Therefore, by sharing one ECC chip 300 by the plurality of NAND chips 200A, a flash memory that realizes high integration and shortens the processing time of the error detection and correction function can be provided.

[0088] Next, the timing of the continuous readout operation of the page of the flash memory of the present embodiment is illustrated in Figure 10 The upper half of the figure shows the operation of the NAND chip 200, and the lower half shows the timing of the ECC chip 300. After the NAND chip 200 outputs the data of the final address of each page, it starts reading the next array, and after transferring the data of the page PO to the latch L2, it substantially starts the continuous readout from the readout of the page PI.

[0089] The NAND chip 200 transfers the data of the sectors SO to S7 of each page to the ECC chip 300 during the period in which the VALID signal is high, and if the ECC chip 300 outputs the data of the sectors SO to S3 or the sectors S4 to S7 from the DO terminal in units of buffers, the NAND chip 200 transfers the data of the next page to the ECC chip 300 in response to the timing. The timing at which the NAND chip 200 transfers the data to the ECC chip 300 becomes the timing at which the ECC chip 300 outputs the final address in units of buffers to the controller chip 400. For example, the NAND chip 200 starts transferring the data of the sectors SO to S3 of the page PI after the ECC chip 300 completes the output of the sectors SO to S3 of the page PO.

[0090] As for the timing of the final address of the controller chip 400 output buffer unit by the ECC chip 300, it is sufficient to recognize the number of toggles of the clock signal CLK connected also to the NAND chip 200 using the address counter in the controller 270 in the NAND chip 200. The ADD counter in the controller 270 of the NAND chip 200 is used to control the data output from the CTL_IF 250 when the ECC chip 300 is not mounted or when error correction is not performed, but the data is not output from the CTL_IF 250 when error correction is performed, and thus can be used for the purpose.

[0091] Figure 11 A timing chart showing the case where an interruption occurs in the continuous readout of a page. As shown in the figure, even if the data output from the DO terminal is interrupted (interruption is shown at the DO terminal) in the continuous readout due to the stop of the clock signal CLK or the like, the readout data is held in the RAMO, RAMl by the ECC chip 300, and thus the data is prevented from disappearing due to the interruption. Further, the NAND chip 200 and the ECC chip 300 share the address of the page being read out, and thus the continuous readout can be correctly started again after the interruption.

[0092] Next, the copyback function of the flash memory of the present embodiment will be described. In the present embodiment, the corrected data generated by the ECC chip can be written back to the NAND chip 200 using the ECC dedicated input and output terminals 220, 320 between the NAND chip 200 and the ECC chip 300, and at this time, the number of cycles required for the copyback can be further reduced compared to the past.

[0093] In the conventional flash memory (structure shown in Figure 1 In order to copy back the corrected data after error correction, a command needs to be input to the NAND chip 20 in the conventional flash memory (structure shown in FIG. 1). In the case where the addresses where errors occur are scattered, a random data input command is used, and the corrected data is transferred to the NAND chip by the number of errors. In the case where 4-bit errors occur at non-continuous addresses in the case where the interface of the NAND chip 20 is ONFi, an example of the action of the copyback is shown in (A) of FIG. 8. Figure 12

[0094] ​If the error correction is completed, the controller chip 30 outputs the correction address and the correction data to the NAND chip 20. During the period when the CLE terminal is input as an H level, the random data input command is input to the I / O terminal, during the period when the ALE is input as an H level, the correction address ADD0 to ADD3 is input to the I / O terminal, and during the period when the CLE terminal and the ALE terminal are input as L levels, the correction data DA0 to the correction data DA3 is input to the I / O terminal at the rising edge of #WE. The NAND chip 20 sets the correction data in the latch LI based on the correction address, and then programs the data held in the latch LI to the memory array according to the input program command.

[0095] Figure 12 (B) indicates an example of the copyback operation of the present embodiment. After the error position is found, the ECC core 360 inverts the error bits of the data held in the RAM0 or the RAM1, and holds the error-corrected data in the RAM0 or the RAM1. The ECC control section 370 supplies the VALID signal to the NAND_IF 340, and the NAND_IF 340 transfers the correction data DA0 to the correction data DA3 and the correction address ADD0 to the correction address ADD3 read from the RAM0 or the RAM1 to the NAND chip 200 via the DATA terminal according to the VALID signal. In the present embodiment, the command does not need to be input every time the correction address and the correction data are transferred, and thus the copyback operation can be performed in a shorter time than in the past.

[0096] Figure 13 is a timing chart of each section of the ECC chip at the time of the copyback operation of the present embodiment. The operations at times t0 to t4 are the same as those of Figure 5 At time t4, the error position polynomial of the sector S3 is started to be calculated, the error position search of the sector S3 is started at time ta, and the error position search of the sector S3 is ended at time tb. During the period from time t4 to time tb, the NAND_IF 340 transfers the correction data D0, D1, and D2 of the sectors S0, S1, and S2 to the NAND chip 200 via the DATA terminal, and if the error position search (including error correction) of the sector S3 is ended at time tb, the NAND_IF 340 transfers the correction data D3 of the sector S3 to the NAND chip 200, and the transfer of the correction data D3 is ended at time tc. Then, the data held in the latch LI is programmed to the memory array from the controller chip 400.

[0097] According to the present embodiment, the input and output terminals dedicated to the ECC are provided in the NAND chip 200 and the ECC chip 300, and data related to the ECC is transmitted via the dedicated input and output terminals, so that the ECC processing can be performed at high speed although it is off-chip. Further, in the present embodiment, an example in which the bit width of the DATA terminal dedicated to the ECC is 32 bits (x 32) is shown, but this is only an example. Also, the frequency of the clock signal CK does not necessarily have to be higher than the frequency of the clock signal CLK. If the bit width of the DATA terminal is larger than the bit width of the data transmission of the SPI, the frequency of the clock signal CK can be the same as or lower than the frequency of the clock signal CLK.

[0098] The preferred embodiments of the present application have been described in detail, but the present application is not limited to the specific embodiments, and various modifications and changes can be made within the scope of the gist of the present application recited in the claims.

Claims

1. A semiconductor memory device comprising: a NAND chip including a memory array of a NAND type and a control section that controls an operation related to the memory array; and an error detection and correction chip including an error detection and correction function; the NAND chip includes a first dedicated terminal for performing data transmission related to error detection and correction, and the error detection and correction chip includes a second dedicated terminal connected to the first dedicated terminal, wherein the first dedicated terminal includes a first clock terminal and a first data terminal, the second dedicated terminal includes a second clock terminal connected to the first clock terminal and a second data terminal connected to the first data terminal, the NAND chip includes a generation circuit that generates a clock signal shared by the first clock terminal and the second clock terminal, data between the first data terminal and the second data terminal is transmitted in synchronization with the clock signal, the first dedicated terminal further includes a first active terminal, and the second dedicated terminal further includes a second active terminal connected to the first active terminal, an active signal that activates data transmission is supplied to the first active terminal or the second active terminal.

2. The semiconductor memory device according to claim 1, wherein the NAND chip transmits readout data including parity data read out from the memory array by the control section to the error detection and correction chip via the first dedicated terminal, the error detection and correction chip performs error detection and correction of the readout data received via the second dedicated terminal.

3. The semiconductor memory device according to claim 1, wherein the error detection and correction chip transmits parity data generated based on program data to the NAND chip via the second dedicated terminal, the control section programs program data including the parity data received via the first dedicated terminal to the memory array.

4. The semiconductor memory device according to claim 1, wherein the NAND chip generates the active signal when transmitting readout data to the error detection and correction chip, and supplies the generated active signal to the first active terminal.

5. The semiconductor memory device according to claim 1, wherein the error detection and correction chip generates the active signal when transmitting parity data to the NAND chip, and supplies the generated active signal to the second active terminal.

6. The semiconductor memory device according to any one of claims 1 to 3, wherein the error detection and correction chip performs error detection and correction of readout data while receiving the readout data.

7. The semiconductor memory device according to any one of claims 1 to 3, wherein the NAND chip and the error detection and correction chip are housed in one package.

8. The semiconductor memory device according to any one of claims 1 to 3, wherein The NAND chip includes a plurality of NAND chips stacked, and the first dedicated terminals of the plurality of NAND chips are commonly connected to the second dedicated terminals of the error detection / correction chip.

9. A semiconductor memory device, comprising: a NAND chip including a memory array of a NAND type and a control section that controls an operation related to the memory array; and an error detection / correction chip including an error detection and correction function; the NAND chip includes first dedicated terminals for data transfer related to error detection / correction, and the error detection / correction chip includes second dedicated terminals connected to the first dedicated terminals, the NAND chip further includes first input / output terminals capable of transmitting and receiving data between the NAND chip and the error detection / correction chip, the error detection / correction chip further includes second input / output terminals capable of transmitting and receiving data between the error detection / correction chip and the NAND chip, and the first input / output terminals are connected to the second input / output terminals, a data transfer width of the first dedicated terminals and the second dedicated terminals is larger than a data transfer width of the first input / output terminals and the second input / output terminals.

10. The semiconductor memory device according to claim 9, wherein a clock frequency of data transfer between the first dedicated terminals and the second dedicated terminals is higher than a clock frequency of data transfer of the first input / output terminals and the second input / output terminals.

11. The semiconductor memory device according to claim 9, wherein the error detection / correction chip further includes third input / output terminals capable of transmitting and receiving data between the error detection / correction chip and a controller chip, the first input / output terminals are commonly connected to the second input / output terminals and the third input / output terminals.

12. The semiconductor memory device according to claim 9, wherein the error detection / correction chip outputs error-corrected data to a controller chip via the second input / output terminals.

13. The semiconductor memory device according to claim 9, wherein the error detection / correction chip outputs error-corrected data to the NAND chip via the first dedicated terminals and the second dedicated terminals.

14. The semiconductor memory device according to claim 11, wherein the error detection / correction chip receives program data via the third input / output terminals, the NAND chip receives program data from the first input / output terminals connected to the second input / output terminals and the third input / output terminals.

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