Fault bit count circuit for memory and method thereof

Abstract

A failure bit counting circuit of a memory array, wherein the memory array includes a plurality of pages, each of the plurality of pages includes a plurality of sectors and a redundancy column. The failure bit counting circuit of each page includes a plurality of failure bit counting units, each of the plurality of failure bit counting units is coupled to a respective sector to provide a failure bit counting current, a redundancy failure bit counting unit coupled to the redundancy column to provide a redundancy current, a switch having a first terminal and a second terminal, wherein the switch is switched to couple to one of the outputs of the plurality of failure bit counting units to receive the failure bit counting current from one of the plurality of failure bit counting units, and a comparator having a first input terminal, a second input terminal and an output terminal, wherein the first input terminal receives a reference current, the second input terminal receives a measurement current that is a sum of the failure bit counting current and the redundancy current, and the comparator outputs a decision signal at the output terminal to indicate a number of failure bits of the respective sector by comparing the reference current and the measurement current.

Description

Technical Field

[0001] This invention relates to a fault bit counting circuit and method for a memory. Background Technology

[0002] For example, memory devices such as flash memory require a failure bit count (FBC) function during programmed verification operations because the memory device allows n-bit failures in a sector. To correct these failure bits, the memory device needs an error correction code (ECC) engine.

[0003] Figure 1 The diagram illustrates the configuration of the memory cell and fault bit counting mechanism used to repair memory devices. For example... Figure 1 As shown, a page 10 of the memory device may include multiple general regions 12, such as sector-1, sector-2, sector-3, and sector-4, and a redundant region 14. The structure of the redundant region 14 is substantially the same as that of the general regions 12. When the number of fault bits in any general region 12 exceeds the allowable number of fault bits, the redundant region 14 is used to replace the general region to repair the memory.

[0004] also, Figure 2 A fault bit counting circuit for a memory device is illustrated. The page buffer includes a fault bit counting unit FBC-1, but it does not provide row redundancy address information. Therefore, in the prior art, a possible way to obtain the number of fault bits is to calculate it for each page rather than for each sector. Finally, the fault bit counting unit FBC-1 outputs a fault bit counting current I. SEC1 The fault bit counting current I SEC1 The current increases as the number of fault bits n increases. Comparator CMP1 counts the fault bits using the current I. SEC1 With reference current I REF The comparison is performed to output the judgment signal JUDGE[n].

[0005] Through the fault bit counting unit FBC-1, when the programmed verification fails (as shown by the dashed line, a low level L is provided to the fault bit counting unit FBC-1) and node L1S remains at a low level L, the NMOS transistor N2 turns on. When the number of fault bits is n, the fault bit counting current I... SEC1 Equal to fault current I FB Multiply by the value of the number n. Furthermore, the reference current generator (current mirror) including NMOS transistors N11 and N12 provides a reference current I to comparator CMP1. REF Therefore, comparator CMP1 can output a judgment signal JUDGE[n] to indicate the number of fault bits n.

[0006] However, the above configuration only allows for fault bit counting on a per-page basis. Therefore, it is necessary to provide a fault bit counting circuit capable of counting fault bits for each sector. Summary of the Invention

[0007] Based on the above description, according to an embodiment of the present invention, a fault bit counting circuit for a memory array is provided, wherein the memory array includes multiple pages, each of the multiple pages including multiple sectors and a redundant column. The fault bit counting circuit for each of the multiple pages includes: multiple fault bit counting units, each of which is coupled to one of the multiple sectors to provide a fault bit counting current; a redundant fault bit counting unit coupled to the redundant column and providing redundant current; a switch having a first terminal and a second terminal, wherein the switch is switched to couple to one of the outputs of the multiple fault bit counting units to receive the fault bit counting current from one of the multiple fault bit counting units; and a comparator having a first input terminal, a second input terminal, and an output terminal, wherein the first input terminal receives a reference current, the second input terminal receives a measured current obtained by adding the fault measurement current and the redundant current, and the comparator, by comparing the reference current and the fault measurement current, causes the output terminal to output a judgment signal to indicate the number of fault bits in each of the multiple sectors.

[0008] According to one embodiment of the present invention, the above-described fault position counting circuit further includes: a first current-to-voltage converter for converting the reference current into a reference voltage; and a second current-to-voltage converter for converting the measured current into a measured voltage.

[0009] According to one embodiment of the present invention, the above-described fault bit counting circuit further includes a voltage divider that divides the reference voltage into N voltage divider reference voltages, wherein N is equal to the allowable number of fault bits for each of the plurality of sectors.

[0010] According to one embodiment of the present invention, in the above-described fault bit counting circuit, the comparator further includes N comparator modules, wherein each of the N comparator modules has a first input terminal for receiving a corresponding voltage divider reference voltage from the N voltage divider reference voltages; each of the N comparator modules has a second input terminal for receiving the measured voltage, and the outputs of the N comparator modules provide the judgment signal.

[0011] According to one embodiment of the present invention, in the above-described fault bit counting circuit, the switch includes a plurality of transistors having the same number as the plurality of sectors, the plurality of transistors being respectively connected to the plurality of sectors, and the plurality of transistors being connected in parallel and operated in such a manner that only one of the plurality of transistors is turned on at a time.

[0012] According to one embodiment of the present invention, in the above-described fault bit counting circuit, each of the plurality of fault bit counting units includes a current mirror and a latch coupled to the current mirror, and the result of the programmed verification of the sector is latched in the latch so as to enable the current mirror when the programmed verification fails.

[0013] According to one embodiment of the present invention, in the above-described fault bit counting circuit, the redundant fault bit counting unit has the same configuration as each of the plurality of fault bit counting units.

[0014] According to one embodiment of the present invention, the fault bit counting circuit further includes at least one reference current generator for generating the reference current. According to another embodiment of the present invention, in the fault bit counting circuit, the at least one reference current generator is disposed in the well pickup area of ​​the page buffer of the memory array.

[0015] According to one embodiment of the present invention, in the above-described fault bit counting circuit, the plurality of fault bit counting units and the redundant fault bit counting units are provided in the page buffer of the memory array.

[0016] According to one embodiment of the present invention, in the above-described fault bit counting circuit, the comparator and the switch are disposed in the peripheral area of ​​the memory array.

[0017] According to one embodiment of the present invention, in the above-mentioned fault position counting circuit, the judgment signal adopts a hot code or a binary code.

[0018] According to another embodiment of the present invention, a counting method for a fault bit counting circuit of a memory array is provided, wherein the memory array includes a plurality of pages, each of the pages includes a plurality of sectors and a redundant column, each of the plurality of sectors is provided with a fault bit counting unit and the redundant column has redundant fault bit counting units. The counting method for each sector includes: providing a fault bit counting current with the fault bit counting unit; providing a redundant current through the redundant fault bit counting unit; generating a fault measurement current by adding the fault bit counting current and the redundant current; and comparing the fault measurement current with a reference current to provide a judgment signal indicating the number of fault bits in each of the plurality of sectors.

[0019] According to an embodiment of the present invention, the above-described fault position counting method includes: converting the fault measurement current into a fault measurement voltage; converting the reference current into a reference voltage; and comparing the fault measurement voltage with the reference voltage to provide the judgment signal.

[0020] According to one embodiment of the present invention, in the above-described fault bit counting method, the judgment signal adopts a hot code or a binary code.

[0021] According to the present invention, a fault bit counting unit is provided for each sector of a page, and the same fault bit counting unit is also provided for redundant rows. Furthermore, by adding the fault bit counting current and the redundant current and comparing it with a reference current, the number of fault bits in each sector can be effectively determined. Attached Figure Description

[0022] Figure 1 The diagram illustrates the architecture and fault bit counting mechanism used to repair memory cells in memory devices.

[0023] Figure 2 A fault bit counting circuit for memory is illustrated according to the prior art.

[0024] Figure 3 A fault bit counting circuit for a memory array according to an embodiment of the present invention is illustrated.

[0025] Figure 4 A schematic diagram showing the layout of the fault bit counting circuit of the memory array.

[0026] Figure 5 A schematic diagram illustrating an exemplary detailed architecture of a fault bit counting circuit according to an embodiment of the present invention is shown.

[0027] Figure 6 A flowchart illustrating a fault bit counting method for a memory according to an embodiment of the present invention is shown.

[0028] 10, 100: Memory array

[0029] Page 101

[0030] 12, 102: General Area

[0031] 14, 104: Redundant areas

[0032] 106: Comparator

[0033] 108: Page Buffer

[0034] 110: Well Picking Area

[0035] 112: X Decoder

[0036] 120: Surrounding Area

[0037] 130: Voltage divider

[0038] FBC-1~FBC-4: Fault Position Counting Unit

[0039] FBC-RED: Redundant Fault Bit Counting Unit

[0040] I SEC1 ~I SEC4 Fault position counting current

[0041] I RED Redundant current

[0042] I REF Reference current

[0043] I FB Fault position current

[0044] I MEAS Fault measurement current

[0045] I BIAS Current source

[0046] JUDGE[n], JUDGE[0]~JUDGE[3]: Judgment signal

[0047] INV1, INV2: Inverters

[0048] L1S, L1R: Nodes

[0049] CMP1: Comparator

[0050] COMP0~COMP3: Comparator modules

[0051] A1: Operational amplifier

[0052] SHC1: Sample-and-hold comparator

[0053] LAT1: Latch

[0054] N11, N12: NMOS transistors

[0055] N1~N4: NMOS transistors

[0056] N30~N33, N40: NMOS transistors

[0057] N20, N21[1]~N21[4], N22, N23: NMOS transistors

[0058] SEL[1]~SEL[4]: Control signals

[0059] NET21~NET23, NET30, NET31: Nodes

[0060] VDD: Voltage source

[0061] BIAS1: Bias voltage

[0062] FBREF, REF: Reference current generator

[0063] SW1~SW4: Switches

[0064] V REF V REF0 ~V REF3 Reference voltage

[0065] V MEAS Fault measurement voltage

[0066] V NEG Negative terminal voltage

[0067] V POS Positive terminal voltage

[0068] V HOLD Maintaining voltage

[0069] R: Resistance

[0070] C1: Capacitor

[0071] S100~S106: Each step Detailed Implementation

[0072] Figure 3 A fault bit counting circuit for a memory array according to an embodiment of the present invention is illustrated. In this embodiment, a flash memory can be used as an example. The flash memory includes a memory array having multiple banks, and each bank has multiple pages, each page further comprising multiple sectors. Figure 3 As shown, an example of a page 101 of a memory array 100 is illustrated. Each page 101 includes multiple general regions 102 (e.g., sector-1, sector-2, sector-3, sector-4) and redundant regions (or redundant columns) 104. The redundant regions 104 are used to repair memory cells in any of the general regions 102.

[0073] Furthermore, the page buffer 108 is equipped with multiple fault bit counting units FBC-1, FBC-2, FBC-3, and FBC-4, and each fault bit counting unit FBC-1, FBC-2, FBC-3, and FBC-4 is coupled to sector-1, sector-2, sector-3, and sector-4 (general area 102), respectively. For example, when a fault bit exists in sector-1, i.e., when the programmed verification fails, a low-level signal L is sent to the fault bit counting unit FBC-1, and the fault bit counting unit FBC-1 outputs a fault bit counting current I. SEC1 It is the fault current I FB n times. That is, the fault position counting current I. SEC1 Equal to fault current I FB n times, where n is the number of fault bits.

[0074] Furthermore, a redundant fault bit counting unit FBC-RED is provided in the page buffer 108 for the redundant region 104. The redundant fault bit counting unit FBC-RED has the same structure as the fault bit counting units FBC-1, FBC-2, FBC-3, and FBC-4. The redundant fault bit counting unit FBC-RED can output a redundant current I. RED .

[0075] Furthermore, the fault position counting circuit also includes a switch SW1 with a first terminal and a second terminal, which can be switched to the output terminals of fault position counting units FBC-1, FBC-2, FBC-3, and FBC-4. That is, switch SW1 can be switched to each of the fault position counting units FBC-1, FBC-2, FBC-3, and FBC-4 at predetermined time intervals, such that the fault position counting current I of the fault position counting units FBC-1, FBC-2, FBC-3, and FBC-4... SEC1 ~I SEC4 They can be read out separately.

[0076] In addition, the fault bit counting circuit also includes a comparator 106, whose first input receives a reference current I. REF The second input terminal receives the fault measurement current I. MEAS And for each sector, by comparing the reference current I REF and fault measurement current I MEAS This causes comparator 106 to output a judgment signal JUDGE[n] indicating the number of fault bits. Fault measurement current I MEAS It is achieved by using the fault bit counting current I SEC1 (I SEC2 I SEC3 Or I SEC4 and redundant current I RED It is obtained by adding them together.

[0077] For example, when switch SW1 is switched to connect to fault position counting unit FBC-1, fault position counting unit FBC-1 will provide fault position counting current I. SEC1 To the second input terminal of comparator 106. Additionally, the redundant current I... RED This is also provided to the second input of comparator 106. As a result, the second input of comparator 106 receives the fault measurement current I. MEAS1 It is the fault position counting current I. SEC1 and redundant current I RED The sums are then added together. Then, comparator 106 will add the fault measurement current I... MEAS1 The reference current I supplied to the first input terminal of comparator 106 REF The comparison is performed, and the judgment signal JUDGE[n] for sector-1 of general region 102 is output. Therefore, the number of fault bits in sector-1 can be determined. Then, the fault bit count is performed sequentially for other sectors-2, sector-3, and sector-4.

[0078] Figure 4 A schematic diagram showing the layout of a fault bit counting circuit in a memory array. For example, as shown... Figure 4 As shown, the memory may include a memory array 100, a page buffer 108, an X decoder 112, and a peripheral area 120. Only the necessary parts are illustrated here, and the memory may also include other components that can be added at will by those skilled in the art. Within the memory array 100 and page buffer 108, the memory may also provide multiple well pick-up (well taps) areas 110, arranged along the vertical direction (or column direction) of the memory array 100. The memory array 100 may include multiple general areas 102 (sectors) and redundant areas 104.

[0079] like Figure 4 As shown, Figure 3 The fault bit counting units FBC-1, FBC-2, FBC-3, and FBC-4 shown are configured in the page buffer 108 of each general area (sector) 102. Figure 4 As shown, only the fault bit counting unit FBC-1 is used as an example for illustration; the configuration of other fault bit counting units FBC-2, FBC-3, and FBC-4 is the same. It is worth noting that, for simplicity, only one output I of the fault bit counting unit FBC-1 is shown. SEC1 .

[0080] like Figure 4As shown, the fault bit counting unit FBC-1 includes NMOS transistors N1 and N2 and inverters INV1 and INV2. The gate of NMOS transistor N2 is coupled to node L1R, and the drain of NMOS transistor N2 is coupled to the source of NMOS transistor N1. The drain of NMOS transistor N1 is grounded, and the gate of NMOS transistor N1 is biased by bias voltage BIAS1. The source of NMOS transistor N2 receives the fault bit current I from the target sector (sector-1 in this example). FB .

[0081] In addition, the reference current I supplied to comparator 106 REF This can be achieved using a current mirror. The reference current generator FBREF is repositioned in the well pickup area 110 within the page buffer 108. The location of the reference current generator FBREF is marked with an asterisk. Furthermore, the number and location of the reference current generator FBREF can be considered using "basic device mismatch improvement." The more reference current generators FBREF there are, the smaller the device mismatch. In this example, m reference current generators FBREF are provided.

[0082] For example, the reference current generator FBREF includes NMOS transistors N11 and N12. The gate of NMOS transistor N12 is coupled to a voltage source VDD, and the drain of NMOS transistor N12 is connected to the source of NMOS transistor N11. The drain of NMOS transistor N11 is grounded, and the gate of NMOS transistor N11 is biased by a bias voltage BIAS1. NMOS transistors N11 and N12 have the same pattern density as NMOS transistors N1 and N2 in the fault bit counting unit FBC-1 (or FBC-2 to FBC-4). Furthermore, the dimensions of NMOS transistors N11-N12 in the reference current generator FBREF can be the same as the dimensions of NMOS transistors N1-N2 in the fault bit counting unit FBC.

[0083] also, Figure 3 The switch SW1 and comparator 106 of the fault position counting circuit shown are located in the peripheral area 120. Furthermore, the bias voltage BIAS1 provided to the reference current generator FBREF can also be located in the peripheral area 120.

[0084] Figure 5 An exemplary detailed configuration of a fault bit counting circuit according to an embodiment of the present disclosure is shown, and reference will be made to... Figure 5 To describe the detailed operation. In this exemplary embodiment, four sectors are provided for each page of the memory array, and in the page buffer 108 (see...) Figure 4 Eight reference current generators FBREF are provided in well pickup area 110.

[0085] refer to Figure 5 It also provides four comparator modules COM0 to COM3 as... Figure 3 The comparator 106 is shown. According to the embodiment, if n fault bits are allowed in a sector, n comparator modules can be provided. In this embodiment, four fault bits are allowed in a sector as an example. When there are no fault bits in a sector, the JUDGE[n] outputs of comparator modules COM0-3 are all at a low level L. Table 1 illustrates the combination of the outputs JUDGE[n] of comparator modules COM0-3. Referring to Table 1, when there are two fault bits in a sector, the JUDGE[0] and JUDGE[1] outputs of comparator modules COM0-1 are at a high level H, while the outputs JUDGE[2] and JUDGE[3] of comparator modules COM2-3 are at a low level L. Therefore, the number of fault bits in each sector can be determined based on the outputs JUDGE[n] of comparator modules COM0-3. As a result, the judgment signals JUDGE[3:0] present a thermometer code, which can identify three fault bits. In the case of 4 or more fault bits, all JUDGE[3:0] bits of the judgment signal JUDGE[n] go high (H). Alternatively, the judgment signal JUDGE[n] can also use binary code.

[0086] Table 1

[0087]

[0088] In addition, such as Figure 5 As shown, although eight reference current generators FBREF are provided to generate 8·I REF The reference current is required, but only one reference current generator FBREF is needed. Therefore, a pair of source-coupled NMOS transistors N32 and N33 are provided to generate the 8.1 I REF The reference current is separated into the reference current I flowing through the NMOS transistor N12. REF and the reference current 7·I flowing through NMOS transistor N13 REF As shown in the figure, each reference current generator FBREF is a current mirror composed of NMOS transistors N1 and N2, and the eight reference current generators FBREF have the same configuration and size.

[0089] exist Figure 5 The document also provides a first current-to-voltage (IV) converter with a unity-gain negative feedback configuration, comprising NMOS transistors N30, N32, and N33 and a current source I. BIAS Node NET30 is forced by negative feedback to the critical voltage V of NMOS transistor N30.TH The first IV converter can convert the reference current I at node NET30. REF Convert to reference voltage V REF .

[0090] In addition, a voltage divider 130 with resistors connected in series is included. In this example, the voltage divider 130 includes four resistors 0.5R, R, R, R to divide the reference voltage V. REF The voltage divider consists of four reference voltages (voltage divider reference voltages) V. REF0 ~V REF3 Reference voltage V REF0 ~V REF3 These are respectively provided to one input terminal of the comparator module COM0~3. Additionally, the number of reference voltages after voltage division corresponds to the number of allowed fault bits. In this example, each sector can allow 4 fault bits, therefore the reference voltage V... REF Divided into four reference voltages V REF0 ~V REF3 .

[0091] For example, reference voltage V REF0 One input terminal of comparator A1 provided to comparator module COM0 is reference voltage V. REF1 One input terminal of comparator A1 provided to comparator module COM1 is reference voltage V. REF2 One input terminal of comparator A1 of comparator module COM2 is provided, and the reference voltage V REF3 This provides one input to comparator A1 of comparator module COM3.

[0092] Furthermore, taking four fault bit counting units FBC-1 to FBC-4 as an example, each fault bit counting unit FBC includes NMOS transistors N3 and N4, which are as follows: Figure 4 The fault bit counting units FBC-1 to FBC-4 are used, but the latches are omitted for simplicity. For example... Figure 5 As shown, the fault bit counting units FBC-1 to FBC-4 respectively provide the fault bit counting current I. SEC1 ~I SEC4 .

[0093] Furthermore, to maintain the same pattern density between the reference current generator FBREF and the fault bit counting units FBC-1 to FBC-4, the NMOS transistors N1 and N2 and NMOS transistors N3 and N4 are of the same size. As a result, the reference current I... REF Equal to fault current I FB .

[0094] In addition, NMOS transistors N21[1]~N21[4] serve as Figure 3The switch SW1 is shown. NMOS transistors N21[1] to N21[4] are respectively connected to fault bit counting units FBC-1 to FBC-4. For example, fault bit counting unit FBC-1 is connected to NMOS transistor N21[1], and fault bit counting unit FBC-3 is connected to NMOS transistor N21[3]. NMOS transistors N21[1] to N21[4] are controlled to be turned on or off by control signals SEC[1] to SEC[3]. Only one of NMOS transistors N21[1] to N21[4] is turned on at any time, and the others are turned off. The function of NMOS transistors N21[1] to N21[4] is similar to the OR operation.

[0095] like Figure 5 As shown, an NMOS transistor N23 is further provided to connect to provide redundant current I. RED Redundant fault bit counting unit FBC-RED (e.g.) Figure 3 (As shown). The gate of NMOS transistor N23 is connected to the voltage source VDD to ensure that NMOS transistor N23 can always be turned on.

[0096] NMOS transistors N21[1] to N21[4] and NMOS transistor N23 are used to provide fault measurement current I MEAS It is the redundant current I RED and fault position counting current I SEC1 ~I SEC4 The sum of one of them. Then, the fault measurement current I... MEAS Provided to comparator modules COM0~3.

[0097] Furthermore, a second current-to-voltage (IV) converter with a unity-gain negative feedback configuration is provided, and includes NMOS transistors N20 and N22 and current source I. BIAS Node NET22 is forced by negative feedback to the critical voltage V of NMOS transistor N20. TH The second IV converter can measure the fault current I at node NET23. MEAS Converted to fault measurement voltage V MEAS Afterwards, the fault measurement voltage V MEAS Provided to the other input terminal of comparator module COM0~3.

[0098] Next, taking sector -1 as an example, NMOS transistor N21[1] is turned on, while NMOS transistors N21[2] to N21[4] are turned off. As a result, the fault measurement current I MEAS Become the fault position counting current I SEC1 and redundant current I RED The sum of these values ​​is converted into a fault measurement V. MEASThis is then provided to another input terminal of the comparator module COM0~3. Additionally, the reference voltage V... REF0 ~V REF3 Each of these inputs corresponds to one of the input terminals of comparator modules COM0 to COM3. For example, comparator module COM0 is the reference voltage V. REF0 The comparator module COM2 is the reference voltage V. REF2 Wait a minute. Then, the comparator module COM0 will read the fault measurement value V. MEAS With reference voltage V REF0 The comparator module COM1 compares the fault measurement value V. MEAS With reference voltage V REF1 The comparator module COM2 compares the fault measurement voltage V. MEAS With reference voltage V REF2 The comparison is performed, and the comparator module COM3 will measure the fault voltage V. MEAS With reference voltage V REF3 Comparisons are made. As listed in Table 1, for example, if there are 2 fault bits in sector-1, the fault measurement current I... MEAS Become 2I FB Therefore, the outputs JUDGE[0] and JUDGE[1] of comparator modules COM0 and COM1 are at a high level H, and the outputs JUDGE[2] and JUDGE[3] of comparator modules COM2 and COM3 are at a low level L. Therefore, if the low level L is defined as "0" and the high level H is defined as "1", the judgment signal JUDGE[n] output from comparator 106 becomes "1100". Therefore, the fault bit number of sector -1 can be determined.

[0099] Next, the operation of comparator modules COM0 to COM3 will be described in detail. Each comparator module COM0 to COM3 has the same configuration. In this embodiment, comparator modules COM0 to COM3 are sample-and-hold comparators as an example. Figure 5 As shown, each comparator module COM0~COM3 includes a sample-and-hold comparator SHC1 and a latch LAT1. As illustrated, the sample-and-hold comparator SHC1 includes an operational amplifier A1, a capacitor C1, and switches SW1 and SW3. The latch LAT1 includes inverters INV1 and INV2, which are as follows... Figure 5 The connections are shown. Each comparator module COM0 to COM3 also includes a switch SW4, which is turned on during the hold period, allowing latch LAT1 to latch the output of operational amplifier A1.

[0100] For each sector, after programmatic verification, the result of the programmatic verification is latched by latches (including inverters INV1, INV2, etc.). Figure 4(As shown) The latch exists at node L1R. Initially, comparator modules COM0 to COM3 are in the sampling period. Taking sector-1 as an example, one of the NMOS transistors N21[1] to N21[4] is turned on, that is, NMOS transistor N21[1] is turned on by the control signal SEL[1], and the fault bit counting current I SEC1 and redundant current I RED The fault measurement current I is generated by adding the two. MEAS At the same time, switch SW2 switches to the negative terminal voltage V. NEG (i.e. V) REF And switch SW3 is turned on while switch SW4 is turned off. As a result, operational amplifier A1 becomes a unity-gain buffer and maintains voltage V. HOLD This is equal to the output voltage of operational amplifier A1. Furthermore, since the output voltage of operational amplifier A1 is the negative terminal voltage V... NEG Therefore, the two ends of capacitor C1 are at the same potential.

[0101] Afterwards, comparator modules COM0 to COM3 enter the holding period. Switch SW2 therefore switches to the positive terminal voltage V. POS (that is, V) MEAS When switch SW3 is open and switch SW4 is closed, switch SW2 switches to voltage V. POS At that time, the potential of capacitor C1 on the side of switch SW2 changes from the negative terminal voltage V. NEG Transform into positive terminal voltage V POS Additionally, maintain voltage V HOLD The voltage of C1 follows the voltage on the SW2 side of the switch. Therefore, operational amplifier A1 acts as a comparator to compare the fault measurement voltage V. MEAS (V POS ) and reference voltage V REF (V NEG Furthermore, the output of operational amplifier A1 is latched by latch LAT1. Therefore, comparator modules COM0 to COM3 output judgment signals JUDGE[3:0].

[0102] Figure 6 A flowchart of a memory fault bit counting method according to an embodiment of the present invention is shown. This flowchart is executed for each sector in a page of a memory array. For simplicity, it will be referred to as... Figure 3 Taking sector-1 as an example, the number of fault bits for other sectors (sector-2 to sector-4) can be determined in the same way.

[0103] like Figure 6 and Figure 3 As shown, in step S100, the fault bit counting unit FBC-1 provides the fault bit counting current I. SEC1For example, when a programmed verification of sector-1 fails, the fault bit counter unit FBC-1 latches the result of the programmed verification, thereby enabling the current mirror of the fault bit counter unit FBC-1 to generate a fault bit counting current I. SEC1 That is, the fault current I FB n times, where n is the number of fault bits.

[0104] In step S102, the redundant fault bit counting unit FBC-RED also provides redundant current I. RED ,like Figure 3 As shown above, the redundant fault bit counting unit FBC-RED continuously provides a redundant current I to the second input terminal of comparator 106. RED ,like Figure 3 As shown.

[0105] Next, in step S104, by controlling the fault bit counting current I... SEC1 and redundant current I RED The summation is used to generate the fault measurement current I. MEAS Fault bit counting current I SEC1 It is also provided to the same second input terminal of comparator 106, thereby converting the fault bit counting current I. SEC1 With redundant current I RED Add (i.e., fault measurement current I) MEAS And provide it to comparator 106.

[0106] In step S106, the fault measurement current I is... MEAS With reference current I REF A comparison is made to provide a judgment signal JUDGE[n], which indicates the number of faulty bits in the sector. The judgment signal JUDGE[n] can be represented using hotcode or binary, as illustrated in Table 1 above. The number of faulty bits can be determined by using the judgment signal JUDGE[n].

[0107] In summary, according to the present invention, a fault bit counting unit is set for each sector of a page, and the same fault bit counting unit is also set for redundant columns. Furthermore, by adding the fault bit counting current and the redundant current and comparing it with a reference current, the number of fault bits in each sector can be effectively determined.

Claims

1. A fault bit counting circuit for a memory array, wherein the memory array includes multiple pages, each of the multiple pages including multiple sectors and a redundant column, and the fault bit counting circuit for each of the multiple pages includes: Multiple fault bit counting units, each of which is coupled to one of the multiple sectors to provide fault bit counting current; A redundant fault bit counting unit is coupled to the redundant column and provides redundant current. A switch having a first terminal and a second terminal, wherein the switch is switched to couple to one of the outputs of the plurality of fault bit counting units to receive the fault bit counting current from one of the plurality of fault bit counting units; as well as The comparator has a first input terminal, a second input terminal, and an output terminal, wherein the first input terminal receives a reference current, the second input terminal receives a measured current obtained by adding the fault measurement current and the redundant current, and the comparator outputs a judgment signal at the output terminal by comparing the reference current and the fault measurement current to indicate the number of fault bits in each of the plurality of sectors.

2. The fault bit counting circuit for the memory array as described in claim 1, further comprising: A first current-to-voltage converter converts the reference current into a reference voltage; as well as A second current-to-voltage converter converts the measured current into a measured voltage.

3. The fault bit counting circuit for the memory array as described in claim 2, further comprising: A voltage divider divides the reference voltage into N voltage divider reference voltages, where N is equal to the allowable number of fault bits for each of the plurality of sectors.

4. The fault bit counting circuit for a memory array as described in claim 3, wherein the comparator further comprises N comparator modules, wherein Each of the N comparator modules has a first input terminal, which receives the corresponding voltage divider reference voltage from the N voltage divider reference voltages. Each of the N comparator modules has a second input terminal to receive the measured voltage, and The outputs of the N comparator modules provide the judgment signal.

5. The fault bit counting circuit for the memory array as claimed in claim 1, wherein the switch comprises a plurality of transistors having the same number as the plurality of sectors. The plurality of transistors are respectively connected to the plurality of sectors, and The plurality of transistors are connected in parallel and operate in such a manner that only one of the plurality of transistors is turned on at a time.

6. The fault bit counting circuit for the memory array of claim 1, wherein each of the plurality of fault bit counting units includes a current mirror and a latch coupled to the current mirror, and the result of programmed verification of the sector is latched in the latch so as to enable the current mirror in the event of failure of the programmed verification.

7. The fault bit counting circuit for the memory array as claimed in claim 1, wherein the redundant fault bit counting unit has the same configuration as each of the plurality of fault bit counting units.

8. The fault bit counting circuit of the memory array as claimed in claim 1 further includes at least one reference current generator for generating the reference current.

9. The fault bit counting circuit of the memory array as claimed in claim 8, wherein the at least one reference current generator is disposed in the well pickup area of ​​the page buffer of the memory array.

10. The fault bit counting circuit of the memory array as claimed in claim 1, wherein the plurality of fault bit counting units and the redundant fault bit counting unit are provided in the page buffer of the memory array.

11. The fault bit counting circuit for a memory array as claimed in claim 1, wherein the comparator and the switch are disposed in the peripheral area of ​​the memory array.

12. The fault bit counting circuit of the memory array as described in claim 1, wherein the judgment signal adopts a hot code or a binary code.

13. A counting method for a fault bit counting circuit of a memory array, wherein the memory array comprises multiple pages, each of the pages comprises multiple sectors and a redundant column, each of the multiple sectors is provided with a fault bit counting unit and the redundant column has redundant fault bit counting units, the counting method for each sector comprising: The fault bit counting unit provides the fault bit counting current; Redundant current is provided through a redundant fault bit counting unit; The fault measurement current is generated by adding the fault bit counting current and the redundant current; The fault measurement current is compared with a reference current to provide a judgment signal indicating the number of fault bits in each of the plurality of sectors.

14. The counting method of the fault bit counting circuit of the memory array as described in claim 13, further comprising: Convert the fault measurement current into a fault measurement voltage; Convert the reference current into a reference voltage; as well as The fault measurement voltage is compared with the reference voltage to provide the judgment signal.

15. The counting method of the fault bit counting circuit of the memory array as described in claim 13, wherein the judgment signal adopts a hot code or a binary code.

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