Method for manufacturing a semiconductor device

Abstract

A method of fabricating a semiconductor device includes forming a channel layer and a barrier layer sequentially on a substrate by epitaxy to form the semiconductor device, wherein the channel layer includes a first III-V compound, and wherein the barrier layer includes a second III-V compound; placing the semiconductor device in a chamber; and flowing a high pressure fluid into the chamber to perform a passivation process on defects within the semiconductor device, wherein the high pressure fluid is doped with a compound including at least one of nitrogen, oxygen, and fluorine. After the passivation process, defects within the semiconductor device can be reduced, and material properties of the semiconductor device can be improved.

Description

Technical Field

[0001] This invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for low-temperature passivation of a semiconductor device. Background Technology

[0002] Gallium nitride (GaN) is an ideal material for power devices due to its wide bandgap and high electron mobility. However, traditional GaN epitaxy on silicon substrates is prone to high-density defects due to lattice mismatch. Furthermore, the epitaxy process requires buffer layers, channel layers, and barrier layers to form a two-dimensional electron gas, which can lead to defects at the interfaces between layers. These defects result in increased leakage current, decreased conduction current, and poor reliability. Summary of the Invention

[0003] The present invention aims to provide a method for manufacturing a semiconductor device, comprising: sequentially forming a channel layer and a barrier layer on a substrate using an epitaxial process to form a semiconductor device, wherein the channel layer comprises a first III-V compound, and the barrier layer comprises a second III-V compound; placing the semiconductor device in a cavity; and introducing a high-pressure fluid into the cavity to perform passivation treatment on defects in the semiconductor device, wherein the high-pressure fluid is doped with a compound composed of at least one of nitrogen, oxygen, and fluorine.

[0004] In some embodiments, the method of manufacturing the semiconductor device further includes: forming a P-type III-V compound layer on the barrier layer. The passivation process is performed before the formation of the P-type III-V compound layer, after the formation of the P-type III-V compound layer, or both before and after the formation of the P-type III-V compound layer.

[0005] In some embodiments, the method of manufacturing the semiconductor device further includes forming a dielectric layer on a p-type III-V compound layer. The passivation process is performed before, after, or both before and after the formation of the dielectric layer.

[0006] In some embodiments, the method of manufacturing the semiconductor device further includes forming a gate on a P-type III-V compound layer. The passivation process is performed before, after, or both before and after gate formation.

[0007] In some embodiments, the method of manufacturing the semiconductor device further includes forming a gate on a barrier layer. The passivation process is performed before, after, or both before and after gate formation.

[0008] In some embodiments, the method of manufacturing the semiconductor device further includes forming a dielectric layer on the barrier layer. The passivation process is performed before, after, or both before and after the formation of the dielectric layer.

[0009] In some embodiments, the method of manufacturing the semiconductor device further includes forming a gate on a dielectric layer. The passivation process is performed before, after, or both before and after gate formation.

[0010] In some embodiments, the method of manufacturing the semiconductor device further includes: forming a first insulating layer on a barrier layer; forming source / drain metals on a channel layer, a barrier layer, and a first insulating layer; forming a second insulating layer on the first insulating layer and the source / drain metals; forming a P-type III-V compound layer on the barrier layer and the second insulating layer; and forming a gate metal on the P-type III-V compound layer. Passivation processing is performed before the formation of the source / drain metals, after the formation of the source / drain metals, or before and after the formation of the source / drain metals. Passivation processing is performed before the formation of the second insulating layer, after the formation of the second insulating layer, or before and after the formation of the second insulating layer.

[0011] In some embodiments, the method of manufacturing the semiconductor device further includes: forming an insulating layer on the barrier layer and the gate; and forming source / drain metal on the channel layer. Passivation processing is performed before, after, or both before and after the formation of the source / drain metal. Passivation processing is performed before, after, or both before and after the formation of the insulating layer.

[0012] In some embodiments, the method of manufacturing the semiconductor device further includes: forming an insulating layer on a dielectric layer and a gate; and forming source / drain metal on a channel layer. Passivation processing is performed before, after, or both before and after the formation of the source / drain metal. Passivation processing is performed before, after, or both before and after the formation of the insulating layer.

[0013] In some embodiments, the compound doped by the high-pressure fluid is selected from the group consisting of O2, N2, NO, N2O, NO2, NH3, NH4OH, NH4CL, NH4F, NH4I, NH4Br, (NH4)2SO4, NH4HSO4, NH4NO3, H2O, H2O2, D2O, CO(NH2)2, (NH4)2CO3, NH4HCO3, CO2, CO, SO2, NF3, CF4, HF, WF6, SF6, F2, COF2, CLF3, XeF3, MOF6, TeF6, PF3, PF5, AsF3, AsF5, CH3F, CH2F2, CHF3, C2HF5, C2F6, C3F8, C4F6, C4F8, C5HF7, C5F8, SiF4, BF3, GeF4, CCLF3, C2CLF5, and CHFCL2.

[0014] In some embodiments, high-pressure fluid is used to passivate material defects within a semiconductor device, and the element introduced during the passivation treatment accounts for 10 ppb to 1% of the elemental concentration of the material in the region of the material defect.

[0015] In some embodiments, high-pressure fluid is used to passivate material defects within a semiconductor device, and the concentration of the element introduced during the passivation treatment in the semiconductor material is 1.0 × 10⁻⁶. 15 atom / cm 3 ~1.0×10 21 atom / cm 3 between.

[0016] In some embodiments, the pressure inside the cavity ranges from 10 to 300 atmospheres, and the temperature inside the cavity is below 850°C.

[0017] In some embodiments, the pressure inside the cavity ranges from 50 to 250 atmospheres, and the temperature inside the cavity ranges from 100 to 600°C.

[0018] In some embodiments, the passivation treatment of the semiconductor device by the high-pressure fluid is anisotropic.

[0019] In some embodiments, the first III-V compound is gallium nitride (GaN), and the second III-V compound is aluminum gallium nitride (AlGaN).

[0020] In some embodiments, the above-mentioned P-type III-V compound layer is a P-type gallium nitride (p-GaN) layer.

[0021] In some embodiments, the defects in the semiconductor device include at least one of the following: interface defects between the channel layer and the barrier layer, lattice defects, and defects caused by etching and heterojunctions between material layers.

[0022] To make the above features and advantages of the present invention more apparent and understandable, specific embodiments are described below in conjunction with the accompanying drawings. Attached Figure Description

[0023] A better understanding of the invention can be obtained from the following detailed description taken in conjunction with the accompanying drawings. It should be noted that, according to industry standard practice, the features are not drawn to scale. In fact, the dimensions of the features can be arbitrarily increased or decreased for clarity of discussion.

[0024] Figure 1 This is a flowchart of a method for manufacturing a semiconductor device according to an embodiment of the present invention.

[0025] Figure 2 This is a schematic diagram of the passivation process of a semiconductor device according to a first embodiment of the present invention.

[0026] Figure 3 This is a schematic diagram of the passivation process of a semiconductor device according to a second embodiment of the present invention.

[0027] Figure 4 This is a schematic diagram of the passivation process of a semiconductor device according to a third embodiment of the present invention.

[0028] Figure 5 This is a schematic diagram of the passivation process of a semiconductor device according to a fourth embodiment of the present invention.

[0029] Figure 6 This is a schematic diagram of the passivation process of a semiconductor device according to a fifth embodiment of the present invention.

[0030] Figure 7 This is a schematic diagram of the passivation process of a semiconductor device according to a sixth embodiment of the present invention.

[0031] Figure 8 This is a schematic diagram of the passivation process of a semiconductor device according to the seventh embodiment of the present invention.

[0032] Figure 9A This is a schematic diagram of the passivation process of a semiconductor device according to the eighth embodiment of the present invention.

[0033] Figure 9B This is a schematic diagram of the passivation process of a semiconductor device according to the ninth embodiment of the present invention.

[0034] Figure 9CThis is a schematic diagram of the passivation process of a semiconductor device according to the tenth embodiment of the present invention.

[0035] Figure 10 This is a schematic diagram of the interface defect density of a semiconductor device without passivation treatment and after passivation treatment according to an embodiment of the present invention.

[0036] Figure 11 This is a schematic diagram showing the relationship between the drain voltage and drain current of a semiconductor device without passivation treatment and after passivation treatment according to an embodiment of the present invention.

[0037] [Explanation of Key Component Symbols]

[0038] 110: Substrate

[0039] 120: Channel Layer

[0040] 130: Barrier Layer

[0041] 140: Layer of P-type III-V compounds

[0042] 150: Dielectric layer

[0043] 160: Source / Drain Metal

[0044] 170, 172, 174: Insulation layer

[0045] G: Gate

[0046] C1, C2: Line segments

[0047] S1, S2, S3: Steps Detailed Implementation

[0048] The embodiments of the present invention will be discussed in detail below. However, it will be understood that the embodiments provide many applicable concepts that can be implemented in a wide variety of specific contexts. The discussed and disclosed embodiments are for illustrative purposes only and are not intended to limit the scope of the invention. The terms "first," "second," etc., used herein do not specifically refer to any order or sequence, but are merely used to distinguish elements or operations described using the same technical terms.

[0049] Figure 1 This is a flowchart of a method for manufacturing a semiconductor device according to an embodiment of the present invention. Figure 2 This is a schematic diagram of the passivation process of a semiconductor device according to a first embodiment of the present invention. In step S1 of the semiconductor device manufacturing method, a channel layer 120 and a barrier layer 130 are sequentially formed on a substrate 110 using an epitaxial process to form a semiconductor device.

[0050] In embodiments of the present invention, the material of the substrate 110 may be sapphire, silicon (Si), aluminum nitride (AlN), silicon carbide (SiC), or gallium nitride (GaN), but the present invention is not limited thereto. In embodiments of the present invention, the substrate 110 may also be selectively doped with a material to form a conductive substrate or a non-conductive substrate. In the case of a silicon substrate (Si), the dopant may be boron (P) or magnesium (Mg).

[0051] In embodiments of the present invention, the channel layer 120 comprises a first III-V compound. The first III-V compound is, for example, gallium nitride (GaN), but the present invention is not limited thereto. The channel layer 120 may be a doped or undoped layer with a thickness of at least 500 nm.

[0052] In an embodiment of the present invention, the barrier layer 130 comprises a second III-V compound. The second III-V compound is, for example, aluminum gallium nitride (AlGaN), wherein the proportion of Al is not more than half that of Ga, such as Al... 0.2 Ga 0.8 N or Al 0.3 Ga 0.7 N, etc., but the present invention is not limited thereto. The barrier layer 130 has a higher bandgap than the channel layer 120, the thickness of the barrier layer 130 is between 10 and 30 nm, and the lattice constant of the barrier layer 130 is smaller than that of the channel layer 120. Due to the spontaneous polarization of the barrier layer 130, and the piezoelectric polarization formed by the mismatch of the lattice constants of the channel layer 120 and the barrier layer 130, a two-dimensional electron gas is formed at the interface between the channel layer 120 and the barrier layer 130.

[0053] In other embodiments of the present invention, a buffer layer (not shown) may be epitaxially formed on the substrate 110 before forming the channel layer 120. The buffer layer is used to improve the epitaxial quality of the channel layer 120 and the barrier layer 130 subsequently formed thereon. The buffer layer is used to reduce the difference in lattice constant and coefficient of thermal expansion between the substrate 110 and the channel layer 120. The material of the buffer layer is, for example, a group III nitride, such as a group III-V compound semiconductor material, and may have a single-layer or multi-layer structure. The materials of the buffer layer include aluminum nitride (AlN), aluminum gallium nitride (AlGaN), indium gallium nitride (InGaN), aluminum indium nitride (AlInN), aluminum gallium indium nitride (AlGaInN), or combinations thereof.

[0054] In other embodiments of the present invention, a nucleation layer (not shown) may be provided between the buffer layer and the substrate 110. The nucleation layer is used to improve the epitaxial quality of the buffer layer and channel layer 120 subsequently formed thereon, and to further reduce the defect density of the channel layer 120, which is beneficial to the growth of subsequent film layers. The material of the nucleation layer is a III-V compound semiconductor material, such as aluminum nitride (AlN), gallium nitride (GaN), or aluminum gallium nitride (AlGaN).

[0055] Specifically, the semiconductor device of the present invention is a compound semiconductor device.

[0056] In an embodiment of the present invention, in step S2 of the semiconductor device manufacturing method, the semiconductor device is placed in a cavity. The cavity is a cavity having a reaction chamber and fluid inlet / outlet ports to facilitate the introduction of high-pressure fluid.

[0057] In an embodiment of the present invention, in step S3 of the semiconductor device manufacturing method, a high-pressure fluid is introduced into a cavity to perform passivation treatment on defects within the semiconductor device. In this embodiment, during passivation treatment, the pressure within the cavity ranges from 10 to 300 atmospheres, and the temperature within the cavity is below 850°C. In another embodiment, during passivation treatment, the pressure within the cavity ranges from 50 to 250 atmospheres, and the temperature within the cavity ranges from 100 to 600°C. Specifically, conventionally, the pressure for depositing passivation layers is typically a vacuum. In contrast, the present invention utilizes a high-pressure and low-temperature cavity environment to perform passivation treatment on defects within the semiconductor device. Compared to a vacuum environment, a high-pressure environment has a greater total number of gas molecules, allowing more gas molecules to diffuse into the semiconductor device and then react with the material defects within the semiconductor device to passivate them.

[0058] In embodiments of the present invention, the passivation treatment of the semiconductor device by the high-pressure fluid is anisotropic, for example, the passivation treatment is... Figures 2-8 as well as Figures 9A-9C The diagram illustrates two sizes of non-directional gas molecules.

[0059] In embodiments of the present invention, the high-pressure fluid is doped with a compound composed of at least one of nitrogen, oxygen, and fluorine as a co-solvent. Specifically, the compound doped with the high-pressure fluid is selected from O2, N2, NO, N2O, NO2, NH3, NH4OH, NH4Cl, NH4F, NH4I, NH4Br, (NH4)2SO4, NH4HSO4, NH4NO3, H2O, H2O2, D2O, CO(NH2)2, (NH4)2CO3, NH4HCO3, CO2, CO, SO2, NF3, CF4, HF, WF6, SF6, F2, COF2, CLF3, XeF3, MOF6, TeF6, PF3, etc. The proportion of compounds in the group consisting of PF5, AsF3, AsF5, CH3F, CH2F2, CHF3, C2HF5, C2F6, C3F8, C4F6, C4F8, C5HF7, C5F8, SiF4, BF3, GeF4, CCLF3, C2CLF5, and CHFCL2 can be adjusted according to actual needs. In an embodiment of the present invention, high-pressure fluid is used to passivate material defects within the semiconductor device, and the concentration of the element introduced by the passivation treatment in the semiconductor material is 1.0 × 10⁻⁶. 15 atom / cm 3 ~1.0×10 21 atom / cm 3 Between. In embodiments of the present invention, high-pressure fluid is used to passivate material defects within a semiconductor device. The material defects include defects within the bulk material and interface defects. The element concentration ratio of the element introduced during the passivation treatment in the material defect region can be 10ppb~100ppm, 10ppb~1000PPM, 10ppb~0.1%, or 10ppb~1%.

[0060] In embodiments of the present invention, the defects in the semiconductor device repaired by passivation treatment include at least one of the following: interface defects between the channel layer 120 and the barrier layer 130, lattice defects, and defects caused by etching and heterojunctions between material layers. In embodiments of the present invention, since the density, diffusivity, viscosity, and other properties of high-pressure fluids are between those of liquids and gases, compared to the high permeability and insolubility of gases and the low permeability and extremely high solubility of liquids, high-pressure fluids can possess both high permeability and high solubility. Therefore, lattice defect passivation, interface defect passivation, and thin film modification (such as reducing leakage current, but not limited thereto) can be performed on semiconductor devices. Passivation refers to the process of reacting the aforementioned defects, which may have dangling bonds or unstable bonds, with the elements of the high-pressure gas flow to form more stable bonds.

[0061] Figure 3This is a schematic diagram of the passivation process of a semiconductor device according to a second embodiment of the present invention. In the second embodiment of the present invention, the method of manufacturing the semiconductor device further includes forming a p-type III-V compound layer 140 on the barrier layer 130. The p-type III-V compound layer 140 is, for example, a p-type conductive gallium nitride (p-GaN) layer, the thickness of which is between 50 and 150 nm, but the present invention is not limited thereto. The p-type III-V compound layer 140 has a smaller band gap than the barrier layer 130, and the difference in the working function between the p-type III-V compound layer 140 and the barrier layer 130 can be used to adjust the turn-on voltage of the semiconductor device.

[0062] In a second embodiment of the present invention, passivation is performed before the formation of the P-type III-V compound layer 140, after the formation of the P-type III-V compound layer 140, or both before and after the formation of the P-type III-V compound layer 140. Specifically, the passivation process of the present invention can be performed immediately after the epitaxy of each layer (i.e., passivation is performed layer by layer), or the passivation process can be performed after all layers have been epitaxially formed. After passivation, defects in the semiconductor device material can be reduced, and the material performance of the semiconductor device can be improved.

[0063] Figure 4 This is a schematic diagram of the passivation process of a semiconductor device according to a third embodiment of the present invention. In the third embodiment of the present invention, the method of manufacturing the semiconductor device further includes: forming a p-type III-V compound layer 140 on a barrier layer 130, and forming a dielectric layer 150 on the p-type III-V compound layer 140. The p-type III-V compound layer 140 is, for example, a p-type conductive gallium nitride (p-GaN) layer, but the present invention is not limited thereto. The dielectric layer 150 is made of a dielectric material and may have a single-layer or multi-layer structure, with a thickness between 10 and 100 nm. The dielectric layer 150 may be made of aluminum oxide (Al2O3), silicon nitride (Si3N4), silicon oxide, aluminum nitride (AlN), or a combination thereof, but the present invention is not limited thereto.

[0064] In a third embodiment of the present invention, the passivation process is performed before the formation of the dielectric layer 150, after the formation of the dielectric layer 150, or both before and after the formation of the dielectric layer 150. Specifically, the passivation process of the present invention can be performed immediately after each layer is epitaxially plotted (i.e., passivation is performed on each layer individually), or the passivation process of the present invention can be performed after all layers have been epitaxially plotted.

[0065] Figure 5This is a schematic diagram of the passivation process of a semiconductor device according to a fourth embodiment of the present invention. In the fourth embodiment of the present invention, the method of manufacturing the semiconductor device further includes: forming a p-type III-V compound layer 140 on a barrier layer 130, and forming a gate G on the p-type III-V compound layer 140. The p-type III-V compound layer 140 is, for example, a p-type conductive gallium nitride (p-GaN) layer, but the present invention is not limited thereto. The material of the gate G may include a metal or a metal nitride (e.g., Ta, TaN, Ti, TiN, W, Pd, Ni, Au, Al or combinations thereof), a metal silicide (e.g., WSix), or other materials that can form a Schottky contact with the III-V compound semiconductor. For example, the gate G may be formed by etching or lift-off.

[0066] In the fourth embodiment of the present invention, the passivation process is performed before the formation of the gate G, after the formation of the gate G, or both before and after the formation of the gate G. Specifically, the passivation process of the present invention can be performed immediately after each layer is epitaxially formed (i.e., passivation is performed on each layer one by one), or the passivation process of the present invention can be performed after all layers are epitaxially formed.

[0067] Figure 6 This is a schematic diagram of the passivation process of a semiconductor device according to a fifth embodiment of the present invention. In the fifth embodiment of the present invention, the method of manufacturing the semiconductor device further includes: forming a gate G on the barrier layer 130. The material of the gate G may include a metal or a metal nitride (e.g., Ta, TaN, Ti, TiN, W, Pd, Ni, Au, Al or combinations thereof), a metal silicide (e.g., WSix), or other materials that can form a Schottky contact with a III-V compound semiconductor. For example, the gate G may be formed by etching or lift-off.

[0068] In the fifth embodiment of the present invention, the passivation process is performed before the formation of the gate G, after the formation of the gate G, or both before and after the formation of the gate G. Specifically, the passivation process of the present invention can be performed immediately after each layer is epitaxially formed (i.e., passivation is performed on each layer one by one), or the passivation process of the present invention can be performed after all layers are epitaxially formed.

[0069] Figure 7This is a schematic diagram of the passivation process of a semiconductor device according to a sixth embodiment of the present invention. In the sixth embodiment of the present invention, the method of manufacturing the semiconductor device further includes forming a dielectric layer 150 on the barrier layer 130. The dielectric layer 150 is made of a dielectric material and may have a single-layer or multi-layer structure. The material of the dielectric layer 150 includes aluminum oxide (Al2O3), silicon nitride (Si3N4), silicon oxide, aluminum nitride (AlN), or a combination thereof, but the present invention is not limited thereto.

[0070] In the sixth embodiment of the present invention, the passivation process is performed before the formation of the dielectric layer 150, after the formation of the dielectric layer 150, or both before and after the formation of the dielectric layer 150. Specifically, the passivation process of the present invention can be performed immediately after each layer is epitaxially formed (i.e., passivation process is performed on each layer one by one), or the passivation process of the present invention can be performed after all layers are epitaxially formed.

[0071] Figure 8 This is a schematic diagram of the passivation process of a semiconductor device according to a seventh embodiment of the present invention. In the seventh embodiment of the present invention, the method of manufacturing the semiconductor device further includes: forming a dielectric layer 150 on a barrier layer 130, and forming a gate G on the dielectric layer 150. The dielectric layer 150 is made of a dielectric material and may have a single-layer or multi-layer structure. The material of the dielectric layer 150 includes aluminum oxide (Al2O3), silicon nitride (Si3N4), silicon oxide, aluminum nitride (AlN), or combinations thereof, but the present invention is not limited thereto. The material of the gate G may include a metal or a metal nitride (e.g., Ta, TaN, Ti, TiN, W, Pd, Ni, Au, Al, or combinations thereof), a metal silicide (e.g., WSix), or other materials that can form a Schottky contact with a III-V compound semiconductor. For example, the gate G may be formed by etching or lift-off.

[0072] In the seventh embodiment of the present invention, the passivation process is performed before the formation of the gate G, after the formation of the gate G, or both before and after the formation of the gate G. Specifically, the passivation process of the present invention can be performed immediately after each layer is epitaxially formed (i.e., passivation is performed on each layer one by one), or the passivation process of the present invention can be performed after all layers are epitaxially formed.

[0073] Figure 9AThis is a schematic diagram of the passivation process of a semiconductor device according to an eighth embodiment of the present invention. In the eighth embodiment of the present invention, the method of manufacturing the semiconductor device further includes: forming an insulating layer 172 on a barrier layer 130; forming a source / drain metal 160 (S / D metal) on a channel layer 120, a barrier layer 130, and an insulating layer 172; forming an insulating layer 174 on an insulating layer 172 and a source / drain metal 160; forming a P-type III-V compound layer 140 on a barrier layer 130 and an insulating layer 174; and forming a gate metal (gate G) on the P-type III-V compound layer 140.

[0074] In the eighth embodiment of the present invention, the p-type III-V compound layer 140 is, for example, a p-type conductive gallium nitride (p-GaN) layer, but the present invention is not limited thereto. In the eighth embodiment of the present invention, the materials of insulating layers 172 and 174 may be silicon dioxide, silicon nitride, or silicon oxynitride. In the eighth embodiment of the present invention, the material of the source / drain metal 160 may comprise a metal or a metal nitride (e.g., Ta, TaN, Ti, TiN, W, Pd, Ni, Au, Al, or combinations thereof).

[0075] In the eighth embodiment of the present invention, the passivation process is performed before or after the formation of the source / drain metal 160, and before or after the protective layer (insulating layer 172 and / or insulating layer 174) is applied. Specifically, the passivation process of the present invention can be performed immediately after each layer is epitaxially formed (i.e., passivation is performed layer by layer), or the passivation process of the present invention can be performed after all layers have been epitaxially formed.

[0076] Figure 9B This is a schematic diagram of the passivation process of a semiconductor device according to a ninth embodiment of the present invention. In the ninth embodiment of the present invention, the method of manufacturing the semiconductor device further includes: forming a gate G on a barrier layer 130; forming an insulating layer 170 on the barrier layer 130 and the gate G; and forming a source / drain metal 160 on a channel layer 120.

[0077] In a ninth embodiment of the present invention, the material of the gate G may include a metal or a metal nitride (e.g., Ta, TaN, Ti, TiN, W, Pd, Ni, Au, Al, or combinations thereof), a metal silicide (e.g., WSix), or other materials capable of forming a Schottky contact with a III-V compound semiconductor. For example, the gate G may be formed using an etching or lift-off method. In a ninth embodiment of the present invention, the material of the insulating layer 170 may be silicon dioxide, silicon nitride, or silicon oxynitride. In a ninth embodiment of the present invention, the material of the source / drain metal 160 may comprise a metal or a metal nitride (e.g., Ta, TaN, Ti, TiN, W, Pd, Ni, Au, Al, or combinations thereof).

[0078] In the ninth embodiment of the present invention, the passivation process is performed before or after the formation of the source / drain metal 160, and before or after the protective layer (insulating layer 170) is applied. Specifically, the passivation process of the present invention can be performed immediately after each layer is epitaxially formed (i.e., passivation is performed on each layer individually), or the passivation process of the present invention can be performed after all layers have been epitaxially formed.

[0079] Figure 9C This is a schematic diagram of the passivation process of a semiconductor device according to a tenth embodiment of the present invention. In the tenth embodiment of the present invention, the method of manufacturing the semiconductor device further includes: forming a dielectric layer 150 on a barrier layer 130; forming a gate G on the dielectric layer 150; forming an insulating layer 170 on the dielectric layer 150 and the gate G; and forming a source / drain metal 160 on a channel layer 120.

[0080] In the tenth embodiment of the present invention, the dielectric layer 150 is made of a dielectric material and may have a single-layer or multi-layer structure. The dielectric layer 150 may be made of aluminum oxide (Al2O3), silicon nitride (Si3N4), silicon oxide, aluminum nitride (AlN), or combinations thereof, but the present invention is not limited thereto. In the tenth embodiment of the present invention, the gate G may be made of a metal or metal nitride (e.g., Ta, TaN, Ti, TiN, W, Pd, Ni, Au, Al, or combinations thereof), a metal silicide (e.g., WSix), or other materials capable of forming a Schottky contact with a III-V compound semiconductor. For example, the gate G may be formed using an etching or lift-off method. In the tenth embodiment of the present invention, the insulating layer 170 may be made of silicon dioxide, silicon nitride, or silicon oxynitride. In the tenth embodiment of the present invention, the source / drain metal 160 may be made of a metal or metal nitride (e.g., Ta, TaN, Ti, TiN, W, Pd, Ni, Au, Al, or combinations thereof).

[0081] In the tenth embodiment of the present invention, the passivation process is performed before or after the formation of the source / drain metal 160, and before or after the protective layer (insulating layer 170) is applied. Specifically, the passivation process of the present invention can be performed immediately after each layer is epitaxially formed (i.e., passivation is performed on each layer individually), or the passivation process of the present invention can be performed after all layers have been epitaxially formed.

[0082] The passivation treatment of this invention targets defects in the epitaxial growth process and thin film deposition process. It utilizes high-pressure fluid in a high-pressure and low-temperature environment to passivate defects in the lattice, interfaces, and within the material. The preferred timing for passivation is immediately after defect formation to achieve the best improvement effect. In semiconductor manufacturing, after epitaxy, there are internal lattice defects and interface defects between buffer layers, channel layers, and barrier layers. Therefore, passivation after epitaxy can effectively repair these defects. Furthermore, defects arising from etching and heterojunctions between material layers in subsequent processes must also be addressed by incorporating passivation technology into subsequent device fabrication processes after epitaxy to repair these defects. Passivation after epitaxy and during device fabrication can effectively reduce defect density, increase conduction current, reduce leakage current, and improve device reliability. In embodiments of this invention, the interface defect density between the channel layer 120 and the barrier layer 130 in the semiconductor device ranges from 1×10⁻⁶. 11 Up to 1×10 14 cm -2 eV -1 (See references: Trap states analysis in AlGaN / AlN / GaN and InAlN / AlN / GaN high electron mobility transistors; September 2017; Current Applied Physics 17(12)).

[0083] Figure 10 The present invention relates to the channel interface defect density (D0) of semiconductor devices without passivation treatment and after passivation treatment, according to embodiments of the present invention. it A schematic diagram of the interface defect density (D) it The unit is eV. -1 cm -2 ,like Figure 10 As shown, the interface defects of the semiconductor device are significantly reduced after passivation treatment, which also indicates that the dangling bonds at the channel interface of the semiconductor device are largely repaired.

[0084] Figure 11This is a schematic diagram illustrating the relationship between drain voltage and drain current of a semiconductor device without passivation treatment and after passivation treatment according to an embodiment of the present invention, wherein... Figure 11 This is a schematic diagram showing the relationship between the drain voltage (in volts (V)) and the current (in nanoamperes (nA)) measured after the gate of a semiconductor device is turned off. Figure 11 As shown, the off-state leakage current of a passivated semiconductor device (as shown in line segment C2) is reduced by about 30% to 40% compared to the off-state leakage current of an unpassivated semiconductor device (as shown in line segment C1). The lower the leakage current, the lower the system power consumption. Therefore, a passivated semiconductor device can improve system power consumption.

[0085] In summary, this invention proposes a method for manufacturing a semiconductor device, which addresses defects in the epitaxial growth process and the thin film deposition process by using a high-pressure fluid in a high-pressure and low-temperature environment to passivate defects in the lattice, interface, and within the material.

[0086] The foregoing has outlined the features of several embodiments, thus enabling those skilled in the art to better understand the nature of the invention. Those skilled in the art should recognize that they can easily use this invention as a basis to design or modify other processes and structures, thereby achieving the same objectives and / or advantages as the embodiments described herein. Those skilled in the art should also understand that these equivalent constructions do not depart from the spirit and scope of the invention, and that various changes, substitutions, and modifications can be made without departing from the spirit and scope of the invention.

Claims

1. A method for manufacturing a semiconductor device, characterized by, Comprising: forming a channel layer and a barrier layer on a substrate to form a semiconductor device by epitaxial process, wherein the channel layer comprises a first III-V compound, and wherein the barrier layer comprises a second III-V compound; placing the semiconductor device in a chamber; and introducing a high pressure fluid into the chamber to perform a passivation process on defects in the semiconductor device, wherein the high pressure fluid comprises a compound comprising at least one of nitrogen, oxygen, and fluorine; wherein the pressure in the chamber ranges from 10 to 300 atmospheres, and the temperature in the chamber is less than 850 °C.

2. The method for manufacturing a semiconductor device according to claim 1, wherein Further comprising: forming a P-type III-V compound layer on the barrier layer; wherein the passivation process is performed before the P-type III-V compound layer is formed, after the P-type III-V compound layer is formed, or both before and after the P-type III-V compound layer is formed.

3. The method for manufacturing a semiconductor device according to claim 2, wherein Further comprising: forming a dielectric layer on the P-type III-V compound layer; wherein the passivation process is performed before the dielectric layer is formed, after the dielectric layer is formed, or both before and after the dielectric layer is formed.

4. The method for manufacturing a semiconductor device according to claim 2, wherein Further comprising: forming a gate on the P-type III-V compound layer; wherein the passivation process is performed before the gate is formed, after the gate is formed, or both before and after the gate is formed.

5. The method for manufacturing a semiconductor device according to claim 1, wherein Further comprising: forming a gate on the barrier layer; wherein the passivation process is performed before the gate is formed, after the gate is formed, or both before and after the gate is formed.

6. The method for manufacturing a semiconductor device according to claim 1, wherein Further comprising: forming a dielectric layer on the barrier layer; wherein the passivation process is performed before the dielectric layer is formed, after the dielectric layer is formed, or both before and after the dielectric layer is formed.

7. The method for manufacturing a semiconductor device according to claim 6, wherein Further comprising: forming a gate on the dielectric layer; wherein the passivation process is performed before the gate is formed, after the gate is formed, or both before and after the gate is formed.

8. The method for manufacturing a semiconductor device according to claim 1, wherein Further comprising: forming a first insulating layer on the barrier layer; forming a source / drain metal on the channel layer, the barrier layer, and the first insulating layer; forming a second insulating layer on the first insulating layer and the source / drain metal; forming a P-type III-V compound layer on the barrier layer and the second insulating layer; and forming a gate metal on the P-type III-V compound layer; wherein the passivation process is performed before the source / drain metal is formed, after the source / drain metal is formed, or both before and after the source / drain metal is formed; wherein the passivation process is performed before the second insulating layer is formed, after the second insulating layer is formed, or both before and after the second insulating layer is formed.

9. The method for manufacturing a semiconductor device according to claim 5, wherein Further comprising: forming an insulating layer on the barrier layer and the gate; and forming a source / drain metal on the channel layer; wherein the passivation process is performed before the source / drain metal is formed, after the source / drain metal is formed, or both before and after the source / drain metal is formed; wherein the passivation process is performed before the insulating layer is formed, after the insulating layer is formed, or both before and after the insulating layer is formed. Further comprising:

10. The method for manufacturing a semiconductor device according to claim 7, wherein forming an insulating layer on the dielectric layer and the gate; and forming a source / drain metal on the channel layer; ​ wherein the passivation treatment is performed before the source / drain metal formation, after the source / drain metal formation, or both before and after the source / drain metal formation; wherein the passivation treatment is performed before the insulating layer formation, after the insulating layer formation, or both before and after the insulating layer formation.

11. The method of manufacturing a semiconductor device according to Claim 1, wherein wherein the compound doped with the high pressure fluid is selected from the group consisting of O2, N2, NO, N2O, NO2, NH3, NH4OH, NH4Cl, NH4F, NH4I, NH4Br, (NH4)2SO4, NH4HSO4, NH4NO3, H2O, H2O2, D2O, CO(NH2)2, (NH4)2CO3, NH4HCO3, CO2, CO, SO2, NF3, CF4, HF, WF6, SF6, F2, COF2, ClF3, XeF3, MOF6, TeF6, PF3, PF5, AsF3, AsF5, CH3F, CH2F2, CHF3, C2HF5, C2F6, C3F8, C4F6, C4F8, C5HF7, C5F8, SiF4, BF3, GeF4, CClF3, C2ClF5, CHFCl2.

12. The method of manufacturing a semiconductor device according to Claim 1, wherein wherein material defects within the semiconductor device are passivated using the high pressure fluid, wherein the passivation treatment introduces an element into the material defects at a concentration of 10 ppb to 1% of the element in the material in the region of the material defects.

13. The method of manufacturing a semiconductor device according to Claim 1, wherein wherein material defects within the semiconductor device are passivated with the high pressure fluid, wherein the concentration of the introduced element from the passivation process in the material within the semiconductor device is between 1.0 x 10 15 atom / cm 3 and 1.0 x 10 21 atom / cm 3 .

14. The method of manufacturing a semiconductor device according to Claim 1, wherein wherein the pressure within the chamber is in the range of 50 to 250 atmospheres, and wherein the temperature within the chamber is in the range of 100 to 600 °C.

15. The method of manufacturing a semiconductor device according to Claim 1, wherein wherein the passivation treatment of the semiconductor device by the high pressure fluid is anisotropic.

16. The method of manufacturing a semiconductor device according to Claim 1, wherein wherein the first III-V compound is gallium nitride (GaN), and wherein the second III-V compound is aluminum gallium nitride (AlGaN).

17. The method of manufacturing a semiconductor device according to claim 2, wherein wherein the P-type III-V compound layer is a P-type gallium nitride (p-GaN) layer.

18. The method of manufacturing a semiconductor device according to Claim 1, wherein wherein the defects within the semiconductor device include at least one of: interface defects between the channel layer and the barrier layer, lattice defects, and defects due to etching and heterointerfaces between material layers.

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