Chip package and method of manufacturing the same

Abstract

The present application is a chip package and a manufacturing method thereof. The chip package includes a redistribution layer, a chip and a sealing member. The redistribution layer includes an insulating portion, a plurality of first connection pads and a plurality of second connection pads. The insulating portion has a first surface, a second surface opposite to the first surface, and a side surface between the first surface and the second surface. The first connection pads and the second connection pads are located on the first surface and the second surface, respectively. The chip is disposed on the first surface and electrically connected to the first connection pads. The sealing member covers the chip and the redistribution layer, and covers the first surface and the side surface. The sealing member exposes the second connection pads, and the sealing member does not cut the first surface and the side surface. Since the sealing member covers the chip and the redistribution layer, and covers the first surface and the side surface of the redistribution layer, the sealing member can strengthen the structure of the chip package and improve the reliability.

Description

Technical Field

[0001] This invention relates to a chip package and a method for manufacturing the same, and more particularly to a chip package including a redistribution layer (RDL) and a method for manufacturing the same. Background Technology

[0002] After manufacturing, existing chip packages undergo a series of reliability tests to ensure their quality. Current reliability tests include thermal cycling tests (TCTs). During TCTs, the chip package is exposed to extreme temperature variations. For example, the chip package may be tested in an environment with a temperature range of -55°C to 125°C. Therefore, the manufactured chip package needs a structurally robust structure to pass the thermal cycling test, ensuring its reliability. Summary of the Invention

[0003] At least one embodiment of the present invention provides a chip package that improves reliability by using a seal that covers the chip and the redistribution layer.

[0004] At least one embodiment of the present invention provides a method for manufacturing a chip package to manufacture the aforementioned chip package.

[0005] The chip package provided in at least one embodiment of the present invention includes a redistribution layer, a chip, and a seal. The redistribution layer includes an insulating portion, a plurality of first pads, and a plurality of second pads, wherein the insulating portion has a first surface, a second surface opposite to the first surface, and a side surface located between the first and second surfaces. The first pads and the second pads are respectively located on the first and second surfaces. The chip is disposed on the first surface and electrically connected to the first pads. The seal covers the chip and the redistribution layer, and covers the first and side surfaces, wherein the seal exposes the second pads, and the seal is not flush with the first and side surfaces.

[0006] In at least one embodiment of the present invention, the redistribution layer includes a first outer insulating layer and a second outer insulating layer. The first outer insulating layer has a first surface, and the second outer insulating layer has a second surface, wherein the first outer insulating layer is located between the chip and the second outer insulating layer.

[0007] In at least one embodiment of the present invention, the first outer insulating layer comprises an insulating material and a plurality of fillers. These fillers are distributed within the insulating material.

[0008] In at least one embodiment of the present invention, the second outer insulating layer comprises an insulating material and a plurality of fillers. These fillers are distributed within the insulating material.

[0009] In at least one embodiment of the present invention, the redistribution layer further includes at least one inner insulating layer. The inner insulating layer is located between the first outer insulating layer and the second outer insulating layer, wherein each of the first outer insulating layer, the second outer insulating layer, and the inner insulating layer includes an insulating material and a plurality of fillers. These fillers are distributed within the insulating material.

[0010] In at least one embodiment of the present invention, these fillers are a plurality of filler particles or a plurality of filler fibers.

[0011] In at least one embodiment of the present invention, the seal does not cover the second surface.

[0012] In at least one embodiment of the present invention, the seal further covers the second surface.

[0013] In at least one embodiment of the present invention, a portion of the aforementioned sealant fills the gap between the chip and the redistribution layer.

[0014] In at least one embodiment of the present invention, the chip package further includes a plurality of solder blocks, wherein the solder blocks are respectively connected to the second pads.

[0015] In at least one embodiment of the present invention, the second surface is flush with the outer surface of each second pad.

[0016] In at least one embodiment of the present invention, the length and width of the sealing element are respectively greater than the length and width of the redistribution layer.

[0017] A method for manufacturing a chip package according to at least one embodiment of the present invention includes the following steps: First, an initial redistribution layer is formed on a carrier substrate. Then, a plurality of chips are mounted on the initial redistribution layer. Next, the initial redistribution layer is cut to form a plurality of separate redistribution layers, wherein a plurality of trenches are formed between these redistribution layers. Then, a sealant is formed, wherein the sealant covers the chips and redistribution layers and fills the trenches. The carrier substrate is removed. Then, the sealant is cut along the trenches.

[0018] In at least one embodiment of the invention, each redistribution layer has a first surface, a second surface opposite to the first surface, and a side surface located between the first surface and the second surface. The step of forming the seal includes forming a first molding compound on a carrier substrate, wherein the first molding compound covers the chips, the first surface, and the side surface, but does not cover the second surface, and the first molding compound fills the trenches. The carrier substrate is removed after the formation of the first molding compound.

[0019] In at least one embodiment of the present invention, the step of forming a seal further includes forming a second molding material on the second surfaces after removing the carrier substrate, wherein the second molding material is connected to the first molding material.

[0020] In at least one embodiment of the present invention, the method of manufacturing a chip package further includes forming a plurality of solder blocks on these redistribution layers after removing the carrier substrate and before cutting the seal, wherein each redistribution layer is located between one of the chips and the plurality of solder blocks.

[0021] Based on the above, since the seal covers the chip and the redistribution layer, and covers the first surface and side surface of the redistribution layer, the seal can strengthen the structure of the chip package to improve the reliability of the chip package, thereby enabling the chip package to have a structure with sufficient strength to pass the thermal cycling test. Attached Figure Description

[0022] Figure 1A This is a top view schematic diagram of a chip package according to at least one embodiment of the present invention.

[0023] Figure 1B yes Figure 1A A schematic diagram of the cross section drawn along section 1B-1B of the central line.

[0024] Figures 2A to 2G yes Figure 1B A schematic diagram of the manufacturing process of the chip package.

[0025] Figures 3A to 3B This is a schematic flowchart of a method for manufacturing a chip package according to another embodiment of the present invention.

[0026] Figure 4A This is a cross-sectional schematic diagram of a chip package according to another embodiment of the present invention.

[0027] Figure 4B This is a cross-sectional schematic diagram of a chip package according to another embodiment of the present invention.

[0028] Figure 5 This is a cross-sectional schematic diagram of a chip package according to another embodiment of the present invention.

[0029] [Explanation of Key Component Symbols]

[0030] 20: Substrate

[0031] 41m: Insulation material

[0032] 41p, 51f: Filler

[0033] 100, 300, 400a, 400b, 500: Chip package

[0034] 110, 410a, 410b, 510: Rewiring Layer

[0035] 110L, 130L: Length

[0036] 110W, 130W: Width

[0037] 111, 411a, 411b, 511: Insulation parts

[0038] 120: Chip

[0039] 121: Side view

[0040] 129: Wiring

[0041] 130, 330: Seals

[0042] 131: First mold sealing material

[0043] 132: Second mold sealing material

[0044] D11, D41, D51: First outer insulating layer

[0045] D12, D42, D52: Second outer insulating layer

[0046] D13, D43, D53: Inner insulation layer

[0047] F11a: First surface

[0048] F11b: Second surface

[0049] F11c: Side surface

[0050] G1: Gap

[0051] P11a, P11b: Conductive connection structure

[0052] S11, S12: Solder blocks

[0053] T2: Trench

[0054] W11: First outer circuit layer

[0055] W11p: First bonding pad

[0056] W12: Second outer circuit layer

[0057] W12p: Second pad

[0058] W12s: Outer surface

[0059] W13: Inner circuit layer Detailed Implementation

[0060] In the following text, to clearly present the technical features of this application, the dimensions (e.g., length, width, thickness, and depth) of the elements (e.g., layers, films, substrates, and regions) in the drawings will be enlarged proportionally. Therefore, the description and explanation of the embodiments below are not limited to the dimensions and shapes presented by the elements in the drawings, but should cover dimensions, shapes, and deviations from both caused by actual manufacturing processes and / or tolerances. For example, a flat surface shown in the drawings may have rough and / or non-linear characteristics, and an acute angle shown in the drawings may be rounded. Therefore, the elements presented in the drawings of this application are primarily for illustration and are not intended to precisely depict the actual shape of the elements, nor are they intended to limit the scope of the claims in this application.

[0061] Secondly, the terms "approximately," "approximately," or "substantially" used in this application not only cover explicitly stated numerical values ​​and ranges, but also the permissible deviation range understandable to someone skilled in the art. This deviation range can be determined by errors that occur during measurement, such as those arising from limitations of the measurement system or process conditions. Furthermore, "approximately" can mean within one or more standard deviations of the aforementioned numerical values, such as ±30%, ±20%, ±10%, or ±5%. The terms "approximately," "approximately," or "substantially" used in this application can be chosen based on optical, etching, mechanical, or other properties to select an acceptable deviation range or standard deviation, and do not apply a single standard deviation to all optical, etching, mechanical, and other properties.

[0062] Figure 1A This is a top view schematic diagram of a chip package according to at least one embodiment of the present invention, and Figure 1B yes Figure 1A A schematic cross-sectional view drawn along section 1B-1B of the central axis. Please refer to [link / reference]. Figure 1A and Figure 1B The chip package 100 includes a redistribution layer 110. The redistribution layer 110 includes an insulating portion 111, wherein the insulating portion 111 has a first surface F11a, a second surface F11b opposite to the first surface F11a, and a side surface F11c located between the first surface F11a and the second surface F11b.

[0063] In this embodiment, the first surface F11a and the second surface F11b can be the upper and lower surfaces of the insulating portion 111, respectively, while the side surface F11c can be annular in shape and extend along the edges of both the first surface F11a and the second surface F11b. Furthermore, the side surface F11c can be the outer edge of the redistribution layer 110, while... Figure 1AIn the illustrated embodiment, the side surface F11c may be formed into a rectangle and has four side lengths (not shown). The length 110L of the redistribution layer 110 is the distance between two opposite side lengths, while the width 110W of the redistribution layer 110 is the distance between the other two opposite side lengths.

[0064] The insulating portion 111 may have a multilayer structure. For example, the insulating portion 111 may include a first outer insulating layer D11, a second outer insulating layer D12, and multiple inner insulating layers D13. These inner insulating layers D13 are located between the first outer insulating layer D11 and the second outer insulating layer D12, and the first outer insulating layer D11, the second outer insulating layer D12, and these inner insulating layers D13 are stacked on top of each other, wherein the first outer insulating layer D11 has a first surface F11a, and the second outer insulating layer D12 has a second surface F11b.

[0065] The materials of the first outer insulating layer D11, the second outer insulating layer D12, and the inner insulating layer D13 may be the same. In this embodiment, the first outer insulating layer D11, the second outer insulating layer D12, and the inner insulating layer D13 may be made of photoimageable dielectric (PID) material or other insulating materials, such as ABF (Ajinomoto Build-up Film) resin or polypropylene (PP). Furthermore, in other embodiments, at least two of the first outer insulating layer D11, the second outer insulating layer D12, and the inner insulating layer D13 may be different from each other.

[0066] The redistribution layer 110 may further include a first outer wiring layer W11, a second outer wiring layer W12, and multiple inner wiring layers W13, wherein these inner wiring layers W13 are located between the first outer wiring layer W11 and the second outer wiring layer W12. The first outer wiring layer W11 and the second outer wiring layer W12 each include multiple pads. Figure 1B For example, the first outer circuit layer W11 includes multiple first pads W11p, while the second outer circuit layer W12 includes multiple second pads W12p.

[0067] At least one of the first outer wiring layer W11 and the second outer wiring layer W12 may also include traces. For example, in Figure 1B In the illustrated embodiment, the second outer wiring layer W12 may include multiple traces 129, while the first outer wiring layer W11 only includes these first pads W11p and does not include any traces. However, in other embodiments, the first outer wiring layer W11 may also include multiple traces, while the second outer wiring layer W12 may not include any traces. Therefore, Figure 1BThere is no limitation on whether the first outer wiring layer W11 and the second outer wiring layer W12 include traces. In addition, in this embodiment, each inner wiring layer W13 may include multiple traces and multiple pads (not shown).

[0068] Each inner circuit layer W13 is located between adjacent inner insulation layers D11, D12, and the first outer insulation layer D11. Figure 1B In this configuration, the upper inner circuit layer W13 can be located between the adjacent first outer insulating layer D11 and the inner insulating layer D13, while the lower inner circuit layer W13 can be located between the adjacent second outer insulating layer D12 and the inner insulating layer D13. The middle inner circuit layer W13 can be located between two adjacent inner insulating layers D13.

[0069] These first outer circuit layers W11 are located on the first outer insulating layer D11, while these second outer circuit layers W12 are located on the second outer insulating layer D12. It should be noted that the first outer circuit layer W11 being located on the first outer insulating layer D11 means... Figure 1B The first outer circuit layer W11 can be located on or above the first outer insulating layer D11, or the first outer circuit layer W11 can be located inside the first outer insulating layer D11. Similarly, the second outer circuit layer W12 being located in the second outer insulating layer D12 means... Figure 1B The second outer circuit layer W12 can be located on or below the second outer insulation layer D12, or the second outer circuit layer W12 can be located inside the second outer insulation layer D12.

[0070] exist Figure 1B In this embodiment, the first outer circuit layer W11 is located on the first surface F11a of the first outer insulating layer D11, while the second outer circuit layer W12 is located within the second outer insulating layer D12 and does not substantially protrude from the second surface F11b. Therefore, the first pads W11p located on the first surface F11a can be located on and protrude from the first surface F11a, while the second pads W12p located on the second surface F11b can be located within the second surface F11b, wherein the second surface F11b can be flush with the outer surface W12s of each second pad W12p, such as... Figure 1B As shown.

[0071] Additionally, the redistribution layer 110 may also include multiple conductive connection structures P11a and P11b, wherein these conductive connection structures P11a and P11b are located within the insulating portion 111. Figure 1BFor example, these conductive connection structures P11a can be located in the first outer insulating layer D11, while these conductive connection structures P11b can be located in the second outer insulating layer D12 and the inner insulating layer D13. Furthermore, since the first outer insulating layer D11, the second outer insulating layer D12, and the inner insulating layer D13 can all be made of photosensitive dielectric (PID) materials, the methods for forming these conductive connection structures P11a and P11b can include laser ablation or lithography.

[0072] These conductive connection structures P11a and P11b are electrically connected to the first outer circuit layer W11, the second outer circuit layer W12, and the inner circuit layer W13. Specifically, each conductive connection structure P11a connects to the first pad W11p of the first outer circuit layer W11 and the adjacent inner circuit layer W13, while each conductive connection structure P11b connects to the second pad W12p of the second outer circuit layer W12 and two adjacent inner circuit layers W13. In this way, current can be transmitted between the first outer circuit layer W11, the second outer circuit layer W12, and the inner circuit layer W13 through the conductive connection structures P11a and P11b.

[0073] exist Figure 1B In the illustrated embodiment, both conductive connection structures P11a and P11b are conductive pillars, wherein conductive connection structure P11a can be a solid conductive pillar, while conductive connection structure P11b can be a hollow conductive pillar. However, in other embodiments, conductive connection structure P11a can also be a hollow conductive pillar, while conductive connection structure P11b can also be a solid conductive pillar. Alternatively, both conductive connection structures P11a and P11b can be either solid or hollow conductive pillars. Therefore, conductive connection structures P11a and P11b are not limited to... Figure 1B Limited to.

[0074] It is worth mentioning that, in this embodiment, the redistribution layer 110 may include three or more wiring layers (i.e., a first outer wiring layer W11, a second outer wiring layer W12, and an inner wiring layer W13) and three or more insulating layers (i.e., a first outer insulating layer D11, a second outer insulating layer D12, and an inner insulating layer D13). However, in other embodiments, the redistribution layer 110 may include only two wiring layers (e.g., a first outer wiring layer W11 and a second outer wiring layer W12) and an insulating layer located between these two wiring layers.

[0075] Therefore, in a single redistribution layer 110, the number of wiring layers (e.g., including a first outer wiring layer W11, a second outer wiring layer W12, and an inner wiring layer W13) can be two, while the number of insulating layers (e.g., including a first outer wiring layer W11, a second outer wiring layer W12, and an inner wiring layer W13) can be only one. Thus, the number of wiring layers and insulating layers in the redistribution layer 110 is not... Figure 1B This is a limitation. For example, in other embodiments, the number of inner insulating layers D13 included in the redistribution layer 110 may be only one.

[0076] The chip package 100 also includes a chip 120, which is disposed on the first surface F11a of the first outer insulating layer D11, so the first outer insulating layer D11 is located between the chip 120 and the second outer insulating layer D12. The chip 120 can be an unpackaged die or a packaged chip. The chip 120 can be mounted on the first surface F11a and electrically connected to the first pads W11p. Furthermore, the chip package 100 can be a fan-out packaged structure, wherein the size of the chip 120 is smaller than the size of the redistribution layer 110, and the redistribution layer 110 can protrude from the side 121 of the chip 120, such as... Figure 1A and Figure 1B As shown.

[0077] exist Figure 1B In the illustrated embodiment, chip 120 can be electrically connected to the first pads W11p using a flip-chip method. Therefore, chip 120 can be electrically connected to these first pads W11p through multiple solder blocks S11. In other embodiments, chip 120 can also be electrically connected to the first pads W11p using a wire bonding method, so the connection between chip 120 and the first pads W11p is not limited to a flip-chip method.

[0078] The chip package 100 also includes a seal 130, which encloses the chip 120 and the redistribution layer 110. The seal 130 covers the first surface F11a, the second surface F11b, and the side surface F11c of the chip 120 and the redistribution layer 110, but does not cut flush with the first surface F11a and the side surface F11c. In other words, the length 130L and the width 130W of the seal 130 are respectively larger than the length 110L and the width 110W of the redistribution layer 110, so that both the chip 120 and the redistribution layer 110 can be located within the seal 130.

[0079] The seal 130 exposes the second pads W12p without completely covering the first pads W11p, allowing the solder blocks S11 to connect to the first pads W11p. In this embodiment, the chip package 100 may also include a plurality of solder blocks S12. Because the seal 130 exposes the second pads W12p, the outer surfaces W12s of the second pads W12p are exposed, allowing the solder blocks S12 to connect to the second pads W12p respectively. Thus, the second pads W12p are electrically connected to the solder blocks S12, enabling the chip package 100 to be electrically connected to a circuit board, such as a printed circuit board or electronic carrier board, through the solder blocks S12.

[0080] The seal 130 may include a first molding compound 131 and a second molding compound 132, wherein the first molding compound 131 and the second molding compound 132 are connected, and the materials of the first molding compound 131 and the second molding compound 132 may be the same or different from each other. The first molding compound 131 covers the chip 120 and the redistribution layer 110, wherein the first molding compound 131 covers the first surface F11a and the side surface F11c of the redistribution layer 110, but does not cover the second surface F11b. The second molding compound 132 covers the second surface F11b, so the second molding compound 132 also covers the trace 129. The second molding compound 132 exposes the second pad W12p so that the solder block S12 can connect to the second pad W12p.

[0081] Furthermore, after the chip 120 is mounted on the first surface F11a, a gap G1 can be formed between the chip 120 and the redistribution layer 110, and the first molding compound 131 will fill the gap G1. In other words, a portion of the sealant 130 will fill the gap G1 between the chip 120 and the redistribution layer 110, and the sealant 130 will cover the upper surface, lower surface, and side surface 121 of the chip 120, thereby encapsulating the entire chip 120. Figure 1A and Figure 1B As shown.

[0082] Since the seal 130 covers the chip 120 and the redistribution layer 110, and covers the first surface F11a and the side surface F11c of the redistribution layer 110, the seal 130 can strengthen the structure of the chip package 100 and reduce the probability of the redistribution layer 110 breaking, thereby improving the reliability of the chip package 100 and enabling the chip package 100 to have a structure with sufficient strength to pass the thermal cycling test.

[0083] Figures 2A to 2G yes Figure 1B A flowchart illustrating the manufacturing process of the chip package. Please refer to [link / reference]. Figure 2AIn the manufacturing method of the chip package 100, firstly, an initial redistribution layer 110i is formed on a carrier substrate 20, wherein the initial redistribution layer 110i can be formed by a layer-addition method or a stacking method. The carrier substrate 20 is used to support the initial redistribution layer 110i and can be a rigid substrate, such as a ceramic plate or a glass plate.

[0084] In subsequent processes, the initial redistribution layer 110i can be cut into multiple redistribution layers 110, so the initial redistribution layer 110i can include multiple redistribution layers 110. In other words, the initial redistribution layer 110i and the redistribution layer 110 both include the same film layers and components, namely the first outer insulating layer D11, the second outer insulating layer D12, the inner insulating layer D13, the first outer circuit layer W11, the second outer circuit layer W12, the inner circuit layer W13, and the conductive connection structures P11a and P11b.

[0085] Please see Figure 2B Then, multiple chips 120 are mounted on the initial redistribution layer 110i. In this embodiment, these chips 120 can be mounted on the initial redistribution layer 110i using a flip-chip method. That is, these chips 120 can be electrically connected to the first pads W11p through multiple solder blocks S11. After these chips 120 are mounted on the initial redistribution layer 110i, a gap G1 can be formed between each chip 120 and the initial redistribution layer 110i. In other embodiments, these chips 120 can also be mounted on the initial redistribution layer 110i using a wire bonding method, so the mounting method between the chips 120 and the initial redistribution layer 110i is not limited to a flip-chip method.

[0086] Please see Figure 2C and Figure 2D ,in Figure 2D yes Figure 2C A top-down view diagram, and Figure 2C It can be Figure 2D The diagram is drawn along a 2C-2C cross section. Next, the initial redistribution layer 110i is cut to form multiple separate redistribution layers 110. After cutting the initial redistribution layer 110i, multiple trenches T2 are formed between these redistribution layers 110. The chips 120 can be arranged in an array, and the trenches T2 can be arranged in a mesh pattern, such as... Figure 2D As shown. Furthermore, since the first outer insulating layer D11, the second outer insulating layer D12, and the inner insulating layer D13 can all be made of photosensitive dielectric (PID) material, the method for cutting the initial redistribution layer 110i can be laser ablation or lithography.

[0087] Please see Figure 2E and Figure 2FThen, the formation of seal 130 begins. In this embodiment, forming seal 130 includes the following steps. Please refer to... Figure 2E First, a first molding material 131 is formed on the carrier substrate 20, wherein the first molding material 131 fills the trenches T2 and the gaps G1, and covers the first surface F11a and side surface F11c of the chips 120 and the redistribution layers 110, but does not cover the second surface F11b of the redistribution layers 110.

[0088] Please see Figure 2F After the first molding compound 131 is formed, the carrier substrate 20 is removed to expose the second surfaces F11b of the redistribution layers 110. Then, a second molding compound 132 is formed on the second surfaces F11b of the redistribution layers 110, wherein the second molding compound 132 exposes the second pads W12p. Thus, the seal 130 is formed. Furthermore, after forming the second molding compound 132, a plurality of solder blocks S12 can be formed on the redistribution layers 110, wherein each redistribution layer 110 is located between one of the chips 120 and the plurality of solder blocks S12.

[0089] Please see Figure 2F and Figure 2G Then, the seals 130 are cut along these trenches T2 to form multiple separate chip packages 100. Since the seals 130 fill the trenches T2 before being cut, after cutting the seals 130 along the trenches T2, the seals 130 in the same chip package 100 can cover the first surface F11a, side surface F11c, and second surface F11b of the redistribution layer 110. Thus, the seals 130 of each chip package 100 can enclose the chip 120 and the redistribution layer 110, improving reliability.

[0090] Figures 3A to 3B This is a schematic flowchart illustrating a method for manufacturing a chip package according to another embodiment of the present invention. Please refer to [link / reference]. Figure 3A and Figure 3B The manufacturing method of the chip package 300 in this embodiment is similar to the manufacturing method of the aforementioned chip package 100. The following text and figures mainly disclose the differences between chip packages 100 and 300, while the common features of chip packages 100 and 300 will not be described again.

[0091] Please refer to the following first. Figure 3BCompared to the chip package 100 in the aforementioned embodiments, the chip package 300 includes a seal 330, wherein the seal 330 covers the chip 120 and the redistribution layer 110, and covers the chip 120, the first surface F11a, and the side surface F11c, but does not cover the second surface F11b. Therefore, the seal 330 will not cover these second pads W12p. In addition, the seal 330 may be the first molding material 131 in the aforementioned embodiments.

[0092] Please see Figure 3A After the seal 330 (which may be the first molding material 131) is formed on the carrier substrate 20 (see reference) Figure 2E The carrier substrate 20 is removed, and the sealant 330 fills the trenches T2. Next, multiple solder blocks S12 are formed on these second pads W12p. Then, the sealant 330 is cut along the trenches T2 to form multiple separate chip packages 300. Thus, compared to the manufacturing method of the chip package 100, the manufacturing method of the chip package 300 essentially omits the step of forming the second molding material 132.

[0093] Figure 4A This is a cross-sectional schematic diagram of a chip package according to another embodiment of the present invention. Please refer to [link / reference]. Figure 4A The chip package 400a in this embodiment is similar to the chip package 100 in the aforementioned embodiment. For example, the chip package 400a includes a redistribution layer 410a, which includes an insulating portion 411a, wherein the insulating portion 411a may include a first outer insulating layer D41, a second outer insulating layer D42, and multiple inner insulating layers D13. However, unlike the chip package 100, the first outer insulating layer D41 and the second outer insulating layer D42 are different from the first outer insulating layer D11 and the second outer insulating layer D12.

[0094] Specifically, at least one of the first outer insulating layer D41 and the second outer insulating layer D42 includes an insulating material 41m and a plurality of fillers 41p, wherein the fillers 41p are distributed within the insulating material 41m. The insulating material 41m can be a polymer material, such as epoxy resin, polyimide (PI), polybenzoxazole (PBO), benzocyclobutene (BCB), or other materials, or any combination of these materials with other materials, and the fillers 41p can be a plurality of filler particles, which can be made of silicon dioxide. Through these fillers 41p, at least one of the first outer insulating layer D41 and the second outer insulating layer D42 can also strengthen the structure of the chip package 100, reduce the probability of breakage of the redistribution layer 410a, and thus improve reliability.

[0095] It is worth mentioning that, Figure 4A In the illustrated embodiment, each of the first outer insulating layer D41 and the second outer insulating layer D42 includes an insulating material 41m and fillers 41p. However, in other embodiments, only one of the first outer insulating layer D41 and the second outer insulating layer D42 may include the insulating material 41m and fillers 41p. Therefore, in Figure 4A In this design, the filler 41p within either the first outer insulating layer D41 or the second outer insulating layer D42 can be omitted. Alternatively, either the first outer insulating layer D41 or the second outer insulating layer D42 can be replaced with an insulating layer made of a photosensitive dielectric material, such as the first outer insulating layer D11 or the second outer insulating layer D12.

[0096] Figure 4B This is a cross-sectional schematic diagram of a chip package according to another embodiment of the present invention. Please refer to [link / reference]. Figure 4B The chip package 400b includes a redistribution layer 410b, which includes an insulating portion 411b. The insulating portion 411b may include a first outer insulating layer D41, a second outer insulating layer D42, and multiple inner insulating layers D43. The chip package 400b is similar to the chip package 400a, with the only difference being that in the chip package 400b, each of the first outer insulating layer D41, the second outer insulating layer D42, and each of the inner insulating layers D43 includes an insulating material 41m and fillers 41p. Therefore, the entire insulating portion 411b strengthens the structure of the chip package 400b and reduces the probability of breakage of the redistribution layer 410b, thereby improving reliability.

[0097] It should be noted that, in Figure 4B In the illustrated embodiment, each inner insulating layer D43 includes an insulating material 41m and fillers 41p. However, in other embodiments, at least one of these inner insulating layers D43 includes an insulating material 41m and fillers 41p. Therefore, in Figure 4B In this configuration, the filler 41p within one inner insulating layer D43 can be omitted. Alternatively, one inner insulating layer D43 can be replaced with an insulating layer made of a photosensitive dielectric material, namely, inner insulating layer D13. Furthermore, Figure 4B The first outer insulating layer D41 and the second outer insulating layer D42 may each include an insulating material 41m and fillers 41p.

[0098] Figure 5 This is a cross-sectional schematic diagram of a chip package according to another embodiment of the present invention. Please refer to [link / reference]. Figure 5The chip package 500 of this embodiment includes a redistribution layer 510, which includes an insulating portion 511. The insulating portion 511 may include a first outer insulating layer D51, a second outer insulating layer D52, and multiple inner insulating layers D53. Each of the first outer insulating layer D51, the second outer insulating layer D52, and these inner insulating layers D53 includes an insulating material 41m and a plurality of fillers 51f, wherein the fillers 51f are distributed in the insulating material 41m.

[0099] Chip package 500 is similar to chip package 400b, and the only difference between chip package 500 and 400b is that the fillers 51f can be multiple filler fibers, such as glass fibers. Through these fillers 51f, the entire insulating portion 511 can also strengthen the structure of chip package 500 and reduce the probability of redistribution layer 510 breakage, thereby improving reliability.

[0100] It is worth mentioning that, Figure 5 In the illustrated embodiment, each of the first outer insulating layer D51, the second outer insulating layer D52, and the inner insulating layers D53 includes an insulating material 41m and fillers 51f. However, in other embodiments, at least one of the first outer insulating layer D51, the second outer insulating layer D52, and the inner insulating layers D53 may include an insulating material 41m and fillers 51f.

[0101] In other words, in Figure 5 In this configuration, the filler 51f within at least one of the first outer insulating layer D51, the second outer insulating layer D52, and the inner insulating layers D53 may be omitted. Alternatively, at least one of the first outer insulating layer D51, the second outer insulating layer D52, and the inner insulating layers D53 may be replaced with an insulating layer made of a photosensitive dielectric material, namely, the first outer insulating layer D11, the second outer insulating layer D12, or the inner insulating layer D13.

[0102] in addition, Figure 5 The filler 51f shown can be replaced with filler 41p, so that the insulating portion 511 can include two fillers 41p and 51f, wherein the filler 51f in at least one of the first outer insulating layer D51, the second outer insulating layer D52, and these inner insulating layers D53 can be replaced with filler 41p. Furthermore, in Figure 4A , Figure 4B and Figure 5 In the chip packages 400a, 400b and 500 shown, the seal 130 can be replaced with Figure 3B The seal 330 is shown. In other words, Figure 3B The chip package 300 may also include at least one of fillers 41p and 51f.

[0103] In summary, since the sealing components disclosed in the above embodiments all cover the chip and the redistribution layer, and cover the first surface and side surface of the redistribution layer, the sealing components can strengthen the structure of the chip package to improve the reliability of the chip package, thereby enabling the chip package to have a structure with sufficient strength to pass the thermal cycling test.

[0104] Although the present invention has been disclosed above by way of embodiments, it is not intended to limit the present invention. Those skilled in the art to which this invention pertains may make some modifications and refinements without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be determined by the scope of the claims.

Claims

1. A chip package, characterized in that, include: Redeployment layers, including: An insulating portion having a first surface, a second surface opposite to the first surface, and a side surface extending from the first surface to the second surface; An outer circuit layer is located in the insulating portion, wherein the outer surface of the outer circuit layer is coplanar with the second surface; Multiple first pads are located on the first surface; Multiple second pads, formed by the outer circuit layer, are located on the second surface; A chip, disposed on the first surface and electrically connected to the first pad; and A seal encapsulates the chip and the redistribution layer, and covers the first surface and the side surface, wherein the seal exposes the second pad, and the seal is not flush with the first surface and the side surface. The seal is made of molding material and directly contacts the first surface without completely covering the first gasket.

2. The chip package according to claim 1, characterized in that, The redistribution layer includes: A first outer insulating layer having the first surface; and The second outer insulating layer has the second surface, wherein the first outer insulating layer is located between the chip and the second outer insulating layer.

3. The chip package according to claim 2, characterized in that, The first outer insulating layer includes: Insulating materials; and Multiple fillers are distributed within the insulating material.

4. The chip package according to claim 2, characterized in that, The second outer insulating layer includes: Insulating materials; and Multiple fillers are distributed within the insulating material.

5. The chip package according to claim 1, characterized in that, The redistribution layer includes: The first outer insulating layer has the first surface; A second outer insulating layer having the second surface, wherein the first outer insulating layer is located between the chip and the second outer insulating layer; and At least one inner insulating layer is located between the first outer insulating layer and the second outer insulating layer, wherein each of the first outer insulating layer, the second outer insulating layer, and the at least one inner insulating layer comprises: Insulating materials; and Multiple fillers are distributed within the insulating material.

6. The chip package according to claim 3, 4 or 5, characterized in that, The filler is a plurality of filler particles or a plurality of filler fibers.

7. The chip package according to claim 1, characterized in that, The seal does not cover the second surface.

8. The chip package according to claim 1, characterized in that, The seal covers the second surface.

9. The chip package according to claim 1, characterized in that, A portion of the seal fills the gap between the chip and the redistribution layer.

10. The chip package according to claim 1, characterized in that, It also includes multiple solder blocks, wherein each solder block is connected to the second pad.

11. The chip package according to claim 1, characterized in that, The second surface is flush with the outer surface of each of the second pads.

12. The chip package according to claim 1, characterized in that, The length and width of the seal are greater than the length and width of the redistribution layer, respectively.

13. A method for manufacturing a chip package, characterized in that, include: An initial redistribution layer is formed on a carrier substrate, wherein the initial redistribution layer has an outer circuit layer and the outer circuit layer is in direct contact with the carrier substrate. Multiple chips are mounted on this initial redistribution layer; The initial redistribution layer is cut to form multiple redistribution layers that are separate from each other, wherein multiple trenches are formed between the redistribution layers; A seal is formed, wherein the seal covers the chip and the redistribution layer and fills the trench; Remove the carrier substrate; Multiple solder blocks are formed on these redistribution layers, wherein multiple solder blocks are in direct contact with the outer circuit layer, and each redistribution layer is located between the chip and the multiple solder blocks. as well as Cut the seal along the groove. Each of the redistribution layers has a first surface, a second surface opposite to the first surface, and a side surface extending from the first surface to the second surface. The outer surface of the outer circuit layer is coplanar with the second surface. The steps of forming the seal include: A first molding compound is formed on the carrier substrate, wherein the first molding compound covers the chip, the first surface, and the side surface, but does not cover the second surface, and the first molding compound fills the trench, wherein the carrier substrate is removed after the formation of the first molding compound. The seal directly contacts the first surface but does not completely cover the first gasket.

14. The method for manufacturing a chip package according to claim 13, characterized in that, The steps for forming the seal also include: After the carrier substrate is removed, a second molding material is formed on the second surface, wherein the second molding material is connected to the first molding material.

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