Image sensor and method of manufacturing the same

Abstract

The application discloses an image sensor and a preparation method thereof. The image sensor comprises a semiconductor structure layer, the semiconductor structure layer has a plurality of photosensitive pixel areas arranged in an array and a groove isolation structure for spacing the plurality of photosensitive pixel areas, the groove isolation structure is provided with a first capacitor plate and a second capacitor plate, the first capacitor plate and the second capacitor plate jointly form a capacitor, and the capacitor is electrically connected between a conversion gain control transistor and a reset transistor. The capacitor is arranged in the groove isolation structure, the design of the capacitor is not limited by the size of the pixel and the layout of the circuit, the capacitance value can be made larger, the low gain value is reduced, the characteristics of the high gain value of the pixel are maintained, a higher high-low gain ratio is obtained, the possibility of better HDR performance is provided, and the performance of the groove isolation structure is not affected.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of image sensors, and particularly to an image sensor and a preparation method thereof. BACKGROUND

[0002] An image sensor is a device that converts optical signals into electrical signals. Commonly used image sensor chips include charge-coupled device (CCD) and complementary metal-oxide semiconductor (CMOS) image sensor chips. Compared with traditional CCD sensors, CMOS image sensors have the characteristics of low power consumption, low cost and compatibility with CMOS processes, and thus are increasingly widely used. Nowadays, CMOS image sensors are not only used in consumer electronics, such as digital still cameras (DSC), mobile phone cameras, camcorders and digital single-lens reflex (DSLR) cameras, but also widely used in automotive electronics, monitoring, biotechnology and medicine.

[0003] A pixel unit of a CMOS image sensor is a core device for realizing light sensing of the image sensor. The most commonly used pixel unit is an active pixel structure including a light sensing element and a plurality of transistors. The light sensing element in these devices is a light sensing unit, which realizes light collection and photoelectric conversion, and the other MOS transistors are control units, which mainly realize the control of selection, reset, signal amplification and readout of the light sensing element.

[0004] CMOS image sensors can be divided into front-illuminated and back-illuminated image sensors according to the path of incident light entering the light sensing element. The front-illuminated image sensor refers to an image sensor in which incident light enters the light sensing element from the side close to the circuit connection layer, while the back-illuminated image sensor refers to an image sensor in which incident light enters the light sensing element from the side away from the circuit connection layer.

[0005] Existing standard image sensors have a limited dynamic range of approximately 60 dB to 70 dB. However, the dynamic range of real-world brightness is much larger. Natural scenes often span a range of 90 dB and above. To capture both bright light and shadows at the same time, high dynamic range (HDR) techniques have been used in image sensors to increase the captured dynamic range. The most common technique for increasing the dynamic range is to combine multiple exposures captured with a standard (low dynamic range) image sensor into a single linear high dynamic image with a much larger dynamic range than a single exposure image.

[0006] In a method in the most common high dynamic range image sensor solution, a plurality of exposures are made into a single image sensor with different exposure integration times or different sensitivities, one image sensor can have a plurality of different exposures in a single frame, using such a high dynamic range image sensor, a plurality of exposure images can be obtained in a single shot. However, compared with a normal resolution image sensor, the total image resolution is reduced in the case of using such a high dynamic image sensor, for example, corresponding to combining 4 different exposures in one image sensor, the resolution of each high dynamic range image sensor is only one quarter of the full resolution image. Another high dynamic range image sensor is to use device capacitance or directly use the parasitic capacitance generated by the connection point of the reset transistor RST and the DCG control transistor to the ground to enhance the conversion gain of the image sensor and improve the dynamic range of the image sensor output. However, the setting of such capacitance is limited by the pixel size and layout, the capacitance value of the capacitance cannot be made larger, and the effect of improving the dynamic range is not ideal. Therefore, there is an urgent need for an image sensor that can improve the dynamic range without affecting the resolution of the image sensor. SUMMARY

[0007] In order to overcome the shortcomings and deficiencies existing in the prior art, the purpose of the present application is to provide an image sensor to solve the problem that the dynamic range of the image sensor in the prior art is difficult to effectively improve.

[0008] The purpose of the present application is achieved by the following technical solutions:

[0009] The present application provides an image sensor, which comprises:

[0010] A semiconductor structure layer, which has a plurality of light-sensitive pixel regions arranged in an array and a plurality of trench isolation structures for spacing the light-sensitive pixel regions;

[0011] The light-sensitive pixel region is provided with a light-sensitive element, and the trench isolation structure is provided with a first capacitor plate and a second capacitor plate, and the first capacitor plate and the second capacitor plate together form a capacitor;

[0012] A reset transistor and a conversion gain control transistor, and the capacitor is electrically connected between the conversion gain control transistor and the reset transistor.

[0013] Optionally, the first capacitor plate comprises a first plate portion, an intermediate bending portion and a second plate portion connected in sequence, wherein the first plate portion and the second plate portion are oppositely arranged, and the second capacitor plate is arranged between the first plate portion and the second plate portion.

[0014] Optionally, the longitudinal cross-sectional shape of the first capacitor plate includes a "V" shape or a "U" shape.

[0015] Optionally, a projection of the trench isolation structure on the surface of the semiconductor structure layer has the same shape as a projection of the capacitor on the surface of the semiconductor structure layer; or a projection of the trench isolation structure on the surface of the semiconductor structure layer has a grid shape, and the trench isolation structure is provided with a plurality of capacitors.

[0016] Optionally, a projection of the capacitor on the surface of the semiconductor structure layer has at least one of a straight line shape, a "T" shape, an inverted "T" shape, and a "cross" shape.

[0017] Optionally, one of the first capacitor plate and the second capacitor plate is electrically connected to the conversion gain control transistor and the reset transistor, and the other of the first capacitor plate and the second capacitor plate is grounded or connected to a variable voltage.

[0018] Optionally, the image sensor includes a circuit connection layer disposed on the semiconductor structure layer, and the circuit connection layer is provided with a conductive portion, wherein the second capacitor plate is electrically connected to the conversion gain control transistor and the reset transistor through the conductive portion.

[0019] Optionally, the image sensor further includes a transfer transistor, a floating diffusion region, a source follower transistor, and a selection transistor.

[0020] The transfer transistor is connected to the light sensing element and the floating diffusion region, and is used to transfer an electrical signal of the light sensing element to the floating diffusion region, the source follower transistor and the reset transistor are electrically connected to the floating diffusion region, and the selection transistor is electrically connected to the source follower transistor.

[0021] Optionally, the conversion gain control transistor and the reset transistor are arranged between two rows of the light sensing pixel regions and arranged along a row direction; and / or the source follower transistor and the selection transistor are arranged between two columns of the light sensing pixel regions and arranged along a column direction.

[0022] Optionally, each floating diffusion region is electrically connected to the gates of two adjacent transfer transistors; and / or the gate of each source follower transistor is electrically connected to two adjacent floating diffusion regions.

[0023] Optionally, the image sensor comprises an optical structure layer, the trench isolation structure comprises a corresponding first reflective structure and a second reflective structure, wherein the first reflective structure is located between the optical structure layer and the second reflective structure, and the first capacitor plate and the second capacitor plate are arranged in the second reflective structure.

[0024] Optionally, the trench isolation structure comprises a corresponding reflective structure and a light-absorbing structure, the reflective structure is located at one end of the trench isolation structure close to the optical structure layer and is used for reflecting light, and the light-absorbing structure is located at one end of the trench isolation structure close to the circuit connection layer and is used for absorbing light.

[0025] Optionally, the first capacitor plate and the second capacitor plate are arranged in the light-absorbing structure.

[0026] The present application also provides a preparation method of an image sensor, which is suitable for the image sensor according to any one of the above-mentioned schemes, and the preparation method comprises the following steps:

[0027] A substrate is provided, the substrate comprises a first surface and a second surface opposite to each other;

[0028] An isolation structure is formed in the substrate, and a capacitor is prepared in the isolation structure, the capacitor comprises a first capacitor plate and a second capacitor plate;

[0029] From the first surface, a plurality of light-sensitive pixel regions arranged in an array are formed in the substrate, the light-sensitive pixel regions are provided with light-sensitive elements, and the isolation structure separates the light-sensitive pixel regions;

[0030] A reset transistor and a conversion gain control transistor are prepared in the light-sensitive pixel regions, and the capacitor is electrically connected between the conversion gain control transistor and the reset transistor.

[0031] Optionally, the preparation method further comprises the following steps:

[0032] The substrate is thinned from the second surface of the substrate to obtain a thinned surface, and a back compensation isolation structure corresponding to the isolation structure is prepared in the substrate from one side of the thinned surface, and a corresponding group of the isolation structure and the back compensation isolation structure form a trench isolation structure.

[0033] Optionally, the preparation method further comprises the step of preparing a circuit connection layer, wherein the reset transistor and the conversion gain transistor have a shared active region, and the preparation of the circuit connection layer comprises the following steps:

[0034] A dielectric layer is formed on the first surface of the substrate;

[0035] preparing a first contact hole corresponding to one plate of the capacitor and a second contact hole corresponding to the common active region in the dielectric layer,

[0036] preparing a conductive layer on the dielectric layer, the conductive layer realizing electrical connection of the capacitor, the reset transistor and the conversion gain transistor based on the first contact hole and the second contact hole.

[0037] Optionally, the process of preparing the circuit connection layer further comprises:

[0038] preparing a third contact hole in the dielectric layer, and the conductive layer realizing electrical lead-out of the transistors in the light-sensitive pixel region and / or electrical interconnection between the transistors based on the third contact hole.

[0039] The present application has the advantages that: by arranging the capacitor in the trench isolation structure, the design of the capacitor is not limited by the size of the pixel and the layout, the capacitance value of the capacitor can be made larger, the low gain value is reduced while the characteristics of the high gain value of the pixel are maintained, the low gain part of the dual gain can be continuously reduced to obtain a higher high-low gain ratio, and the possibility of better HDR performance is provided. BRIEF DESCRIPTION OF DRAWINGS

[0040] Figure 1 is a cross-sectional structure schematic diagram of an image sensor in the present application;

[0041] Figure 2 is a cross-sectional structure schematic diagram of a trench isolation structure in the present application;

[0042] Figure 3 is one of pixel circuit diagrams of an image sensor in the present application;

[0043] Figure 4 is one of plane schematic diagrams of an image sensor in the present application;

[0044] Figure 5 is the second of plane schematic diagrams of an image sensor in the present application;

[0045] Figure 6 is a pixel circuit diagram of an image sensor in another embodiment of the present application; Figure 4

[0046] Figure 7 is a pixel circuit diagram of an image sensor in another embodiment of the present application;

[0047] Figure 8 is a pixel circuit diagram of an image sensor in another embodiment of the present application;

[0048] Figure 9 is a cross-sectional structure schematic diagram of an image sensor in another embodiment of the present application;​

[0049] Figure 10 is a cross-sectional structure diagram of a trench isolation structure in another embodiment of the present application. DETAILED DESCRIPTION

[0050] In order to further clarify the technical means and effects adopted by the present application to achieve the predetermined inventive objectives, the specific embodiments, structures, features and effects of the image sensor according to the present application are described in detail below in combination with the drawings and preferred embodiments:

[0051] Figure 1 is a cross-sectional structure diagram of an image sensor in the present application, Figure 2 is a cross-sectional structure diagram of a trench isolation structure in the present application, Figure 3 is one of pixel circuit diagrams of an image sensor in the present application, Figure 4 is one of plan view diagrams of an image sensor in the present application, Figure 5 is another of plan view diagrams of an image sensor in the present application, Figure 6 is a cross-sectional structure diagram of a connection between a capacitor and a conversion gain control transistor and a reset transistor in the present application, Figure 7 is a plan view diagram of an image sensor in another embodiment of the present application, Figure 8 is a plan view diagram of an image sensor in still another embodiment of the present application, Figure 9 is a cross-sectional structure diagram of an image sensor in another embodiment of the present application, Figure 10 is a cross-sectional structure diagram of a trench isolation structure in another embodiment of the present application.

[0052] Embodiment One:

[0053] As shown in Figures 1 to 6 , the present application provides an image sensor, which includes a semiconductor structure layer 20, the semiconductor structure layer 20 has a plurality of light-sensitive pixel areas 21 (pixel units) distributed in an array and a trench isolation structure 22 spacing the plurality of light-sensitive pixel areas 21. The light-sensitive pixel area 21 is provided with a light-sensitive element (such as a photodiode PD), which is used to convert a light signal containing image information into an electrical signal through a photoelectric effect during an exposure process. In addition, in an example, the trench isolation structure 22 can penetrate through the semiconductor structure layer 20.

[0054] In addition, the semiconductor structure 20 is further provided with a reset transistor RST and a conversion gain control transistor DCG in the light-sensitive pixel area 21. The reset transistor RST resets the voltage of a floating diffusion region FD according to a reset control signal, and the conversion gain control transistor DCG is electrically connected with the reset transistor RST and the floating diffusion region FD, respectively.

[0055] In the present application, the capacitor VC is arranged between and electrically connected to the conversion gain control transistor DCG and the reset transistor RST, so as to realize conversion gain control of the pixel circuit through high-low gain mode switching and improve the dynamic range of the image sensor. Further, the first capacitor plate 221 and the second capacitor plate 222 are arranged in the trench isolation structure 22, the first capacitor plate 221 and the second capacitor plate 222 are insulated and arranged at intervals, and the first capacitor plate 221 and the second capacitor plate 222 jointly form the capacitor VC, which is electrically connected to the conversion gain control transistor DCG and the reset transistor RST. The first capacitor plate 221 and the second capacitor plate 222 can be insulated and spaced apart by the material of the trench isolation structure 22, and of course, can also be insulated and spaced apart by other dielectric layers.

[0056] In the present application, the capacitor VC is arranged in the trench isolation structure 22, the design of the capacitor VC is not limited by the size of the pixel and the layout of the circuit, the capacitance value of the capacitor VC can be larger, the low gain value is reduced while the high gain value of the pixel is maintained, the low gain part of the dual gain can be further reduced to obtain a higher high-low gain ratio, which provides the possibility for better HDR performance, and the capacitor VC is arranged in the trench isolation structure 22, which increases the available space of the capacitor VC in the layout design, increases the capacitance of the low gain without affecting the isolation performance between pixels, provides the possibility for further reducing the low gain, and improves the overall performance of the image sensor.

[0057] In an example, the number of the first capacitor plate 221 is two and connected together at one end away from the gate of the reset transistor and the conversion gain control transistor, and the second capacitor plate 222 is located between the two first capacitor plates 221. In another example, the first capacitor plate 221 includes a first plate portion, an intermediate bending portion and a second plate portion connected in sequence, wherein the first plate portion and the second plate portion are oppositely arranged, and the second capacitor plate 222 is arranged between the first plate portion and the second plate portion. It should be noted that the first plate portion and the second plate portion can be completely opposite or have partial misalignment, and the second capacitor plate 222 is formed between the two and forms the capacitor VC with the first plate portion and the second plate portion on both sides.

[0058] Preferably, the cross section of the first capacitor plate 221 forms an inverted "V" shape or an inverted "U" shape. Of course, in other embodiments, the number of the first capacitor plate 221 and the second capacitor plate 222 can be set to multiple, the cross section of the multiple first capacitor plates 221 is comb-shaped, the cross section of the multiple second capacitor plates 222 is comb-shaped, and the first capacitor plate 221 and the second capacitor plate 222 are mutually embedded.

[0059] As an example, the planar structure of the capacitor VC is linear ( Figure 4 and Figure 5 ), "T" shape, inverted "T" shape ( Figure 7 ) or "cross" shape ( Figure 8 ), so that the trench isolation structure 22 can be maximally utilized as needed, so that the capacitance of the capacitor VC is larger, which is further applicable to the pixel layout of the application. It should be noted that the planar structure of the capacitor VC can be understood as the shape of the projection of the capacitor on the surface of the semiconductor structure layer 20.

[0060] In this embodiment, the planar structure of the trench isolation structure 22 (the shape of the projection of the trench isolation structure on the surface of the semiconductor structure layer) is the same as the planar structure of the capacitor VC (the shape of the projection of the capacitor on the surface of the semiconductor structure layer), that is, one capacitor VC is provided on one trench isolation structure 22, and a plurality of trench isolation structures 22 are provided in the semiconductor structure layer 20, and the light sensing pixel areas 21 are spaced apart from each other by the plurality of trench isolation structures 22. Of course, in other embodiments, the planar structure of the trench isolation structure 22 is a grid structure, and a plurality of capacitors VC are provided in the trench isolation structure 22, that is, the trench isolation structure 22 is a grid structure, and a plurality of light sensing pixel areas 21 are spaced apart by the trench isolation structure 22 of the grid structure, and a plurality of capacitors VC are arranged in the trench isolation structure 22.

[0061] As an example, one of the first capacitor plate 221 and the second capacitor plate 222 is electrically connected with the conversion gain control transistor DCG and the reset transistor RST, and the other of the first capacitor plate 221 and the second capacitor plate 222 is grounded or connected with a variable voltage, which can be electrically led out through the metal layer (such as M1, M2, etc.) above the light sensing pixel area 21.

[0062] Further, as shown in Figure 6 , the image sensor comprises a circuit connection layer 10 provided on the semiconductor structure layer 20, and the circuit connection layer 10 is provided with a conductive part 11, which electrically connects the capacitor VC with the conversion gain control transistor DCG and the reset transistor RST.

[0063] Specifically, the circuit connection layer 10 is provided with a dielectric layer 101 covering the conversion gain control transistor DCG, the reset transistor RST and the capacitor VC, and the dielectric layer 101 is provided with a contact hole at a position corresponding to the capacitor VC, the conversion gain control transistor DCG and the reset transistor RST, and the conductive part 11 electrically connects the capacitor VC with the conversion gain control transistor DCG and the reset transistor RST through the contact hole.

[0064] In this embodiment, the second capacitor plate 222 is electrically connected with the drain of the conversion gain control transistor DCG and the source of the reset transistor RST, and the contact hole corresponds to the second capacitor plate 222, the drain of the conversion gain control transistor DCG and the source of the reset transistor RST. Optionally, the conversion gain control transistor DCG and the reset transistor RST are in a source-drain sharing structure, that is, the drain of the conversion gain control transistor DCG and the source of the reset transistor RST share an active region, and the first capacitor plate 221 is grounded or connected to a variable voltage. Of course, the first capacitor plate 221 can also be electrically connected with the drain of the conversion gain control transistor DCG and the source of the reset transistor RST, and the second capacitor plate 222 is grounded or connected to a variable voltage.

[0065] As an example, the semiconductor structure layer 20 further comprises a transfer transistor TX, a floating diffusion region FD, a source follower transistor SF and a selection transistor RS. The transfer transistor TX is connected to the photosensitive element PD and the floating diffusion region FD, and is used to transfer the electrical signal of the photosensitive element PD to the floating diffusion region FD. The source follower transistor SF and the reset transistor RST are both electrically connected to the floating diffusion region FD. The source follower transistor SF is used to amplify the electrical signal of the floating diffusion region FD, and the reset transistor RST is used to reset the voltage of the floating diffusion region FD according to a reset control signal. The selection transistor RS is electrically connected to the source follower transistor SF, and is used to select and output the amplified signal of the source follower transistor SF to the column line (PIEOUT). The conversion gain control transistor DCG is electrically connected to the reset transistor RST, and the capacitor VC is arranged between and electrically connected to the conversion gain control transistor DCG and the reset transistor RST, so as to switch between high and low gain modes and achieve conversion gain control of the pixel circuit, thereby improving the dynamic range of the image sensor.

[0066] As an example, the conversion gain control transistor DCG and the reset transistor RST are arranged between two rows of photosensitive pixel regions 21 and arranged along the row direction, and the source follower transistor SF and the selection transistor RS are arranged between two columns of photosensitive pixel regions 21 and arranged along the column direction. Of course, in other embodiments, the conversion gain control transistor DCG and the reset transistor RST are arranged between two columns of photosensitive pixel regions 21 and arranged along the column direction, and the source follower transistor SF and the selection transistor RS are arranged between two rows of photosensitive pixel regions 21 and arranged along the row direction.

[0067] In an example, each photosensitive element PD is connected to one transfer transistor TX, each floating diffusion region FD is electrically connected to the gates of two transfer transistors TX, and the gate of each source follower transistor SF is electrically connected to two floating diffusion regions FD, i.e., two photosensitive pixel regions 21 share one floating diffusion region FD, and four photosensitive pixel regions 21 share one source follower transistor SF, so that the four photosensitive pixel regions 21 near the connection between the source follower transistor SF and the selection transistor RS also share one capacitance VC. Sharing one floating diffusion region FD or one source follower transistor SF by multiple photosensitive pixel regions 21 can make the pixel circuit more compact and improve the aperture ratio and conversion gain of the photosensitive pixel region 21. Of course, in other embodiments, each photosensitive element PD of each photosensitive region can be connected to one transfer transistor TX, each floating diffusion region FD can be electrically connected to the gate of one transfer transistor TX, and the gate of each source follower transistor SF can be electrically connected to one floating diffusion region FD. Alternatively, each floating diffusion region FD can be electrically connected to the gates of two transfer transistors TX, and the gate of each source follower transistor SF can be electrically connected to one floating diffusion region FD, i.e., two photosensitive pixel regions 21 share one floating diffusion region FD.

[0068] In the present embodiment, the reset transistor RST and the conversion gain control transistor DCG are arranged between two pixel units, and the two adjacent pixel units in the same column are symmetrical along the reset transistor RST. The selection transistor RS is arranged between two pixel units, and the selection transistor RS is arranged in the same direction as the source follower transistor SF, and the two adjacent pixel units in the same row are symmetrical along the selection transistor RS. Thus, the layout design of the pixel circuit has good symmetry, the performance difference of each device is small, and the performance of the pixel circuit is improved.

[0069] In an example, the trench isolation structure 22 can extend into the circuit connection layer 10 towards one end of the circuit connection layer 10. Of course, in other embodiments, the trench isolation structure 22 can not extend into the circuit connection layer 10 towards one end of the circuit connection layer 10, and the conductive portion 11 can be conductively connected to the second capacitor plate 222 by increasing the depth of the contact hole.

[0070] As an example, the circuit connection layer 10 and the semiconductor structure layer 20 are provided with a first insulating layer 40. Optionally, the trench isolation structure 22 also penetrates the first insulating layer 40 towards one end of the circuit connection layer 10.

[0071] As an example, the trench isolation structure 22 is made of a material with a refractive index lower than that of the semiconductor structure layer 20, preferably, the trench isolation structure 22 has a refractive index n less than 2.5, so that total reflection is formed between the trench isolation structure 22 and the semiconductor structure layer 20, and the trench isolation structure 22 can be made of oxide (OX), silicon nitride (SiN), high dielectric material or air. By reflecting the light between the trench isolation structures 22, the light receiving element PD can receive more light, such as increasing the receiving performance of red light and near-infrared light, while avoiding or reducing optical crosstalk caused by light penetrating the trench isolation structure 22 into other light receiving pixel areas 21. In an example, the trench isolation structure 22 is made of a shallow trench isolation structure (STI), and the capacitor VC is made in the shallow trench isolation structure.

[0072] In other embodiments, referring to Figure 9 and Figure 10 As shown, the image sensor includes an optical structure layer 30, and in a further example, the semiconductor structure layer 20 is located between the optical structure layer 30 and the circuit connection layer 10. The trench isolation structure 22 includes a first reflection structure and a second reflection structure corresponding to each other, the first reflection structure is located at one end of the trench isolation structure 22 close to the optical structure layer 30 and is used for reflecting light, and the second reflection structure is located at one end of the trench isolation structure 22 close to the circuit connection layer 10 and is used for reflecting light. The first capacitor plate 221 and the second capacitor plate 222 are arranged in the second reflection structure. The materials of the first reflection structure and the second reflection structure can be the same or different. The reflection structure 22a is made of a material with a refractive index lower than that of the semiconductor structure layer 20, preferably, the reflection structure 22a has a refractive index n less than 2.5, so that total reflection is formed between the reflection structure 22a and the semiconductor structure layer 20, and the reflection structure 22a can be made of oxide (OX), silicon nitride (SiN), high dielectric material or air. The second reflection structure is made of a non-conductive material to prevent the first capacitor plate 221 and the second capacitor plate 222 from short-circuiting. In an example, the first reflection structure is a back deep trench isolation structure (BDTI), and the second reflection structure is a front shallow trench isolation structure (STI), which together form the trench isolation structure 22.

[0073] Further, the optical structure layer 30 comprises a color filter layer 31 and a microlens array structure 32, the color filter layer 31 comprises red (R), green (G) and blue (B) color filter layers and is arranged in an array, each color filter layer 31 corresponds to a pixel unit, and the microlens array structure 32 has a light condensing effect to make light converge on a photosensitive element. Each pixel unit can comprise one pixel or a plurality of shared pixels.

[0074] In other embodiments, as shown in Figure 9 and Figure 10 The trench isolation structure 22 comprises a reflection structure 22a and a light absorption structure 22b corresponding to each other, the reflection structure 22a is located at one end of the trench isolation structure 22 close to the optical structure layer 30 and is used for reflecting light, and the light absorption structure 22b is located at one end of the trench isolation structure 22 close to the circuit connection layer 10 and is used for absorbing light. The first and second capacitor plates 221 and 222 are arranged in the light absorption structure 22b. The reflection structure 22a is made of a material with a refractive index lower than that of the semiconductor structure layer 20, preferably, the refractive index n of the reflection structure 22a is less than 2.5, so that total reflection is formed between the reflection structure 22a and the semiconductor structure layer 20, and the reflection structure 22a can be made of oxide (OX), silicon nitride (SiN), high dielectric material or air. The light absorption structure 22b needs to be made of a non-conductive material to prevent the first and second capacitor plates 221 and 222 from short-circuiting.

[0075] Embodiment Two:

[0076] Referring to Figures 1-10 The present application also provides a preparation method of an image sensor, which is suitable for the image sensor according to any one of the solutions in Embodiment One. The specific description of the features involved in the preparation method of the present embodiment two can be referred to Embodiment One. The preparation method comprises the following steps:

[0077] S1, providing a substrate, the substrate comprising opposite first and second surfaces.

[0078] Specifically, the material of the substrate can be any substrate difficult to use in the field of image sensors, such as silicon, germanium, germanium silicon, silicon carbide, group III-V semiconductor compounds and SOI, etc. Of course, it can also be a laminated structure composed of a silicon substrate and an epitaxial layer (epi). The substrate forms the semiconductor structure layer 20 in Embodiment One after subsequent process preparation. In addition, here, the first and second surfaces of the substrate can be the opposite upper and lower surfaces of the substrate.

[0079] S2, forming an isolation structure in the substrate and preparing a capacitor in the isolation structure, the capacitor comprising a first capacitor plate 221 and a second capacitor plate 222;

[0080] S3, forming light-sensitive pixel regions 21 in the substrate from the first surface in an array distribution, the light-sensitive pixel regions being provided with light-sensitive elements, and the isolation structure separating the light-sensitive pixel regions.

[0081] S4, preparing a reset transistor and a conversion gain control transistor in the light-sensitive pixel regions, and electrically connecting the capacitor between the conversion gain control transistor and the reset transistor.

[0082] In which, the structure and arrangement of the first capacitor plate, the second capacitor plate, the isolation structure, the light-sensitive pixel region, and the reset transistor and the conversion gain transistor are described in Embodiment One, and will not be described here. In addition, the isolation structure here can be understood as the trench isolation structure in Embodiment One. In addition, it needs to be explained that the above steps S1-S4 are only an example, and the preparation order of each step can be adjusted according to the common sense in the art, and is not limited to this.

[0083] As an example, the preparation method further comprises the steps of:

[0084] Thinning the substrate from the second surface of the substrate to obtain a thinned surface, and preparing a back compensation isolation structure corresponding to the isolation structure in the substrate from the thinned surface side, and a corresponding group of the isolation structure and the back compensation isolation structure constitute a trench isolation structure.

[0085] Specifically, in this example, the BSI process image sensor can be based on, and then the design of the application is suitable for BSI structure, wherein the isolation structure in step S2 can be a shallow trench isolation structure (STI), which is further used as the second reflection structure in Embodiment One, and the back compensation isolation structure here is a back deep trench isolation structure (BDTI), which is further used as the first reflection structure in Embodiment One, and the two together constitute the trench isolation structure of the image sensor. Of course, in other embodiments, the image sensor can also be prepared based on FSI process, so that the design of the application is suitable for BSI structure.

[0086] As an example, the preparation method of the image sensor further comprises the step of preparing a circuit connection layer 10, which can be a structure comprising a plurality of metal layers and dielectric layers, and can be used as interconnection, rewiring and electrical lead-out of the device. In which, the reset transistor and the conversion gain transistor have a common active region, and the preparation of the circuit connection layer comprises the following steps:

[0087] 1) forming a dielectric layer on a first surface of the substrate, wherein the dielectric layer can adopt the material of the existing interconnection layer, including but not limited to a high-k dielectric layer;

[0088] 2) preparing a first contact hole corresponding to one plate of the capacitor and a second contact hole corresponding to the common active region in the dielectric layer, each contact hole can be prepared by a photolithography etching process;

[0089] 3) preparing a conductive layer on the dielectric layer, the conductive layer realizes the electrical connection of the capacitor, the reset transistor and the conversion gain transistor based on the first contact hole and the second contact hole. The material of the conductive layer can be a commonly used metal as an interconnection, such as copper.

[0090] As an example, the process of preparing the circuit connection layer further includes:

[0091] preparing a third contact hole in the dielectric layer, and the conductive layer realizes the electrical lead-out of the transistors in the photosensitive pixel region and / or the electrical interconnection between the transistors based on the third contact hole.

[0092] Specifically, in this example, the preparation of the electrical connection of the capacitor, the reset transistor and the conversion gain transistor can be prepared based on the same process as the interconnection line and the electrical lead-out line of the transistors in the existing image sensor, which improves the performance of the device without additional interconnection process, simplifying the process.

[0093] In this article, the orientation words such as up, down, left, right, front, back, etc. are defined by the position of the structure in the drawing and the position of the structure relative to each other in the drawing. Only to express the technical solution clearly and conveniently. It should be understood that the use of orientation words should not limit the scope of the application claimed. It should also be understood that the terms "first" and "second" used herein are only used for name distinction and do not limit the quantity and order.

[0094] The above is only the preferred embodiment of the present application, and is not intended to limit the present application in any form. Although the present application has been disclosed as above with the preferred embodiment, it is not intended to limit the present application. Any person skilled in the art can make some changes or modifications to the above disclosed technical content without departing from the scope of the technical solution of the present application, and the equivalent embodiments of equivalent changes. Any simple modification, equivalent change and modification made to the above embodiments according to the technical essence of the present application, without departing from the technical solution of the present application, are still within the protection scope of the present application.

Claims

1. An image sensor, characterized by, The image sensor comprises: a semiconductor structure layer, the semiconductor structure layer having a plurality of light-sensitive pixel regions arranged in an array and a plurality of trench isolation structures separating the plurality of light-sensitive pixel regions; a light-sensitive element is arranged in each of the light-sensitive pixel regions, and a first capacitor plate and a second capacitor plate are arranged in the trench isolation structure, the first capacitor plate and the second capacitor plate together forming a capacitor; a reset transistor and a conversion gain control transistor, the capacitor being electrically connected between the conversion gain control transistor and the reset transistor.

2. The image sensor of claim 1, wherein, The first capacitor plate comprises a first plate portion, an intermediate bending portion and a second plate portion connected in sequence, wherein the first plate portion is arranged opposite to the second plate portion, and the second capacitor plate is arranged between the first plate portion and the second plate portion.

3. The image sensor of claim 2, wherein, The longitudinal cross-sectional shape of the first capacitor plate comprises a "V" shape or a "U" shape.

4. The image sensor of claim 1, wherein, The projection of the trench isolation structure on the surface of the semiconductor structure layer has the same shape as the projection of the capacitor on the surface of the semiconductor structure layer; or the projection of the trench isolation structure on the surface of the semiconductor structure layer is in a grid shape, and the trench isolation structure is provided with a plurality of capacitors.

5. The image sensor of claim 1, wherein, The projection of the capacitor on the surface of the semiconductor structure layer comprises at least one of a straight line shape, a "T" shape, an inverted "T" shape and a "cross" shape.

6. The image sensor of claim 1, wherein, One of the first capacitor plate and the second capacitor plate is electrically connected to the conversion gain control transistor and the reset transistor, and the other of the first capacitor plate and the second capacitor plate is grounded or connected to a variable voltage.

7. The image sensor of claim 6, wherein, The image sensor further comprises a circuit connection layer arranged on the semiconductor structure layer, and the circuit connection layer is provided with a conductive portion, wherein the second capacitor plate is electrically connected to the conversion gain control transistor and the reset transistor through the conductive portion.

8. The image sensor of claim 1, wherein, The image sensor further comprises a transfer transistor, a floating diffusion region, a source follower transistor and a selection transistor; The transfer transistor is connected to the light-sensitive element and the floating diffusion region, and is used to transfer an electrical signal of the light-sensitive element to the floating diffusion region, the source follower transistor and the reset transistor are both electrically connected to the floating diffusion region, and the selection transistor is electrically connected to the source follower transistor.

9. The image sensor of claim 8, wherein, The conversion gain control transistor and the reset transistor are arranged between two rows of the light-sensitive pixel regions and arranged along a row direction; and / or, the source follower transistor and the selection transistor are arranged between two columns of the light-sensitive pixel regions and arranged along a column direction.

10. The image sensor of claim 9, wherein, Each of the floating diffusion regions is electrically connected to the gates of two adjacent transfer transistors; and / or, the gate of each of the source follower transistors is electrically connected to two adjacent floating diffusion regions.

11. The image sensor according to any one of claims 1 to 10, wherein The image sensor comprises an optical structure layer, the trench isolation structure comprises corresponding first and second reflection structures, wherein the first reflection structure is located between the optical structure layer and the second reflection structure, and the first and second capacitor plates are arranged in the second reflection structure.

12. The image sensor according to any one of claims 1 to 10, wherein The image sensor comprises an optical structure layer and a circuit connection layer arranged on opposite sides of the semiconductor structure layer, the trench isolation structure comprises corresponding reflection and light absorption structures, the reflection structure is located at one end of the trench isolation structure close to the optical structure layer and is used for reflecting light, and the light absorption structure is located at one end of the trench isolation structure close to the circuit connection layer and is used for absorbing light, and the first and second capacitor plates are arranged in the light absorption structure.

13. A method of manufacturing an image sensor, suitable for use in an image sensor as claimed in any one of claims 1-12, characterized in that, The preparation method comprises the following steps: providing a substrate comprising opposite first and second surfaces; forming an isolation structure in the substrate and preparing a capacitor in the isolation structure, the capacitor comprising a first capacitor plate and a second capacitor plate; forming an array of light-sensitive pixel regions in the substrate from the first surface, the light-sensitive pixel regions comprising light-sensitive elements, and the isolation structure separating the light-sensitive pixel regions; preparing a reset transistor and a conversion gain control transistor in the light-sensitive pixel regions, and electrically connecting the capacitor between the conversion gain control transistor and the reset transistor.

14. The method of fabricating an image sensor according to claim 13, wherein The preparation method further comprises the following steps: thinning the substrate from the second surface of the substrate to obtain a thinned surface, and preparing a back compensation isolation structure corresponding to the isolation structure in the substrate from one side of the thinned surface, and a corresponding set of the isolation structure and the back compensation isolation structure forming a trench isolation structure.

15. The method of producing an image sensor according to claim 13 or 14, wherein The preparation method further comprises the step of preparing a circuit connection layer, wherein the reset transistor and the conversion gain control transistor have a shared active region, and the preparation of the circuit connection layer comprises the following steps: forming a dielectric layer on the first surface of the substrate; forming at least a first contact hole corresponding to one plate of the capacitor and a second contact hole corresponding to the shared active region in the dielectric layer, forming a conductive layer on the dielectric layer, and the conductive layer electrically connecting the capacitor, the reset transistor and the conversion gain control transistor based on the first and second contact holes.

16. The method of fabricating an image sensor according to claim 15, wherein In the process of preparing the circuit connection layer, the following steps are further included: forming a third contact hole in the dielectric layer, and the conductive layer electrically connecting the transistors in the light-sensitive pixel regions and / or electrically interconnecting the transistors based on the third contact hole.

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