A full-time multi-channel recording circuit and method

Abstract

The present invention provides a full-time multi-channel waveform recording circuit and method. The circuit includes at least one buffer function module composed of a memory A, a memory B, and a channel waveform control unit, a clock and transmission control center, and a communication and timing unit, which are connected in sequence. The circuit realizes the caching and transmission of waveform data according to channel numbers and complete time information. The full-time waveform recording can record various conditions occurring during the operation of the power grid in real time, completely, and accurately, providing effective support for power grid operation parameters and fault diagnosis. The clock and transmission control center of the present invention reasonably and orderly frames multi-channel waveforms and non-waveform data of other data source modules, realizing the scientific sharing of a communication unit for waveform recording data and non-waveform recording data; the time slice transmission mechanism avoids the influence of the recording of other channels when a hardware failure occurs in a certain waveform recording channel. The circuit has strong robustness and fault tolerance and has good engineering application value.

Description

Technical Field

[0001] The present invention relates to the technical fields of data acquisition and power monitoring, and more specifically to the field of oscillograph recording in power monitoring. Background Art

[0002] With the rapid growth of power demand, the scale of the power grid is also growing day by day, the grid structure is becoming more and more complex, and grid security is becoming increasingly important. An efficient and reliable power system is the basic guarantee for the normal operation of modern industrial equipment. Improving power quality must be based on long-term real-time monitoring. The power oscillograph device is the basic unit for the development of smart grids, and its information is an important basis for judging the operation state of the system and the action of protection devices. Power oscillograph data can record the daily operation conditions of the power grid system and the waveform changes of the system before and after a fault occurs, providing necessary data support for studying the operation conditions of the power grid system and the causes and laws of faults.

[0003] As an important guarantee for the safe operation of the power grid, the relay protection technology has made rapid development in recent years. The power oscillograph technology can correctly evaluate the working conditions of relay protection devices. When the protection device operates, it is helpful for us to accurately find the oscillograph recording points of the power grid operation in time, take effective measures to reduce the probability of power grid oscillograph occurrence, and reduce the losses caused by faults.

[0004] The most commonly used solution in the field of power monitoring oscillograph recording is triggered oscillograph recording, that is, when specific triggering conditions (frequency deviation, overcurrent, undervoltage, etc.) are met, the waveform information before and after the triggering conditions is recorded. However, due to the complexity of power grid operation and the uncertainty of triggering conditions (sometimes the time difference between the fault time point and the triggering time point is uncertain), triggered oscillograph recording cannot ensure the acquisition and recording of sensitive waveforms.

[0005] Although full-time oscillograph recording will increase the resource utilization of oscillograph recording and storage, it has a wide range of application requirements in power system scenarios such as ship power systems and small power stations that perform tasks periodically. The mission cycle of some ships on a single voyage is several months to dozens of months. Implementing full-cycle multi-channel oscillograph recording during this period can record various conditions that occur during the operation of the power grid in real time, completely and accurately, which has very important practical significance for the operation conditions of the power grid system and the study of the causes of faults. Summary of the Invention

[0006] The object of the present invention is to provide a full-time multi-channel waveform recording circuit and method, which can meet the monitoring requirements of a power grid operating in stages, achieve multi-channel full-cycle waveform recording within an operating cycle of several months to dozens of months, so as to record various conditions occurring during the operation of the power grid in real time, completely and accurately, and provide effective support for power grid operation parameters and fault diagnosis. In addition, operating according to the method of the present invention enables the reasonable and orderly framing of multi-channel waveforms and non-waveform data of other data source modules, and the scientific sharing of a communication unit by waveform recording data and non-waveform recording data, greatly improving the utilization rate of equipment. At the same time, when a failure occurs in the waveform recording channel hardware or other data source devices, this method can effectively shield relevant failure signals and ensure the recording of waveform recording data of normal channels.

[0007] Specifically, the present invention provides a full-time multi-channel waveform recording circuit, characterized in that the waveform recording circuit includes a communication and timing unit, a clock and transmission control center, and a plurality of buffer function modules, which are connected in sequence. Each buffer function module is externally connected to a monitoring channel for buffering the waveform recording data of the channel. The communication and timing unit is used for communication connection with an external module. The number of buffer function modules connected to the clock and transmission control center is set according to the number of monitoring channels. Each buffer function module consists of a channel waveform control unit and two identical memories, namely memory A and memory B, which are used for alternately storing raw waveform data of duration T1. According to the time slice transmission mechanism, the clock and transmission control center divides the time period T1 into multiple data transmission sub-periods, extracts the normal waveform recording data in one buffer function module and receives the non-waveform recording data of other data sources in each data transmission sub-period, and outputs them through the communication and timing unit to achieve full-time multi-channel waveform recording.

[0008] The time and transmission control center has a non-wave-recording communication data interface for receiving non-wave-recording data from other data sources. The time and transmission control center assigns corresponding transmission times to each wave-recording data transmission channel. For each channel within a time period, only one channel reading control signal is sent. Before sending the channel reading control signal for any channel, the time and transmission control center monitors whether the non-wave-recording communication data interface is receiving non-wave-recording data. If it is receiving, the transmission of the corresponding channel reading control signal is delayed. If no non-wave-recording data is being received, the channel reading control signal is sent to the corresponding channel. The channel waveform control unit controls the read control signals of the two memories based on whether the channel reading control signal and the write control signals of the two memories are valid. That is, when the channel reading control signal is valid, if the write control signal of memory A is valid, then only the read control signal of memory B is controlled to be valid. When the channel reading control signal is valid, if the write control signal of memory B is valid, then only the read control signal of memory A is controlled to be valid. The channel waveform control unit extracts waveform data with the channel number and complete time information from the memory with the valid read control signal and sends it to the time and transmission control center. Once the time and transmission control center receives the wave-recording data, it sets the wave-recording transmission busy flag to be valid. The other data sources suspend sending non-wave-recording data when they receive the wave-recording transmission busy flag. If the other data sources still send data due to a fault, the time and transmission control center masks the non-wave-recording data based on the wave-recording transmission busy flag. When the time and transmission control center monitors that the wave-recording data transmission of this channel is completed, it sets the wave-recording transmission busy flag to be invalid and receives non-wave-recording data from other data sources through the non-wave-recording data interface.

[0009] The wave-recording data extracted from the cache function module is waveform data containing the channel number and complete time information. The channel number is provided by the channel waveform control unit, and the complete time information is the complete time information with milliseconds and microseconds generated by the clock and transmission control center based on the time reference provided by the external module.

[0010] The content of the time slice transmission mechanism is as follows:

[0011] If the transmission of waveform information of N channels needs to be completed within the single cache time T1, the maximum number of channels N, the single cache time T1, the reserved time τ for single-channel transmission, and the transmission time Δτ need to satisfy the following relationship: T1 / N ≥ τ + Δτ, and τ > Δτ;

[0012] Among them, the transmission time Δτ is the time taken by the clock and transmission control center to send the serial data frame of the wave-recording data to the communication and timing unit, which is determined by the circuit of the clock and transmission control center;

[0013] For a single caching time T1, starting from its initial moment, it is divided into N parts according to the unit time duration (τ + Δτ). Within (n - 1)×(τ + Δτ) to nτ+(n - 1)×Δτ, where n is the channel number and 1 ≤ n ≤ N, and when the clock and the channel reading control signal of the sending control center are valid, the data entry of the non-recording communication data interface is blocked, and the waveform data with the channel and complete time sent by the corresponding caching function module of the nth channel is received. After adding the frame header information, a serial data frame is formed, and the task of sending the serial data frame to the communication and timing unit is completed before the moment of n×(τ + Δτ);

[0014] Within N×(τ + Δτ) to T1 in T1, the clock and the sending control center have no recording and sending tasks, and receive non-recording data sent by other data sources.

[0015] The channel reading control signal is a start sending signal sent by the clock and the sending control center to each caching function module. Within the single storage duration T1, each caching function module only receives a start sending action command once within a fixed time period, that is, the caching function module corresponding to the nth channel only starts a sending action within the time period of (n - 1)×(τ + Δτ) to nτ+(n - 1)×Δτ.

[0016] Within the time period of (n - 1)×(τ + Δτ) to n×(τ + Δτ), if the recorded data of the nth channel has been processed into a serial data frame and the sending has been completed, the recording and sending busy flag is invalid, and other data sources send non-recording data to the time and sending control center through the non-recording communication data interface during the remaining time.

[0017] The recording method includes the following steps:

[0018] 1. Set relevant information: The clock and the sending control center determine the transmission time Δτ according to the number of monitoring channels and the circuit sending speed of the clock and the sending control center, and set the single caching time T1 and the single-channel transmission reservation time τ;

[0019] 2. Input time information: The communication and timing unit receives the system time information of the external timing node in the form of communication, and sends the year, month, day, hour, minute, and second information to the clock and the sending control center. The clock and the sending control center generate the time information of milliseconds and microseconds to form the complete time information, and send the complete time information to the memory through the channel control unit;

[0020] 3. Within the first single caching time T1, the channel waveform control center in the N caching function modules stores the waveform data of the corresponding channels in the first memory with the write control signal being valid, and the storage duration is T1; the data transmission process within this T1 is as follows:

[0021] 1), within 0 to τ, and when it is determined that there is no valid data in the non-recording communication data interface, the clock and the transmission control center shield the data of the non-recording communication data interface, send a channel reading control signal to the buffer function module corresponding to the first channel, and the second memory B in the buffer function module sends the waveform data with the channel and the complete time stored in the previous cycle T1 to the clock and the transmission control center. After adding the frame header information in the clock and the transmission control center, the waveform data with the channel and the complete time forms a serial data frame, and the formed serial data frame starts to be sent to the communication and timing unit. When the serial data frame is sent, the recording transmission busy flag of the clock and the transmission control center is valid;

[0022] 2), before the moment of (τ + Δτ), the corresponding serial data frame completes the transmission to the external communication and timing unit; within 0 to (τ + Δτ), after the serial data frame of the corresponding recording signal completes the transmission to the external communication and timing unit, the recording transmission busy flag becomes invalid, and the clock and the transmission control center receive the non-recording static data frames of other data sources and send them to the communication and timing unit;

[0023] 3), within (τ + Δτ) to 2τ + Δτ, the processes of steps 1) to 2) are executed for the second channel, and the corresponding serial data frame completes the transmission to the communication and timing unit before the moment of 2×(τ + Δτ); and so on, before the moment of n(τ + Δτ), the waveform data with the channel and the complete time of the nth channel is converted into the corresponding serial data frame and completes the transmission to the communication and timing unit;

[0024] 4), there is no recording transmission task within N×(τ + Δτ) to T1, and the clock and the transmission control center receive and send the non-recording static data frames of other data sources;

[0025] 4. Within T1 to 2×T1, the waveform data of each channel is recorded into the corresponding second memory B, and the storage duration is still T1; the processes as in steps 1) to 4) occur during this cycle; and so on for multiple consecutive cycles in a long time, realizing the recording of N channels in all time periods.

[0026] The beneficial effects brought by the present invention are as follows: The present invention realizes the caching and sending of waveform data according to the channel number and the complete time information, can record various situations occurring during the operation of the power grid in real time, completely and accurately, and provides effective support for the operation parameters and fault diagnosis of the power grid. The clock and the transmission control center of the present invention reasonably and orderly frame the multi-channel waveforms and the non-waveform data of other data source modules, realizing the scientific sharing of a communication unit by the recording data and the non-recording data; the time slice sending mechanism avoids the influence on the recording of other channels when a hardware failure occurs in a certain recording channel, and this circuit has strong robustness and fault tolerance, and has good engineering application value. Description of the Drawings

[0027] Figure 1 Full-time multi-channel recording wave circuit and method block diagram of the present invention

[0028] Figure 2 Full-time dual-channel recording wave effect diagram of the present invention

[0029] Figure 3 Full-time recording wave effect diagram recorded by the present invention when a fault occurs Specific implementation manners

[0030] Next, the technical solutions in the embodiments of the present invention will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present invention. It should be noted that in the description of the present invention, unless otherwise clearly specified and limited, those skilled in the art should understand the specific meanings of the terms in the present invention according to the specific circumstances.

[0031] Embodiment

[0032] As Figure 1 shown, a full-time multi-channel recording wave circuit and method in this embodiment includes a communication and timing unit 1, a clock and transmission control center 2, and a buffer function module 3, which are connected in sequence. The communication and timing unit is externally connected to an external module, and the buffer function module is externally connected to a monitoring channel. The number of buffer function modules 3 connected to the clock and transmission control center 2 is set according to the number of monitoring channels. Each buffer function module 3 consists of a channel waveform control unit 31 and two identical memories, namely memory A 32 and memory B 33, which are used to alternately store the original waveform data. The clock and transmission control center 2 alternately extracts the recording wave data of memory A 32 and memory B 33 in the buffer function module 3 according to the time slice transmission mechanism to achieve full-time multi-channel recording wave.

[0033] The communication and timing unit 1 is connected to the clock and transmission control center 2. The communication and timing unit 1 receives the system time information of the timing node of the external module in the form of communication and sends the year, month, day, hour, minute, and second information to the clock and transmission control center 2. The communication and timing unit 1 receives the serial data frame of the full-time multi-channel recording wave signal output by the clock and transmission control center 2 externally and performs the external sending action through the communication line in the form of communication.

[0034] The clock and transmission control center 2 is located between the communication and timing unit 1 and the buffer function module 3, and is simultaneously connected to multiple buffer function modules 3. On the one hand, the clock and transmission control center 2 is responsible for providing the buffer function module 3 with complete time information converted into milliseconds and microseconds. On the other hand, after adding the frame header information to the waveform data with channel numbers and complete time output by multiple buffer function modules 3 in sequence to form a serial data frame, it is sent to the communication and timing unit 1. The frame header information includes the destination address, local address, and data length. The clock and transmission control center 2 has a non-recording communication data interface and receives and processes static data frames from other data sources when no recording data is being transmitted.

[0035] The buffer function module 3 consists of a channel waveform control unit 31, a memory A 32, and a memory B 33. The memory A 32 and the memory B 33 are storage chips or units with read-write control ports that can store and read data. The channel waveform control unit 31 receives the original waveform data from the corresponding monitoring channel, receives the complete time information from the clock and transmission control center 2, alternately stores the original waveform data and the complete time information in the memory A 32 and the memory B 33, and transports the waveform data with channel numbers and complete time output by the memory A 32 and the memory B 33 to the clock and transmission control center 2.

[0036] The channel waveform control unit 31 controls the memory A 32 and the memory B 32 to alternately store the waveform information for a single duration T1. When the write control signal of the memory A 32 is valid, its read control signal is invalid and the read control signal of the memory B 33 is valid. When the write control signal of the memory B 33 is valid, its read control signal is invalid and the read control signal of the memory A 32 is valid. That is, the valid signals of the read and write controls of the memory A 32 and the memory B 33 are alternately valid within the full cycle time, thereby realizing that the memory A 32 and the memory B 33 alternately cache the waveform data within the full cycle and alternately send the waveform data with channels and complete time.

[0037] The channel waveform control unit 31 of the cache function module 3 controls the read control signals of the memory A 32 and the memory B 33 according to the write control signals and clocks of the memory A 32 and the memory B 33 and the channel read control signal of the transmission control center 2. During the single storage duration T1, if the write control signal of the memory A 32 is valid when the channel read control signal of the clock and the transmission control center 2 is valid, the read control signal of the memory A 32 is invalid, and the read control signal of the memory B 33 is valid, then the waveform data with channels and complete time in the memory B 33 is output; if the write control signal of the memory B 33 is valid when the channel read control signal of the clock and the transmission control center 2 is valid, the read control signal of the memory B 33 is invalid, and the read control signal of the memory A 32 is valid, then the waveform data with channels and complete time in the memory A 32 is output. Furthermore, the read and write control signals of the memory A 32 and the memory B 33 are not valid at the same time, and the clock and the transmission control center 2 can alternately extract the waveform data with channels and complete time in the memory A 32 and the memory B 33 throughout the whole period.

[0038] The clock and the transmission control center 2 has a recording wave transmission busy flag, which is used to indicate that the clock and the transmission control center 2 is currently in the time of transmitting the recording wave waveform data and does not receive the data of the non-recording wave communication data interface.

[0039] The content of the time slice transmission mechanism is as follows:

[0040] Because the transmission of the waveform information of N channels needs to be completed within the single cache time T1, the maximum number of channels N, the single cache time T1, the reserved time τ for single-channel transmission, and the transmission time Δτ need to satisfy the following relationship:

[0041] T1 / N ≥ τ + Δτ, and τ > Δτ;

[0042] Among them, the transmission time Δτ is the time taken for the clock and the transmission control center 2 to send the serial data frame to the communication and timing unit 1, which is determined by the circuit of the clock and the transmission control center 2;

[0043] The clock and the transmission control center 2 sets the recording wave transmission busy flag to be valid during the transmission duration, and sets the recording wave transmission busy flag to be invalid at other times. When the recording wave transmission busy flag of the clock and the transmission control center 2 is invalid, it receives other data from the non-recording wave communication data interface, adds the frame header information, and then forms a serial data frame and sends it to the communication and timing unit 1;

[0044] During the single storage duration T1, the clock and the transmission control center 2 initiate the transmission action only once for each channel, avoiding the influence on the recording of other channels when a hardware failure occurs in a certain recording channel. The clock and the transmission control center 2 initiate the transmission action only once for the buffer function unit 3 corresponding to the nth channel within the time period from (n - 1)×(τ + Δτ) to nτ+(n - 1)×Δτ, and complete the transmission of the corresponding serial data frame to the communication and timing unit 1 before the moment of n×(τ + Δτ), avoiding conflicts with the transmission action initiated by the clock and the transmission control center 2 for the (n + 1)th channel; moreover, when the clock and the transmission control center 2 receive the data of the nth channel including the channel number and the complete time waveform data, they shield the interference data sent by other faulty buffer function modules 3 during non-transmission time.

[0045] Within (n - 1)×(τ + Δτ) to nτ+(n - 1)×Δτ in T1, and when there is no valid data at the non-recording communication data interface, the clock and the transmission control center 2 control the channel reading control signal to be valid, receive the waveform data with the channel and the complete time connected to the nth channel from the buffer function module 3, shield the data at the non-recording communication data interface, add the frame header information to form a serial data frame, and complete the transmission of the corresponding serial data frame to the communication and timing unit 1 before the moment of n×(τ + Δτ);

[0046] Within the time period from (n - 1)×(τ + Δτ) to n×(τ + Δτ), if the data of the nth channel has been processed into a serial data frame and the transmission has been completed, the recording transmission busy flag is invalid, and the static data frames of other data sources enter the clock and the transmission control center 2 through the non-recording communication data interface and are sent to the communication and timing unit 1 for external output.

[0047] The clock and the transmission control center 2 do not perform recording transmission within N×(τ + Δτ) to T1 in T1, receive and process the non-recording data of other data sources, and wait for the waveform data cached in memory A or memory B for the next T1 duration.

[0048] The recording method of the present invention includes the following steps:

[0049] 1. Set the initial relevant information: The clock and the transmission control center 2 set the single cache time T1 and the single-channel transmission reservation time τ according to the number of monitoring channels and Δτ determined by the circuit of the clock and the transmission control center 2;

[0050] 2. Input time information: The communication and timing unit 1 receives the system time information of the external timing node in a communication manner, and sends the year, month, day, hour, minute, and second information to the clock and the transmission control center 2. The clock and the transmission control center 2 generate millisecond and microsecond information to form the complete time information, and send the complete time information to the memory through the channel waveform control unit 31;

[0051] 3. During the first single - cache time T1, the channel waveform control unit 31 in the N cache function modules stores the waveform data of the corresponding channel into the memory with a valid write control signal, such as memory A32, for a storage duration of T1. The following processes occur within this T1:

[0052] 1). When within 0 to τ and there is no valid data at the non - recording communication data interface, the clock and transmission control center 2 masks the data at the non - recording communication data interface and sends a channel read control signal to the cache function module 3 corresponding to the first channel. In the cache function module 3, the memory B33 sends the waveform data with the channel and complete time stored in the previous cycle T1 to the clock and transmission control center 2. After adding the frame header information in the clock and transmission control center 2, the formed serial data frame starts to be sent to the communication and timing unit 1. When the above - mentioned serial data frame occurs, the recording transmission busy flag in the clock and transmission control center is valid;

[0053] 2). Before the moment of (τ + Δτ), the serial data frame formed by the recording data completes the transmission to the communication and timing unit 1. When within 0 to (τ + Δτ), if the serial data frame of the corresponding recording data completes the transmission to the communication and timing unit 1, then the recording transmission busy flag is shown to be invalid, and the clock and transmission control center 2 receives the non - recording static data frames from other data sources and sends them to the communication and timing unit 1;

[0054] 3). During (τ + Δτ) to 2τ + Δτ, the processes of steps 1) - 2) are executed for channel 2, and the corresponding serial data frame completes the transmission to the communication and timing unit 1 before the moment of 2×(τ + Δτ). And so on, before the moment of n×(τ + Δτ), the waveform data with the channel and complete time of the nth channel is converted into the corresponding serial data frame and the transmission to the communication and timing unit 1 is completed;

[0055] 4). There is no recording transmission task during N×(τ + Δτ) to T1, and the clock and transmission control center 2 receives and sends the non - recording static data frames from other data sources.

[0056] 4. During the second single - cache time T1, the waveform data of each channel is recorded into the corresponding memory B, and the storage duration is still T1. The processes within this cycle are as in steps 1) - 4). And so on, the present invention realizes full - time multi - channel recording.

[0057] Taking an all - time multi - channel recording circuit of the present invention as an example, the implementation process is illustrated as follows:

[0058] This embodiment Figure 1The communication and timing unit 1 is implemented based on fiber optic FC-AE (Fiber Channel-Avionics Environment) communication.

[0059] In this embodiment Figure 1 The clock and transmission control center 2 is a logic state machine hardware circuit.

[0060] In this embodiment, the channel waveform control unit 31 is a logic state machine hardware circuit.

[0061] In this embodiment, both memory A and memory B use field programmable gate arrays (FPGAs) with a main frequency of 125 MHz, and FIFOs (First In First Out) of model XC7K325T are selected. The read and write enable control of the FIFO corresponds to the effective read and write control of memory A or memory B.

[0062] In this embodiment, other external data sources come from the TMS320F28377 DSP chip. The clock and transmission control center receives static data frames of non-recorded wave data at a frequency of 10 times per 500 ms. The static data frame occupies a single transmission time of 0.2 ms in the clock and transmission control center. The DSP chip side waits for a duration of Δτ = 1 ms, and then sends the static frame data to the non-recorded wave communication data interface.

[0063] In this example, the number of channels N is 14, that is, a total of 14 channels need to record waves, corresponding to 14 cache function modules. T1 is selected as 500 ms, that is, the single storage duration of memory A and memory B is 500 ms. The reserved time τ for single-channel transmission is 19 ms, and the transmission setting time Δτ is determined by the circuit of the clock and transmission control center, which is 1 ms in this example. It meets the requirements in the above text:

[0064] (τ + Δτ = 20 ms) ≤ (T1 / N = 500 ms / 14 = 35.71 ms), τ > Δτ

[0065] In this embodiment, the original waveform data at the front end of each cache function module is updated every 200 us (the corresponding data refresh rate or sampling rate is 5 kSPS). Since T1 is 500 ms, memory A and memory B store 2500 waveform data points per single storage.

[0066] As Figure 2 shown, the names of 14 channels are displayed above the waveform diagram. The recorded wave data of each channel is displayed on the display screen. To facilitate viewing the waveform effect, except for the two channels of the 3# distribution board voltage Uab and the 3# distribution board voltage Ucb, no analog signals are connected to the other channels. It can be seen from the figure the effect after the recorded wave data is restored.

[0067] To facilitate the viewing of the full-time waveform recording effect of the present invention, the waveform data of the voltage Uab channel of the 3# distribution board is intermittently turned off, and the recording effect is observed on the display screen as Figure 3 , the white analog waveform of the voltage Ucb channel of the 3# distribution board always exists, while the signal source corresponding to the voltage Uab channel of the 3# distribution board is manually intermittently turned on and off, and the waveform interface can reflect the effect diagram of the recording channel following the external waveform, which shows that the present invention can accurately record the full-time multi-channel waveform recording.

[0068] The above has described the present invention in detail through specific implementation manners and embodiments, but these do not constitute limitations on the present invention. Without departing from the principle of the present invention, those skilled in the art can also make many deformations and improvements, which should also be regarded as the protection scope of the present invention.

Claims

1. A full-time multi-channel recording circuit, characterized in that, The oscillograph circuit includes a communication and timing unit, a clock and transmission control center, and multiple buffer function modules, which are connected in sequence. Each buffer function module is externally connected to a monitoring channel for buffering the oscillograph data of that channel. The communication and timing unit is used for communication connection with an external module. The number of buffer function modules connected to the clock and transmission control center is set according to the number of monitoring channels. Each buffer function module consists of a channel waveform control unit and two identical memories, namely memory A and memory B, which alternately store the original waveform data for a duration of T1; According to the time slice transmission mechanism, the clock and transmission control center divides the time period T1 into multiple data transmission sub-periods. In each data transmission sub-period, it extracts the normal oscillograph data from one buffer function module and receives the non-oscillograph data from other data sources, and outputs them through the communication and timing unit to achieve full-time multi-channel oscillograph; The time and transmission control center has a non-oscillograph communication data interface for receiving the non-oscillograph data from other data sources. The time and transmission control center assigns corresponding transmission times to each oscillograph data transmission channel. For each channel within a time period, it only sends a channel read control signal once. Before sending the channel read control signal for any channel, the time and transmission control center monitors whether the non-oscillograph communication data interface is receiving non-oscillograph data. If it is receiving, the sending of the corresponding channel read control signal is delayed. If it is not receiving non-oscillograph data, it sends the channel read control signal to the corresponding channel. The channel waveform control unit controls the read control signals of the two memories according to whether the channel read control signal and the write control signals of the two memories are valid. That is, when the channel read control signal is valid, if the write control signal of memory A is valid, it controls only the read control signal of memory B to be valid. When the channel read control signal is valid, if the write control signal of memory B is valid, it controls only the read control signal of memory A to be valid. The channel waveform control unit extracts the waveform data with the channel number and complete time information from the memory with the valid read control signal and sends it to the time and transmission control center. Once the time and transmission control center receives the oscillograph data, it sets the oscillograph transmission busy flag to be valid. The other data sources suspend sending non-oscillograph data when they receive the oscillograph transmission busy flag. If the other data sources still send data due to a fault, the time and transmission control center masks the non-oscillograph data according to the oscillograph transmission busy flag. When the time and transmission control center monitors that the oscillograph data transmission of this channel is completed, it sets the oscillograph transmission busy flag to be invalid and receives the non-oscillograph data from other data sources through the non-oscillograph data interface.

2. The full-time multi-channel recording circuit according to claim 1, characterized in that The oscillograph data extracted from the buffer function module is waveform data containing the channel number and complete time information. The channel number is provided by the channel waveform control unit, and the complete time information is the complete time information containing milliseconds and microseconds generated by the clock and transmission control center according to the time reference provided by the external module.

3. A full-time multi-channel recording circuit according to claim 1, characterized in that The content of the time slice transmission mechanism is as follows: If the transmission of waveform information for N channels needs to be completed within a single caching time T1, the maximum number of channels N, the single caching time T1, the reserved time τ for single-channel transmission, and the transmission time Δτ need to satisfy the following relationship: T1 / N ≥ τ + Δτ, and τ > Δτ; Among them, the transmission time Δτ is the time taken for the clock and the sending control center to send the serial data frame of the recorded wave data to the communication and timing unit, which is determined by the circuit of the clock and the sending control center; For the single caching time T1, it is divided into N parts at unit time length (τ + Δτ) starting from its initial moment. Within (n - 1)×(τ + Δτ) to nτ + (n - 1)×Δτ, n is the channel number, 1 ≤ n ≤ N, and when the channel reading control signal of the clock and the sending control center is valid, the data entry of the non-recorded wave communication data interface is blocked, and the waveform data with the channel and complete time sent by the corresponding caching function module of the nth channel is received. After adding the frame header information, a serial data frame is formed, and the task of sending the serial data frame to the communication and timing unit is completed before the moment of n×(τ + Δτ); Within N×(τ + Δτ) to T1 in T1, the clock and the sending control center have no recorded wave sending task and receive non-recorded wave data sent by other data sources.

4. The full-time multi-channel recording circuit according to claim 1, wherein The channel reading control signal is the start sending signal sent by the clock and the sending control center to each caching function module. Within the single storage time T1, each caching function module only receives a start sending action command once within a fixed time period, that is, the caching function module corresponding to the nth channel only starts a sending action within the time period of (n - 1)×(τ + Δτ) to nτ + (n - 1)×Δτ.

5. The full-time multi-channel recording circuit according to claim 3, characterized in that Within the time period of (n - 1)×(τ + Δτ) to n×(τ + Δτ), if the recorded wave data of the nth channel has been processed into a serial data frame and the sending has been completed, the recorded wave sending busy flag is invalid, and other data sources send non-recorded wave data to the time and sending control center through the non-recorded wave communication data interface during the remaining time.

6. A method for performing waveform recording using the waveform recording circuit according to claim 1, characterized in that, The recorded wave method includes the following steps: A. Set relevant information: The clock and the sending control center determine the transmission time Δτ according to the number of monitoring channels and the sending speed of the circuit of the clock and the sending control center, and set the single caching time T1 and the reserved time τ for single-channel transmission; B. Input time information: The communication and timing unit receives the system time information of the external timing node in a communication form and sends the year, month, day, hour, minute, and second information to the clock and the sending control center. The clock and the sending control center generate the time information of milliseconds and microseconds to form complete time information, and send the complete time information to the memory through the channel control unit; C. Within the first single caching time T1, the channel waveform control center in the N caching function modules stores the waveform data of the corresponding channels into the first memory with the write control signal being valid, and the storage duration is T1; the data transmission process within this T1 is as follows: C1). Within 0 to τ, when it is determined that there is no valid data in the non-recording communication data interface, the clock and the transmission control center mask the data of the non-recording communication data interface and send a channel read control signal to the buffer function module corresponding to the first channel. In the buffer function module, the second memory B sends the waveform data with the channel and the complete time stored in the previous period T1 to the clock and the transmission control center. After adding the frame header information in the clock and the transmission control center, the waveform data with the channel and the complete time forms a serial data frame, and the formed serial data frame starts to be sent to the communication and timing unit. When the serial data frame is sent, the recording transmission busy flag of the clock and the transmission control center is valid; C2). Before the moment of (τ + Δτ), the corresponding serial data frame completes the transmission to the communication and timing unit. Within 0 to (τ + Δτ), after the serial data frame of the corresponding recording signal completes the transmission to the communication and timing unit, the recording transmission busy flag becomes invalid, and the clock and the transmission control center receive the non-recording static data frames from other data sources and send them to the communication and timing unit; C3). Within (τ + Δτ) to 2τ + Δτ, the processes of steps C1) to C2) are executed for the second channel, and the corresponding serial data frame completes the transmission to the communication and timing unit before the moment of 2×(τ + Δτ). And so on, before the moment of n(τ + Δτ), the waveform data with the channel and the complete time of the nth channel is converted into the corresponding serial data frame and the transmission to the communication and timing unit is completed; C4). There is no recording transmission task within N×(τ + Δτ) to T1, and the clock and the transmission control center receive and send the non-recording static data frames from other data sources; D. Within T1 to 2×T1, the waveform data of each channel is recorded into the corresponding second memory B, and the storage duration is still T1. The processes in steps C1) to C4) occur during this period. And so on for multiple consecutive long periods, realizing the recording of N channels in all time periods.

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