A fault-tolerant architecture for a flight tube data acquisition computer

Abstract

The application belongs to the technical field of airborne computer, and particularly relates to a fault-tolerant architecture's flight tube data acquisition computer. The flight tube data acquisition computer comprises at least two acquisition channels; the acquisition channel comprises a processing unit, a multi-channel bus receiving interface, a bus sending interface, a data cross-transmission interface and a time synchronization interface. The application can complete half redundancy flight tube data forwarding after one channel failure, and improves the availability of the flight tube data acquisition computer. Online maintenance and autonomous monitoring are designed based on DSP, and the maintenance and reliability of the data acquisition computer are improved.

Description

Technical Field

[0001] The present invention belongs to the technical field of airborne computers, and in particular relates to a flight control data acquisition computer with a fault-tolerant architecture. Background Art

[0002] Modern aircraft's protective recording devices and flight data recorders are connected to the avionics system network. To ensure real-time and deterministic network transmission, flight control system devices are generally interconnected using a bus network separate from the avionics system. Therefore, protective recording devices and flight data recorders cannot directly access flight control system data through the avionics network. To ensure that flight control data can be recorded by protective recording devices and flight data recorders, a dedicated computer is required to forward flight control system data to the protective recording devices and flight data recorders.

[0003] The flight control data acquisition computer primarily collects, filters, and forwards flight control system data. Typically, this computer integrates and packages redundant flight control data before forwarding it. The data processing section lacks redundancy, creating the risk of data loss in the event of a single failure. Summary of the Invention

[0004] In light of this, and to mitigate this risk, the present invention proposes a fault-tolerant flight control data acquisition computer. Through independent power supply design, dual-channel fault-tolerant design, and cross-data transmission strategies, the flight control data acquisition computer possesses a certain degree of fault tolerance. In the event of partial circuit failure, redundant flight control data will not be completely lost. This improves the availability of the flight control data acquisition computer and enhances the reliability of the flight control system's data forwarding and recording.

[0005] In order to achieve the above technical objectives, the specific technical solutions adopted by the present invention are:

[0006] A flight control data acquisition computer with a fault-tolerant architecture, the flight control data acquisition computer comprising at least two acquisition channels; the acquisition channels comprising a processing unit, a multi-channel bus receiving interface, a bus transmitting interface, a data cross transmission interface and a time synchronization interface;

[0007] Each of the bus interfaces collects flight control data from the flight control computer and communicates with the processing unit;

[0008] The processing unit is used to process the flight control data and process the flight control data into data packets that can be received by a flight parameter recorder and a protection recording device;

[0009] The bus sending interface communicates with the processing unit and is used to send the data packet;

[0010] The data packets are cross-transmitted between the acquisition channels based on the data cross-transmission interfaces;

[0011] Cross-transmitting time stamp information between the acquisition channels based on the timing interfaces;

[0012] Each of the acquisition channels communicates with the protection recording device; at least one of the acquisition channels communicates with the flight parameter recorder.

[0013] Furthermore, the flight control data acquisition computer also includes an intelligent maintenance unit; the intelligent maintenance unit is connected to each of the acquisition channels, and is used to regularly collect the working status of each of the acquisition channels, initialize each of the acquisition channels, and maintain each of the acquisition channels online.

[0014] Furthermore, the flight control data acquisition computer includes two acquisition channels; the two acquisition channels are channel A and channel B;

[0015] Channel A is provided with a first FPGA, four 1394B bus receiving interfaces, one 1394B bus transmitting interface, one data cross transmission interface, and a time synchronization interface; channel B is provided with a second FPGA, four 1394B bus receiving interfaces, one 1394B bus transmitting interface, one FC transmitting interface, one data cross transmission interface, and a time synchronization interface; wherein:

[0016] VMC_A is connected to the two 1394 receive interfaces of channel A through 1394B_A_1 and 1394B_A_2, VMC_B is connected to the two 1394 receive interfaces of channel A through 1394B_B_1 and 1394B_B_2, and the protection recording device is connected to the one 1394 transmit interface of channel A through 1394B_1; VMC_C is connected to the two 1394 receive interfaces of channel B through 1394B_C_1 and 1394B_C_2, VMC_D is connected to the two 1394 receive interfaces of channel B through 1394B_D_1 and 1394B_D_2, the protection recording device is connected to the one 1394 transmit interface of channel B through 1394B_2, and the flight parameter recorder is connected to the one FC transmit interface of channel B through the FC bus; Channel A and Channel B are connected through the Aurora interface to achieve cross-channel data transmission.

[0017] Furthermore, the bus receiving interfaces are hardware independent; and the data cross transmission interface is an Aurora interface.

[0018] Furthermore, the processing unit processes the flight control data by integrating, filtering, and sending the flight control data.

[0019] Furthermore, the power supply between the acquisition channels is independent.

[0020] Furthermore, the intelligent maintenance unit is integrated on the DSP.

[0021] By adopting the above technical solution, the present invention can bring the following beneficial effects:

[0022] This invention utilizes independent power supply design, dual-channel fault-tolerant design, and cross-data transmission to provide the flight control data acquisition computer with a certain degree of fault tolerance. This prevents all redundant flight control data from being lost in the event of partial circuit failure. This improves the availability of the flight control data acquisition computer and enhances the reliability of data forwarding and recording in the flight control system. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the following briefly introduces the drawings required for use in the embodiments. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0024] Figure 1 The system structure block diagram of a flight control data acquisition computer with a fault-tolerant architecture in a specific embodiment of the present invention.

[0025] Figure 2 This is a diagram of an independent power supply architecture of a flight control data acquisition computer with a fault-tolerant architecture in a specific embodiment of the present invention;

[0026] Figure 3 A single-channel power conversion diagram of a flight control data acquisition computer with a fault-tolerant architecture in a specific embodiment of the present invention;

[0027] Figure 4 This is a diagram of the dual-channel timing structure of the flight control data acquisition computer with a fault-tolerant architecture in a specific embodiment of the present invention. DETAILED DESCRIPTION

[0028] The embodiments of the present disclosure are described in detail below with reference to the accompanying drawings.

[0029] The following describes the embodiments of the present disclosure through specific examples, and those skilled in the art can easily understand other advantages and effects of the present disclosure from the contents disclosed in this specification. Obviously, the described embodiments are only a part of the embodiments of the present disclosure, rather than all of the embodiments. The present disclosure can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present disclosure. It should be noted that, in the absence of conflict, the following embodiments and features in the embodiments can be combined with each other. Based on the embodiments in the present disclosure, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present disclosure.

[0030] It should be noted that various aspects of the embodiments within the scope of the appended claims are described below. It should be apparent that the aspects described herein can be embodied in a wide variety of forms, and any specific structure and / or function described herein is merely illustrative. Based on this disclosure, it should be understood by those skilled in the art that an aspect described herein can be implemented independently of any other aspect, and two or more of these aspects can be combined in various ways. For example, any number of aspects described herein can be used to implement an apparatus and / or practice a method. In addition, other structures and / or functionalities other than one or more of the aspects described herein can be used to implement this apparatus and / or practice this method.

[0031] It should also be noted that the illustrations provided in the following embodiments are only schematic illustrations of the basic concept of the present disclosure. The illustrations only show components related to the present disclosure and are not drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component can be changed at will, and the component layout type may also be more complicated.

[0032] Additionally, in the following description, specific details are provided to provide a thorough understanding of the examples. However, one skilled in the art will appreciate that the aspects described can be practiced without these specific details.

[0033] In one embodiment of the present invention, a flight control data acquisition computer with a fault-tolerant architecture is provided. The flight control data acquisition computer includes at least two acquisition channels. The acquisition channels include a processing unit, a multi-channel bus receiving interface, a bus transmitting interface, a data cross transmission interface, and a timing interface.

[0034] Each of the bus interfaces collects flight control data from the flight control computer and communicates with the processing unit;

[0035] The processing unit is used to process the flight control data and process the flight control data into data packets that can be received by a flight parameter recorder and a protection recording device;

[0036] The bus sending interface communicates with the processing unit and is used to send the data packet;

[0037] The data packets are cross-transmitted between the acquisition channels based on the data cross-transmission interfaces;

[0038] Cross-transmitting time stamp information between the acquisition channels based on the timing interfaces;

[0039] Each of the acquisition channels communicates with the protection recording device; at least one of the acquisition channels communicates with the flight parameter recorder.

[0040] In this embodiment, the flight control data acquisition computer further includes an intelligent maintenance unit; the intelligent maintenance unit is connected to each of the acquisition channels, and is used to regularly acquire the working status of each of the acquisition channels, initialize each of the acquisition channels, and perform online maintenance on each of the acquisition channels.

[0041] In this embodiment, the flight control data acquisition computer includes two acquisition channels; the two acquisition channels are channel A and channel B;

[0042] Channel A is provided with a first FPGA, four 1394B bus receiving interfaces, one 1394B bus transmitting interface, one data cross transmission interface, and a time synchronization interface; channel B is provided with a second FPGA, four 1394B bus receiving interfaces, one 1394B bus transmitting interface, one FC transmitting interface, one data cross transmission interface, and a time synchronization interface; wherein:

[0043] VMC_A is connected to the two 1394 receive interfaces of channel A through 1394B_A_1 and 1394B_A_2, VMC_B is connected to the two 1394 receive interfaces of channel A through 1394B_B_1 and 1394B_B_2, and the protection recording device is connected to the one 1394 transmit interface of channel A through 1394B_1; VMC_C is connected to the two 1394 receive interfaces of channel B through 1394B_C_1 and 1394B_C_2, VMC_D is connected to the two 1394 receive interfaces of channel B through 1394B_D_1 and 1394B_D_2, the protection recording device is connected to the one 1394 transmit interface of channel B through 1394B_2, and the flight parameter recorder is connected to the one FC transmit interface of channel B through the FC bus; Channel A and Channel B are connected through the Aurora interface to achieve cross-channel data transmission.

[0044] In this embodiment, the bus receiving interfaces are hardware independent; the data cross transmission interface is an Aurora interface.

[0045] In this embodiment, the processing unit processes the flight control data by integrating, filtering, and sending the flight control data.

[0046] In this embodiment, the power supply between the acquisition channels is independent.

[0047] In this embodiment, the intelligent maintenance unit is integrated on the DSP.

[0048] This embodiment utilizes independent power supply design, dual-channel fault-tolerant design, and cross-data transmission to ensure a certain degree of fault tolerance in the flight control data acquisition computer. This prevents all redundant flight control data from being lost in the event of a partial circuit failure. This improves the availability of the flight control data acquisition computer and enhances the reliability of the flight control system's data forwarding and recording.

[0049] The flight control data acquisition computer has channel A, channel B and an intelligent maintenance unit. Channel A contains the first FPGA, 4 1394B bus receiving interfaces, 1 1394B bus sending interface, 1 data cross transmission interface and a time synchronization interface; channel B contains the second FPGA, 4 1394B bus receiving interfaces, 1 1394B bus sending interface, 1 FC sending interface, 1 data cross transmission interface and a time synchronization interface; the intelligent maintenance unit completes the flight control data acquisition computer's online maintenance, autonomous monitoring and other functions. Among them:

[0050] VMC_A is connected to the two 1394 receive interfaces of channel A through 1394B_A_1 and 1394B_A_2, VMC_B is connected to the two 1394 receive interfaces of channel A through 1394B_B_1 and 1394B_B_2, and the protection recording device is connected to the one 1394 transmit interface of channel A through 1394B_1; VMC_C is connected to the two 1394 receive interfaces of channel B through 1394B_C_1 and 1394B_C_2, VMC_D is connected to the two 1394 receive interfaces of channel B through 1394B_D_1 and 1394B_D_2, the protection recording device is connected to the one 1394 transmit interface of channel B through 1394B_2, and the flight parameter recorder is connected to the one FC transmit interface of channel B through the FC bus; Channel A and Channel B are connected through the Aurora interface to achieve cross-channel data transmission.

[0051] Channel A and channel B of the flight control data acquisition computer are respectively connected to two redundant flight control buses (4-way 1394B bus data), and the 1394B receiving interface hardware of the two redundant flight control buses are independent.

[0052] Channel A and channel B of the flight control data acquisition computer are connected via the Aurora interface to achieve cross-transmission of flight control data between channels. After cross-transmission, each channel can obtain 4-degree redundant flight control bus data (8-channel 1394B bus data).

[0053] The first FPGA and the second FPGA of the flight control data acquisition computer both realize the functions of 8-channel 1394B bus data packet integration, data screening and data sending.

[0054] An inter-channel timing function is designed between channel A and channel B of the flight tube data acquisition computer to ensure the consistency of the time scales of the dual-channel data.

[0055] The quad-redundant flight control data receiving circuit of the flight control data acquisition computer, namely the 8-channel 1394B bus interface, the first FPGA and the second FPGA are powered independently.

[0056] The DSP design of the flight control data acquisition computer realizes the online maintenance and autonomous monitoring functions of the flight control bus acquisition computer, improving the maintainability of the data acquisition computer.

[0057] The dual-channel time synchronization of the flight tube data acquisition computer means that after the flight tube data acquisition computer is powered on, the first FPGA and the second FPGA respectively perform timing according to the clock of their own channels, with channel A as the master and channel B as the backup. The first FPGA periodically sends the time information of channel A to the second FPGA of channel B, and the second FPGA calibrates the time of channel B according to the received time; if the second FPGA does not receive the time stamp information sent by the first FPGA of channel A within a fixed time, the master and backup channels are swapped, the second FPGA stops receiving the time of channel A, and sends the time of channel B to the first FPGA of channel A. After the first FPGA receives the clock information sent by the second FPGA of channel B, it stops sending clock information to the second FPGA of channel B, and uses the clock information sent by the second FPGA of channel B to calibrate the clock of channel A.

[0058] The 8-channel 1394B bus interface, the first FPGA and the second FPGA of the flight control data acquisition computer are independently powered by 6 independent power conversion circuits, which convert the input 4 redundant 28V power supplies into 6 5V, which are respectively provided to the 4-channel flight control bus data acquisition interface and 2 FPGA circuits.

[0059] This embodiment is described in further detail below.

[0060] The flight control system, as the aircraft's control core, implements centralized information collection, integrated control and management, and output control. The flight control data acquisition computer (FDC) serves as a data bridge between FDC data and the protective recording equipment and flight parameter recorder, enabling the collection, screening, packaging, and forwarding of FDC data. The protective recording equipment and flight parameter recorder receive and record the flight parameter data forwarded by the FDC.

[0061] A certain flight control system is a four-redundant configuration, and a certain flight control data acquisition computer is a two-redundant design, completing the collection and forwarding of flight control data. Each channel of the flight control data acquisition computer receives two-redundant flight control bus data, and the two channels of the flight control data acquisition computer cross-transmit the flight control data received by the channel through the Aurora interface. And the time synchronization between channels is performed through the timing interface. Each channel of the flight control data acquisition computer packages and filters the four-redundant flight control data, and then forwards it to the protection recording equipment and flight parameter recorder through the 1394B interface and FC interface. The flight control bus acquisition computer system architecture is as follows Figure 1 shown.

[0062] Channel A is designed with an FPGA circuit unit, four 1394B bus receiving interfaces, one 1394B bus transmitting interface, one data cross transmission interface and a time synchronization interface.

[0063] Channel B is designed with an FPGA circuit unit, four 1394B bus receiving interfaces, one 1394B bus transmitting interface, one FC transmitting interface, one data cross transmission interface and a time synchronization interface.

[0064] An intelligent maintenance unit for the flight control data acquisition computer was designed based on DSP, which realized the functions of online maintenance, online upgrade, and autonomous monitoring of the flight control data acquisition computer.

[0065] To ensure the independence of the 4-redundant 1394 interface and prevent the spread of faults, the physical layer and PHY layer of the 4-redundant 1394 interface are designed and powered independently. To ensure the independence of the dual-channel FPGA, each channel is implemented with an independent FPGA chip and uses an independent power supply. Figure 2 As shown. The single-channel power conversion circuit is as follows Figure 3 shown.

[0066] A timing strategy is designed to meet the dual-channel timing requirements of the flight tube data acquisition computer. After the flight tube data acquisition computer is powered on, the first FPGA and the second FPGA respectively perform timing according to the clock of their own channels, with channel A as the master and channel B as the backup. The first FPGA periodically sends the time information of channel A to the second FPGA of channel B, and the second FPGA calibrates the time of channel B according to the received time; if the second FPGA does not receive the time stamp information sent by the first FPGA of channel A within a fixed time, the master and backup channels are swapped, the second FPGA stops receiving the time of channel A, and sends the time of channel B to the first FPGA of channel A. After the first FPGA receives the clock information sent by the second FPGA of channel B, it stops sending clock information to the second FPGA of channel B, and uses the clock information sent by the second FPGA of channel B to calibrate the clock of channel A. The dual-channel FPGA timing strategy is as follows Figure 4 shown.

[0067] In summary, the present application proposes a new fault-tolerant structure for the flight control data acquisition computer. Through independent power supply design, dual-channel fault-tolerant design, data cross-transmission and other methods, the flight control data acquisition computer realizes a dual-channel design architecture and has a certain fault-tolerant capability. When a certain channel data processing circuit (FPGA circuit) fails, the flight control data will not be completely lost. The risk of the flight control data acquisition computer losing all flight control data due to the failure of part of the data processing circuit (FPGA circuit) is reduced. The availability of the flight control data acquisition computer is improved, and the reliability of the data forwarding record of the flight control system is improved.

[0068] The above description is merely a specific embodiment of the present disclosure, but the scope of protection of the present disclosure is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in this disclosure should be included in the scope of protection of the present disclosure. Therefore, the scope of protection of the present disclosure should be based on the scope of protection of the claims.

Claims

1. A flight control data acquisition computer with a fault-tolerant architecture, characterized in that: The flight control data acquisition computer includes at least two acquisition channels; the acquisition channels include a processing unit, a multi-channel bus receiving interface, a bus sending interface, a data cross transmission interface and a time synchronization interface; Each of the bus interfaces collects flight control data from the flight control computer and communicates with the processing unit; The processing unit is used to process the flight control data and process the flight control data into data packets that can be received by a flight parameter recorder and a protection recording device; The bus sending interface communicates with the processing unit and is used to send the data packet; The data packets are cross-transmitted between the acquisition channels based on the data cross-transmission interfaces; Cross-transmitting time stamp information between the acquisition channels based on the timing interfaces; Each of the acquisition channels communicates with the protection recording device; at least one of the acquisition channels communicates with the flight parameter recorder; The flight control data acquisition computer further includes an intelligent maintenance unit; the intelligent maintenance unit is connected to each of the acquisition channels and is used to regularly acquire the working status of each of the acquisition channels, initialize each of the acquisition channels, and perform online maintenance on each of the acquisition channels; The flight tube data acquisition computer includes two acquisition channels; the two acquisition channels are channel A and channel B; Channel A is provided with a first FPGA, four 1394B bus receiving interfaces, one 1394B bus transmitting interface, one data cross transmission interface, and a time synchronization interface; channel B is provided with a second FPGA, four 1394B bus receiving interfaces, one 1394B bus transmitting interface, one FC transmitting interface, one data cross transmission interface, and a time synchronization interface; wherein: VMC_A is connected to the two 1394 receive interfaces of channel A through 1394B_A_1 and 1394B_A_2. VMC_B is connected to the two 1394 receive interfaces of channel A through 1394B_B_1 and 1394B_B_2. The protection recording device is connected to the one 1394 transmit interface of channel A through 1394B_1. VMC_C is connected to the two 1394 receive interfaces of channel B through 1394B_C_1 and 1394B_C_2. VMC_D is connected to the two 1394 receive interfaces of channel B through 1394B_D_1 and 1394B_D_2. The protection recording device is connected to the one 1394 transmit interface of channel B through 1394B_2. The flight parameter recorder is connected to the one FC transmit interface of channel B through the FC bus. Channel A and channel B are connected through the Aurora interface to achieve cross-channel data transmission. The power supply between the acquisition channels is independent.

2. The flight control data acquisition computer with a fault-tolerant architecture according to claim 1, characterized in that: The bus receiving interfaces are hardware independent; the data cross transmission interface is an Aurora interface.

3. The flight control data acquisition computer with a fault-tolerant architecture according to claim 2, characterized in that: The processing unit processes the flight control data in the following manner: integrating, filtering and sending the flight control data.

4. The flight control data acquisition computer with a fault-tolerant architecture according to claim 3, characterized in that: The intelligent maintenance unit is integrated on the DSP.

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