Display panel

Abstract

This invention provides a display panel in which sub-pixels include connection transistors electrically connected to the gates of driving transistors. Each connection transistor includes a first channel portion, a second channel portion, and a first electrical connection portion connecting the first channel portion and the second channel portion. Two adjacent sub-pixels in the same row are mirror-mounted. The first electrical connection portions of multiple adjacent sub-pixels in the same row are alternately arranged with a first spacing and a second spacing. Two sub-pixels are spaced apart between adjacent overlapping portions of each variable signal line, and each overlapping portion at least partially overlaps with the first electrical connection portions of the two sub-pixels arranged with the first spacing to form two capacitors. This design achieves a solution to improve low-frequency flicker by using variable signals transmitted through variable signal lines and capacitors, while saving layout space.

Description

Technical Field

[0001] This invention relates to the field of display technology, and more specifically to a display panel. Background Technology

[0002] LTPO (Low Temperature Polycrystalline Oxide) backplanes, which combine low temperature polycrystalline silicon transistor technology and oxide transistor technology, can be used to improve the low-frequency flicker problem of display panels. However, the structure and manufacturing process of LTPO backplanes are more complex and the manufacturing cost is also higher. Summary of the Invention

[0003] This invention provides a display panel that can improve the problem of low-frequency flicker in display panels.

[0004] This invention provides a display panel including multiple sub-pixels and multiple variable signal lines. Each sub-pixel includes a light-emitting device and a pixel driving circuit. The pixel driving circuit includes a driving transistor and a connecting transistor. The driving transistor and the light-emitting device are connected in series between a first power line and a second power line. The connecting transistor is electrically connected to the gate of the driving transistor. The multiple variable signal lines are configured to transmit variable signals, and each variable signal line includes multiple overlapping portions. The connecting transistor includes a first active layer. The first active layer includes a first channel portion, a second channel portion, and a first electrical connection portion connecting the first channel portion and the second channel portion. Two adjacent sub-pixels in the same row are mirrored. The first electrical connection portions of the multiple adjacent sub-pixels in the same row are alternately arranged with a first spacing and a second spacing, where the first spacing is smaller than the second spacing. Two sub-pixels are spaced apart between adjacent overlapping portions of each variable signal line, and each overlapping portion at least partially overlaps with the first electrical connection portions of the two sub-pixels arranged with the first spacing to form two capacitors.

[0005] This invention provides a display panel in which sub-pixels include connection transistors electrically connected to the gates of driving transistors. Each connection transistor includes a first channel portion, a second channel portion, and a first electrical connection portion connecting the first channel portion and the second channel portion. Two adjacent sub-pixels in the same row are mirror-mounted. The first electrical connection portions of multiple adjacent sub-pixels in the same row are alternately arranged with a first spacing and a second spacing. Two sub-pixels are spaced apart between adjacent overlapping portions of each variable signal line, and each overlapping portion at least partially overlaps with the first electrical connection portions of the two sub-pixels arranged with the first spacing to form two capacitors. This design achieves a solution to improve low-frequency flicker by using variable signals transmitted through variable signal lines and capacitors, while saving layout space. Attached Figure Description

[0006] Figures 1A-1B This is a schematic diagram of the sub-pixel structure provided in an embodiment of the present invention;

[0007] Figure 2 This is a timing diagram provided in an embodiment of the present invention;

[0008] Figure 3 This is a schematic diagram of display brightness changes provided in an embodiment of the present invention;

[0009] Figures 4A-4B This is a schematic diagram of the film structure of a sub-pixel provided in an embodiment of the present invention;

[0010] Figures 5A-5B This is a magnified view of the area where the variable signal line overlaps with the first electrical connection.

[0011] Figure 5C It is along Figure 5A or Figure 5B A sectional view cut by p-p' in the middle;

[0012] Figure 5D It is along Figure 5A or Figure 5B A cross-sectional view cut by z-z' in the middle;

[0013] Figures 6A-6B This is a schematic diagram of the active layer structure provided in an embodiment of the present invention;

[0014] Figures 7A-7B This is a schematic diagram of the structure of the first conductive layer provided in an embodiment of the present invention;

[0015] Figures 8A-8B This is a schematic diagram of the structure of the second conductive layer provided in an embodiment of the present invention;

[0016] Figures 9A-9B This is a schematic diagram of the structure of the third conductive layer provided in an embodiment of the present invention;

[0017] Figure 10 This is a schematic diagram of the structure of the fourth conductive layer provided in an embodiment of the present invention. Detailed Implementation

[0018] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. The described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0019] Specifically, such as Figures 1A-1B This is a schematic diagram of the structure of a sub-pixel provided in an embodiment of the present invention. The present invention provides a display panel including multiple signal lines and multiple sub-pixels Px.

[0020] The multiple signal lines include multiple scan lines, multiple data lines DL, multiple light emission control lines EML, multiple reset lines, and at least one variable signal line EML1.

[0021] The multiple scan lines include multiple first scan lines and multiple second scan lines. The first scan lines are used to transmit a first scan signal S1, and the multiple first scan lines include multiple first sub-scan lines SL11 and multiple second sub-scan lines SL12. The effective pulse duration of the first scan signal transmitted by the first sub-scan line SL11 precedes the effective pulse duration of the first scan signal transmitted by the second sub-scan line SL12. The second scan lines are used to transmit a second scan signal S2, and the multiple second scan lines SL2 include multiple third sub-scan lines SL21 and multiple fourth sub-scan lines SL22. Optionally, the frequency of the first scan signal S1 is lower than the frequency of the second scan signal S2. Optionally, the effective pulse of the first scan signal S1 is located within a write frame of a display cycle, and the effective pulse of the second scan signal S2 is located within both the write frame and the hold frame of a display cycle. Wherein, when a display cycle includes a hold frame, the display panel employs a low refresh rate driving method.

[0022] Optionally, the display panel further includes multiple cascaded first gating drive circuits, multiple cascaded second gating drive circuits, and multiple cascaded third gating drive circuits to provide multiple first scan signals S1 to multiple first scan lines, multiple second scan signals S2 to multiple second scan lines, and light emission control signals to multiple light emission control lines EML, respectively. Optionally, the display panel further includes multiple cascaded fourth gating drive circuits to provide variable signals to the variable signal line EML1. Optionally, the variable signal line EML1 can also be electrically connected to the driver chip to provide variable signals through the driver chip.

[0023] Please continue reading. Figures 1A-1B Each sub-pixel Px includes a light-emitting device D and a pixel driving circuit. Optionally, the light-emitting device D includes an organic light-emitting diode, a sub-millimeter light-emitting diode, a micro light-emitting diode, etc. The pixel driving circuit includes a driving transistor T1, a connecting transistor, and a capacitor Co.

[0024] The source and drain of the driving transistor T1 are connected in series with the light-emitting device D between the first power line VDD and the second power line VSS. The driving transistor T1 is used to generate a driving current to drive the light-emitting device D to emit light based on the data signal transmitted to the gate of the driving transistor T1. The write frame includes the stage in which the data signal is transmitted to the gate of the driving transistor T1, while the hold frame does not include the stage in which the data signal is transmitted to the gate of the driving transistor T1.

[0025] The connecting transistor is electrically connected to the gate of the driving transistor T1. Optionally, depending on the application of the connecting transistor, the connection positions of the source and drain of the connecting transistor may differ. For example, if the connecting transistor is used to reset the gate potential of the driving transistor T1, then the source and drain of the connecting transistor are electrically connected between the gate of the driving transistor T1 and the first reset line VL1. If the connecting transistor is used to detect and compensate the threshold voltage of the driving transistor T1, then the source and drain of the connecting transistor are electrically connected between the gate of the driving transistor T1 and one of the source and drain of the driving transistor T1.

[0026] Optionally, the connecting transistor includes a first sub-transistor TL1 and a second sub-transistor TL2 connected in series, with the first sub-transistor TL1 and the second sub-transistor TL2 having a first connection node A. One of the source and drain of the first sub-transistor TL1 is electrically connected to the gate of the driving transistor T1, and the other of the source and drain of the first sub-transistor TL1 is electrically connected to one of the source and drain of the second sub-transistor TL2 through the first connection node A. The gates of both the first sub-transistor TL1 and the second sub-transistor TL2 are electrically connected to a first scan line. If the connecting transistor is used to reset the gate potential of the driving transistor T1, then the other of the source and drain of the second sub-transistor TL2 is electrically connected to the first reset line VL1, and the gates of the first sub-transistor TL1 and the second sub-transistor TL2 are electrically connected to the first sub-scan line SL11, as shown below. Figure 1A As shown. If the connecting transistor is used to detect and compensate the threshold voltage of the driving transistor T1, then the other of the source and drain of the second sub-transistor TL2 is electrically connected to one of the source and drain of the driving transistor T1, and the gate of the first sub-transistor TL1 and the gate of the second sub-transistor TL2 are electrically connected to the second sub-scan line SL12, as shown. Figure 1B As shown.

[0027] Capacitor Co is connected in series between the variable signal line EML1 and the first connection node A, and is used to couple the potential of connection node A according to the variable signal EM1 transmitted by the variable signal line EML1, so as to change the difference between the gate potential of connection node A and the driving transistor T1.

[0028] Please continue reading. Figures 1A-1B The pixel driving circuit also includes a data transistor T2, a light-emitting transistor, an initial transistor T5, and a storage capacitor Cst.

[0029] The source and drain of data transistor T2 are electrically connected between the other of the source and drain of driving transistor T1 and the data line DL, and the gate of data transistor T2 is electrically connected to the third sub-scan line SL21. Data transistor T2 is used to transmit the data signal transmitted by data line DL to the gate of driving transistor T1 according to the second scan signal S2 transmitted by the corresponding third sub-scan line SL21, so that the gate of driving transistor T1 has a first potential.

[0030] During the light-emitting phase in which the driving transistor T1 drives the light-emitting device D to emit light, the variable signal EM1 has at least one transition from the second potential V2 to the third potential V3. The first potential is located between the second potential V2 and the third potential V3.

[0031] The light-emitting transistor (LED), driving transistor T1, and light-emitting device D are connected in series between the first power line VDD and the second power line VSS. Optionally, the LED includes a first switching transistor T3 and a second switching transistor T4. The source and drain of the first switching transistor T3 are electrically connected between the other of the source and drain of the driving transistor T1 and the first power line VDD. The source and drain of the second switching transistor T4 are electrically connected between one of the source and drain of the driving transistor T1 and a second connection node B. The gates of both the first switching transistor T3 and the second switching transistor T4 are electrically connected to the light-emitting control line EML. The LED is used to drive the light-emitting device D to emit light according to the light-emitting control signal EM transmitted by the light-emitting control line EML. Optionally, the gates of LEDs of multiple sub-pixels located in the same row are electrically connected to the same light-emitting control line EML.

[0032] The source and drain of the initial transistor T5 are electrically connected between the second reset line VL2 and the second connection node B, and the gate of the initial transistor T5 is electrically connected to the fourth sub-scan line SL22. The initial transistor T5 is used to reset the potential at the second connection node B according to the second reset signal transmitted through the second reset line VL2. The light-emitting device D is connected in series between the second connection node B and the second power supply line VSS.

[0033] The storage capacitor Cst is connected in series between the first power supply line VDD and the gate of the driving transistor T1 to maintain the gate potential of the driving transistor T1.

[0034] Please continue reading. Figure 1AThe pixel driving circuit also includes a compensation transistor. The source and drain of the compensation transistor are electrically connected between the gate of the driving transistor T1 and one of the source and drain of the driving transistor T1. The gate of the compensation transistor is electrically connected to the second sub-scan line SL12. The compensation transistor is used to detect and compensate the threshold voltage of the driving transistor T1 according to the first scan signal transmitted by the second sub-scan line SL12. Optionally, the compensation transistor may include a first sub-compensation transistor Tc1 and a second sub-compensation transistor Tc2 connected in series. Optionally, the compensation transistor may include silicon semiconductor material or oxide semiconductor material.

[0035] Please continue reading. Figure 1B The pixel driving circuit also includes a reset transistor. The source and drain of the reset transistor are electrically connected between the gate of the driving transistor T1 and the first reset line VL1. The gate of the reset transistor is electrically connected to the first sub-scan line SL11. The reset transistor is used to reset the gate potential of the driving transistor T1 according to the first scan signal transmitted by the first sub-scan line SL11. Optionally, the reset transistor may include a first sub-reset transistor Ti1 and a second sub-reset transistor Ti2 connected in series. Optionally, the reset transistor may include silicon semiconductor material or oxide semiconductor material.

[0036] Optionally, each transistor includes a silicon semiconductor or an oxide semiconductor. The silicon semiconductor material includes polycrystalline silicon, monocrystalline silicon, etc.; the oxide semiconductor material includes indium gallium zinc oxide, indium gallium tin oxide, or indium gallium zinc tin oxide, etc.

[0037] like Figure 2 This is a timing diagram provided in an embodiment of the present invention. Taking the transistors included in each sub-pixel as P-type transistors, and the pixel driving circuit driving the light-emitting device D in the nth row to emit light as an example, for example... Figure 1A The working principle of the sub-pixels shown is explained. Here, n is greater than or equal to 1; when driving the light-emitting device D in the nth row, the first sub-scan line SL11, electrically connected to the gate of the first sub-transistor TL1 and the gate of the second sub-transistor TL2, transmits the first scan signal S1(n-1) of the (n-1)th level; the second sub-scan line SL12, electrically connected to the gate of the first sub-compensation transistor Tc1 and the gate of the second sub-compensation transistor Tc2, transmits the first scan signal S1(n) of the nth level; the third sub-scan line SL21, electrically connected to the gate of the data transistor T2, transmits the second scan signal S2(n) of the nth level; the light-emitting control line EML, electrically connected to the gate of the first switching transistor T3 and the gate of the second switching transistor T4, transmits the light-emitting control signal EM(n) of the nth level; and the fourth sub-scan line SL22, electrically connected to the gate of the initial transistor T5, transmits the second scan signal S2(n+1) of the (n+1)th level.

[0038] During the gate reset phase t1, the first scan signal S1(n-1) transmitted by the first sub-scan line SL11 is valid, the first sub-transistor TL1 and the second sub-transistor TL2 are turned on, and the first reset signal transmitted by the first reset line VL1 is transmitted to the gate of the driving transistor T1 through the second sub-transistor TL2 and the first sub-transistor TL1 to reset the gate potential of the driving transistor T1.

[0039] During the data writing phase t2, the first scan signal S1(n) transmitted by the second sub-scan line SL12 and the second scan signal S2(n) transmitted by the third sub-scan line SL21 are valid. The first sub-compensation transistor Tc1, the second sub-compensation transistor Tc2 and the data transistor T2 are turned on. The data signal transmitted by the data line DL is transmitted to the gate of the driving transistor T1 through the data transistor T2, the second sub-compensation transistor Tc2 and the first sub-compensation transistor Tc1, so that the gate of the driving transistor T1 has a first potential.

[0040] During the anode reset phase t3, the second scan signal S2(n+1) transmitted by the fourth sub-scan line SL22 is valid, the initial transistor T5 is turned on, and the second reset signal transmitted by the second reset line VL2 is transmitted to the second connection node B via the initial transistor T5 to reset the anode potential of the light-emitting device D.

[0041] During the light-emitting stage t4, the light-emitting control signal EM(n) transmitted by the light-emitting control line EML is valid. The first switching transistor T3 and the second switching transistor T4 turn on in response to the light-emitting control signal EM(n), and the driving transistor T1 generates the driving current to drive the light-emitting device D to emit light.

[0042] Optionally, the frequency of the light emission control signal EM(n) is greater than the frequency of the first scan signal S1(n) to improve the low-frequency flicker problem by continuously changing the brightness of the light-emitting device D.

[0043] Figure 1B In the sub-pixels shown, the first sub-scan line SL11, which is electrically connected to the gate of the first sub-reset transistor Ti1 and the gate of the second sub-reset transistor Ti2, transmits the first scan signal S1(n-1) of the (n-1)th level, and the second sub-scan line SL12, which is electrically connected to the gate of the first sub-transistor TL1 and the gate of the second sub-transistor TL2, transmits the first scan signal S1(n) of the nth level. Figure 1B The working principle of the sub-pixel shown is similar to Figure 1A The working principle of the sub-pixels shown is similar, and will not be repeated here.

[0044] When driving the display using a low frequency, a display cycle includes at least one hold frame HF. Therefore, the light-emitting phase t4 can continue from the write frame WF to the hold frame HF; the second scan signal S2 has an effective pulse within the hold frame HF, which can correct the gate potential of the driving transistor T1 and the anode potential of the light-emitting device D, compensating for the brightness changes of the light-emitting device D.

[0045] Optionally, the transition time of the variable signal EM1(n) is located after the data signal is transmitted to the gate of the driving transistor T1. To avoid the change in brightness of the light-emitting device D caused by the transition of the variable signal EM1(n) being perceptible to the human eye, the transition time of the variable signal EM1(n) is located within the invalid pulse duration of the light-emitting control signal EM(n), or the transition time of the variable signal EM1(n) is the same as the transition time of the light-emitting control signal EM(n). Optionally, the first potential is greater than the third potential V3 and less than the second potential V2.

[0046] The duration for which the variable signal EM1(n) maintains the second potential V2 is the first time period t11, and the duration for which the variable signal EM1(n) maintains the third potential V3 is the second time period t12. During the first time period t11 of writing frame WF, the gate of driving transistor T1 is mainly affected by the first reset signal and the data signal. Whether the variable signal EM1(n) is at the third potential V3 or the second potential V2 does not affect the gate potential of driving transistor T1. After the variable signal EM1(n) jumps during the light emission stage t4, the potential of the first connection node A changes accordingly due to coupling, thereby causing the gate potential of driving transistor T1 to change accordingly. Taking the example that each transistor of the sub-pixel is still a P-type transistor, when the variable signal EM1(n) jumps from the third potential V3 to the second potential V2, the potential of the first connection node A is coupled up to a level greater than the gate potential of driving transistor T1 through the capacitor Co. The first connection node A leaks current to the gate of driving transistor T1, causing the gate potential of driving transistor T1 to increase accordingly, thereby reducing the driving current and causing a decrease in the brightness of light-emitting device D. When the variable signal EM1(n) transitions from the second potential V2 to the third potential V3, the potential of the first connection node A is coupled down to a level lower than the gate potential of the driving transistor T1 through the capacitor Co. This causes leakage current from the gate of the driving transistor T1 to the first connection node A, resulting in a corresponding decrease in the gate potential of the driving transistor T1. Consequently, the driving current increases, leading to an increase in the brightness of the light-emitting device D. Therefore, the transition of the variable signal EM1(n) can cause a change in the brightness of the light-emitting device D. By continuously transitioning the variable signal EM1(n) between the second potential V2 and the third potential V3, the average value of the gate potential of the driving transistor T1 can be kept essentially stable at the first potential.

[0047] Optionally, the duration of the first time period t11 may be equal to or unequal to the duration of the second time period t12. The duration for which the variable signal EM1(n) maintains the second potential V2 each time may be equal or unequal. The duration for which the variable signal EM1(n) maintains the third potential V3 each time may also be equal or unequal.

[0048] This application utilizes the relatively long light-emitting phase t4 that inevitably exists during low-frequency driving, so that the potential of the first connection node A can be varied within the light-emitting phase t4 through the action of capacitor Co. This integrates the influence of the second potential V2 and the third potential V3 on the gate potential of the driving transistor T1, so that the average value of the gate potential of the driving transistor T1 is basically stable at the first potential. This allows the light-emitting device D to maintain its initial light-emitting brightness, which can improve the flickering problem in low-frequency driving and thus improve the display quality.

[0049] like Figure 3 This is a schematic diagram of display brightness variation provided in an embodiment of the present invention; wherein, L1 represents the sub-pixel used in this application ( Figure 1A and Figure 1B The curves showing the display brightness variation of the sub-pixel (L1) as a function of the gate potential of the driving transistor T1 are shown below. L2 represents the display brightness variation curve as a function of the gate potential of the driving transistor obtained using a sub-pixel in the prior art (the prior art sub-pixel has no capacitor Co). A comparison shows that within one display cycle (1 Display), the light-emitting device D using the sub-pixel of this application changes its brightness multiple times, but the amplitude of the brightness variation of the light-emitting device D is significantly smaller than the brightness variation amplitude of the light-emitting device in the prior art sub-pixel.

[0050] Furthermore, even if the number of times the second potential V2 is greater than the gate potential of the driving transistor T1 is not equal to the number of times the third potential V3 is less than the gate potential of the driving transistor T1, it only manifests as a difference in the number of brightness change switching in L1. From the perspective of the duration of one display cycle (1 Display), the difference in the number of brightness change switching has little impact on the overall brightness change.

[0051] Figure 4A Is with Figure 1A A schematic diagram of the film structure corresponding to the pixel driving circuit shown; Figure 4B Is with Figure 1B A schematic diagram of the film structure corresponding to the pixel driving circuit is shown. Figure 5A yes Figure 4A A magnified view of the variable signal line overlapping with the first electrical connection in the membrane structure diagram shown; Figure 5B yes Figure 4B A magnified view of the variable signal line overlapping with the first electrical connection in the membrane structure diagram shown; Figure 6A It corresponds Figure 4A A schematic diagram of the active layer in the membrane structure diagram shown; Figure 6B It corresponds Figure 4B The diagram shows a schematic of the active layer in the membrane structure diagram.

[0052] The connecting transistor includes a first active layer pc, which includes a first channel portion Ch1, a second channel portion Ch2, and a first electrical connection portion ec connecting the first channel portion Ch1 and the second channel portion Ch2. Two adjacent sub-pixels Px in the same row are mirrored, and the first electrical connection portions ec of multiple adjacent sub-pixels Px in the same row are alternately arranged with a first spacing P1 and a second spacing P2, where the first spacing P1 is smaller than the second spacing P2.

[0053] Optionally, the first active layer pc includes a first sub-active portion and a second sub-active portion; the first sub-transistor TL1 includes a first sub-active portion, which includes a first channel portion Ch1; the second sub-transistor TL2 includes a second sub-active portion, which includes a second channel portion Ch2; and the first electrical connection portion ec serves as a first connection node A. STL2 and DTL2 represent the first and second terminals of the second sub-active portion, respectively.

[0054] Optionally, the driving transistor T1 includes a second active layer, the data transistor T2 includes a third active layer, the first switching transistor T3 includes a fourth active layer, the second switching transistor T4 includes a fifth active layer, and the initial transistor T5 includes a sixth active layer. The first terminal ST1 of the second active layer is connected to the second terminal DT2 of the third active layer and the second terminal DT3 of the fourth active layer; the second terminal DT1 of the second active layer is connected to the first terminal ST4 of the fifth active layer; and the second terminal DT4 of the fifth active layer is connected to the first terminal ST5 of the sixth active layer.

[0055] like Figure 6A The first sub-compensation transistor Tc1 includes a seventh active layer, and the second sub-compensation transistor Tc2 includes an eighth active layer. The first terminal STc1 of the seventh active layer is connected to the second terminal DTc2 of the eighth active layer, and the first terminal STc2 of the eighth active layer is connected to the second terminal DT1 of the second active layer.

[0056] like Figure 6B The first sub-reset transistor Ti1 includes a ninth active layer, and the second sub-reset transistor Ti2 includes a tenth active layer. The second terminal DTi1 of the ninth active layer is connected to the first terminal STi2 of the tenth active layer. DTi2 represents the second terminal of the tenth active layer.

[0057] Optionally, the first active layer (pc) is co-layered with each of the other active layers to fabricate the display panel using existing manufacturing processes. Optionally, the first active layer (pc) comprises a silicon semiconductor material or an oxide semiconductor material. Silicon semiconductor materials include monocrystalline silicon, polycrystalline silicon, etc.; oxide semiconductor materials may include indium gallium zinc oxide, indium gallium tin oxide, or indium gallium zinc tin oxide, etc. Optionally, the first active layer (pc) is fabricated using a low-temperature polycrystalline silicon process.

[0058] Optionally, such as Figures 5C to 5D The first active layer pc is located on the substrate 100. Optionally, the substrate 100 includes a rigid substrate and a flexible substrate. For example, the substrate 100 includes glass, polyimide, quartz, etc. Optionally, a buffer layer 100a is also provided on the substrate 100.

[0059] Please continue reading. Figures 4A-4B and Figures 5A-5B Each variable signal line EML1 includes multiple overlapping portions EML11. Two sub-pixels Px are spaced between two adjacent overlapping portions EML11 of each variable signal line EML1. Each overlapping portion EML11 and the first electrical connection portions ec of the two sub-pixels arranged at a first spacing P1 at least partially overlap to form two capacitors Co. This saves layout space and helps to achieve a solution to improve the low-frequency flicker problem.

[0060] Optionally, to reduce interference between the variable signal line EML1 and the scan line, light emission control line, and reset line, each variable signal line EML1 further includes a routing portion EML13 and multiple connecting portions EML12. The routing portion EML13 extends along the row direction x, and each connecting portion EML12 extends along the column direction y. Each connecting portion EML12 is electrically connected between an overlapping portion EML11 and the routing portion EML13, so that multiple overlapping portions EML11 are electrically connected to the routing portion EML13 through multiple connecting portions EML12.

[0061] Each variable signal line EML1 has two adjacent connection portions EML12 spaced between two sub-pixels Px, and each connection portion EML12 is located between the first electrical connection portions ec arranged with a first spacing P1 between the two sub-pixels Px, thereby reducing the winding distance of the connection portion EML12, so as to reduce the probability of the connection portion EML12 overlapping with other signal traces while realizing the electrical connection between the trace portion EML13 and the overlapping portion EML11.

[0062] Optionally, the connecting portion EML12 and the overlapping portion EML11 are on different layers to avoid the connecting portion EML12 crossing with other signal traces, which could cause short circuits or generate parasitic capacitance, affecting the normal operation of the pixel driving circuit. Optionally, the trace portion EML13 and the overlapping portion EML11 are on the same layer.

[0063] Optionally, such as Figures 5C to 5D The display panel includes a second conductive layer 102 located on a first active layer pc, the second conductive layer 102 including a trace portion EML 13 and an overlapping portion EML 11. Optionally, the display panel includes a third conductive layer 103 located on the second conductive layer 102, the third conductive layer 103 including a connection portion EML 12. Optionally, the display panel further includes a first conductive layer located between the first active layer pc and the second conductive layer, the first conductive layer including the gate of a driving transistor T1. Optionally, a first insulating layer 1001 is located between the first active layer pc and the first conductive layer, a second insulating layer 1002 is located between the first conductive layer and the second conductive layer 102, and an interlayer dielectric layer 1003 is located between the second conductive layer 102 and the third conductive layer 103.

[0064] Optionally, the first conductive layer, the second conductive layer 102, and the third conductive layer 103 include at least one of molybdenum (Mo), aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), calcium (Ca), titanium (Ti), tantalum (Ta), tungsten (W), and copper (Cu). Optionally, the first conductive layer, the second conductive layer 102, or the third conductive layer 103 can be a single-layer film structure or a stacked structure such as Ti / Al / Ti, Mo / Al / Mo, Mo / AlGe / Mo, Cu / Mo, Cu / Ti, Cu / MoTi, or Cu / MoNb. Optionally, the first insulating layer 1001 and the second insulating layer 1002 include silicon oxide, silicon nitride, silicon nitride, aluminum oxide, tantalum oxide, hafnium oxide, zirconium oxide, and titanium oxide.

[0065] Please continue reading. Figures 4A-4B and Figures 5A-5B The gates of the multiple sub-pixels px located in the same row are electrically connected to the corresponding first scan line; the first scan line electrically connected to the gates of the multiple sub-pixels px located in the same row includes multiple first gate portions, each first gate portion including a first sub-gate portion SL11b1 and a second sub-gate portion SL11b2 disposed opposite to each other, and a third sub-gate portion SL11b3 connected between the first sub-gate portion SL11b1 and the second sub-gate portion SL11b2.

[0066] The first sub-gate portion SL11b1 and the second sub-gate portion SL11b2 both extend along the column direction y, and SL11b3 extends along the row direction x. The first sub-gate portion SL11b1 and the second sub-gate portion SL11b2 overlap with the two first channel portions Ch1 of the sub-pixel Px that are electrically connected to the first electrical connection portions ec that are adjacent to each other with a first spacing P1. The third sub-gate portion SL11b3 overlaps with the two second channel portions Ch2 of the two sub-pixels Px that are electrically connected to the first electrical connection portions ec that are adjacent to each other with a first spacing P1. Each overlapping portion EML11 is located between the first sub-gate portion SL11b1 and the second sub-gate portion SL11b2 of the corresponding first gate portion.

[0067] Depending on the position of the first active layer pc, the first scan line electrically connected to the gate of the connecting transistors of the multiple sub-pixels px located in the same row will also be different, and the layout of the variable signal line EML1 will also be different.

[0068] Specifically, such as Figures 7A-7B This is a schematic diagram of the structure of the first conductive layer provided in an embodiment of the present invention. Figures 8A-8B This is a schematic diagram of the structure of the second conductive layer provided in an embodiment of the present invention. Figures 9A-9B This is a schematic diagram of the structure of the third conductive layer provided in an embodiment of the present invention.

[0069] Please continue reading. Figure 4A , Figure 5A , Figure 6A , Figure 7A , Figure 8A and Figure 9A The first sub-scan line SL11 is electrically connected to the gates of the connection transistors of a plurality of sub-pixels Px located in the same row. Each first sub-scan line SL11 includes a first gate portion and a plurality of first sub-routes SL11a. Each first sub-route SL11a extends along the row direction x, and both ends of each first sub-route SL11a are electrically connected to the junction of the first sub-gate portion SL11b1 and the third sub-gate portion SL11b3, and the junction of the second sub-gate portion SL11b2 and the third sub-gate portion SL11b3, respectively.

[0070] Each connecting portion EML12 overlaps at least partially with the third sub-gate portion SL11b3 of the corresponding first gate portion. The trace portion EML13 and the overlapping portion EML11, which are electrically connected through the connecting portion EML12, are located on opposite sides of the third sub-gate portion SL11b3, so as to reduce the degree of mutual interference between the trace portion EML13 and the reset line and scan line, and reduce the design complexity.

[0071] To reduce the impact of the parasitic capacitance generated by the connecting portion EML12 and the first gate portion on the sub-pixel, in the thickness direction of the display panel, the distance between each connecting portion EML12 and the corresponding third sub-gate portion SL11b3 is greater than the distance between each connecting portion EML12 and the corresponding overlapping portion EML11, so that the capacitance of the parasitic capacitance formed by the connecting portion EML12 and the third sub-gate portion SL11b3 is significantly smaller than the capacitance of capacitor Co.

[0072] Optionally, each second sub-scan line SL12 includes at least one second sub-trace portion SL12a and a plurality of second gate portions. The second sub-trace portion SL12a extends along the row direction x, and the second sub-trace portion SL12a and the plurality of second gate portions are electrically connected. Optionally, the second gate portion includes a fourth sub-gate portion SL12b1, a fifth sub-gate portion SL12b2, and a sixth sub-gate portion SL12b3. The fourth sub-gate portion SL12b1 extends along the column direction y, the fifth sub-gate portion SL12b2 is parallel to and spaced apart from the fourth sub-gate portion SL12b1, and the sixth sub-gate portion SL12b3 extends along the row direction x, with its two ends connected to the fourth sub-gate portion SL12b1 and the fifth sub-gate portion SL12b2, respectively. The fourth sub-gate portion SL12b1 and the fifth sub-gate portion SL12b2 overlap with the eighth active layer corresponding to the two adjacent pixel driving circuits, respectively, and serve as the gates of the second sub-compensation transistor Tc2 in the two adjacent pixel driving circuits. The sixth sub-gate portion SL12b3 overlaps with the seventh active layer corresponding to the two adjacent pixel driving circuits, and serves as the gate of the first sub-compensation transistor Tc1 in the two adjacent pixel driving circuits.

[0073] Optionally, each second sub-scan line SL12 further includes multiple gate connection portions. Each gate connection portion includes a first sub-gate connection portion SL12c1 and a second sub-gate connection portion SL12c2. The first end of the first sub-gate connection portion SL12c1 and the first end of the second sub-gate connection portion SL12c2 of the same gate connection portion are connected to and electrically connected to the second sub-trace portion SL12a. The second end of the first sub-gate connection portion SL12c1 and the second end of the second sub-gate connection portion SL12c2 of the same gate connection portion are respectively electrically connected to the same second gate portion. Optionally, the second end of the first sub-gate connection portion SL12c1 is electrically connected to the junction of the fourth sub-gate portion SL12b1 and the sixth sub-gate portion SL12b3, and the second end of the second sub-gate connection portion SL12c2 is electrically connected to the junction of the fifth sub-gate portion SL12b2 and the sixth sub-gate portion SL12b3.

[0074] Optionally, the first sub-gate connection portion SL12c1 and the second sub-gate connection portion SL12c2 are symmetrical about the connection portion EML12, so that the first scan signal transmitted to the two-pixel driving circuit via the first sub-gate connection portion SL12c1 and the second sub-gate connection portion SL12c2 has similar loss.

[0075] Please continue reading. Figure 4B , Figure 5B , Figure 6B , Figure 7B , Figure 8B and Figure 9B The second sub-scan line SL12 is electrically connected to the gate of the connection transistor of a plurality of sub-pixels Px located in the same row. Each second sub-scan line SL11 includes a first gate portion, a second sub-line portion SL12a and a plurality of gate connection portions.

[0076] The second sub-routing section SL12a extends along the row direction x. Each gate connection is electrically connected between the corresponding first gate section and the second sub-routing section SL12a. Each gate connection includes a first sub-gate connection section SL12c1 and a second sub-gate connection section SL12c2 symmetrical about the connection section EML12. Specifically, the first end of the first sub-gate connection section SL12c1 and the first end of the second sub-gate connection section SL12c2 of each gate connection are connected to and electrically connected to the second sub-routing section SL12a. The second end of the first sub-gate connection section SL12c1 of each gate connection is electrically connected to the junction of the first sub-gate section SL11b1 and the third sub-gate section SL11b3 of the corresponding first gate section. The second end of the second sub-gate connection section SL12c2 of each gate connection is electrically connected to the junction of the second sub-gate section SL11b2 and the third sub-gate section SL11b3 of the corresponding first gate section.

[0077] Each connection portion EML12 is located on the side of the corresponding overlapping portion EML11 away from the third sub-gate portion SL11b3, and each trace portion EML13 is located on the side of the corresponding connection portion EML12 away from the overlapping portion EML11, so as to reduce the mutual interference between the variable signal line EML1 and the reset line and scan line.

[0078] Optionally, each light-emitting control line EML extends along the row direction x, and each light-emitting control line EML and a plurality of connection portions EML12 of a variable signal line EML1 at least partially overlap. To avoid short circuits between the light-emitting control line EML and the connection portions EML12 of the variable signal line EML1, the connection portions EML12 of the light-emitting control line EML and the variable signal line EML1 are on different layers.

[0079] Optionally, in order to reduce the parasitic capacitance between the light-emitting control line EML and the connecting part EML12, in the thickness direction of the display panel, the distance from each connecting part EML12 to the corresponding light-emitting control line EML is greater than the distance from each connecting part EML12 to the corresponding overlapping part EML11.

[0080] Optionally, each first sub-scan line SL11 includes a plurality of first sub-line portions SL11a and a plurality of second gate portions. The second gate portions include a fourth sub-gate portion SL12b1 and a fifth sub-gate portion SL12b2 extending along the column direction y, and a sixth sub-gate portion SL12b3 extending along the row direction x and connected between the fourth sub-gate portion SL12b1 and the fifth sub-gate portion SL12b2. The fourth sub-gate portion SL12b1 and the fifth sub-gate portion SL12b2 overlap with the ninth active layer corresponding to two adjacent pixel driving circuits, respectively, to serve as the gate of the first sub-reset transistor Ti1 in the two adjacent pixel driving circuits. The sixth sub-gate portion SL12b3 overlaps with the tenth active layer corresponding to two adjacent pixel driving circuits, to serve as the gate of the second sub-reset transistor Ti2 in the two adjacent pixel driving circuits. Each first sub-routing section SL11a extends along the row direction x, and the two ends of each first sub-routing section SL11a are electrically connected to the junctions of the fourth sub-gate section SL12b1 and the sixth sub-gate section SL12b3, and the junctions of the fifth sub-gate section SL12b2 and the sixth sub-gate section SL12b3, respectively.

[0081] Optionally, the first gate portion and the first sub-routing portion SL11a are on different layers, and the second gate portion and the second sub-routing portion SL12a are on different layers. Optionally, the first sub-routing portion SL11a, the second sub-routing portion SL12a, the routing portion EML13, and the overlapping portion EML11 are on the same layer. Optionally, the gate connection portion and the connection portion EML12 are on the same layer.

[0082] Optionally, the center line of the connecting portion EML12 along the column direction y coincides with the center line of the first gate portion along the column direction y and the center line of the second gate portion along the column direction y, so that the first scan signal transmitted through the first gate portion and the second gate portion to the two pixel driving circuits has similar loss.

[0083] Please continue reading. Figures 7A-7BThe first conductive layer further includes a first electrode portion E1, which overlaps with the second active layer and serves as the gate of the driving transistor T1. Optionally, the first conductive layer also includes a third sub-scan line SL21, a fourth sub-scan line SL22, and a light-emitting control line EML. The third sub-scan line SL21 extends along the row direction x and overlaps with the third active layer to serve as the gate of the data transistor T2. The fourth sub-scan line SL22 extends along the row direction x and is located on the side of the light-emitting control line EML away from the second active layer. The fourth sub-scan line SL22 overlaps with the sixth active layer to serve as the gate of the initial transistor T5. The light-emitting control line EML and the third sub-scan line SL21 are located on opposite sides of the second active layer. The light-emitting control line EML extends along the row direction x and overlaps with the fourth and fifth active layers to serve as the gates of the first switching transistor T3 and the second switching transistor T4, respectively.

[0084] like Figures 8A-8B The second conductive layer 102 includes a plurality of second electrode portions E2, each of which at least partially overlaps with two first electrode portions E1 located between two sub-pixels Px and two first electrical connection portions ec arranged at a second spacing P2, so that the storage capacitors of the two sub-pixels share a single electrode, thereby saving process steps and layout space.

[0085] Please continue reading. Figures 4A-4B , Figures 6A-6B , Figures 8A-8B and Figures 9A-9B Optionally, the reset line includes at least one first reset trace VLa, multiple second reset traces VLb, and multiple third reset traces VLc. The first reset trace VLa extends along the row direction x, overlaps with and is electrically connected to the first active connection portion cn1, thereby achieving an electrical connection between the corresponding transistor in each pixel driving circuit and the reset line. Each second reset trace VLb extends along the row direction x, and both ends of each second reset trace VLb are electrically connected to the second end DT5 of the sixth active layer corresponding to two adjacent pixel driving circuits, thereby achieving an electrical connection between the initial transistor T5 in each pixel driving circuit and the reset line. Each third reset trace VLc extends along the column direction y, and each third reset trace VLc is connected between the first reset trace VLa and a second reset trace VLb, thereby achieving an electrical connection between the first reset trace VLa and the second reset trace VLb.

[0086] Optionally, the first reset routing section VLa may be on the same layer as the routing section EML13 and the overlapping section EML11, and the second reset routing section VLb and the third reset routing section VLc may be on the same layer as the connecting section EML12.

[0087] Optionally, the third conductive layer 103 includes a first reset trace VLa, a second reset trace VLb, and a third reset trace VLc.

[0088] It should be noted that each reset line is electrically connected to the driving circuits of the two adjacent pixels along the column direction y. For example, in... Figure 4A In this circuit, the second reset line VL2 is electrically connected to the initial transistor T5 in the pixel driving circuit, and also electrically connected to the second sub-transistor TL2 in the next pixel driving circuit adjacent to the pixel driving circuit along the column direction y. Therefore, both the first reset line VL1 and the second reset line VL2 include a first reset trace VLa, a second reset trace VLb, and a third reset trace VLc.

[0089] Optionally, the first active connection portion cn1 is located on the side of the variable signal line EML1 away from the first sub-scan line SL11, so that the electrical connection between the first reset trace portion VLa and the first active connection portion cn1 is spaced apart from the electrical connection between the connection portion EML12 and the trace portion EML13, thereby reducing the degree of mutual interference between the reset line and the variable signal line EML1.

[0090] Please refer to 9A. Figure 9B The third conductive layer 103 also includes a first conductive part F1, a second conductive part F2, a third conductive part F3, a fourth conductive part F4, a fifth conductive part F5, and a sixth conductive part F6.

[0091] like Figure 9A The first conductive portion F1 is electrically connected between the first electrode portion E1 and the second terminal DTc1 of the seventh active layer and the first terminal STL1 of the first sub-active portion, thereby realizing the electrical connection between the gate of the driving transistor T1 and the first sub-transistor TL1 and the first sub-compensation transistor Tc1. Specifically, the second electrode portion E2 includes a first opening that exposes the first electrode portion E1, and the first conductive portion F1 is electrically connected to the first electrode portion E1 through the first opening and a via penetrating the interlayer dielectric layer 1003 and the second insulating layer 1002 (e.g., Figure 9A At point J1 in the diagram, two vias penetrating the interlayer dielectric layer 1003, the second insulating layer 1002, and the first insulating layer 1001 are electrically connected to the second end DTc1 of the seventh active layer and the first end STL1 of the first sub-active part, respectively (e.g., at point J1 in the diagram). Figure 9A (at locations J2 and J3 in the middle).

[0092] like Figure 9BThe first conductive portion F1 is electrically connected between the first electrode portion E1 and the first terminal STi1 of the ninth active layer and the second terminal DTL1 of the first sub-active portion, thereby realizing the electrical connection between the gate of the driving transistor T1 and the first sub-transistor TL1 and the first sub-reset transistor Ti1. Specifically, the second electrode portion E2 includes a first opening exposing the first electrode portion E1, and the first conductive portion F1 is electrically connected to the first electrode portion E1 through the first opening and a via penetrating the interlayer dielectric layer 1003 and the second insulating layer 1002 (e.g., Figure 9B At point H1 in the diagram, two vias penetrating the interlayer dielectric layer 1003, the second insulating layer 1002, and the first insulating layer 1001 are electrically connected to the second terminal DTL1 of the first sub-active part and the first terminal STi1 of the ninth active layer, respectively (e.g., at point H1 in the diagram). Figure 9B (at H2 and H3 in the middle).

[0093] like Figures 9A-9B The second conductive portion F2 overlaps with the first end ST2 of the third active layer to serve as the source of the data transistor T2. Specifically, the second conductive portion F2 is electrically connected to the first end ST2 of the third active layer through a via penetrating the interlayer dielectric layer 1003, the second insulating layer 1002, and the first insulating layer 1001 (e.g., ...). Figure 9A J4 and such Figure 9B (at point H4 in the text).

[0094] like Figure 9A The third conductive portion F3 is electrically connected between the first gate portion and the first sub-trace portion SL11a to achieve electrical connection between the first gate portion and the first sub-trace portion SL11a. Specifically, the third conductive portion F3 is electrically connected to the first sub-trace portion SL11a through a via penetrating the interlayer dielectric layer 1003 (e.g., Figure 9A At point J5 in the diagram, it is electrically connected to the first gate portion through a via penetrating the interlayer dielectric layer 1003 and the second insulating layer 1002 (e.g., at point J5 in the diagram). Figure 9A (at point J6 in the middle).

[0095] like Figure 9B The third conductive portion F3 is electrically connected between the second gate portion and the first sub-trace portion SL11a to achieve electrical connection between the second gate portion and the first sub-trace portion SL11a. Specifically, the third conductive portion F3 is electrically connected to the first sub-trace portion SL11a through a via penetrating the interlayer dielectric layer 1003 (e.g., Figure 9B At point H5 in the diagram, it is electrically connected to the second gate portion through a via penetrating the interlayer dielectric layer 1003 and the second insulating layer 1002 (e.g., at point H5 in the diagram). Figure 9B (at position H6 in the text).

[0096] The fourth conductive portion F4 is electrically connected between the second electrode portion E2 and the first end ST3 of the fourth active layer to achieve an electrical connection between the second electrode portion E2 and the first switching transistor. Specifically, the fourth conductive portion F4 is electrically connected to the second electrode portion E2 through a via penetrating the interlayer dielectric layer 1003 (e.g., Figure 9A J7 and such Figure 9B At point H7 in the diagram, it is electrically connected to the first end ST3 of the fourth active layer through a via penetrating the interlayer dielectric layer 1003, the second insulating layer 1002, and the first insulating layer 1001 (e.g., at point H7 in the diagram). Figure 9A J8 and such Figure 9B (at point H8 in the text).

[0097] The fifth conductive part F5 is electrically connected to the second end DT4 of the fifth active layer and the first end ST5 of the sixth active layer to function as the second connection node B. Specifically, the fifth conductive part F5 is electrically connected to the second end DT4 of the fifth active layer and the first end ST5 of the sixth active layer through a via penetrating the interlayer dielectric layer 1003, the second insulating layer 1002, and the first insulating layer 1001 (e.g., Figure 9A J9 and Figure 9B (H9 in the text).

[0098] The sixth conductive portion F6 is electrically connected between the first active connection pattern cn1 and the first reset trace portion VLa to achieve an electrical connection between the first active connection pattern cn1 and the reset trace. Specifically, the sixth conductive portion F6 is electrically connected to the first active connection pattern cn1 through a via penetrating the interlayer dielectric layer 1003, the second insulating layer 1002, and the first insulating layer 1001 (e.g., ...). Figure 9A J10 and Figure 9B (at H10 in the middle).

[0099] When the third conductive layer 103 includes a connection portion EML12, a gate connection portion, and a second reset trace portion VLb, the connection portion EML12 is electrically connected to the overlapping portion EML11 and the trace portion EML13 through two vias penetrating the interlayer dielectric layer 1003 (e.g., Figures 9A-9B (At HE1 and HE2 in the middle). The gate connection is electrically connected to the second sub-trace SL12a through the interlayer dielectric layer 1003 (e.g., at HE1 and HE2 in the middle). Figures 9A-9B (At HG1 in the middle). Electrically connected to the junctions of the fourth sub-gate portion SL12b1 and the sixth sub-gate portion SL12b3, and the junctions of the fifth sub-gate portion SL12b2 and the sixth sub-gate portion SL12b3, through two vias penetrating the interlayer dielectric layer 1003 and the second insulating layer 1002 (e.g., Figure 9A(At HG2 and HG3 in the middle). Electrically connected to the junctions of the first sub-gate portion SL11b1 and the third sub-gate portion SL11b3, and the junctions of the second sub-gate portion SL11b2 and the third sub-gate portion SL11b3, through two vias penetrating the interlayer dielectric layer 1003 and the second insulating layer 1002 (e.g. Figure 9B (At HG2 and HG3 in the middle). The second reset trace VLb is electrically connected to the second end DT5 of the sixth active layer through a via penetrating the interlayer dielectric layer 1003, the second insulating layer 1002 and the first insulating layer 1001 (e.g. Figure 9A J11 and Figure 9B (at H11 in the middle).

[0100] Optionally, the third conductive layer 103 further includes a third reset trace VLc, the second conductive layer further includes a first reset trace VLa, and the sixth conductive portion F6 is electrically connected to the first reset trace VLa through a via penetrating the interlayer dielectric layer 1003. Figure 9A J12); the third reset trace VLc is electrically connected to the first reset trace VLa through a via penetrating the interlayer dielectric layer 1003. Figure 9A (at point J13 in the middle).

[0101] like Figure 10 This is a schematic diagram of the structure of the fourth conductive layer provided in an embodiment of the present invention. The display panel also includes a first planarization layer and a fourth conductive layer. The first planarization layer is located on the third conductive layer 103, and the fourth conductive layer is located on the first planarization layer. The fourth conductive layer includes multiple data line groups and multiple power line groups. Each data line group and each power line group are alternately arranged at intervals.

[0102] Each data line group includes two data lines DL symmetrically arranged about the center line of the second pitch. Each data line DL includes a data trace portion DL1 and an extension portion DL2. The data trace portion DL1 extends along the column direction y, and the extension portion DL2 is connected to the data trace portion DL1. The extension portion DL2 overlaps with and is electrically connected to the second conductive portion F2 to realize the electrical connection between the data transistor T2 and the data line DL; specifically, the extension portion DL2 is electrically connected to the second conductive portion F2 through a via penetrating the first planarization layer (e.g., ...). Figure 10 (at PLN1 in the middle).

[0103] Each power line group includes two first power lines VDD symmetrically arranged about the center line of the first spacing, and a power connection portion VDDC electrically connected between the two first power lines VDD and extending along the row direction x. The power connection portion VDDC is located on the side of the first gate portion away from the trace portion EML13. Each first power line VDD includes a first power part VDD1, a second power part VDD2, and a clearance portion VDD3 connected between the first power part VDD1 and the second power part VDD2. The first power part VDD1 and the second power part VDD2 both extend along the column direction y. The clearance portion VDD3 is provided corresponding to the extension portion DL2. The power connection portion VDDC is connected to the side of the clearance portion VDD3 away from the extension portion DL2 to avoid short circuit between the first power line VDD and the data line DL. The second power supply section VDD2 overlaps with and is electrically connected to the fourth conductive section F4, thereby achieving an electrical connection between the first power line VDD and the first switching transistor and the second electrode section E2; specifically, the second power supply section VDD2 is electrically connected to the fourth conductive section F4 through a via penetrating the first planarization layer (e.g., Figure 10 (at PLN2 in the middle).

[0104] Optionally, the fourth conductive layer further includes a plurality of second node connection portions B1, each second node connection portion B1 being located on the side of the first power line VDD away from the data line DL, each second node connection portion B1 overlapping with and electrically connected to the fifth conductive portion F5, and the second node connection portion B1 being electrically connected to the fifth conductive portion F5 through a via penetrating the first planarization layer (e.g., Figure 10 (at PLN3 in the middle).

[0105] The light-emitting device is electrically connected to the second connection node. Optionally, the anode of the light-emitting device is located on the second planarization layer, the second planarization layer is located on the fourth conductive layer, the pixel definition layer is located on the anode, the light-emitting layer of the light-emitting device is located within the pixel definition area of ​​the pixel definition layer that exposes the anode, and the cathode of the light-emitting device is located on the light-emitting layer. The light-emitting device is electrically connected to the source and drain of the corresponding driving transistor between a first voltage terminal and a second voltage terminal. Optionally, a first power line is electrically connected between the first voltage terminal and one of the source and drain of the driving transistor, and a second power line is electrically connected between the cathode of the light-emitting device and the second voltage terminal.

[0106] Optionally, Figure 5C 100b in the text refers to a multilayer composite insulating layer (i.e., including a first planarization layer, a second planarization layer, and a pixel definition layer). Figure 5D 100c in the text refers to a multilayer composite insulating layer (i.e., including an interlayer dielectric layer, a first planarization layer, a second planarization layer, and a pixel definition layer).

[0107] The present invention also provides a display device, including a display panel. The display device includes portable display devices (such as laptops, mobile phones, etc.), fixed terminals (such as desktop computers, televisions, etc.), measuring devices (such as fitness trackers, thermometers, etc.), etc.

[0108] For those skilled in the art, based on the ideas of this invention, there will be changes in the specific implementation methods and application scope. Therefore, the content of this specification should not be construed as a limitation of this invention.

Claims

1. A display panel, characterized in that, include: Multiple sub-pixels, each of which includes a light-emitting device and a pixel driving circuit; The pixel driving circuit includes a driving transistor and a connecting transistor. The driving transistor is connected in series with the light-emitting device between a first power line and a second power line, and the connecting transistor is electrically connected to the gate of the driving transistor. as well as Multiple variable signal lines are configured to transmit variable signals, and each of the variable signal lines includes multiple overlapping portions; The connection transistor includes: The first active layer includes a first channel portion, a second channel portion, and a first electrical connection portion connecting the first channel portion and the second channel portion; The two sub-pixels located in the same row and adjacent to each other are mirrored. The first electrical connection portions of the multiple sub-pixels located in the same row and adjacent to each other are alternately arranged with a first spacing and a second spacing, wherein the first spacing is smaller than the second spacing. The two adjacent overlapping portions of each variable signal line are spaced apart by two sub-pixels, and each overlapping portion at least partially overlaps with the first electrical connection portions of the two sub-pixels arranged with the first spacing to form two capacitors.

2. The display panel according to claim 1, characterized in that, Each of the aforementioned variable signal lines further includes: A plurality of connecting portions, each of the connecting portions extending along a column direction, and each of the connecting portions being electrically connected to one of the overlapping portions; and The wiring section extends along the direction of travel, and the wiring section is electrically connected to the plurality of overlapping sections through the plurality of connecting sections; Wherein, two sub-pixels are spaced between two adjacent connection portions of each variable signal line, and each connection portion is located between the first electrical connection portions of the two sub-pixels arranged at the first spacing.

3. The display panel according to claim 2, characterized in that, Also includes: Multiple first scan lines, wherein the gates of the connecting transistors of multiple sub-pixels located in the same row are electrically connected to the corresponding first scan lines; the first scan lines electrically connected to the gates of the connecting transistors of multiple sub-pixels located in the same row include multiple first gate portions, each first gate portion including a first sub-gate portion and a second sub-gate portion disposed opposite to each other, and a third sub-gate portion connected between the first sub-gate portion and the second sub-gate portion; Wherein, the first sub-gate portion and the second sub-gate portion both extend along the column direction, and the third sub-gate portion extends along the row direction; the first sub-gate portion and the second sub-gate portion overlap with two first channel portions of two sub-pixels that are electrically connected to the first electrical connection portions adjacent to each other at the first spacing, and the third sub-gate portion overlaps with two second channel portions of two sub-pixels that are electrically connected to the first electrical connection portions adjacent to each other at the first spacing; each overlapping portion is located between the first sub-gate portion and the second sub-gate portion of the corresponding first gate portion.

4. The display panel according to claim 3, characterized in that, The source and drain of the connecting transistor are electrically connected between the gate of the driving transistor and the first reset line; Each of the connecting portions overlaps at least partially with the third sub-gate portion of the corresponding first gate portion, and the trace portion and the overlapping portion electrically connected by the connecting portion are located on opposite sides of the third sub-gate portion.

5. The display panel according to claim 4, characterized in that, In the thickness direction of the display panel, the distance from each connecting portion to the corresponding third sub-gate portion is greater than the distance from each connecting portion to the corresponding overlapping portion.

6. The display panel according to claim 4, characterized in that, The first scan line, which is electrically connected to the gate of the connecting transistor of the plurality of sub-pixels located in the same row, further includes a plurality of first sub-trace portions; Wherein, both ends of each of the first sub-routes are electrically connected to the junction of the first sub-gate and the third sub-gate, and the junction of the second sub-gate and the third sub-gate, respectively.

7. The display panel according to claim 3, characterized in that, The source and drain of the connecting transistor are electrically connected between the gate of the driving transistor and one of the source and drain of the driving transistor. Each of the connecting portions is located on the side of the corresponding overlapping portion away from the third sub-gate portion, and each of the routing portions is located on the side of the corresponding connecting portion away from the overlapping portion.

8. The display panel according to claim 7, characterized in that, Also includes: Multiple light-emitting control lines, each of which extends along the row direction; In this configuration, each of the light-emitting control lines and a plurality of the connection portions of a variable signal line at least partially overlap, and in the thickness direction of the display panel, the distance of each connection portion from the corresponding light-emitting control line is greater than the distance of each connection portion from the corresponding overlapping portion.

9. The display panel according to claim 8, characterized in that, The pixel driving circuit also includes: A light-emitting transistor, the driving transistor, and the light-emitting device are connected in series between the first power line and the second power line; The gates of the light-emitting transistors of the multiple sub-pixels located in the same row are electrically connected to the same light-emitting control line.

10. The display panel according to claim 7, characterized in that, The first scan line, electrically connected to the gate of the connection transistor of the plurality of sub-pixels located in the same row, further includes: The second sub-routing section extends along the row direction; and Multiple gate connection portions, each of the gate connection portions being electrically connected between a corresponding first gate portion and a second sub-trace portion, each of the gate connection portions including a first sub-gate connection portion and a second sub-gate connection portion symmetrical about the connection portion; In each of the gate connection portions, the first end of the first sub-gate connection portion and the first end of the second sub-gate connection portion are connected and electrically connected to the second sub-trace portion. The second end of the first sub-gate connection portion of each of the gate connection portions is electrically connected to the junction of the first sub-gate portion and the third sub-gate portion of the corresponding first gate portion. The second end of the second sub-gate connection portion of each of the gate connection portions is electrically connected to the junction of the second sub-gate portion and the third sub-gate portion of the corresponding first gate portion.

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