Driving circuit, display substrate and display device

Abstract

The present invention provides a driving circuit, a display substrate and a display device. The driving circuit is characterized in that it includes an output circuit, a first node reset circuit and a second node control capacitor; the output circuit is used to control the driving signal end to output a driving signal under the control of the potential of the first node; the first node reset circuit is used to control the resetting of the first node under the control of the potential of the second node; the second node control capacitor is electrically connected to the second node; the output transistor included in the output circuit has a width-to-length ratio less than or equal to a first predetermined width-to-length ratio; and / or the first node reset transistor included in the first node reset circuit has a width-to-length ratio greater than or equal to a second predetermined width-to-length ratio; and / or the capacitance value of the second node control capacitor is greater than or equal to a predetermined capacitance value. The present invention optimizes the design so that the waveform of the driving signal output by the driving circuit is normal.

Description

Technical Field

[0001] The present invention relates to the field of display technology, and in particular to a driving circuit, a display substrate and a display device. Background Art

[0002] In the related art, when an N-type driving circuit (an N-type driving circuit refers to a driving circuit that outputs a high-level valid driving signal) is working, when the performance of the transistor and the storage capacitor do not match, the output of the N-type driving circuit will be abnormal, thereby causing abnormal display. Summary of the invention

[0003] The main purpose of the present invention is to provide a driving circuit, a display substrate and a display device to solve the problem that when the performance of the transistor and the storage capacitor do not match during operation of the existing N-type driving circuit, the N-type driving circuit output will be abnormal, thereby causing abnormal display.

[0004] In one aspect, an embodiment of the present invention provides a driving circuit, including an output circuit, a first node reset circuit, and a second node control capacitor;

[0005] The output circuit is used to control the driving signal terminal to output a driving signal under the control of the potential of the first node;

[0006] The first node reset circuit is used to control the resetting of the first node under the control of the potential of the second node;

[0007] The second node control capacitor is electrically connected to the second node;

[0008] The output circuit includes an output transistor whose width-to-length ratio is less than or equal to a first predetermined width-to-length ratio; and / or, the first node reset circuit includes a first node reset transistor whose width-to-length ratio is greater than or equal to a second predetermined width-to-length ratio; and / or, the capacitance value of the second node control capacitor is greater than or equal to a predetermined capacitance value;

[0009] The value range of the first predetermined width-to-length ratio is greater than or equal to 150 / 3.8 and less than or equal to 230 / 3.8, the value range of the second predetermined width-to-length ratio is greater than or equal to 4 / 4.9 and less than or equal to 6 / 4.9; the value range of the predetermined capacitance value is greater than or equal to 143fF and less than or equal to 243fF.

[0010] Optionally, the first predetermined width-to-length ratio is 210 / 3.8, the second predetermined width-to-length ratio is 5 / 4.9, and the predetermined capacitance value is 243fF.

[0011] Optionally, the control electrode of the output transistor is electrically connected to the first node, the first electrode of the output transistor is electrically connected to the first clock signal line, and the second electrode of the output transistor is electrically connected to the drive signal terminal;

[0012] A control electrode of the first-node reset transistor is electrically connected to the second node, a first electrode of the first-node reset transistor is electrically connected to the first node, and a second electrode of the first-node reset transistor is electrically connected to the first clock signal line.

[0013] Optionally, the driving circuit further includes a third node control circuit, a fourth node control circuit, a fifth node control circuit, a second node control circuit, a first node control circuit and an output reset circuit;

[0014] The third node control circuit is electrically connected to the second clock signal line, the first voltage line and the third node respectively, and is used to control the first voltage signal provided by the first voltage line to be written into the third node under the control of the second clock signal provided by the second clock signal line;

[0015] The fourth node control circuit is electrically connected to the sixth node, the third clock signal line and the fourth node respectively, and is used to control the third clock signal line to write the third clock signal into the fourth node under the control of the potential of the sixth node, and control the potential of the fourth node according to the potential of the sixth node;

[0016] The fifth node control circuit is electrically connected to the second clock signal line, the first clock signal line, the input terminal and the fifth node respectively, and is used to control the input terminal to provide an input signal to the fifth node under the control of the second clock signal provided by the second clock signal line and the first clock signal provided by the first clock signal line;

[0017] The second node control circuit is electrically connected to the third node, the seventh node, the second voltage line, the second node and the third clock signal line respectively, and is used to control the seventh node to be connected to the second voltage line under the control of the potential of the third node, and to control the seventh node to be connected to the third clock signal line under the control of the potential of the second node;

[0018] The first electrode plate of the second node control capacitor is electrically connected to the seventh node, and the second electrode plate of the second node control capacitor is electrically connected to the second node;

[0019] The first node control circuit is electrically connected to the fourth node, the third clock signal line and the first node respectively, and is used to control the fourth node to be connected to the first node under the control of the third clock signal provided by the third clock signal line;

[0020] The output reset circuit is electrically connected to the second node, the drive signal terminal and the first voltage line respectively, and is used to control the connection between the drive signal terminal and the first voltage line under the control of the potential of the second node.

[0021] Optionally, the third node and the sixth node are the same node; or,

[0022] The driving circuit further includes a first conduction control circuit; the first conduction control circuit is used to control the connection between the third node and the sixth node under the control of a first voltage signal provided by a first voltage line.

[0023] Optionally, the fifth node and the second node are the same node; or,

[0024] The driving circuit further includes a second conduction control circuit; the second conduction control circuit is used to control the connection between the fifth node and the second node under the control of a first voltage signal provided by a first voltage line.

[0025] Optionally, the third node control circuit includes a first transistor and a second transistor;

[0026] The control electrode of the first transistor is electrically connected to the second clock signal line, the first electrode of the first transistor is electrically connected to the first voltage line, and the second electrode of the first transistor is electrically connected to the third node;

[0027] The control electrode of the second transistor is electrically connected to the fifth node, the first electrode of the second transistor is electrically connected to the second clock signal line, and the second electrode of the second transistor is electrically connected to the third node;

[0028] The fourth node control circuit includes a third transistor and a first capacitor;

[0029] The control electrode of the third transistor is electrically connected to the sixth node, the first electrode of the third transistor is electrically connected to the third clock signal line, and the second electrode of the third transistor is electrically connected to the fourth node;

[0030] The first plate of the first capacitor is electrically connected to the sixth node, and the second plate of the first capacitor is electrically connected to the fourth node;

[0031] The fifth node control circuit includes a fourth transistor and a fifth transistor;

[0032] The control electrode of the fourth transistor is electrically connected to the first clock signal line, and the first electrode of the fourth transistor is electrically connected to the input terminal;

[0033] The control electrode of the fifth transistor is electrically connected to the second clock signal line, the first electrode of the fifth transistor is electrically connected to the second electrode of the fourth transistor, and the second electrode of the fifth transistor is electrically connected to the fifth node;

[0034] The second node control circuit includes a sixth transistor and a seventh transistor;

[0035] The control electrode of the sixth transistor is electrically connected to the third node, the first electrode of the sixth transistor is electrically connected to the second voltage line, and the second electrode of the sixth transistor is electrically connected to the seventh node;

[0036] The control electrode of the seventh transistor is electrically connected to the second node, the first electrode of the seventh transistor is electrically connected to the third clock signal line, and the second electrode of the seventh transistor is electrically connected to the seventh node;

[0037] The first node control circuit includes an eighth transistor and a second capacitor;

[0038] The control electrode of the eighth transistor is electrically connected to the third clock signal line, the first electrode of the eighth transistor is electrically connected to the fourth node, and the second electrode of the eighth transistor is electrically connected to the first node;

[0039] The first plate of the second capacitor is electrically connected to the first node, and the second plate of the second capacitor is electrically connected to the first clock signal line;

[0040] The output reset circuit includes a ninth transistor;

[0041] The control electrode of the ninth transistor is electrically connected to the second node, the first electrode of the ninth transistor is electrically connected to the first voltage line, and the second electrode of the ninth transistor is electrically connected to the driving signal terminal.

[0042] In a second aspect, an embodiment of the present invention further provides a display substrate including the above-mentioned driving circuit disposed on a base.

[0043] Optionally, the driving circuit includes an output circuit; the output circuit includes an output transistor;

[0044] The active layer of the output transistor includes at least one first channel portion extending along a first direction;

[0045] A sum of widths of the at least one first channel portion along the first direction is less than or equal to a first predetermined width, so that a width-to-length ratio of the output transistor is less than or equal to the first predetermined width-to-length ratio.

[0046] The driving circuit includes a first node reset circuit; the first node reset circuit includes a first node reset transistor;

[0047] The active layer of the first node reset transistor includes at least one second channel portion;

[0048] The sum of the widths of the at least one second channel portion along the second direction is greater than or equal to a second predetermined width, so that the width-to-length ratio of the first node reset transistor is greater than or equal to the second predetermined width-to-length ratio;

[0049] The first direction intersects the second direction.

[0050] Optionally, the display substrate described in at least one embodiment of the present invention further includes gate lines and data lines arranged in the display area;

[0051] The gate line includes a portion extending along the first direction, and the data line includes a portion extending along the second direction.

[0052] Optionally, the driving circuit includes a second node control capacitor; the second node control capacitor includes a first electrode plate and a second electrode plate arranged in different layers; the first electrode plate and the second electrode plate are provided with an insulating layer;

[0053] The orthographic projection of the first electrode plate on the substrate at least partially overlaps with the orthographic projection of the second electrode plate on the substrate, and the overlapping area between the orthographic projection of the first electrode plate on the substrate and the orthographic projection of the second electrode plate on the substrate is greater than or equal to a predetermined area, so that the capacitance value of the second node control capacitor is greater than or equal to the predetermined capacitance value.

[0054] In a third aspect, an embodiment of the present invention provides a display device, including a display substrate.

[0055] Optionally, the display device described in at least one embodiment of the present invention further includes a voltage providing circuit; the first voltage signal is a low voltage signal, and the second voltage signal is a high voltage signal;

[0056] The voltage providing circuit is used to provide a first voltage signal and a second voltage signal, and to control the difference between the second voltage value and the first voltage value to be greater than a predetermined difference;

[0057] The second voltage value is the voltage value of the second voltage signal, and the first voltage value is the voltage value of the first voltage signal;

[0058] When the potential of the clock signal provided by each clock signal line included in the driving circuit in the display substrate is a low voltage, the voltage value of the clock signal is a first voltage value;

[0059] When the potential of the clock signal provided by each clock signal line is a high voltage, the voltage value of the clock signal is a second voltage value.

[0060] The driving circuit, display substrate and display device described in the embodiments of the present invention are optimized in design to control the width-to-length ratio of the output transistor to be less than or equal to a first predetermined width-to-length ratio, and / or to control the width-to-length ratio of the first node reset transistor to be greater than or equal to a second predetermined width-to-length ratio, and / or to control the capacitance value of the second node control capacitor to be greater than or equal to a predetermined capacitance value, so that the waveform of the driving signal output by the driving circuit is normal. BRIEF DESCRIPTION OF THE DRAWINGS

[0061] Figure 1 is a structural diagram of a driving circuit according to an embodiment of the present invention;

[0062] Figure 2 is a structural diagram of a driving circuit according to at least one embodiment of the present invention;

[0063] Figure 3 is a structural diagram of a driving circuit according to at least one embodiment of the present invention;

[0064] Figure 4 is a circuit diagram of a driving circuit according to at least one embodiment of the present invention;

[0065] Figure 5-Figure 9 is a simulation waveform diagram of the driving circuit according to at least one embodiment of the present invention;

[0066] Fig.10 is Figure 4 On the basis of the above, mark the schematic diagram of the gate of each transistor and the plate of each capacitor;

[0067] Fig.11 is a schematic diagram of a layout of a driving circuit provided by at least one embodiment of the present invention;

[0068] Fig.12 yes Fig.11 Schematic diagram of the active layer in;

[0069] Fig.13 yes Fig.11 A schematic diagram of the first gate metal layer in FIG.

[0070] Fig.14 yes Fig.11 A schematic diagram of a second gate metal layer in FIG.

[0071] Fig.15 It is a schematic diagram of a plurality of via holes provided on a substrate provided with an active layer, a first gate insulating layer, a first gate metal layer, a second gate insulating layer, a second gate metal layer and a first interlayer dielectric layer;

[0072] Fig.16 is Fig.15 A schematic diagram of a conductive connection portion L1 is provided on the basis of;

[0073] Fig.17 yes Fig.11 A schematic diagram of the first source and drain metal layer in FIG.

[0074] Fig.18 yes Fig.11 A schematic diagram of the superposition of an active layer, a first gate metal layer, a second gate metal layer, a third gate metal layer and a first source-drain metal layer in FIG.

[0075] Fig.19 yes Fig.11 A schematic diagram of a second source / drain metal layer in FIG.

[0076] Fig. 20 It is a schematic diagram of the superposition of the first source-drain metal layer and the second source-drain metal layer. DETAILED DESCRIPTION

[0077] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0078] The transistors used in all embodiments of the present invention may be triodes, thin film transistors, field effect transistors or other devices with the same characteristics. In the embodiments of the present invention, in order to distinguish the two electrodes of the transistor except the control electrode, one of the electrodes is called the first electrode and the other is called the second electrode.

[0079] In actual operation, when the transistor is a triode, the control electrode may be a base, the first electrode may be a collector, and the second electrode may be an emitter; or, the control electrode may be a base, the first electrode may be an emitter, and the second electrode may be a collector.

[0080] In actual operation, when the transistor is a thin film transistor or a field effect transistor, the control electrode can be a gate, the first electrode can be a drain, and the second electrode can be a source; or, the control electrode can be a gate, the first electrode can be a source, and the second electrode can be a drain.

[0081] The driving circuit according to the embodiment of the present invention comprises an output circuit, a first node reset circuit and a second node control capacitor;

[0082] The output circuit is used to control the driving signal terminal to output a driving signal under the control of the potential of the first node;

[0083] The first node reset circuit is used to control the resetting of the first node under the control of the potential of the second node;

[0084] The second node control capacitor is electrically connected to the second node;

[0085] The output circuit includes an output transistor whose width-to-length ratio is less than or equal to a first predetermined width-to-length ratio; and / or, the first node reset circuit includes a first node reset transistor whose width-to-length ratio is greater than or equal to a second predetermined width-to-length ratio; and / or, the capacitance value of the second node control capacitor is greater than or equal to a predetermined capacitance value;

[0086] The value range of the first predetermined width-to-length ratio is greater than or equal to 150 / 3.8 and less than or equal to 230 / 3.8, the value range of the second predetermined width-to-length ratio is greater than or equal to 4 / 4.9 and less than or equal to 6 / 4.9; the value range of the predetermined capacitance value is greater than or equal to 143fF and less than or equal to 243fF.

[0087] The driving circuit described in the embodiment of the present invention is designed to optimize the width-to-length ratio of the output transistor to be less than or equal to a first predetermined width-to-length ratio, and / or to control the width-to-length ratio of the first node reset transistor to be greater than or equal to a second predetermined width-to-length ratio, and / or to control the capacitance value of the second node control capacitor to be greater than or equal to a predetermined capacitance value, so that the waveform of the driving signal output by the driving circuit is normal.

[0088] In the embodiment of the present invention, at least one of the following conditions must be met:

[0089] The output circuit includes an output transistor whose width-to-length ratio is less than or equal to a first predetermined width-to-length ratio;

[0090] The first node reset circuit includes a first node reset transistor whose width-to-length ratio is greater than or equal to a second predetermined width-to-length ratio;

[0091] The capacitance value of the second node control capacitor is greater than or equal to a predetermined capacitance value.

[0092] That is, in at least one embodiment of the present invention,

[0093] The output circuit includes an output transistor whose width-to-length ratio is less than or equal to a first predetermined width-to-length ratio; or,

[0094] The first node reset circuit includes a first node reset transistor whose width-to-length ratio is greater than or equal to a second predetermined width-to-length ratio; or,

[0095] The capacitance value of the second node control capacitor is greater than or equal to a predetermined capacitance value; or,

[0096] The output circuit includes an output transistor whose width-to-length ratio is less than or equal to a first predetermined width-to-length ratio; the first node reset circuit includes a first node reset transistor whose width-to-length ratio is greater than or equal to a second predetermined width-to-length ratio; or,

[0097] The first node reset circuit includes a first node reset transistor whose width-to-length ratio is greater than or equal to a second predetermined width-to-length ratio; the second node control capacitor whose capacitance value is greater than or equal to a predetermined capacitance value; or,

[0098] The output circuit includes an output transistor whose width-to-length ratio is less than or equal to a first predetermined width-to-length ratio; the capacitance value of the second node control capacitor is greater than or equal to a predetermined capacitance value; or,

[0099] The output circuit includes an output transistor whose width-to-length ratio is less than or equal to a first predetermined width-to-length ratio; the first node reset circuit includes a first node reset transistor whose width-to-length ratio is greater than or equal to a second predetermined width-to-length ratio; and the capacitance value of the second node control capacitor is greater than or equal to a predetermined capacitance value.

[0100] like Figure 1 As shown, the driving circuit according to the embodiment of the present invention includes an output circuit 11 and a first node reset circuit 12;

[0101] The output circuit 11 is electrically connected to N1 and the driving signal terminal O1 respectively, and is used to control the driving signal terminal O1 to output a driving signal under the control of the potential of the first node N1;

[0102] The first node reset circuit 12 is electrically connected to the second node N2 and the first node N1 respectively, and is used to control the first node N1 to be reset under the control of the potential of the second node N2;

[0103] The output circuit 11 includes an output transistor whose width-to-length ratio is less than or equal to a first predetermined width-to-length ratio; and / or the first node reset circuit 12 includes a first node reset transistor whose width-to-length ratio is greater than or equal to a second predetermined width-to-length ratio.

[0104] The driving circuit described in the embodiment of the present invention is optimized in design to control the width-to-length ratio of the output transistor to be less than or equal to a first predetermined width-to-length ratio, and / or to control the width-to-length ratio of the first node reset transistor to be greater than or equal to a second predetermined width-to-length ratio, so that the waveform of the driving signal output by the driving circuit is normal.

[0105] In at least one embodiment of the present invention, the driving circuit may be a gate driving circuit or a light emitting control signal generating circuit, but is not limited thereto.

[0106] In at least one embodiment of the present invention, the first predetermined width-to-length ratio may range from greater than or equal to 150 / 3.8 to less than or equal to 230 / 3.8, and the second predetermined width-to-length ratio may range from greater than or equal to 4 / 4.9 to less than or equal to 6 / 4.9.

[0107] Optionally, the first predetermined width-to-length ratio is 2.10 / 3.8, and the second predetermined width-to-length ratio is 5 / 4.9, but is not limited thereto.

[0108] In at least one embodiment of the present invention, by setting the width-to-length ratio of the output transistor to be smaller, the inter-electrode capacitance of the output transistor is reduced, so that the response time of the output transistor is fast and it can be turned on or off quickly;

[0109] The width-to-length ratio of the first node reset transistor is set to be larger, so that there are more instantaneous carriers in the first node reset transistor, so that the voltage response speed is fast, and the output transistor can be instantly controlled to be turned on or off.

[0110] like Figure 2 As shown, in Figure 1 Based on the embodiment of the driving circuit shown, the driving circuit according to at least one embodiment of the present invention may further include a second node control capacitor C0;

[0111] The second node control capacitor C0 is electrically connected to the second node N2 , and a capacitance value of the second node control capacitor C0 is greater than or equal to a predetermined capacitance value, so that the waveform of the driving signal output by the driving circuit is normal.

[0112] In at least one embodiment of the present invention, the predetermined capacitance value may range from greater than or equal to 143 fF to less than or equal to 243 fF.

[0113] Optionally, the predetermined capacitance value is 243fF, but is not limited thereto.

[0114] In at least one embodiment of the present invention, the optimal combination of the width-to-length ratio of the output transistor, the width-to-length ratio of the first node reset transistor, and the capacitance value of the second node control capacitor can be: the width-to-length ratio of the output transistor is 210 / 3.8, the width-to-length ratio of the first node reset transistor is 6 / 4.9, and the capacitance value of the second node control capacitor is 243fF.

[0115] In at least one embodiment of the present invention, the control electrode of the output transistor is electrically connected to the first node, the first electrode of the output transistor is electrically connected to the first clock signal line, and the second electrode of the output transistor is electrically connected to the drive signal terminal;

[0116] A control electrode of the first-node reset transistor is electrically connected to the second node, a first electrode of the first-node reset transistor is electrically connected to the first node, and a second electrode of the first-node reset transistor is electrically connected to the first clock signal line.

[0117] The driving circuit described in at least one embodiment of the present invention may further include a third node control circuit, a fourth node control circuit, a fifth node control circuit, a second node control circuit, a first node control circuit and an output reset circuit;

[0118] The third node control circuit is electrically connected to the second clock signal line, the first voltage line and the third node respectively, and is used to control the first voltage signal provided by the first voltage line to be written into the third node under the control of the second clock signal provided by the second clock signal line;

[0119] The fourth node control circuit is electrically connected to the sixth node, the third clock signal line and the fourth node respectively, and is used to control the third clock signal line to write the third clock signal into the fourth node under the control of the potential of the sixth node, and control the potential of the fourth node according to the potential of the sixth node;

[0120] The fifth node control circuit is electrically connected to the second clock signal line, the first clock signal line, the input terminal and the fifth node respectively, and is used to control the input terminal to provide an input signal to the fifth node under the control of the second clock signal provided by the second clock signal line and the first clock signal provided by the first clock signal line;

[0121] The second node control circuit is electrically connected to the third node, the seventh node, the second voltage line, the second node N2 and the third clock signal line respectively, and is used to control the seventh node to be connected to the second voltage line under the control of the potential of the third node, and to control the seventh node to be connected to the third clock signal line under the control of the potential of the second node;

[0122] The first electrode plate of the second node control capacitor is electrically connected to the seventh node, and the second electrode plate of the second node control capacitor is electrically connected to the second node;

[0123] The first node control circuit is electrically connected to the fourth node, the third clock signal line and the first node respectively, and is used to control the fourth node to be connected to the first node under the control of the third clock signal provided by the third clock signal line;

[0124] The output reset circuit is electrically connected to the second node, the drive signal terminal and the first voltage line respectively, and is used to control the connection between the drive signal terminal and the first voltage line under the control of the potential of the second node.

[0125] Optionally, the third node and the sixth node are the same node; or,

[0126] The driving circuit further includes a first conduction control circuit; the first conduction control circuit is used to control the connection between the third node and the sixth node under the control of a first voltage signal provided by a first voltage line.

[0127] Optionally, the fifth node and the second node are the same node; or,

[0128] The driving circuit further includes a second conduction control circuit; the second conduction control circuit is used to control the connection between the fifth node and the second node under the control of a first voltage signal provided by a first voltage line.

[0129] like Figure 3 As shown, in Figure 2 Based on the embodiment of the driving circuit shown in FIG. 1 , the driving circuit according to at least one embodiment of the present invention further includes a third node control circuit 31, a fourth node control circuit 32, a fifth node control circuit 33, a second node control circuit 34, a first node control circuit 35, an output reset circuit 36, a first conduction control circuit 41 and a second conduction control circuit 42;

[0130] The output circuit 11 is also electrically connected to the first clock signal line K1, and is used to control the first clock signal line K1 to provide the first clock signal to the driving signal terminal under the control of the potential of the first node N1;

[0131] The first node reset circuit 12 is also electrically connected to the first clock signal line K1, and is used to control the connection between the first node N1 and the first clock signal line K1 under the control of the potential of the second node N2;

[0132] The third node control circuit 31 is electrically connected to the second clock signal line K2, the first voltage line V1 and the third node N3 respectively, and is used to control the first voltage signal provided by the first voltage line V1 to be written into the third node N3 under the control of the second clock signal provided by the second clock signal line K2;

[0133] The fourth node control circuit 32 is electrically connected to the sixth node N6, the third clock signal line K3 and the fourth node N4 respectively, and is used to control the third clock signal line K3 to write the third clock signal into the fourth node N4 under the control of the potential of the sixth node N6, and control the potential of the fourth node N4 according to the potential of the sixth node N6;

[0134] The fifth node control circuit 33 is electrically connected to the second clock signal line K2, the first clock signal line K1, the input terminal I1 and the fifth node N5 respectively, and is used to control the input terminal I1 to provide an input signal to the fifth node N5 under the control of the second clock signal provided by the second clock signal line K2 and the first clock signal provided by the first clock signal line K1;

[0135] The second node control circuit 34 is electrically connected to the third node N3, the seventh node N7, the second voltage line V2, the second node N2 and the third clock signal line K3, respectively, and is used to control the seventh node N7 to be connected to the second voltage line V2 under the control of the potential of the third node N3, and to control the seventh node N7 to be connected to the third clock signal line K3 under the control of the potential of the second node N2;

[0136] The first plate of the second node control capacitor C0 is electrically connected to the seventh node N7, and the second plate of the second node control capacitor is electrically connected to the second node N2;

[0137] The first node control circuit 35 is electrically connected to the fourth node N4, the third clock signal line K3 and the first node N1 respectively, and is used to control the fourth node N4 to be connected to the first node N1 under the control of the third clock signal provided by the third clock signal line K3;

[0138] The output reset circuit 36 ​​is electrically connected to the second node N2, the drive signal terminal O1 and the first voltage line V1 respectively, and is used to control the connection between the drive signal terminal O1 and the first voltage line V1 under the control of the potential of the second node N2;

[0139] The first conduction control circuit 41 is electrically connected to the first voltage line V1, the third node N3 and the sixth node N6 respectively, and is used to control the connection between the third node N3 and the sixth node N6 under the control of the first voltage signal provided by the first voltage line V1;

[0140] The second conduction control circuit 42 is electrically connected to the first voltage line V1, the fifth node N5 and the second node N2 respectively, and is used to control the connection between the fifth node N5 and the second node N2 under the control of the first voltage signal provided by the first voltage line V1.

[0141] The present invention Figure 3 When at least one embodiment of the driving circuit shown is working, the fifth node control circuit 33 controls the potential of the fifth node N5, the third node control circuit 31 controls the potential of the third node N3, the second node control circuit 34 controls the potential of the second node N2, the fourth node control circuit 32 controls the potential of the fourth node N4, the first node control circuit 35 controls the potential of the first node N1, and the first node reset circuit 12 controls the potential of the first node N1 under the control of the potential of the second node N2; the output circuit 11 controls the driving signal terminal O1 to output the first clock signal under the control of the potential of the first node N1; the output reset circuit 36 ​​controls the driving signal terminal O1 to output the first voltage signal under the control of the potential of the second node N2.

[0142] In the present invention, Figure 3 In at least one embodiment of the driving circuit shown, a first conduction control circuit 41 is provided between the third node N3 and the sixth node N6, and a second conduction control circuit 42 is provided between the fifth node N5 and the second node N2.

[0143] In at least one embodiment of the present invention, the third node control circuit includes a first transistor and a second transistor;

[0144] The control electrode of the first transistor is electrically connected to the second clock signal line, the first electrode of the first transistor is electrically connected to the first voltage line, and the second electrode of the first transistor is electrically connected to the third node;

[0145] The control electrode of the second transistor is electrically connected to the fifth node, the first electrode of the second transistor is electrically connected to the second clock signal line, and the second electrode of the second transistor is electrically connected to the third node;

[0146] The fourth node control circuit includes a third transistor and a first capacitor;

[0147] The control electrode of the third transistor is electrically connected to the sixth node, the first electrode of the third transistor is electrically connected to the third clock signal line, and the second electrode of the third transistor is electrically connected to the fourth node;

[0148] The first plate of the first capacitor is electrically connected to the sixth node, and the second plate of the first capacitor is electrically connected to the fourth node;

[0149] The fifth node control circuit includes a fourth transistor and a fifth transistor;

[0150] The control electrode of the fourth transistor is electrically connected to the first clock signal line, and the first electrode of the fourth transistor is electrically connected to the input terminal;

[0151] The control electrode of the fifth transistor is electrically connected to the second clock signal line, the first electrode of the fifth transistor is electrically connected to the second electrode of the fourth transistor, and the second electrode of the fifth transistor is electrically connected to the fifth node;

[0152] The second node control circuit includes a sixth transistor and a seventh transistor;

[0153] The control electrode of the sixth transistor is electrically connected to the third node, the first electrode of the sixth transistor is electrically connected to the second voltage line, and the second electrode of the sixth transistor is electrically connected to the seventh node;

[0154] The control electrode of the seventh transistor is electrically connected to the second node, the first electrode of the seventh transistor is electrically connected to the third clock signal line, and the second electrode of the seventh transistor is electrically connected to the seventh node;

[0155] The first node control circuit includes an eighth transistor and a second capacitor;

[0156] The control electrode of the eighth transistor is electrically connected to the third clock signal line, the first electrode of the eighth transistor is electrically connected to the fourth node, and the second electrode of the eighth transistor is electrically connected to the first node;

[0157] The first plate of the second capacitor is electrically connected to the first node, and the second plate of the second capacitor is electrically connected to the first clock signal line;

[0158] The output reset circuit includes a ninth transistor;

[0159] The control electrode of the ninth transistor is electrically connected to the second node, the first electrode of the ninth transistor is electrically connected to the first voltage line, and the second electrode of the ninth transistor is electrically connected to the driving signal terminal.

[0160] Optionally, the first voltage line is a low voltage end, and the second voltage line is a high voltage end.

[0161] like Figure 4 As shown, in Figure 3 Based on at least one embodiment of the driving circuit shown, the output circuit 11 includes an output transistor T01, and the first node reset circuit 12 includes a first node reset transistor T02;

[0162] The gate of the output transistor T01 is electrically connected to the first node N1, the source of the output transistor T01 is electrically connected to the first clock signal line K1, and the drain of the output transistor T01 is electrically connected to the driving signal terminal O1;

[0163] The gate of the first node reset transistor T02 is electrically connected to the second node N2, the source of the first node reset transistor T02 is electrically connected to the first node N1, and the drain of the first node reset transistor T02 is electrically connected to the first clock signal line K1;

[0164] The first plate of the second node control capacitor C0 is electrically connected to the seventh node N7, and the second plate of the second node control capacitor C0 is electrically connected to the second node N2;

[0165] The third node control circuit 31 may include a first transistor T1 and a second transistor T2;

[0166] The gate of the first transistor T1 is electrically connected to the second clock signal line K2, the source of the first transistor T1 is electrically connected to the low voltage end, and the drain of the first transistor T1 is electrically connected to the third node N3; the low voltage end is used to provide a low voltage signal VGL;

[0167] The gate of the second transistor T2 is electrically connected to the fifth node N5, the source of the second transistor T2 is electrically connected to the second clock signal line K2, and the drain of the second transistor T2 is electrically connected to the third node N3;

[0168] The fourth node control circuit 32 may include a third transistor T3 and a first capacitor C1;

[0169] The gate of the third transistor T3 is electrically connected to the sixth node N6, the source of the third transistor T3 is electrically connected to the third clock signal line K3, and the drain of the third transistor T3 is electrically connected to the fourth node N4;

[0170] The first plate of the first capacitor C1 is electrically connected to the sixth node N6, and the second plate of the first capacitor C1 is electrically connected to the fourth node N4;

[0171] The fifth node control circuit 33 may include a fourth transistor T4 and a fifth transistor T5;

[0172] The gate of the fourth transistor T4 is electrically connected to the first clock signal line K1, and the source of the fourth transistor T4 is electrically connected to the input terminal I1;

[0173] The gate of the fifth transistor T5 is electrically connected to the second clock signal line K2, the source of the fifth transistor T5 is electrically connected to the drain of the fourth transistor T4, and the drain of the fifth transistor T5 is electrically connected to the fifth node N5;

[0174] The second node control circuit 34 may include a sixth transistor T6 and a seventh transistor T7;

[0175] The gate of the sixth transistor T6 is electrically connected to the third node N3, the source of the sixth transistor T6 is electrically connected to the high voltage terminal, and the drain of the sixth transistor T6 is electrically connected to the seventh node N7; the high voltage terminal is used to provide a high voltage signal VGH;

[0176] The gate of the seventh transistor T7 is electrically connected to the second node N2, the source of the seventh transistor T7 is electrically connected to the third clock signal line K3, and the drain of the seventh transistor T7 is electrically connected to the seventh node N7;

[0177] The first node control circuit 35 may include an eighth transistor T8 and a second capacitor C2;

[0178] The gate of the eighth transistor T8 is electrically connected to the third clock signal line K3, the source of the eighth transistor T8 is electrically connected to the fourth node N4, and the drain of the eighth transistor T8 is electrically connected to the first node N1;

[0179] The first plate of the second capacitor C2 is electrically connected to the first node N1, and the second plate of the second capacitor C2 is electrically connected to the first clock signal line K1;

[0180] The output reset circuit 36 ​​may include a ninth transistor T9;

[0181] The gate of the ninth transistor T9 is electrically connected to the second node N2, the source of the ninth transistor T9 is electrically connected to the low voltage terminal, and the drain of the ninth transistor T9 is electrically connected to the driving signal terminal O1;

[0182] The first conduction control circuit 41 includes a tenth transistor T10, and the second conduction control circuit 42 includes an eleventh transistor T11;

[0183] The gate of the tenth transistor T10 is electrically connected to the low voltage terminal, the source of the tenth transistor T10 is electrically connected to the third node N3, and the drain of the tenth transistor T10 is electrically connected to the sixth node N6;

[0184] A gate of the eleventh transistor T11 is electrically connected to the low voltage terminal, a source of the eleventh transistor T11 is electrically connected to the fifth node N5, and a drain of the eleventh transistor T11 is electrically connected to the second node N2.

[0185] exist Figure 4 In at least one embodiment of the driving circuit shown, all transistors may be p-type thin film transistors, but the present invention is not limited thereto.

[0186] exist Figure 4 In at least one embodiment of the driving circuit shown, T10 and T11 may be normally-on transistors. In at least one embodiment of the present invention, by setting T10, the potential of N6 can be stabilized, and by setting T11, the potential of N2 can be stabilized.

[0187] right Figure 4 At least one embodiment of the driving circuit shown in FIG. 1 is simulated. When the inter-electrode capacitance CV of T01 remains unchanged at 400 fF, as shown in FIG. Figure 5 As shown, when the width-to-length ratio of T01 is less than or equal to 210 / 3.8, the driving signal output by the driving signal terminal O1 is normal.

[0188] exist Figure 5 , the waveforms from top to bottom (the waveforms of the driving signals provided by the driving signal end) are: when the channel width of T01 is 100um and the channel length of T01 is 3.8um, the waveform of the driving signal; when the channel width of T01 is 150um and the channel length of T01 is 3.8um, the waveform of the driving signal; when the channel width of T01 is 210um and the channel length of T01 is 3.8um, the waveform of the driving signal; when the channel width of T01 is 250um and the channel length of T01 is 3.8um, the waveform of the driving signal.

[0189] right Figure 4 At least one embodiment of the driving circuit shown in FIG. 1 is simulated. When the CV of T01 is kept constant at 400fF, as shown in FIG. Figure 6 As shown, when the width-to-length ratio of T02 is greater than or equal to 5 / 4.9, the driving signal output by the driving signal terminal O1 is normal.

[0190] exist Figure 6 , the waveforms from top to bottom (the waveforms of the driving signals provided by the driving signal end) are: when the channel width of T02 is 3um and the channel length of T02 is 4.9um, the waveform of the driving signal; when the channel width of T02 is 4um and the channel length of T02 is 4.9um, the waveform of the driving signal; when the channel width of T02 is 5um and the channel length of T02 is 4.9um, the waveform of the driving signal; when the channel width of T02 is 6um and the channel length of T02 is 4.9um, the waveform of the driving signal; when the channel width of T02 is 7um and the channel length of T02 is 4.9um, the waveform of the driving signal.

[0191] right Figure 4 At least one embodiment of the driving circuit shown in FIG. 1 is simulated. When the CV of T01 is kept constant at 400fF, as shown in FIG. Figure 7 As shown, when the capacitance value of C0 is greater than or equal to 143fF, the driving signal output by the driving signal terminal O1 is normal.

[0192] exist Figure 7 , the waveforms from top to bottom (the waveforms of the driving signals provided by the driving signal end) are: when the capacitance value of C0 is 93fF, the waveform of the driving signal; when the capacitance value of C0 is 143fF, the waveform of the driving signal; when the capacitance value of C0 is 193fF, the waveform of the driving signal; when the capacitance value of C0 is 243fF, the waveform of the driving signal; when the capacitance value of C0 is 293fF, the waveform of the driving signal.

[0193] like Figure 8 As shown in the figure, when the width-to-length ratio of T01 is 210 / 3.8, the width-to-length ratio of T02 is 6 / 4.9, and the capacitance value of C0 is 243fF, Figure 4 At least one embodiment of the driving circuit shown is simulated, and the waveform of the driving signal is normal.

[0194] like Fig. 9 As shown in FIG. 1 , when the CV of T01 remains unchanged at 400fF, the waveform of the driving signal will not be improved when the capacitance value of C2 is changed.

[0195] exist Fig. 9 In the figure, the waveforms from top to bottom (the waveform of the driving signal provided by the driving signal terminal) are: when the capacitance value of C2 is 146fF, the waveform of the driving signal; when the capacitance value of C2 is 196fF, the waveform of the driving signal; when the capacitance value of C2 is 246fF, the waveform of the driving signal; when the capacitance value of C2 is 296fF, the waveform of the driving signal; when the capacitance value of C2 is 346fF, the waveform of the driving signal. Fig. 9 As can be seen from the waveform in, adjusting the capacitance value of C2 will not improve the waveform of the driving signal.

[0196] The display substrate described in the embodiment of the present invention includes the above-mentioned driving circuit disposed on a substrate.

[0197] In at least one embodiment of the present invention, the driving circuit includes an output circuit; the output circuit includes an output transistor;

[0198] The active layer of the output transistor includes at least one first channel portion extending along a first direction;

[0199] A sum of widths of the at least one first channel portion along the first direction is less than or equal to a first predetermined width, so that a width-to-length ratio of the output transistor is less than or equal to the first predetermined width-to-length ratio.

[0200] In at least one embodiment of the present invention, when the output transistor includes only one first channel portion, the width of the first channel portion along the first direction is the width of the channel of the output transistor.

[0201] Optionally, the first direction may be substantially the same as an extension direction of a gate line disposed in the display area.

[0202] In at least one embodiment of the present invention, the first predetermined width-to-length ratio may range from greater than or equal to 150 / 3.8 to less than or equal to 230 / 3.8, and the second predetermined width-to-length ratio may range from greater than or equal to 4 / 4.9 to less than or equal to 6 / 4.9.

[0203] Optionally, the first predetermined width-to-length ratio is 210 / 3.8, but is not limited thereto.

[0204] Optionally, when the length of the channel of the output transistor is 3.8 um, the first predetermined width may be 210 um.

[0205] In at least one embodiment of the present invention, the driving circuit includes a first node reset circuit; the first node reset circuit includes a first node reset transistor;

[0206] The active layer of the first node reset transistor includes at least one second channel portion;

[0207] A sum of widths of the at least one second channel portion along the first direction is greater than or equal to a second predetermined width, so that a width-to-length ratio of the first node reset transistor is greater than or equal to the second predetermined width-to-length ratio.

[0208] In at least one embodiment of the present invention, when the active layer of the first node reset transistor includes only one second channel portion, the width of the second channel portion along the second direction is the width of the channel of the first node reset transistor;

[0209] The first direction intersects with the second direction.

[0210] Optionally, the second direction may be substantially the same as an extension direction of a data line disposed in the display area.

[0211] Optionally, the second predetermined width-to-length ratio is 5 / 4.9, but is not limited thereto.

[0212] Optionally, when the length of the channel of the first node reset transistor is 4.9 um, the second predetermined width may be 5 um.

[0213] The display substrate described in at least one embodiment of the present invention further includes gate lines and data lines arranged in the display area;

[0214] The gate line includes a portion extending along the first direction, and the data line includes a portion extending along the second direction.

[0215] In a specific implementation, the display substrate described in at least one embodiment of the present invention may further include a plurality of rows of gate lines and a plurality of columns of data lines arranged in the display area;

[0216] The gate line includes a portion extending along a first direction, the data line includes a portion extending along a second direction, and the driving circuit can be arranged in a first edge region of the display substrate and / or a second edge region of the display substrate. The first edge region can be arranged on the left side of the display region, and the second edge region can be arranged on the right side of the display region.

[0217] In at least one embodiment of the present invention, the driving circuit includes a second node control capacitor; the second node control capacitor includes a first electrode plate and a second electrode plate arranged in different layers; the first electrode plate and the second electrode plate are provided with an insulating layer;

[0218] The orthographic projection of the first electrode plate on the substrate at least partially overlaps with the orthographic projection of the second electrode plate on the substrate, and the overlapping area between the orthographic projection of the first electrode plate on the substrate and the orthographic projection of the second electrode plate on the substrate is greater than or equal to a predetermined area, so that the capacitance value of the second node control capacitor is greater than or equal to the predetermined capacitance value.

[0219] In at least one embodiment of the present invention, the predetermined capacitance value may range from greater than or equal to 143 fF to less than or equal to 243 fF.

[0220] Optionally, the predetermined capacitance value may be 243fF, but is not limited thereto.

[0221] Fig.10 is Figure 4 Based on this, mark the gate of each transistor and the plate of each capacitor.

[0222] exist Fig.10 In the figure, G1 is the gate of T1, G2 is the gate of T2, G3 is the gate of T3, G4 is the gate of T4, G5 is the gate of T5, G6 is the gate of T6, G7 is the gate of T7, G8 is the gate of T8, and G9 is the gate of T9. G10 is the gate of T10, G11 is the gate of T11, G01 is the gate of T01, G02 is the gate of T02, C0a is the first plate of C0, C1a is the first plate of C1, C2a is the first plate of C2, C1b is the second plate of C1, and C2b is the second plate of C2.

[0223] Fig.11 is a schematic diagram of a layout of a driving circuit provided by at least one embodiment of the present invention; Fig.12 yes Fig.11 Schematic diagram of the active layer in; Fig.13 yes Fig.11 A schematic diagram of the first gate metal layer in FIG. Fig.14 yes Fig.11 A schematic diagram of a second gate metal layer in FIG. Fig.17 yes Fig.11 A schematic diagram of the first source and drain metal layer in FIG. Fig.19 yes Fig.11 Schematic diagram of the second source and drain metal layer in .

[0224] exist Fig.11 In the layout diagram shown, the first direction D1 may be a vertical direction, and the second direction D2 may be a horizontal direction.

[0225] like Fig.12 As shown, the active layer of the output transistor T01 includes a first first channel portion 111, a second first channel portion 112, a third first channel portion 113, a fourth first channel portion 114, a fifth first channel portion 115 and a sixth first channel portion 116; the first first channel portion 111, the second first channel portion 112, the third first channel portion 113, the fourth first channel portion 114, the fifth first channel portion 115 and the sixth first channel portion 116 all extend along the first direction;

[0226] The active layer of the ninth transistor T9 includes a first third channel portion 211 extending along the first direction and a second third channel portion 212 extending along the first direction;

[0227] The sum of the width of the first first channel portion 111 along the first direction, the width of the second first channel portion 112 along the first direction, the width of the third first channel portion 113 along the first direction, the width of the fourth first channel portion 114 along the first direction, the width of the fifth first channel portion 115 along the first direction, and the width of the sixth first channel portion 116 along the first direction is the width of the channel of the output transistor T01.

[0228] like Fig.12 As shown, the active layer of the first node reset transistor T02 includes a second channel portion 121; the width of the channel of T02 is the width of the second channel portion 121 along the second direction.

[0229] exist Fig.12 In at least one embodiment shown, the active layer of T01 and the active layer of T9 are formed by a first semiconductor layer 10 and a second semiconductor layer 20; the first semiconductor layer 10 and the second semiconductor layer 20 are independent of each other (in order to prevent the heating effect of the transistor during operation caused by the large area of ​​the continuous active layer of the transistor from affecting the characteristics of the transistor, the first semiconductor layer 10 and the second semiconductor layer 20 can be set to be independent of each other).

[0230] Optionally, the active layer of the output transistor T01 and the active layer of the ninth transistor T9 may also be formed by a continuous semiconductor layer.

[0231] like Fig.13As shown, the gate labeled G91 includes a first output reset gate pattern of T9, the gate labeled G92 includes a second output reset gate pattern of T9, and the gate of G01 includes a first output gate pattern G011, a second output gate pattern G012, a third output gate pattern G013, a fourth output gate pattern G014, a fifth output gate pattern G015 and a sixth output gate pattern G016;

[0232] The gate of T1 is labeled G1, the gate of T2 includes a first gate graphic G21 and a second gate graphic G22, the gate of T3 is labeled G3, the gate of T4 is labeled G4, the gate of T4 is labeled G5, the gate of T5 is labeled G6, the gate of T6, the gate of T7 is labeled G7, the gate of T7 is labeled G8, the gate of T8 is labeled G10, the gate of T10, the gate of T11, G02 is the gate of T02, C0a is the first plate of C0, C1a is the first plate of C1, and C2a is the first plate of C2.

[0233] exist Fig.14 , the one labeled C0b is the second electrode plate of C0, the one labeled C1b is the second electrode plate of C1, and the one labeled C2b is the second electrode plate of C2.

[0234] like Fig.11 , Fig.13 and Fig.14 As shown, the orthographic projection of C0b on the substrate is within the orthographic projection of C0a on the substrate; C0a and C0b may be parallel to the substrate, and the area of ​​the orthographic projection of C0b on the substrate is greater than or equal to a predetermined area, so that the capacitance value of C0 is greater than or equal to the predetermined capacitance value.

[0235] After an active layer, a first gate insulating layer, a first gate metal layer, a second gate insulating layer and a second gate metal layer are sequentially arranged on a substrate, a first interlayer dielectric layer is arranged on a side of the second gate metal layer facing away from the second gate insulating layer, and a via hole penetrating the first interlayer dielectric layer is arranged. Fig.15 The black dots shown in FIG. 1 are via holes penetrating the first interlayer dielectric layer.

[0236] A third gate metal layer is disposed on a side of the first interlayer dielectric layer facing away from the second gate metal layer; Fig.16 As shown, the third gate metal layer is patterned to form a conductive connection portion L1. Then, a second interlayer dielectric layer is provided on the side of the third gate metal layer facing away from the first interlayer dielectric layer, and a via hole penetrating the second interlayer dielectric layer is provided, so that the conductive connection portion L1 is electrically connected to the source electrodes of K1 and T01 respectively (as shown in FIG. Fig.18 shown).

[0237] exist Fig.17 Among them, the line labeled V02 is a high voltage line providing a high voltage signal VGH, the line labeled V01 is a low voltage line providing a low voltage signal VGL; the line labeled K1 is a first clock signal line, the line labeled K2 is a second clock signal line, the line labeled K3 is a third clock signal line, and the line labeled K4 is a fourth clock signal line.

[0238] exist Fig.17 In the figure, the source of T9 is labeled S9, the drain of T01 includes a first drain pattern D011 and a second drain pattern D012, and the source of T01 includes a first source pattern S011 and a second source pattern S012: D011 is multiplexed as the drain of T9.

[0239] Fig. 20 is a stacked layer diagram after a first source-drain metal layer and a second source-drain metal layer are stacked, and a passivation layer and a first planarization layer may be sequentially arranged between the first source-drain metal layer and the second source-drain metal layer; Fig. 20 In the figure, the black rectangles and black dots represent via holes penetrating the passivation layer and the first planar layer.

[0240] When manufacturing the display substrate described in at least one embodiment of the present invention, firstly, a semiconductor material layer is arranged on the substrate, and the semiconductor material layer is patterned to form the active layer of each transistor; a first gate insulating layer is formed on the side of the active layer facing away from the substrate; a first gate metal layer is formed on the side of the first gate insulating layer facing away from the active layer, and the first gate metal layer is patterned to form the gate of each transistor in the driving circuit and the first electrode of each capacitor. Using the gate of each transistor as a mask, the portion of the active layer not covered by the gate is doped, so that the portion of the active layer not covered by the gate is formed into a conductive portion, and the portion of the active layer covered by the gate is formed into a channel portion; the conductive portion is used as a source or a drain; or the conductive portion is coupled to the source or the drain. A second gate insulating layer is formed on the side of the first gate metal layer facing away from the active layer, and a second gate metal layer is arranged on the side of the second gate insulating layer facing away from the first gate metal layer; the second gate metal layer is patterned to form the second electrode plate and the connecting conductive part of each capacitor in the driving circuit; and a first interlayer dielectric layer is arranged on the side of the second gate metal layer facing away from the second gate insulating layer. A plurality of vias are arranged on the substrate on which the active layer, the first gate insulating layer, the first gate metal layer, the second gate insulating layer, the second gate metal layer and the first interlayer dielectric layer are arranged. A third gate metal layer is arranged on the side of the first interlayer dielectric layer facing away from the second gate metal layer. The third gate metal layer is patterned to form a conductive connecting part L1. A second interlayer dielectric layer is arranged on the side of the third gate metal layer facing away from the first interlayer dielectric layer. A first source-drain metal layer is arranged on the side of the second interlayer dielectric layer facing away from the third gate metal layer, and the first source-drain metal layer is patterned to form various clock signal lines, various voltage lines, connecting conductive parts, the source of T9, the source of T01, and the drain of T01. A passivation layer and a planarization layer are sequentially arranged on the side of the first source-drain metal layer facing away from the second interlayer dielectric layer. A via hole is made on a substrate provided with an active layer, a first gate insulating layer, a first gate metal layer, a second gate insulating layer, a second gate metal layer, a first interlayer dielectric layer, a third gate metal layer, a second interlayer dielectric layer, a first source-drain metal layer, a passivation layer and a planarization layer. A second source-drain metal layer is arranged on the side of the planarization layer facing away from the first source-drain metal layer. A patterning process is performed on the second source-drain metal layer to form a connecting conductive portion.

[0241] The display device described in the embodiment of the present invention includes the above-mentioned display substrate.

[0242] The display device described in at least one embodiment of the present invention further includes a voltage providing circuit; the first voltage signal is a low voltage signal VGL, and the second voltage signal is a high voltage signal VGH;

[0243] The voltage providing circuit is used to provide a first voltage signal and a second voltage signal, and to control the difference between the second voltage value and the first voltage value to be greater than a predetermined difference;

[0244] The second voltage value is the voltage value of the second voltage signal, and the first voltage value is the voltage value of the first voltage signal;

[0245] When the potential of the clock signal provided by each clock signal line included in the driving circuit in the display substrate is a low voltage, the voltage value of the clock signal is a first voltage value;

[0246] When the potential of the clock signal provided by each clock signal line is a high voltage, the voltage value of the clock signal is a second voltage value.

[0247] The embodiment of the present invention increases the voltage difference between the voltage values ​​of VGH and VGL, so that when T01 needs to be turned off, the gate potential of T01 can turn off T01, so as to achieve normal output of the driving circuit and normal screen display.

[0248] In at least one embodiment of the present invention, the predetermined difference may be 14V, but is not limited thereto.

[0249] For example, when Figure 4 When at least one embodiment of the driving circuit shown is in operation, when the potential of N2 is a low voltage and T02 is turned on so that N1 is connected to the first clock signal provided by K1, then when the potential of the first clock signal is a high voltage, by increasing the voltage difference between the voltage value of the high voltage signal and the voltage value of the low voltage signal, T01 can be controlled to be better closed.

[0250] After simulation, when Figure 4 When at least one embodiment of the driving circuit shown is working, when the voltage value of VGH is 7V, the voltage value of VGL is -7V, and T01 is in PBTS (forward bias stress), the gate-source voltage of T01 is -8.24V, and the drain-source voltage of T01 is 2.98V; when the voltage value of VGH is 10V, the voltage value of VGL is -10V, and T01 is in PBTS (forward bias stress), the gate-source voltage of T01 is -13.65V, and the drain-source voltage of T01 is 0.99V.

[0251] The display device provided in the embodiment of the present invention can be any product or component with a display function, such as a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, a navigator, etc.

[0252] The above is a preferred embodiment of the present invention. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the principles of the present invention. These improvements and modifications should also be regarded as the scope of protection of the present invention.

Claims

1. A driving circuit comprising an output circuit, a first node reset circuit and a second node control capacitor; The output circuit is used to control the driving signal terminal to output a driving signal under the control of the potential of the first node; The first node reset circuit is used to control the resetting of the first node under the control of the potential of the second node; The second node control capacitor is electrically connected to the second node; The output circuit includes an output transistor whose width-to-length ratio is less than or equal to a first predetermined width-to-length ratio; and / or the first node reset circuit includes a first node reset transistor whose width-to-length ratio is greater than or equal to a second predetermined width-to-length ratio; and / or, the capacitance value of the second node control capacitor is greater than or equal to a predetermined capacitance value; The value range of the first predetermined width-to-length ratio is greater than or equal to 150 / 3.8 and less than or equal to 230 / 3.8, and the value range of the second predetermined width-to-length ratio is greater than or equal to 4 / 4.9 and less than or equal to 6 / 4.9; the value range of the predetermined capacitance value is greater than or equal to 143fF and less than or equal to 243fF; The driving circuit also includes a second node control circuit and a second node control capacitor; The second node control circuit is electrically connected to the third node, the seventh node, the second voltage line, the second node and the third clock signal line respectively, and is used to control the seventh node to be connected to the second voltage line under the control of the potential of the third node, and to control the seventh node to be connected to the third clock signal line under the control of the potential of the second node; The first plate of the second node control capacitor is electrically connected to the seventh node, and the second plate of the second node control capacitor is electrically connected to the second node.

2. The driving circuit according to claim 1, in, The first predetermined width-to-length ratio is 210 / 3.8, the second predetermined width-to-length ratio is 5 / 4.9, and the predetermined capacitance value is 243 fF.

3. The driving circuit according to claim 1 or 2, in, The control electrode of the output transistor is electrically connected to the first node, the first electrode of the output transistor is electrically connected to the first clock signal line, and the second electrode of the output transistor is electrically connected to the drive signal terminal; A control electrode of the first-node reset transistor is electrically connected to the second node, a first electrode of the first-node reset transistor is electrically connected to the first node, and a second electrode of the first-node reset transistor is electrically connected to the first clock signal line.

4. The driving circuit according to claim 1 or 2, in, The driving circuit further includes a third node control circuit, a fourth node control circuit, a fifth node control circuit, a first node control circuit and an output reset circuit; The third node control circuit is electrically connected to the second clock signal line, the first voltage line and the third node respectively, and is used to control the first voltage signal provided by the first voltage line to be written into the third node under the control of the second clock signal provided by the second clock signal line; The fourth node control circuit is electrically connected to the sixth node, the third clock signal line and the fourth node respectively, and is used to control the third clock signal line to write the third clock signal into the fourth node under the control of the potential of the sixth node, and control the potential of the fourth node according to the potential of the sixth node; The fifth node control circuit is electrically connected to the second clock signal line, the first clock signal line, the input terminal and the fifth node respectively, and is used to control the input terminal to provide an input signal to the fifth node under the control of the second clock signal provided by the second clock signal line and the first clock signal provided by the first clock signal line; The first node control circuit is electrically connected to the fourth node, the third clock signal line and the first node respectively, and is used to control the fourth node to be connected to the first node under the control of the third clock signal provided by the third clock signal line; The output reset circuit is electrically connected to the second node, the drive signal terminal and the first voltage line respectively, and is used to control the connection between the drive signal terminal and the first voltage line under the control of the potential of the second node.

5. The driving circuit according to claim 4, in, The third node and the sixth node are the same node; or, The driving circuit further includes a first conduction control circuit; the first conduction control circuit is used to control the connection between the third node and the sixth node under the control of a first voltage signal provided by a first voltage line.

6. The driving circuit according to claim 4, in, The fifth node and the second node are the same node; or, The driving circuit further includes a second conduction control circuit; the second conduction control circuit is used to control the connection between the fifth node and the second node under the control of a first voltage signal provided by a first voltage line.

7. The driving circuit according to claim 4, in, The third node control circuit includes a first transistor and a second transistor; The control electrode of the first transistor is electrically connected to the second clock signal line, the first electrode of the first transistor is electrically connected to the first voltage line, and the second electrode of the first transistor is electrically connected to the third node; The control electrode of the second transistor is electrically connected to the fifth node, the first electrode of the second transistor is electrically connected to the second clock signal line, and the second electrode of the second transistor is electrically connected to the third node; The fourth node control circuit includes a third transistor and a first capacitor; The control electrode of the third transistor is electrically connected to the sixth node, the first electrode of the third transistor is electrically connected to the third clock signal line, and the second electrode of the third transistor is electrically connected to the fourth node; The first plate of the first capacitor is electrically connected to the sixth node, and the second plate of the first capacitor is electrically connected to the fourth node; The fifth node control circuit includes a fourth transistor and a fifth transistor; The control electrode of the fourth transistor is electrically connected to the first clock signal line, and the first electrode of the fourth transistor is electrically connected to the input terminal; The control electrode of the fifth transistor is electrically connected to the second clock signal line, the first electrode of the fifth transistor is electrically connected to the second electrode of the fourth transistor, and the second electrode of the fifth transistor is electrically connected to the fifth node; The second node control circuit includes a sixth transistor and a seventh transistor; The control electrode of the sixth transistor is electrically connected to the third node, the first electrode of the sixth transistor is electrically connected to the second voltage line, and the second electrode of the sixth transistor is electrically connected to the seventh node; The control electrode of the seventh transistor is electrically connected to the second node, the first electrode of the seventh transistor is electrically connected to the third clock signal line, and the second electrode of the seventh transistor is electrically connected to the seventh node; The first node control circuit includes an eighth transistor and a second capacitor; The control electrode of the eighth transistor is electrically connected to the third clock signal line, the first electrode of the eighth transistor is electrically connected to the fourth node, and the second electrode of the eighth transistor is electrically connected to the first node; The first plate of the second capacitor is electrically connected to the first node, and the second plate of the second capacitor is electrically connected to the first clock signal line; The output reset circuit includes a ninth transistor; The control electrode of the ninth transistor is electrically connected to the second node, the first electrode of the ninth transistor is electrically connected to the first voltage line, and the second electrode of the ninth transistor is electrically connected to the driving signal terminal.

8. A display substrate, comprising the driving circuit according to any one of claims 1 to 7 arranged on a base.

9. The display substrate according to claim 8, in, The driving circuit includes an output circuit; the output circuit includes an output transistor; The active layer of the output transistor includes at least one first channel portion extending along a first direction; A sum of widths of the at least one first channel portion along the first direction is less than or equal to a first predetermined width, so that a width-to-length ratio of the output transistor is less than or equal to the first predetermined width-to-length ratio.

10. The display substrate according to claim 8, in, The driving circuit includes a first node reset circuit; the first node reset circuit includes a first node reset transistor; The active layer of the first node reset transistor includes at least one second channel portion; The sum of the widths of the at least one second channel portion along the second direction is greater than or equal to a second predetermined width, so that the width-to-length ratio of the first node reset transistor is greater than or equal to the second predetermined width-to-length ratio; The first direction intersects the second direction.

11. The display substrate according to claim 9 or 10, in, Also included are gate lines and data lines arranged in the display area; The gate line includes a portion extending along a first direction, and the data line includes a portion extending along a second direction.

12. The display substrate according to any one of claims 8 to 10, in, The driving circuit includes a second node control capacitor; the second node control capacitor includes a first electrode plate and a second electrode plate arranged in different layers; the first electrode plate and the second electrode plate are provided with an insulating layer; The orthographic projection of the first electrode plate on the substrate at least partially overlaps with the orthographic projection of the second electrode plate on the substrate, and the overlapping area between the orthographic projection of the first electrode plate on the substrate and the orthographic projection of the second electrode plate on the substrate is greater than or equal to a predetermined area, so that the capacitance value of the second node control capacitor is greater than or equal to the predetermined capacitance value.

13. A display device comprising the display substrate according to any one of claims 8 to 12.

14. The display device according to claim 13, in, It also includes a voltage providing circuit; the first voltage signal is a low voltage signal, and the second voltage signal is a high voltage signal; The voltage providing circuit is used to provide a first voltage signal and a second voltage signal, and to control the difference between the second voltage value and the first voltage value to be greater than a predetermined difference; The second voltage value is the voltage value of the second voltage signal, and the first voltage value is the voltage value of the first voltage signal; When the potential of the clock signal provided by each clock signal line included in the driving circuit in the display substrate is a low voltage, the voltage value of the clock signal is a first voltage value; When the potential of the clock signal provided by each clock signal line is a high voltage, the voltage value of the clock signal is a second voltage value.

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