Phase frequency detector based frequency multiplier using rising edge delay

Abstract

Certain aspects of the present disclosure generally relate to techniques and apparatus for frequency doubling of a signal. For example, certain aspects relate to phase frequency detector (PFD) based rising edge only delay frequency multiplication circuits. One example frequency multiplier circuit generally includes a first delay stage, a second delay stage, a first PFD, a first rising edge only adjustable delay unit, a second PFD, a second rising edge only adjustable delay unit, a logic gate, and a comparator configured to compare a direct current (DC) voltage value of an output of the logic gate to a reference voltage and to control the first and second rising edge only adjustable delay units based on the comparison.

Description

[0001] Cross Reference to Related Applications

[0002] This application claims the benefit of and priority to U.S. Nonprovisional Application No. 16 / 928,218, filed July 14, 2020, which is assigned to the assignee of the present application and expressly incorporated herein by reference in its entirety, as if fully set forth below, and for all purposes. TECHNICAL FIELD

[0003] Certain aspects of the present disclosure generally relate to electronic circuits, and more particularly to frequency multiplier circuits. BACKGROUND

[0004] Electronic devices such as computers, smartphones, tablets, and wearable devices often utilize different clock signals having different frequencies. Rather than generating these multiple clock signals separately from different crystal oscillators, it is often more cost effective and saves more space to generate the different clock signals from a single crystal oscillator (e.g., using a frequency synthesizer or other suitable clock generation and distribution circuitry). One example of such a clock circuit is a frequency multiplier that receives an input clock signal having an input frequency (f) and generates an output clock signal having an output frequency that is twice the input frequency (2f). SUMMARY

[0005] The systems, methods, and devices of the present disclosure each have several aspects, no single one of which is solely responsible for its desirable attributes. Without limiting the scope of this disclosure as expressed by the claims which follow, some features will now be discussed briefly. The detailed description, together with the drawings, will describe in further detail the features of the present disclosure and the manner in which they are implemented and used. After considering this discussion, and particularly after reading the section entitled “DETAILED DESCRIPTION” one will be able to appreciate the advantages and features of the disclosure that include providing precise clock signal frequency multiplication capabilities using adjustable delay units designed to be very linear, and having fine resolution only for rising edge delays.

[0006] Certain aspects of the present disclosure generally relate to a frequency multiplier. For certain aspects, the frequency multiplier is a phase frequency detector (PFD)-based rising edge only delay frequency multiplier.

[0007] Certain aspects of the present disclosure provide a frequency multiplier. The frequency multiplier generally includes a first delay stage having an input coupled to an input node of the frequency multiplier and a second delay stage having an input coupled to the input node. The frequency multiplier generally also includes a first PFD having a first input coupled to an output of the first delay stage, a first rising edge only adjustable delay cell having an input coupled to an output of the first delay stage and having an output coupled to a second input of the first PFD, a second PFD having a first input coupled to an output of the second delay stage, and a second rising edge only adjustable delay cell having an input coupled to an output of the second delay stage and having an output coupled to a second input of the second PFD. Further, the frequency multiplier generally includes a logic gate having a first input coupled to an output of the first PFD and having a second input coupled to an output of the second PFD. The frequency multiplier generally also includes a comparator configured to compare a direct current (DC) voltage value of an output of the logic gate to a reference voltage and to control the first rising edge only adjustable delay cell and the second rising edge only adjustable delay cell based on the comparison.

[0008] Certain aspects of the present disclosure provide a half-rate clock generator. The half-rate clock generator generally includes a frequency multiplier described herein.

[0009] Certain aspects of the present disclosure relate to a method for doubling a frequency of an input clock signal. The method generally includes delaying the input clock signal by a first delay to generate a delayed clock signal, inverting and delaying the input clock signal by a second delay to generate a complementary delayed clock signal, applying a first adjustable delay to only a rising edge of the delayed clock signal to generate a first rising edge delayed clock signal, applying a second adjustable delay to only a rising edge of the complementary delayed clock signal to generate a second rising edge delayed clock signal, determining a difference between a rising edge of the delayed clock signal and a rising edge of the first rising edge delayed clock signal to generate a first rising edge difference signal, determining a difference between a rising edge of the complementary delayed clock signal and a rising edge of the second rising edge delayed clock signal to generate a second rising edge difference signal, combining the first rising edge difference signal and the second rising edge difference signal to generate a combined signal, comparing a DC voltage value of the combined signal to a reference voltage, and controlling the first adjustable delay and the second adjustable delay based on the comparison.

[0010] Certain aspects of the present disclosure provide an apparatus for doubling a frequency of an input clock signal. The apparatus generally includes means for delaying the input clock signal by a first delay to generate a delayed clock signal; means for inverting and delaying the input clock signal by a second delay to generate a complementary delayed clock signal; means for applying a first adjustable delay to only a rising edge of the delayed clock signal to generate a first rising edge delayed clock signal; means for applying a second adjustable delay to only a rising edge of the complementary delayed clock signal to generate a second rising edge delayed clock signal; means for determining a difference between the rising edge of the delayed clock signal and the rising edge of the first rising edge delayed clock signal to generate a first rising edge difference signal; means for determining a difference between the rising edge of the complementary delayed clock signal and the rising edge of the second rising edge delayed clock signal to generate a second rising edge difference signal; means for combining the first rising edge difference signal and the second rising edge difference signal to generate a combined signal; means for comparing a DC voltage value of the combined signal to a reference voltage; and means for controlling the first adjustable delay and the second adjustable delay based on the comparison.

[0011] To the accomplishment of the foregoing and related ends, one or more aspects comprise the features hereinafter fully described and particularly pointed out in the claims. The following description and the annexed drawings set forth in detail certain illustrative features of the one or more aspects. These features are indicative, however, of but a few of the various ways in which principles of various aspects can be employed. BRIEF DESCRIPTION OF DRAWINGS

[0012] In order to enable a thorough and complete understanding of the above-described features, a more detailed description can be had by referring to some aspects as shown in the drawings. It is emphasized that the drawings are for illustrative purposes only and are not intended to limit the scope of the disclosure in any way. The description that follows can be best understood in conjunction with the annexed drawings as follows:

[0013] Figure 1 An exemplary frequency doubling circuit is shown in accordance with certain aspects of the present disclosure.

[0014] Figure 2 is a timing diagram showing signal waveforms of a frequency doubling circuit in accordance with certain aspects of the present disclosure. Figure 1

[0015] Figure 3 is a flowchart of exemplary operations for doubling a frequency of a clock signal in accordance with certain aspects of the present disclosure.

[0016] For purposes of clarity, the same reference numbers will be used in the description of the drawings to indicate the same or similar elements. Aspects disclosed in one aspect can be beneficially incorporated into other aspects without specific recitation. DETAILED DESCRIPTION​

[0017] Certain aspects of the present disclosure generally relate to techniques and apparatuses for frequency doubling of a signal. For example, certain aspects relate to phase frequency detector (PFD) based rising edge only delay frequency doubling circuits.

[0018] Example frequency doubling circuits

[0019] Conventionally, frequency doubling circuits can require very linear and fine resolution delay cells for both rising and falling edge delays. However, the design or implementation of such delay cells can be very challenging and / or cost prohibitive. For example, current starved or source delay cells can only be most effective for rising edge or falling edge delays, not both.

[0020] Accordingly, certain aspects of the present disclosure provide techniques and apparatuses for frequency doubling of an input signal using multiple PFDs to implement rising edge only delay.

[0021] Figure 1 An exemplary frequency doubling circuit 100 (also referred to as a “frequency doubler”) configured to frequency double an input signal is shown in accordance with certain aspects of the present disclosure. For example, the circuit 100 can receive an input clock signal 104 having a first frequency (f) and generate an output clock signal 134 having a second frequency that is twice the first frequency (2f). The input clock signal 104 can be generated by a phase-locked loop (PLL), for example, of a frequency synthesizer. The output clock signal 134 can have a 50% duty cycle or any other desired duty cycle. The frequency doubling circuit 100 can include a first delay stage 101, a second delay stage 102, a first delay cell 112, a second delay cell 114, a first phase frequency detector (PFD) 116, and a second PFD 118. The frequency doubling circuit 100 can also include a logic gate 120, a filter 122, and a comparator 124.

[0022] The first delay stage 101 can be coupled between an input node 128 of the circuit 100 and a node 130. For example, the first delay stage 101 can be implemented by a plurality of series connected inverters, such as inverters 106A, 106B (collectively referred to as “inverters 106”), where each inverter contributes to the delay of the input clock signal 104. The first delay stage 101 can have an even number of inverters (e.g., two inverters) such that an output signal (labeled “clk_rising”) from the first delay stage can be a delayed version of the input clock signal 104 with a corresponding rising edge.

[0023] The second delay stage 102 can be coupled between the input node 128 and a node 132. For example, the second delay stage 102 can be implemented by a transmission gate 108 connected in series with an inverter 110, as shown inFigure 1 As shown. The combination of transmission gate 108 and inverter 110 can delay and invert the input clock signal 104. Transmission gate 108 can have a delay similar to the delay of inverter 110 and can be implemented using the same technology as the inverter (e.g., complementary metal oxide semiconductor (CMOS) delay elements and CMOS inverters). The second delay stage 102 can have an odd number of inverters (e.g., one inverter), which can be one less than the number of inverters in the first delay stage 101, so that the output signal from the second delay stage (labeled "clk_falling") can be a delayed inverted version of the input clock signal 104 with a falling edge corresponding to the rising edge of the clk_rising signal and a rising edge corresponding to the falling edge of the clk_rising signal, as shown. Figure 2 In other words, clk_rising and clk_falling may be complementary signals.

[0024] The output of the first delay stage 101 can be coupled to a first input of the first PFD 116 via node 130 and to the first delay unit 112 via node 130. The first delay unit 112 can be an adjustable delay unit, which in some cases can be a rising-edge-only adjustable delay unit, meaning that the delay unit applies an adjustable delay (labeled "rising_dly") only to the rising edge of an input signal (e.g., clk_rising), but leaves the falling edge of the input signal unchanged to generate a rising-edge-only delayed output signal (labeled "clk_rising_dly"). The output of the first delay unit 112 is coupled to a second input of the first PFD 116.

[0025] Similarly, the output of the second delay stage 102 can be coupled to a first input of the second PFD 118 via node 132 and to the second delay unit 114 via node 132. The second delay unit 114 can be an adjustable delay unit, which in some cases can be a rising-edge-only adjustable delay unit that applies an adjustable delay (labeled “rising_dly”) only to the rising edge of an input signal (e.g., clk_falling) to generate an output signal (labeled “clk_falling_dly”) that is only delayed by the rising edge. The output of the second delay unit 114 is coupled to a second input of the second PFD 118.

[0026] The first PFD 116 can be configured to determine the phase difference between a signal on a first input (e.g., clk_rising) and a delayed signal on a second input (e.g., clk_rising_dly). The output signal from the first PFD 116 (labeled "rpulse") represents the phase difference (e.g., the timing difference between the corresponding rising edges of clk_rising and clk_rising_dly) and can be considered as a series of rising edge difference pulses.

[0027] Similarly, the second PFD 118 can be configured to determine the phase difference between the signal on the first input (e.g., clk_falling) and the delayed signal on the second input (e.g., clk_falling_dly). The output signal from the second PFD 118 (labeled "fpulse") represents the phase difference (e.g., the timing difference between the corresponding rising edges of clk_falling and clk_falling_dly) and can be considered as a series of rising edge difference pulses.

[0028] The outputs of the first PFD 116 and the second PFD 118 can be coupled to inputs of a logic gate 120. The logic gate 120 can be, for example, an OR gate, an exclusive OR (XOR) gate, or any other suitable logic gate type. In some aspects, the logic gates can be replaced with logic circuits (e.g., having a plurality of logic gates) configured to perform logic operations on at least the signals rpulse and fpulse. The logic gate 120 can be configured to provide an output signal (labeled “clk_dbler”) to an output node 126, such that the output of the logic gate 120 can provide an output clock signal 134 for the frequency multiplication circuit 100. In some aspects, the output clock signal 134 (clk 2f ) can be the frequency of the input clock signal 104 (clk f ) twice the frequency.

[0029] The output of logic gate 120 may also be coupled to the input of filter 122. In some aspects, filter 122 may be a low-pass filter and may be implemented by one or more resistor-capacitor stages. In this case, the output signal (clk_dbler) from logic gate 120 may be converted to a DC value via filter 122 based on the duty cycle of the clk_dbler signal. The output of filter 122 may be coupled to a first input of comparator 124, while the second input of the comparator is coupled to a node having a reference voltage (Vref). For example, Vref may be 0.5 Vdd, where Vdd is a power rail voltage used to power various components such as logic gate 120 (and comparator 124). In some aspects, Vref may be greater than 0.5 Vdd, or alternatively, less than 0.5 Vdd, depending on the desired duty cycle of the clk_dbler signal.

[0030] The comparator 124 may also be configured to output a control signal (labeled “rising_dly”) via a control line 125 (e.g., a control bus) such that the output of the comparator is coupled to the control inputs of the first delay unit 112 and the second delay unit 114. The output of the comparator 124 may be 8 bits, such as Figure 1 As shown. In other aspects, the output of comparator 124 can be any of a variety of suitable bit lengths. The value of the control signal is a function of the difference between the filtered input from 122 and Vref (which can represent the duty cycle difference between the clk_dbler signal and the representative duty cycle of Vref). For example, the first input can be 0.45Vdd (representing a clk_dbler duty cycle of 45%), while Vref = 0.5Vdd (representing a desired duty cycle of 50%). This difference can cause comparator 124 to adjust the value of the control signal, thereby causing the duty cycle of the clk_dbler signal to increase (e.g., by increasing the adjustable delay of the first delay unit 112 and the second delay unit 114). In this way, filter 122, comparator 124 and the adjustable delay unit act as a feedback mechanism for the frequency multiplication circuit 100.

[0031] Figure 2 is a diagram illustrating certain aspects of the present disclosure. Figure 1 A timing diagram 200 of various signal waveforms of the frequency multiplication circuit 100 is shown. As shown, the clk_rising signal is shown as having a duty cycle of approximately 50% at a particular frequency (f). As shown, the clk_falling signal is an inverted version of the clk_rising signal. The clk_falling signal can be generated by inverting (and delaying) the input clock signal 104 via the second delay stage 102 (e.g., inverter 110).

[0032] As shown, the clk_rising_dly signal has the same falling edge timing as the clk_rising signal (e.g., time 206). However, the clk_rising_dly signal has a rising edge (e.g., time 204) that occurs later than the rising edge (e.g., time 202) of the clk_rising signal. Further, as shown, the clk_falling_dly signal has the same falling edge timing as the clk_falling signal (e.g., time 210). However, the clk_falling_dly signal has a rising edge (e.g., time 208) that occurs later than the rising edge (e.g., time 206) of the clk_falling signal.

[0033] As shown, the rpulse signal represents the difference between the rising edges of the clk_rising and clk_rising_dly signals (e.g., time 202 to time 204) as determined by the first PFD 116. Similarly, as shown, the fpulse signal represents the difference between the rising edges of the clk_falling and clk_falling_dly signals (e.g., time 206 to time 208) as determined by the second PFD 118.

[0034] As shown, the clk_dbler signal can represent the output of performing a logical operation (OR or XOR) on the rpulse and fpulse signals, such that the rpulse signal and the fpulse signal can be effectively combined. In this way, the frequency of the clk_dbler signal is twice the frequency of the clk_rising signal.

[0035] Example frequency doubling method

[0036] Figure 3 is a flow diagram of example operations 300 for doubling the frequency of an input clock signal in accordance with certain aspects of the present disclosure. The operations 300 can be performed by a frequency doubler, such as the frequency doubler circuit 100 of Figure 1 .

[0037] The operations 300 can begin, at block 305, with the frequency doubler delaying an input clock signal (e.g., the input clock signal 104) by a first delay (e.g., via the first delay stage 101) to generate a delayed clock signal (e.g., clk_rising). At block 310, the frequency doubler can invert and delay the input clock signal by a second delay (e.g., via the second delay stage 102) to generate a complementary delayed clock signal (e.g., clk_falling).

[0038] At block 315, the frequency multiplier can apply the first adjustable delay (e.g., rising_dly of the first delay unit 112) to only the rising edge of the delayed clock signal to generate a first rising edge delayed clock signal (e.g., clk_rising_dly). At block 320, the frequency multiplier can apply the second adjustable delay (e.g., rising_dly of the second adjustable delay unit 114) to only the rising edge of the complementary delayed clock signal to generate a second rising edge delayed clock signal (e.g., clk_falling_dly).

[0039] At block 325, the frequency multiplier can determine a difference between the rising edge of the delayed clock signal and the rising edge of the first rising edge delayed clock signal (e.g., via the first PFD 116) to generate a first rising edge difference signal (e.g., rpulse). At block 330, the frequency multiplier can determine a difference between the rising edge of the complementary delayed clock signal and the rising edge of the second rising edge delayed clock signal (e.g., via the second PFD 118) to generate a second rising edge difference signal (e.g., fpulse).

[0040] The frequency multiplier can combine the first rising edge difference signal and the second rising edge difference signal at block 335 to generate a combined signal (e.g., clk_dbler). The frequency of the combined signal can be twice the frequency of the input clock signal. In certain aspects, the combined signal has a 50% duty cycle.

[0041] For certain aspects, the frequency multiplier compares a direct current (DC) voltage value of the combined signal to a reference voltage (e.g., 0.5*Vdd) at block 340. In this case, the frequency multiplier can control the first adjustable delay and / or the second adjustable delay based on the comparison (e.g., with the comparator 124) at block 345.

[0042] According to certain aspects, delaying the input clock signal by the first delay at block 305 can require inverting the input clock signal and inverting the inverted clock signal to generate the delayed clock signal. For example, the input clock signal 104 can be processed by two inverters 106. For certain aspects, inverting the input clock signal and delaying the input clock signal by the second delay at block 310 includes delaying the input clock signal with a transmission gate and inverting the delayed input clock signal to generate the complementary delayed clock signal. For example, the input clock signal 104 can be processed by a transmission gate 108 and an inverter 110.

[0043] According to certain aspects, determining the difference between the rising edge of the delayed clock signal and the rising edge of the first rising edge delayed clock signal at block 325 includes generating a first rising edge difference signal (e.g., rpulse) from the delayed clock signal (e.g., clk rising) and the first rising edge delayed clock signal (e.g., clk rising dly) using the first PFD (e.g., first PFD 116). According to certain aspects, determining the difference between the rising edge of the complementary delayed clock signal and the rising edge of the second rising edge delayed clock signal at block 430 includes generating a second rising edge difference signal (e.g., fpulse) from the complementary delayed clock signal (e.g., clk falling) and the second rising edge delayed clock signal (e.g., clk falling dly) using the second PFD (e.g., second PFD 118).

[0044] According to certain aspects, combining the first rising edge difference signal and the second rising edge difference signal at block 335 requires using an XOR logic gate (e.g., logic gate 120) to generate a combined signal (e.g., clk dbler) from the first rising edge difference signal and the second rising edge difference signal.

[0045] According to certain aspects, the operations 300 can further include low pass filtering (e.g., with filter 122) the combined signal to generate a DC voltage value of the combined signal.

[0046] CONCLUSION

[0047] Certain aspects of the present disclosure provide a frequency multiplier that can be a PFD-based rising edge only delay frequency multiplier. Such a frequency multiplier can detect the edge difference between two delayed signals with a PFD, combine (e.g., add) the rising edge delayed PFD result with the falling edge delayed PFD result, take the DC value of the combined signal (with a low pass filter), and compare that DC value to a voltage reference (Vdd / 2). The frequency multiplier can then adjust the rising edge delay based on the comparison. In this way, the frequency multiplier can operate with high performance in a rising edge only delay environment, and can use a delay cell that is designed to be very linear, and has fine resolution on only the rising edge, not both the rising and falling edges.

[0048] In this disclosure, the word "exemplary" is used to mean "serving as an example, instance, or illustration." Any implementation or aspect described herein as "exemplary" is not necessarily to be construed as preferred or advantageous over other aspects of the disclosure. Likewise, the term "aspect" does not require that all aspects of the disclosure include the feature, advantage, or mode of operation discussed. The term "coupled" is used herein to refer to a direct or indirect coupling between two objects. For example, if object A physically contacts object B and object B contacts object C, then objects A and C may still be considered to be coupled to each other even if objects A and C are not in direct physical contact with each other. For example, a first object may be coupled to a second object even if the first object has never been in direct physical contact with the second object. The terms "circuit" and "circuitry" are used broadly and are intended to include hardware implementations of electrical devices and conductors that, when connected and configured, are capable of performing the functions described in this disclosure, without limitation as to the type of electronic circuitry.

[0049] The apparatus and methods described in the detailed description are illustrated in the accompanying drawings by various blocks, modules, components, circuits, steps, processes, algorithms, etc. (collectively referred to as "elements"). These elements can be implemented using, for example, hardware. For example, a component for delaying can include a delay element, such as an inverter (e.g., Figure 1 Inverter 106 or inverter 110 as shown), a transmission gate (e.g., Figure 1 108) or a delay unit (e.g., as shown in FIG. Figure 1 The first delay unit 112 or the second delay unit 114 shown). The component for inverting may include an inverter (e.g., Figure 1 The components for applying the delay may include a delay unit (e.g., an inverter 106 or an inverter 110). Figure 1 The first delay unit 112 or the second delay unit 114 shown). The means for determining the difference may include a phase detector, such as a phase frequency detector (PFD) (e.g., as Figure 1 The first PFD 116 or the second PFD 118 shown). The means for combining may include a combiner, an adder, or a logic gate (e.g., as shown in FIG. Figure 1 Logic gate 122 shown). The means for comparing may include a comparator (e.g., Figure 1 The means for controlling may include one or more control signals sent on one or more control lines (e.g., a control line 125 having a rising_dly signal, such as Figure 1 ). The means for generating may include any of a variety of suitable circuits for setting the voltage, such as a reference voltage generator, a Zener diode, a voltage divider, a buffer, a voltage regulator, and the like.

[0050] One or more of the components, steps, features and / or functions illustrated herein can be rearranged and / or combined into a single component, step, feature or function or embodied in several components, steps, or functions. Additional elements, components, steps, and / or functions can also be added to the disclosed methods and apparatuses. The apparatuses, devices, and / or components illustrated herein can be configured to perform one or more of the methods, features, or steps described herein.

[0051] It should be understood that the particular order in which the steps in the disclosed methods have been presented and / or described is merely exemplary and / or is for assistance in reducing the methods to practice. It is understood that, based upon design choices, the particular order or hierarchy of steps in methods can be re-arranged without departing from the disclosed subject matter. The accompanying method claims present elements of the various steps in a sample order, and are not meant to be limited to the specific order or hierarchy presented.

[0052] The previous description is provided to enable any person skilled in the art to practice the various aspects described herein. Various modifications to these aspects will be readily apparent to those skilled in the art, and the generic principles defined herein can be applied to other aspects. Thus, the claims are not intended to be limited to the aspects presented herein, but is to be accorded the full scope consistent with the language of the claims, wherein reference to an element in the singular is not intended to mean "one and only one" unless specifically so stated, but rather "one or more." Unless specifically stated otherwise, the term "some" refers to one or more. Phrases such as "at least one of' or "one or more of' a list followed by a term such as "may encompass" one or more of the items in the list- For example, "at least one of a, b, and c" can encompass, for example, a, b, c, a-b, a-c, b-c, and a-b-c or any combination of the elements set forth with multiples of one of the elements (e.g., a-a, a-a-a, a-a-b, a-a-c, a-b-b, a-c-c, b-b, b-b-b, b-b-c, c-c, and c-c-c or any other ordering of a, b, and c). All structural and functional equivalents to the elements of the various aspects described throughout this disclosure that are known or later come to be known to those of ordinary skill in the art are expressly incorporated herein by reference and intended to be encompassed by the claims. Moreover, nothing disclosed herein is intended to be dedicated to the public regardless of whether such disclosure is explicitly recited in the claims. No claim element is to be construed under the provisions of 35 U.S.C. § 112(f) unless the element is expressly recited in the claim as a means plus function. The terms "program," "software program," "software," "application," variants thereof, and like terms generally refer to sequence of instructions designed for execution on a computer or computer implementation, and can refer to programs, services, techniques, or methodologies.

[0053] It is to be understood that the claims are not limited to the precise arrangements and components described above. Various modifications, changes, and variations can be made in the arrangement, operation, and details of the methods and apparatuses described herein without departing from the scope of the claims.

Claims

1. A frequency multiplier, comprising: a first delay stage having an input coupled to an input node of the frequency multiplier; a second delay stage having an input coupled to the input node; a first phase frequency detector (PFD) having a first input coupled to the output of the first delay stage; a first rising-edge-only adjustable delay cell having an input coupled to the output of the first delay stage and having an output coupled to a second input of the first PFD; a second PFD having a first input coupled to the output of the second delay stage; a second rising-edge-only adjustable delay cell having an input coupled to the output of the second delay stage and having an output coupled to a second input of the second PFD; a logic gate having a first input coupled to an output of the first PFD and having a second input coupled to an output of the second PFD; as well as Comparator, configured as: comparing a direct current (DC) voltage value of an output of the logic gate with a reference voltage; as well as The first rising-edge-only adjustable delay unit and the second rising-edge-only adjustable delay unit are controlled based on the comparison.

2. The frequency multiplier of claim 1 , further comprising a low-pass filter having an input coupled to the output of the logic gate and an output coupled to the input of the comparator, the low-pass filter configured to generate the DC value of the output of the logic gate.

3. The frequency multiplier of claim 1, wherein the logic gate comprises an exclusive-OR (XOR) logic gate.

4. The frequency multiplier of claim 1 , wherein the first delay stage comprises: a first inverter having an input coupled to the input node; as well as A second inverter has an input coupled to the output of the first inverter and has an output coupled to the output of the first delay stage.

5. The frequency multiplier of claim 4, wherein the second delay stage comprises a transmission gate and an inverter.

6. The frequency multiplier according to claim 5, wherein: An input of the transmission gate is coupled to the input node; The output of the transmission gate is coupled to the input of the inverter; and The output of the inverter is coupled to the output of the second delay stage.

7. The frequency multiplier of claim 1, wherein the reference voltage is half of a power rail voltage used to power the logic gates. 8 . The frequency multiplier of claim 1 , wherein an output of the comparator is coupled to a control input of the first rising-edge-only adjustable delay unit and a control input of the second rising-edge-only adjustable delay unit.

9. The frequency multiplier of claim 1, wherein the output of the comparator comprises an 8-bit output.

10. The frequency multiplier of claim 1, wherein the output of the logic gate is an output node of the frequency multiplier.

11. A half-rate clock generator comprising the frequency multiplier according to claim 1.

12. A method for doubling the frequency of an input clock signal, the method comprising: delaying the input clock signal by a first delay to generate a delayed clock signal; inverting and delaying the input clock signal by a second delay to generate a complementary delayed clock signal; applying a first adjustable delay only to a rising edge of the delayed clock signal to generate a first rising-edge delayed clock signal; applying a second adjustable delay only to the rising edge of the complementary delayed clock signal to generate a second rising-edge delayed clock signal; determining a difference between a rising edge of the delayed clock signal and a rising edge of the first rising-edge delayed clock signal to generate a first rising-edge difference signal; determining a difference between a rising edge of the complementary delayed clock signal and a rising edge of the second rising-edge delayed clock signal to generate a second rising-edge difference signal; combining the first rising edge difference signal and the second rising edge difference signal to generate a combined signal; comparing a direct current (DC) voltage value of the combined signal with a reference voltage; as well as The first adjustable delay and the second adjustable delay are controlled based on the comparison.

13. The method of claim 12, wherein delaying the input clock signal by the first delay comprises: The input clock signal is inverted and an inverted clock signal is inverted to generate the delayed clock signal.

14. The method of claim 13, wherein inverting the input clock signal and delaying the second delay comprises: The input clock signal is delayed using a transmission gate and the delayed input clock signal is inverted to generate the complementary delayed clock signal.

15. The method of claim 12, wherein: Determining the difference between the rising edge of the delayed clock signal and the rising edge of the first rising-edge delayed clock signal includes: generating the first rising-edge difference signal from the delayed clock signal and the first rising-edge delayed clock signal using a first phase frequency detector (PFD); and Determining the difference between the rising edge of the complementary delayed clock signal and the rising edge of the second rising-edge delayed clock signal includes generating the second rising-edge difference signal from the complementary delayed clock signal and the second rising-edge delayed clock signal using a second PFD.

16. The method of claim 12, wherein combining the first rising edge difference signal and the second rising edge difference signal comprises: The combined signal is generated from the first rising edge difference signal and the second rising edge difference signal using an exclusive OR (XOR) logic gate.

17. The method according to claim 12, further comprising: The combined signal is low-pass filtered to generate the DC voltage value of the combined signal.

18. The method of claim 12, wherein the combined signal has a 50% duty cycle and a frequency twice that of the input clock signal.

19. An apparatus for doubling the frequency of an input clock signal, the apparatus comprising: means for delaying the input clock signal by a first delay to generate a delayed clock signal; means for inverting and delaying the input clock signal by a second delay to generate a complementary delayed clock signal; means for applying a first adjustable delay to only the rising edge of the delayed clock signal to generate a first rising-edge delayed clock signal; means for applying a second adjustable delay to only the rising edge of the complementary delayed clock signal to generate a second rising-edge delayed clock signal; means for determining a difference between a rising edge of the delayed clock signal and a rising edge of the first rising-edge delayed clock signal to generate a first rising-edge difference signal; means for determining a difference between a rising edge of the complementary delayed clock signal and a rising edge of the second rising-edge delayed clock signal to generate a second rising-edge difference signal; means for combining the first rising edge difference signal and the second rising edge difference signal to generate a combined signal; means for comparing a direct current (DC) voltage value of the combined signal with a reference voltage; as well as Means for controlling the first and second adjustable delays based on the comparison.

20. The apparatus according to claim 19, further comprising: means for generating said DC voltage value of said combined signal.

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