Ultrasonic circuit, ultrasonic imaging device and driving method thereof

Abstract

The present invention discloses an ultrasonic circuit, an ultrasonic imaging device and a driving method thereof, comprising: an ultrasonic sensor configured to transmit an ultrasonic signal, receive a reflected ultrasonic signal, and convert the received ultrasonic signal into a first electrical signal; a first control circuit configured to initialize a first node and the ultrasonic sensor respectively, receive the first electrical signal, and transmit the first electrical signal to the first node; a second control circuit configured to transmit a second electrical signal related to curvature to a read signal terminal, and transmit a third electrical signal related to the first electrical signal to the read signal terminal based on the first electrical signal of the first node.

Description

Technical Field

[0001] The present invention relates to the technical field of ultrasonic imaging, and in particular to an ultrasonic circuit, an ultrasonic imaging device and a driving method thereof. Background Art

[0002] Ultrasound (US) medicine is a combination of acoustics, medicine, optics, and electronics. Ultrasound imaging uses ultrasound to scan the human body, receiving and processing the reflected ultrasound signals to obtain images of internal organs. Summary of the Invention

[0003] An ultrasonic circuit provided by an embodiment of the present invention includes:

[0004] an ultrasonic sensor configured to transmit an ultrasonic signal, receive a reflected ultrasonic signal, and convert the received ultrasonic signal into a first electrical signal;

[0005] a first control circuit configured to respectively initialize the first node and the ultrasonic sensor, receive the first electrical signal, and transmit the first electrical signal to the first node;

[0006] The second control circuit is configured to transmit a second electrical signal related to the curvature to a read signal terminal, and transmit a third electrical signal related to the first electrical signal to the read signal terminal according to the first electrical signal of the first node.

[0007] In some possible implementations, the second control circuit includes: a first sub-control circuit and a second sub-control circuit;

[0008] The first sub-control circuit is coupled to the first node, the first reference voltage signal terminal, and the first control signal terminal respectively; the first sub-control circuit is configured to provide a fourth electrical signal related to the curvature to the first node in response to a signal at the first control signal terminal;

[0009] The second sub-control circuit is coupled to the first reference voltage signal terminal, the first node, the read signal terminal and the second control signal terminal respectively; the second sub-control circuit is configured to transmit the second electrical signal related to the fourth electrical signal to the read signal terminal according to the fourth electrical signal of the first node, and to transmit the third electrical signal related to the first electrical signal to the read signal terminal according to the first electrical signal of the first node.

[0010] In some possible implementations, the first sub-control circuit includes: a first transistor and a strain resistor;

[0011] The gate of the first transistor is coupled to the first control signal terminal, the first electrode of the first transistor is coupled to the strain resistor, and the second electrode of the first transistor is coupled to the first node;

[0012] A first electrode of the strain resistor is coupled to the first reference voltage signal terminal, and a second electrode of the strain resistor is coupled to the first electrode of the first transistor.

[0013] In some possible implementations, the second sub-control circuit includes: a second transistor, a third transistor, and a storage capacitor;

[0014] The gate of the second transistor is coupled to the first node, the first electrode of the second transistor is coupled to the first reference voltage signal terminal, and the second electrode of the second transistor is coupled to the first electrode of the third transistor;

[0015] The gate of the third transistor is coupled to the second control signal terminal, and the second electrode of the third transistor is coupled to the read signal terminal;

[0016] A first electrode of the storage capacitor is coupled to the first reference voltage signal terminal, and a second electrode of the storage capacitor is coupled to the first node.

[0017] In some possible implementations, the second control circuit includes: a first sub-control circuit and a second sub-control circuit;

[0018] The first sub-control circuit is coupled to the first reference voltage signal terminal, the first control signal terminal, and the read signal terminal respectively; the first sub-control circuit is configured to provide a second electrical signal related to the curvature to the read signal terminal in response to a signal at the first control signal terminal;

[0019] The second sub-control circuit is coupled to the first reference voltage signal terminal, the first node, the second control signal terminal and the read signal terminal respectively; the second sub-control circuit is configured to transmit the third electrical signal related to the first electrical signal to the read signal terminal according to the first electrical signal of the first node.

[0020] In some possible implementations, the first sub-control circuit includes: a first transistor and a strain resistor;

[0021] The gate of the first transistor is coupled to the first control signal terminal, the first electrode of the first transistor is coupled to the strain resistor, and the second electrode of the first transistor is coupled to the read signal terminal;

[0022] A first electrode of the strain resistor is coupled to the first reference voltage signal terminal, and a second electrode of the strain resistor is coupled to the first electrode of the first transistor.

[0023] In some possible implementations, the second sub-control circuit includes: a second transistor, a third transistor, and a storage capacitor;

[0024] The gate of the second transistor is coupled to the first node, the first electrode of the second transistor is coupled to the first reference voltage signal terminal, and the second electrode of the second transistor is coupled to the first electrode of the third transistor;

[0025] The gate of the third transistor is coupled to the second control signal terminal, and the second electrode of the third transistor is coupled to the read signal terminal;

[0026] A first electrode of the storage capacitor is coupled to the first reference voltage signal terminal, and a second electrode of the storage capacitor is coupled to the first node.

[0027] In some possible implementations, the first control circuit is configured to provide a signal from the second reference voltage signal terminal to the second node in response to a third control signal terminal, and to connect the ultrasonic sensor and the second node to the first node in response to a fourth control signal terminal.

[0028] In some possible implementations, the first control circuit includes: a fourth transistor and a fifth transistor;

[0029] The gate of the fourth transistor is coupled to the third control signal terminal, the first electrode of the fourth transistor is coupled to the second node, and the second electrode of the fourth transistor is coupled to the second reference voltage signal terminal;

[0030] A gate of the fifth transistor is coupled to the fourth control signal terminal, a first electrode of the fifth transistor is coupled to the second node and the ultrasonic sensor, and a second electrode of the fifth transistor is coupled to the first node.

[0031] In some possible implementations, the first control circuit further includes: a sixth transistor, the ultrasonic sensor being coupled to the second node via the sixth transistor;

[0032] A gate of the sixth transistor is coupled to the fifth control signal terminal, a first electrode of the sixth transistor is coupled to the ultrasonic sensor, and a second electrode of the sixth transistor is coupled to the second node.

[0033] An ultrasonic imaging device provided by an embodiment of the present invention includes: a flexible substrate having a plurality of pixels thereon, each pixel including the ultrasonic circuit described above;

[0034] The plurality of pixels are divided into a plurality of pixel groups, each of the pixel groups includes a plurality of adjacent pixels; each of the pixel groups includes a first pixel and a second pixel;

[0035] The strain resistor of the ultrasonic circuit in the first pixel is a first type strain resistor, and the first type strain resistor is configured to deform when the flexible substrate is bent along the row direction of the pixel, thereby adjusting the magnitude of the current flowing through the first type strain resistor;

[0036] The strain resistor of the ultrasonic circuit in the second pixel is a second type strain resistor, which is configured to deform when the flexible substrate is bent along the column direction of the pixels to adjust the magnitude of the current flowing through the second type strain resistor.

[0037] In some possible implementations, each of the pixel groups includes two pixels adjacent to each other along the column direction;

[0038] The strain resistors in the pixels of the odd-numbered rows are strain resistors of the first type, and the strain resistors in the pixels of the even-numbered rows are strain resistors of the second type;

[0039] Alternatively, the strain resistors in the pixels in the even-numbered rows are strain resistors of the first type, and the strain resistors in the pixels in the odd-numbered rows are strain resistors of the second type;

[0040] Alternatively, the strain resistors in the odd-numbered rows of pixels are arranged alternately in the order of the first type of strain resistors and the second type of strain resistors, and the strain resistors in the even-numbered rows of pixels are arranged alternately in the order of the second type of strain resistors and the first type of strain resistors;

[0041] Alternatively, the strain resistors in the odd-numbered rows of pixels are arranged alternately in the order of the second type of strain resistors and the first type of strain resistors, and the strain resistors in the even-numbered rows of pixels are arranged alternately in the order of the first type of strain resistors and the second type of strain resistors.

[0042] In some possible implementations, the pixel has a first side and a second side disposed opposite to each other along the row direction, and a third side and a fourth side disposed opposite to each other along the column direction;

[0043] The first type of strain resistors in the odd-numbered columns of pixels are located on the first side, and the first type of strain resistors in the even-numbered columns of pixels are located on the second side;

[0044] And / or, the second type strain resistors in each column of pixels are located on the fourth side, or the second type strain resistors in odd columns of pixels are located on the fourth side, and the second type strain resistors in even columns of pixels are located on the third side.

[0045] In some possible implementations, the first type of strain resistors are arranged in a straight line along the row direction; or, the first type of strain resistors are arranged in a zigzag line or a serpentine line along the column direction;

[0046] And / or, the second type strain resistors are arranged in a straight line along the column direction; or, the second type strain resistors are arranged in a zigzag line or a serpentine line along the row direction.

[0047] The driving method of an ultrasonic circuit provided by an embodiment of the present invention includes:

[0048] In the curvature detection phase, the first control circuit initializes the first node; the second control circuit transmits a second electrical signal related to the curvature to the signal reading terminal;

[0049] During the ultrasonic detection phase, the ultrasonic sensor transmits an ultrasonic signal, the first control circuit initializes the first node and the ultrasonic sensor respectively, the ultrasonic sensor receives the reflected ultrasonic signal, converts the received ultrasonic signal into a first electrical signal and outputs it, the first control circuit receives the first electrical signal and transmits the first electrical signal to the first node; the second control circuit transmits a third electrical signal related to the first electrical signal to the signal reading terminal. BRIEF DESCRIPTION OF THE DRAWINGS

[0050] Figure 1a Some structural schematic diagrams of ultrasonic circuits provided by embodiments of the present invention;

[0051] Figure 1b A flowchart of a driving method for an ultrasonic circuit provided in an embodiment of the present invention;

[0052] Figure 1c Some signal timing diagrams provided for embodiments of the present invention;

[0053] Figure 2a Other structural schematic diagrams of ultrasonic circuits provided by embodiments of the present invention;

[0054] Figure 2b Other signal timing diagrams provided for embodiments of the present invention;

[0055] Figure 3a Some further structural schematic diagrams of ultrasonic circuits provided by embodiments of the present invention;

[0056] Figure 3b Further signal timing diagrams provided for embodiments of the present invention;

[0057] Figure 4a Some further structural schematic diagrams of ultrasonic circuits provided by embodiments of the present invention;

[0058] Figure 4b Further signal timing diagrams provided for embodiments of the present invention;

[0059] Figure 5a Some structural schematic diagrams of ultrasonic imaging devices provided by embodiments of the present invention;

[0060] Figure 5b Other schematic structural diagrams of ultrasonic imaging devices provided by embodiments of the present invention;

[0061] Figure 5c Some further structural schematic diagrams of ultrasonic imaging devices provided by embodiments of the present invention;

[0062] Figure 5d Some further structural schematic diagrams of ultrasonic imaging devices provided by embodiments of the present invention;

[0063] Figure 5e Some further structural schematic diagrams of ultrasonic imaging devices provided by embodiments of the present invention;

[0064] Figure 5f Some further structural schematic diagrams of ultrasonic imaging devices provided by embodiments of the present invention;

[0065] Figure 6a Some further structural schematic diagrams of ultrasonic imaging devices provided by embodiments of the present invention;

[0066] Figure 6b Some further structural schematic diagrams of ultrasonic imaging devices provided by embodiments of the present invention;

[0067] Figure 6c Some further structural schematic diagrams of ultrasonic imaging devices provided by embodiments of the present invention;

[0068] Figure 7a Some further structural schematic diagrams of ultrasonic imaging devices provided by embodiments of the present invention;

[0069] Figure 7b Some further structural schematic diagrams of ultrasonic imaging devices provided by embodiments of the present invention;

[0070] Figure 7c Some further structural schematic diagrams of ultrasonic imaging devices provided by embodiments of the present invention;

[0071] Figure 8aSome explanatory diagrams provided for embodiments of the present invention;

[0072] Figure 8b Other explanatory diagrams provided for embodiments of the present invention;

[0073] Figure 9a Some further explanatory diagrams are provided for the embodiments of the present invention;

[0074] Figure 9b Some further explanatory diagrams are provided for the embodiments of the present invention. DETAILED DESCRIPTION

[0075] In order to make the purpose, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings of the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. And in the absence of conflict, the embodiments of the present invention and the features in the embodiments can be combined with each other. Based on the described embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0076] Unless otherwise defined, the technical or scientific terms used in the present invention shall have the usual meanings understood by persons of ordinary skill in the field to which the present invention belongs. The words "first", "second" and similar terms used in the present invention do not indicate any order, quantity or importance, but are only used to distinguish different components. Words such as "include" or "comprise" mean that the elements or objects preceding the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Words such as "connect" or "connected" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect.

[0077] It should be noted that the sizes and shapes of the figures in the accompanying drawings do not reflect the actual scale and are only for the purpose of illustrating the present invention. The same or similar reference numerals throughout represent the same or similar elements or elements with the same or similar functions.

[0078] In the medical field, ultrasound imaging typically uses linear array probes and a single-frequency scanning method, but its detection depth and resolution are often limited. Large-area two-dimensional detection arrays, on the other hand, can increase the amount of detection information and, through two-dimensional imaging, improve detection depth and resolution. If a rigid substrate is used for large-area two-dimensional ultrasound imaging, it will not adhere tightly to the skin, resulting in signal loss in areas where it is not adhered. Therefore, a flexible substrate is the best choice. However, flexible substrates also face the problem of varying curvature in different areas, making it difficult to strictly control the curvature for each measurement, resulting in significant variations in the arrival time of echo information. Therefore, direct calibration through algorithms is difficult, resulting in reduced imaging accuracy. Therefore, before each ultrasound imaging test, it is essential to calibrate the curvature of the rows and columns corresponding to the pixels in the flexible substrate.

[0079] In the present invention, an ultrasonic circuit is provided in the pixels of the ultrasonic imaging device so that the ultrasonic circuit outputs a signal related to the curvature. The curvature is then determined based on the signal, and the ultrasonic imaging is corrected using the curvature. This can improve the imaging distortion problem caused by the curvature changes and differences in the flexible substrate during the ultrasonic imaging process, thereby improving the accuracy of flexible large-area two-dimensional ultrasonic imaging.

[0080] An ultrasonic circuit provided by an embodiment of the present invention is as follows: Figure 1a As shown, including:

[0081] The ultrasonic sensor US is configured to transmit an ultrasonic signal, receive a reflected ultrasonic signal, and convert the received ultrasonic signal into a first electrical signal.

[0082] The first control circuit 10 is configured to respectively initialize the first node N1 and the ultrasonic sensor US, receive a first electrical signal, and transmit the first electrical signal to the first node N1.

[0083] The second control circuit 20 is configured to transmit a second electrical signal related to the curvature to the read signal terminal RD, and transmit a third electrical signal related to the first electrical signal to the read signal terminal according to the first electrical signal of the first node N1.

[0084] The ultrasonic circuit provided in an embodiment of the present invention, through the interaction of an ultrasonic sensor, a first control circuit, and a second control circuit, can output a signal related to curvature, thereby determining the curvature based on the signal. Furthermore, through the interaction of the ultrasonic sensor, the first control circuit, and the second control circuit, a third electrical signal related to ultrasonic imaging can be output, and ultrasonic imaging can be performed based on the third electrical signal. Furthermore, by correcting the ultrasonic imaging using the curvature obtained above, the imaging distortion caused by changes and differences in the curvature of the flexible substrate during ultrasonic imaging can be improved, thereby improving the accuracy of flexible large-area two-dimensional ultrasonic imaging.

[0085] For example, the ultrasonic sensor can be a transceiver-integrated type or a separate sound source type. The type of ultrasonic sensor can be designed and determined according to the actual application environment and is not limited here.

[0086] For example, the ultrasonic sensor includes at least one of a PVDF sensor, a CMUT sensor, and a PMUT sensor. In practical applications, the material of the ultrasonic sensor can be designed and determined according to the actual application environment and is not limited here.

[0087] In some embodiments of the present invention, Figure 1a As shown, the second control circuit 20 includes a first sub-control circuit 201 and a second sub-control circuit 202. The first sub-control circuit 201 is coupled to the first node N1, the first reference voltage signal terminal V1, and the first control signal terminal CS1, respectively. The first sub-control circuit 201 is configured to provide a fourth electrical signal related to the curvature to the first node N1 in response to a signal at the first control signal terminal CS1. The second sub-control circuit 202 is coupled to the first reference voltage signal terminal V1, the first node N1, the read signal terminal RD, and the second control signal terminal CS2, respectively. The second sub-control circuit 202 is configured to transmit a second electrical signal related to the fourth electrical signal to the read signal terminal RD based on the fourth electrical signal at the first node N1, and to transmit a third electrical signal related to the first electrical signal to the read signal terminal RD based on the first electrical signal at the first node N1.

[0088] In some embodiments of the present invention, Figure 1a As shown, the first sub-control circuit 201 includes: a first transistor M1 and a strain gauge resistor R; the gate of the first transistor M1 is coupled to the first control signal terminal CS1, the first electrode of the first transistor M1 is coupled to the strain gauge resistor R, and the second electrode of the first transistor M1 is coupled to the first node N1. The first electrode of the strain gauge resistor R is coupled to the first reference voltage signal terminal V1, and the second electrode of the strain gauge resistor R is coupled to the first electrode of the first transistor M1.

[0089] For example, the first transistor M1 can be turned on under the control of the active level of the first control signal transmitted by the first control signal terminal CS1, and can be turned off under the control of the inactive level of the first control signal. For example, if the first transistor M1 is configured as an N-type transistor, the active level of the first control signal is a high level, and the inactive level of the first control signal is a low level. Alternatively, if the first transistor M1 is configured as a P-type transistor, the active level of the first control signal is a low level, and the inactive level of the first control signal is a high level.

[0090] In some embodiments of the present invention, Figure 1a As shown, the second sub-control circuit 202 includes: a second transistor M2, a third transistor M3, and a storage capacitor C. The gate of the second transistor M2 is coupled to the first node N1, the first electrode of the second transistor M2 is coupled to the first reference voltage signal terminal V1, and the second electrode of the second transistor M2 is coupled to the first electrode of the third transistor M3. The gate of the third transistor M3 is coupled to the second control signal terminal CS2, and the second electrode of the third transistor M3 is coupled to the read signal terminal RD. The first electrode of the storage capacitor C is coupled to the first reference voltage signal terminal V1, and the second electrode of the storage capacitor C is coupled to the first node N1.

[0091] For example, the third transistor M3 can be turned on under the control of the active level of the second control signal transmitted by the second control signal terminal CS2, and can be turned off under the control of the inactive level of the second control signal. For example, if the third transistor M3 is configured as an N-type transistor, the active level of the second control signal is a high level, and the inactive level of the second control signal is a low level. Alternatively, if the third transistor M3 is configured as a P-type transistor, the active level of the second control signal is a low level, and the inactive level of the second control signal is a high level.

[0092] In some embodiments of the present invention, Figure 1a As shown, the first control circuit 10 is configured to provide the signal of the second reference voltage signal terminal V2 to the second node N2 in response to the third control signal terminal CS3, and to connect the ultrasonic sensor US and the second node N2 to the first node N1 in response to the fourth control signal terminal CS4.

[0093] In some embodiments of the present invention, Figure 1a As shown, the first control circuit 10 includes a fourth transistor M4 and a fifth transistor M5. The gate of the fourth transistor M4 is coupled to the third control signal terminal CS3, the first electrode of the fourth transistor M4 is coupled to the second node N2, and the second electrode of the fourth transistor M4 is coupled to the second reference voltage signal terminal V2. The gate of the fifth transistor M5 is coupled to the fourth control signal terminal CS4, the first electrode of the fifth transistor M5 is coupled to the second node N2 and the ultrasonic sensor US, and the second electrode of the fifth transistor M5 is coupled to the first node N1.

[0094] For example, the fourth transistor M4 can be turned on under the control of the active level of the third control signal transmitted by the third control signal terminal CS3, and can be turned off under the control of the inactive level of the third control signal. For example, if the fourth transistor M4 is configured as an N-type transistor, the active level of the third control signal is a high level, and the inactive level of the third control signal is a low level. Alternatively, if the fourth transistor M4 is configured as a P-type transistor, the active level of the third control signal is a low level, and the inactive level of the third control signal is a high level.

[0095] For example, the fifth transistor M5 can be turned on under the control of the active level of the fourth control signal transmitted by the fourth control signal terminal CS4, and can be turned off under the control of the inactive level of the fourth control signal. For example, if the fifth transistor M5 is configured as an N-type transistor, the active level of the fourth control signal is a high level, and the inactive level of the fourth control signal is a low level. Alternatively, if the fifth transistor M5 is configured as a P-type transistor, the active level of the fourth control signal is a low level, and the inactive level of the fourth control signal is a high level.

[0096] For example, the first electrode of the transistor can be its source electrode, and the second electrode can be its drain electrode. Alternatively, the first electrode can be its drain electrode, and the second electrode can be its source electrode. This is not limited here.

[0097] Transistors using low-temperature polysilicon (LTPS) as active layers generally have high mobility and can be made thinner and smaller, with lower power consumption. In a specific implementation, the active layer of at least one of the transistors can be made of low-temperature polysilicon. This allows the transistor to be configured as an LTPS transistor, enabling the circuit to achieve high mobility, be thinner and smaller, and have lower power consumption.

[0098] Generally, transistors using metal oxide semiconductor materials as their active layers have low leakage current. Therefore, in order to reduce leakage current, in some embodiments of the present invention, the active layer of at least one of the transistors may include a metal oxide semiconductor material, such as IGZO (Indium Gallium Zinc Oxide). Of course, other metal oxide semiconductor materials are also possible and are not limited here. In this way, the transistor can be configured as an oxide thin film transistor to reduce the leakage current of the circuit.

[0099] For example, all transistors may be configured as LTPS transistors. Alternatively, all transistors may be configured as oxide transistors. Alternatively, some transistors may be configured as oxide transistors, and the remaining transistors may be configured as LTPS transistors. By combining the two transistor manufacturing processes of LTPS transistors and oxide transistors to prepare a low-temperature polysilicon oxide LTPO circuit, the gate leakage current of the transistor can be reduced, and the power consumption can be reduced.

[0100] For example, the first reference voltage signal terminal V1 can be configured to load a constant first reference voltage v1, and the second reference voltage signal terminal V2 can be configured to load a constant second reference voltage v2. In actual applications, the specific values ​​of the first reference voltage v1 and the second reference voltage v2 can be designed and determined based on the actual application environment and are not limited here.

[0101] Exemplarily, the first to fourth electrical signals may be current signals.

[0102] In the embodiment of the present invention, Figure 1b As shown, an embodiment of the present invention provides a driving method for an ultrasonic circuit, comprising the following steps:

[0103] S100 , curvature detection stage: the first control circuit initializes the first node; the second control circuit transmits a second electrical signal related to the curvature to the signal reading terminal.

[0104] S200, ultrasonic detection stage, the ultrasonic sensor transmits an ultrasonic signal, the first control circuit initializes the first node and the ultrasonic sensor respectively, the ultrasonic sensor receives the reflected ultrasonic signal, and converts the received ultrasonic signal into a first electrical signal and outputs it, the first control circuit receives the first electrical signal and transmits the first electrical signal to the first node; the second control circuit transmits a third electrical signal related to the first electrical signal to the signal reading end.

[0105] Below Figure 1a The ultrasonic circuit shown is used as an example, combined with Figure 1c The signal timing diagram shown describes the working process of the ultrasonic circuit provided by the embodiment of the present invention.

[0106] In the embodiment of the present invention, Figure 1c As shown, cs1 represents the first control signal of the first control signal terminal CS1, cs2 represents the second control signal of the second control signal terminal CS2, cs3 represents the third control signal of the third control signal terminal CS3, cs4 represents the fourth control signal of the fourth control signal terminal CS4, v1 represents the first reference voltage signal of the first reference voltage signal terminal V1, and v2 represents the second reference voltage signal of the second reference voltage signal terminal V2.

[0107] During the curvature detection phase F1, the reset phase F11, the first transistor M1 is turned off by the low level of the first control signal cs1, the third transistor M3 is turned off by the low level of the second control signal cs2, the fourth transistor M4 is turned on by the high level of the third control signal cs3, and the fifth transistor M5 is turned on by the high level of the fourth control signal cs4. The turned-on fourth transistor M4 transmits the signal of the first reference voltage signal terminal V1 to the second node N2, thereby initializing the second node N2. The turned-on fifth transistor M5 transmits the signal of the second node N2 to the first node N1, thereby initializing the first node N1.

[0108] In the integration phase F12, the first transistor M1 is turned on under the control of the high level of the first control signal cs1, the third transistor M3 is turned off under the control of the low level of the second control signal cs2, the fourth transistor M4 is turned off under the control of the low level of the third control signal cs3, and the fifth transistor M5 is turned off under the control of the low level of the fourth control signal cs4. The turned-on first transistor M1 turns on the first control subcircuit 201, so that the first control subcircuit 201 generates a current I (i.e., the fourth electrical signal) flowing through the strain resistor R. Where I represents the current value, U represents the voltage value, and R represents the resistance of the strain gauge resistor R. The current is stored in the capacitor C in the form of charge Q, so that the corresponding voltage is stored at the first node N1, Q = I × t, where Q represents the charge value and t represents the integration time. The voltage change value ΔV of the first node N1 is Wherein, ΔV represents the voltage change value of the first node N1, and C represents the capacitance value of the capacitor C.

[0109] In the reading phase F13, the first transistor M1 is turned off under the control of the low level of the first control signal cs1, the third transistor M3 is turned on under the control of the high level of the second control signal cs2, the fourth transistor M4 is turned off under the control of the low level of the third control signal cs3, and the fifth transistor M5 is turned off under the control of the low level of the fourth control signal cs4. The second transistor M2 generates a current I related to the voltage of the first node N1 based on the voltage of the first node N1 and the voltage of the first reference voltage signal terminal V1. read The turned-on third transistor M3 converts the current I generated by the second transistor M2 into read Transmitted to the read signal terminal RD.

[0110] During the ultrasonic detection phase F2, the transmission phase F21, the first transistor M1 is turned off by the low level of the first control signal cs1, the third transistor M3 is turned off by the low level of the second control signal cs2, the fourth transistor M4 is turned on by the high level of the third control signal cs3, and the fifth transistor M5 is turned on by the high level of the fourth control signal cs4. The turned-on fourth transistor M4 transmits the signal from the first reference voltage signal terminal V1 to the second node N2 and the ultrasonic sensor US, initializing the second node N2 and the ultrasonic sensor US and causing the ultrasonic sensor US to transmit an ultrasonic signal. The turned-on fifth transistor M5 transmits the signal from the second node N2 to the first node N1, initializing the first node N1.

[0111] During acquisition phase F22, the first transistor M1 is turned off by the low level of the first control signal cs1, the third transistor M3 is turned off by the low level of the second control signal cs2, the fourth transistor M4 is turned off by the low level of the third control signal cs3, and the fifth transistor M5 is turned on by the high level of the fourth control signal cs4. The ultrasonic sensor US receives the reflected ultrasonic signal and converts it into a first electrical signal. The turned-on fifth transistor M5 transmits the first electrical signal to the first node N1 and inputs it into the capacitor C, causing a corresponding voltage to be stored at the first node N1.

[0112] In the holding phase F23, the first transistor M1 is turned off under the control of the low level of the first control signal cs1, the third transistor M3 is turned off under the control of the low level of the second control signal cs2, the fourth transistor M4 is turned off under the control of the low level of the third control signal cs3, and the fifth transistor M5 is turned off under the control of the low level of the fourth control signal cs4.

[0113] In the read phase F24, the first transistor M1 is turned off by the low level of the first control signal cs1, the third transistor M3 is turned on by the high level of the second control signal cs2, the fourth transistor M4 is turned off by the low level of the third control signal cs3, and the fifth transistor M5 is turned off by the low level of the fourth control signal cs4. The second transistor M2 generates a current related to the voltage of the first node N1 based on the voltage of the first node N1 and the voltage of the first reference voltage signal terminal V1. The turned-on third transistor M3 transmits this current to the read signal terminal RD.

[0114] The embodiment of the present invention provides another schematic diagram of the structure of an ultrasonic circuit, such as Figure 2a As shown, the embodiment described above is modified. The following only describes the differences between this embodiment and the above embodiment, and the similarities are not repeated here.

[0115] In the embodiment of the present invention, Figure 2a As shown, the first control circuit 10 further includes a sixth transistor M6, through which the ultrasonic sensor US is coupled to the second node N2. A gate of the sixth transistor M6 is coupled to the fifth control signal terminal CS5, a first electrode of the sixth transistor M6 is coupled to the ultrasonic sensor US, and a second electrode of the sixth transistor M6 is coupled to the second node N2.

[0116] Exemplarily, the sixth transistor M6 can be turned on under the control of the active level of the fifth control signal transmitted by the fifth control signal terminal CS5, and can be turned off under the control of the inactive level of the fifth control signal. Exemplarily, if the sixth transistor M6 is configured as an N-type transistor, the active level of the fifth control signal is a high level, and the inactive level of the fifth control signal is a low level. Alternatively, if the sixth transistor M6 is configured as a P-type transistor, the active level of the fifth control signal is a low level, and the inactive level of the fifth control signal is a high level.

[0117] Below Figure 2a The ultrasonic circuit shown is used as an example, combined with Figure 2b The signal timing diagram shown describes the working process of the ultrasonic circuit provided by the embodiment of the present invention.

[0118] In the embodiment of the present invention, Figure 2b As shown, cs1 represents the first control signal of the first control signal terminal CS1, cs2 represents the second control signal of the second control signal terminal CS2, cs3 represents the third control signal of the third control signal terminal CS3, cs4 represents the fourth control signal of the fourth control signal terminal CS4, cs5 represents the fifth control signal of the fifth control signal terminal CS5, v1 represents the first reference voltage signal of the first reference voltage signal terminal V1, and v2 represents the second reference voltage signal of the second reference voltage signal terminal V2.

[0119] During the curvature detection phase F1, the reset phase F11, the first transistor M1 is turned off under the control of the low level of the first control signal cs1, the third transistor M3 is turned off under the control of the low level of the second control signal cs2, the fourth transistor M4 is turned on under the control of the high level of the third control signal cs3, the fifth transistor M5 is turned on under the control of the high level of the fourth control signal cs4, and the sixth transistor M6 is turned off under the control of the low level of the fifth control signal cs5. The turned-on fourth transistor M4 transmits the signal of the first reference voltage signal terminal V1 to the second node N2, thereby initializing the second node N2. The turned-on fifth transistor M5 transmits the signal of the second node N2 to the first node N1, thereby initializing the first node N1.

[0120] In the integration phase F12, the first transistor M1 is turned on under the control of the high level of the first control signal cs1, the third transistor M3 is turned off under the control of the low level of the second control signal cs2, the fourth transistor M4 is turned off under the control of the low level of the third control signal cs3, the fifth transistor M5 is turned off under the control of the low level of the fourth control signal cs4, and the sixth transistor M6 is turned off under the control of the low level of the fifth control signal cs5. The turned-on first transistor M1 turns on the first control sub-circuit 201, so that the first control sub-circuit 201 generates a current I (i.e., the fourth electrical signal) flowing through the strain resistor R. The current is stored in the capacitor C in the form of charge Q, so that the corresponding voltage is stored at the first node N1, Q = I × t. The voltage change value of the first node N1 is ΔV,

[0121] In the reading phase F13, the first transistor M1 is turned off under the control of the low level of the first control signal cs1, the third transistor M3 is turned on under the control of the high level of the second control signal cs2, the fourth transistor M4 is turned off under the control of the low level of the third control signal cs3, the fifth transistor M5 is turned off under the control of the low level of the fourth control signal cs4, and the sixth transistor M6 is turned off under the control of the low level of the fifth control signal cs5. The second transistor M2 generates a current I related to the voltage of the first node N1 based on the voltage of the first node N1 and the voltage of the first reference voltage signal terminal V1. read The turned-on third transistor M3 converts the current I generated by the second transistor M2 into read Transmitted to the read signal terminal RD.

[0122] During the ultrasonic detection phase F2, the transmission phase F21, the first transistor M1 is turned off by the low level of the first control signal cs1, the third transistor M3 is turned off by the low level of the second control signal cs2, the fourth transistor M4 is turned on by the high level of the third control signal cs3, the fifth transistor M5 is turned on by the high level of the fourth control signal cs4, and the sixth transistor M6 is turned on by the high level of the fifth control signal cs5. The turned-on fourth transistor M4 transmits the signal from the first reference voltage signal terminal V1 to the second node N2, initializing the second node N2. The turned-on fifth transistor M5 transmits the signal from the second node N2 to the first node N1, initializing the first node N1. The turned-on sixth transistor M6 transmits the signal from the second node N2 to the ultrasonic sensor US, initializing the ultrasonic sensor US and causing it to transmit an ultrasonic signal.

[0123] During acquisition phase F22, the first transistor M1 is turned off by the low level of the first control signal cs1, the third transistor M3 is turned off by the low level of the second control signal cs2, the fourth transistor M4 is turned off by the low level of the third control signal cs3, the fifth transistor M5 is turned on by the high level of the fourth control signal cs4, and the sixth transistor M6 is turned off by the low level of the fifth control signal cs5. The ultrasonic sensor US receives the reflected ultrasonic signal and converts it into a first electrical signal. The turned-on fifth transistor M5 transmits the first electrical signal to the first node N1 and inputs it into the capacitor C, causing a corresponding voltage to be stored at the first node N1.

[0124] In the holding phase F23, the first transistor M1 is turned off under the control of the low level of the first control signal cs1, the third transistor M3 is turned off under the control of the low level of the second control signal cs2, the fourth transistor M4 is turned off under the control of the low level of the third control signal cs3, the fifth transistor M5 is turned off under the control of the low level of the fourth control signal cs4, and the sixth transistor M6 is turned off under the control of the low level of the fifth control signal cs5.

[0125] In the read phase F24, the first transistor M1 is turned off by the low level of the first control signal cs1, the third transistor M3 is turned on by the high level of the second control signal cs2, the fourth transistor M4 is turned off by the low level of the third control signal cs3, the fifth transistor M5 is turned off by the low level of the fourth control signal cs4, and the sixth transistor M6 is turned off by the low level of the fifth control signal cs5. The second transistor M2 generates a current related to the voltage of the first node N1 based on the voltage of the first node N1 and the voltage of the first reference voltage signal terminal V1. The turned-on third transistor M3 transmits this current to the read signal terminal RD.

[0126] The embodiment of the present invention provides a structural diagram of another ultrasonic circuit, such as Figure 3a As shown, the embodiment described above is modified. The following only describes the differences between this embodiment and the above embodiment, and the similarities are not repeated here.

[0127] In the embodiment of the present invention, Figure 3a As shown, the second control circuit 20 includes: a first sub-control circuit 201 and a second sub-control circuit 202 .

[0128] The first sub-control circuit 201 is coupled to the first reference voltage signal terminal V1, the first control signal terminal CS1 and the read signal terminal RD respectively; the first sub-control circuit 201 is configured to provide a second electrical signal related to the curvature to the read signal terminal RD in response to the signal of the first control signal terminal CS1.

[0129] The second sub-control circuit 202 is coupled to the first reference voltage signal terminal V1, the first node N1, the second control signal terminal CS2 and the read signal terminal RD respectively; the second sub-control circuit 202 is configured to transmit a third electrical signal related to the first electrical signal to the read signal terminal RD according to the first electrical signal of the first node N1.

[0130] In an embodiment of the present invention, as shown in 3a, the first sub-control circuit 201 includes a first transistor M1 and a strain gauge resistor R. The gate of the first transistor M1 is coupled to the first control signal terminal CS1, the first electrode of the first transistor M1 is coupled to the strain gauge resistor R, and the second electrode of the first transistor M1 is coupled to the read signal terminal RD. The first electrode of the strain gauge resistor R is coupled to the first reference voltage signal terminal V1, and the second electrode of the strain gauge resistor R is coupled to the first electrode of the first transistor M1.

[0131] In an embodiment of the present invention, as shown in 3a, the second sub-control circuit 202 includes: a second transistor M2, a third transistor M3, and a storage capacitor C. The gate of the second transistor M2 is coupled to the first node N1, the first electrode of the second transistor M2 is coupled to the first reference voltage signal terminal V1, and the second electrode of the second transistor M2 is coupled to the first electrode of the third transistor M3. The gate of the third transistor M3 is coupled to the second control signal terminal CS2, and the second electrode of the third transistor M3 is coupled to the read signal terminal RD. The first electrode of the storage capacitor C is coupled to the first reference voltage signal terminal V1, and the second electrode of the storage capacitor C is coupled to the first node N1.

[0132] Below Figure 3a The ultrasonic circuit shown is used as an example, combined with Figure 3b The signal timing diagram shown describes the working process of the ultrasonic circuit provided by the embodiment of the present invention.

[0133] In the embodiment of the present invention, Figure 3b As shown, cs1 represents the first control signal of the first control signal terminal CS1, cs2 represents the second control signal of the second control signal terminal CS2, cs3 represents the third control signal of the third control signal terminal CS3, cs4 represents the fourth control signal of the fourth control signal terminal CS4, v1 represents the first reference voltage signal of the first reference voltage signal terminal V1, and v2 represents the second reference voltage signal of the second reference voltage signal terminal V2.

[0134] During the curvature detection phase F1, the reset phase F11, the first transistor M1 is turned off by the low level of the first control signal cs1, the third transistor M3 is turned off by the low level of the second control signal cs2, the fourth transistor M4 is turned on by the high level of the third control signal cs3, and the fifth transistor M5 is turned on by the high level of the fourth control signal cs4. The turned-on fourth transistor M4 transmits the signal of the first reference voltage signal terminal V1 to the second node N2, thereby initializing the second node N2. The turned-on fifth transistor M5 transmits the signal of the second node N2 to the first node N1, thereby initializing the first node N1.

[0135] In the reading phase F12, the first transistor M1 is turned on under the control of the high level of the first control signal cs1, the third transistor M3 is turned off under the control of the low level of the second control signal cs2, the fourth transistor M4 is turned off under the control of the low level of the third control signal cs3, and the fifth transistor M5 is turned off under the control of the low level of the fourth control signal cs4. The turned-on first transistor M1 turns on the first control sub-circuit 201, so that the first control sub-circuit 201 generates a current I flowing through the strain resistor R. read (i.e. the second electrical signal), and the current I read Input to the read signal terminal RD.

[0136] During the ultrasonic detection phase F2, the transmission phase F21, the first transistor M1 is turned off by the low level of the first control signal cs1, the third transistor M3 is turned off by the low level of the second control signal cs2, the fourth transistor M4 is turned on by the high level of the third control signal cs3, and the fifth transistor M5 is turned on by the high level of the fourth control signal cs4. The turned-on fourth transistor M4 transmits the signal from the first reference voltage signal terminal V1 to the second node N2 and the ultrasonic sensor US, initializing the second node N2 and the ultrasonic sensor US and causing the ultrasonic sensor US to transmit an ultrasonic signal. The turned-on fifth transistor M5 transmits the signal from the second node N2 to the first node N1, initializing the first node N1.

[0137] During acquisition phase F22, the first transistor M1 is turned off by the low level of the first control signal cs1, the third transistor M3 is turned off by the low level of the second control signal cs2, the fourth transistor M4 is turned off by the low level of the third control signal cs3, and the fifth transistor M5 is turned on by the high level of the fourth control signal cs4. The ultrasonic sensor US receives the reflected ultrasonic signal and converts it into a first electrical signal. The turned-on fifth transistor M5 transmits the first electrical signal to the first node N1 and inputs it into the capacitor C, causing a corresponding voltage to be stored at the first node N1.

[0138] In the holding phase F23, the first transistor M1 is turned off under the control of the low level of the first control signal cs1, the third transistor M3 is turned off under the control of the low level of the second control signal cs2, the fourth transistor M4 is turned off under the control of the low level of the third control signal cs3, and the fifth transistor M5 is turned off under the control of the low level of the fourth control signal cs4.

[0139] In the read phase F24, the first transistor M1 is turned off by the low level of the first control signal cs1, the third transistor M3 is turned on by the high level of the second control signal cs2, the fourth transistor M4 is turned off by the low level of the third control signal cs3, and the fifth transistor M5 is turned off by the low level of the fourth control signal cs4. The second transistor M2 generates a current related to the voltage of the first node N1 based on the voltage of the first node N1 and the voltage of the first reference voltage signal terminal V1. The turned-on third transistor M3 transmits this current to the read signal terminal RD.

[0140] The embodiment of the present invention provides a structural diagram of another ultrasonic circuit, such as Figure 4a As shown, the embodiment described above is modified. The following only describes the differences between this embodiment and the above embodiment, and the similarities are not repeated here.

[0141] In the embodiment of the present invention, Figure 4a As shown, the first control circuit 10 further includes a sixth transistor M6, through which the ultrasonic sensor US is coupled to the second node N2. A gate of the sixth transistor M6 is coupled to the fifth control signal terminal CS5, a first electrode of the sixth transistor M6 is coupled to the ultrasonic sensor US, and a second electrode of the sixth transistor M6 is coupled to the second node N2.

[0142] Exemplarily, the sixth transistor M6 can be turned on under the control of the active level of the fifth control signal transmitted by the fifth control signal terminal CS5, and can be turned off under the control of the inactive level of the fifth control signal. Exemplarily, if the sixth transistor M6 is configured as an N-type transistor, the active level of the fifth control signal is a high level, and the inactive level of the fifth control signal is a low level. Alternatively, if the sixth transistor M6 is configured as a P-type transistor, the active level of the fifth control signal is a low level, and the inactive level of the fifth control signal is a high level.

[0143] Below Figure 4a The ultrasonic circuit shown is used as an example, combined with Figure 4b The signal timing diagram shown describes the working process of the ultrasonic circuit provided by the embodiment of the present invention.

[0144] In the embodiment of the present invention, Figure 4b As shown, cs1 represents the first control signal of the first control signal terminal CS1, cs2 represents the second control signal of the second control signal terminal CS2, cs3 represents the third control signal of the third control signal terminal CS3, cs4 represents the fourth control signal of the fourth control signal terminal CS4, cs5 represents the fifth control signal of the fifth control signal terminal CS5, v1 represents the first reference voltage signal of the first reference voltage signal terminal V1, and v2 represents the second reference voltage signal of the second reference voltage signal terminal V2.

[0145] During the curvature detection phase F1, the reset phase F11, the first transistor M1 is turned off by the low level of the first control signal cs1, the third transistor M3 is turned off by the low level of the second control signal cs2, the fourth transistor M4 is turned on by the high level of the third control signal cs3, the fifth transistor M5 is turned on by the high level of the fourth control signal cs4, and the sixth transistor M6 is turned on by the high level of the fifth control signal cs5. The turned-on fourth transistor M4 transmits the signal from the first reference voltage signal terminal V1 to the second node N2, thereby initializing the second node N2. The turned-on fifth transistor M5 transmits the signal from the second node N2 to the first node N1, thereby initializing the first node N1. The turned-on sixth transistor M6 transmits the signal from the second node N2 to the ultrasonic sensor US, thereby initializing the ultrasonic sensor US.

[0146] In the reading phase F12, the first transistor M1 is turned on under the control of the high level of the first control signal cs1, the third transistor M3 is turned off under the control of the low level of the second control signal cs2, the fourth transistor M4 is turned off under the control of the low level of the third control signal cs3, the fifth transistor M5 is turned off under the control of the low level of the fourth control signal cs4, and the sixth transistor M6 is turned off under the control of the low level of the fifth control signal cs5. The turned-on first transistor M1 turns on the first control sub-circuit 201, so that the first control sub-circuit 201 generates a current I flowing through the strain resistor R. read (i.e. the second electrical signal), and the current I read Input to the read signal terminal RD.

[0147] During the ultrasonic detection phase F2, the transmission phase F21, the first transistor M1 is turned off by the low level of the first control signal cs1, the third transistor M3 is turned off by the low level of the second control signal cs2, the fourth transistor M4 is turned on by the high level of the third control signal cs3, the fifth transistor M5 is turned on by the high level of the fourth control signal cs4, and the sixth transistor M6 is turned on by the high level of the fifth control signal cs5. The turned-on fourth transistor M4 transmits the signal from the first reference voltage signal terminal V1 to the second node N2, initializing the second node N2. The turned-on fifth transistor M5 transmits the signal from the second node N2 to the first node N1, initializing the first node N1. The turned-on sixth transistor M6 transmits the signal from the second node N2 to the ultrasonic sensor US, initializing the ultrasonic sensor US and causing it to transmit an ultrasonic signal.

[0148] During acquisition phase F22, the first transistor M1 is turned off by the low level of the first control signal cs1, the third transistor M3 is turned off by the low level of the second control signal cs2, the fourth transistor M4 is turned off by the low level of the third control signal cs3, the fifth transistor M5 is turned on by the high level of the fourth control signal cs4, and the sixth transistor M6 is turned on by the high level of the fifth control signal cs5. The ultrasonic sensor US receives the reflected ultrasonic signal and converts it into a first electrical signal. The turned-on sixth transistor M6 transmits the first electrical signal to the second node N2. The turned-on fifth transistor M5 transmits the first electrical signal to the first node N1 and inputs it into the capacitor C, causing a corresponding voltage to be stored at the first node N1.

[0149] In the holding phase F23, the first transistor M1 is turned off under the control of the low level of the first control signal cs1, the third transistor M3 is turned off under the control of the low level of the second control signal cs2, the fourth transistor M4 is turned off under the control of the low level of the third control signal cs3, the fifth transistor M5 is turned off under the control of the low level of the fourth control signal cs4, and the sixth transistor M6 is turned off under the control of the low level of the fifth control signal cs5.

[0150] In the read phase F24, the first transistor M1 is turned off by the low level of the first control signal cs1, the third transistor M3 is turned on by the high level of the second control signal cs2, the fourth transistor M4 is turned off by the low level of the third control signal cs3, the fifth transistor M5 is turned off by the low level of the fourth control signal cs4, and the sixth transistor M6 is turned off by the low level of the fifth control signal cs5. The second transistor M2 generates a current related to the voltage of the first node N1 based on the voltage of the first node N1 and the voltage of the first reference voltage signal terminal V1. The turned-on third transistor M3 transmits this current to the read signal terminal RD.

[0151] An embodiment of the present invention provides an ultrasonic imaging device, such as Figures 5a to 5f As shown, the present invention includes: a flexible substrate 100 having a plurality of pixels SPX thereon, each pixel SPX including the ultrasonic circuit described above; the plurality of pixels SPX being divided into a plurality of pixel groups, each pixel group including a plurality of adjacent pixels SPX; each pixel group including a first pixel and a second pixel; the strain resistor of the ultrasonic circuit in the first pixel being a first-type strain resistor X, configured to deform when the flexible substrate 100 is bent along a row direction F1 of the pixels SPX, thereby adjusting the magnitude of the current flowing through the first-type strain resistor X; and the strain resistor of the ultrasonic circuit in the second pixel being a second-type strain resistor Y, configured to deform when the flexible substrate 100 is bent along a column direction F2 of the pixels SPX, thereby adjusting the magnitude of the current flowing through the second-type strain resistor.

[0152] In some embodiments of the present invention, Figures 5a to 5f As shown, each pixel group includes two pixels SPX adjacent to each other along the column direction F2.

[0153] In some embodiments of the present invention, Figure 5a As shown, the strain resistors in the odd-numbered rows of pixels SPX are first-type strain resistors X, and the strain resistors in the even-numbered rows of pixels SPX are second-type strain resistors Y.

[0154] In some embodiments of the present invention, Figure 5b As shown, the strain resistors in the pixels SPX in the even-numbered rows are strain resistors X of the first type, and the strain resistors in the pixels SPX in the odd-numbered rows are strain resistors Y of the second type.

[0155] In some embodiments of the present invention, Figure 5c As shown, the strain resistors in the odd-numbered rows of pixels SPX are arranged alternately in the order of first-type strain resistors X and second-type strain resistors Y, and the strain resistors in the even-numbered rows of pixels SPX are arranged alternately in the order of second-type strain resistors Y and first-type strain resistors X.

[0156] In some embodiments of the present invention, Figure 5d As shown, the strain resistors in the odd-numbered pixels SPX are arranged alternately in the order of the second type strain resistors Y and the first type strain resistors X, and the strain resistors in the even-numbered pixels SPX are arranged alternately in the order of the first type strain resistors X and the second type strain resistors Y.

[0157] In some embodiments of the present invention, Figures 5a to 5f As shown, the pixel SPX has a first side and a second side disposed opposite to each other in the row direction F1 , and a third side and a fourth side disposed opposite to each other in the column direction F2 .

[0158] In some embodiments of the present invention, Figure 5a and 5b As shown, the first type strain resistor X in each column of pixels SPX is located on the first side.

[0159] In some embodiments of the present invention, Figure 5c and 5d As shown, the first type strain resistors X in the odd-numbered columns of pixels SPX are located on the first side, and the first type strain resistors X in the even-numbered columns of pixels SPX are located on the second side.

[0160] In some embodiments of the present invention, Figure 5e and 5f As shown, the second type strain resistor Y in each column of pixels SPX is located on the fourth side.

[0161] In some embodiments of the present invention, Figures 5a to 5d As shown, the second type strain resistors Y in the odd-numbered columns of pixels SPX are located on the fourth side, and the second type strain resistors Y in the even-numbered columns of pixels SPX are located on the third side.

[0162] In some embodiments of the present invention, Figure 6a , the first type strain resistors X can be arranged in a straight line along the row direction F1. Figure 6b As shown, the first type strain resistors X can also be arranged in a broken line manner along the column direction F2. Figure 6c As shown, the first type strain resistors X may also be arranged in a serpentine pattern along the column direction F2.

[0163] In some embodiments of the present invention, Figure 7a As shown, the second type strain resistors Y can be arranged in a straight line along the column direction F2. Figure 7b As shown in FIG. 1 , the second type strain resistor Y can also be arranged in a broken line along the row direction F1. Alternatively, as shown in FIG. Figure 7cAs shown, the second type strain resistors Y may also be arranged in a serpentine pattern along the row direction F1.

[0164] For example, the material used for the strain resistor may be constantan, nickel-chromium alloy or other alloys, etc. The material of the strain resistor may be designed and determined according to the actual application environment and is not limited here.

[0165] For example, the strain resistor may be a wire-wound type, a short-circuit type, or a foil type, etc. The type of strain resistor may be designed and determined according to the actual application environment and is not limited here.

[0166] In some embodiments of the present invention, Figure 8a As shown, when the ultrasonic imaging device does not perform ultrasonic detection, the distance between each pixel site in the flexible substrate and the target A (such as Figure 8a When the ultrasonic imaging device performs ultrasonic detection, it is necessary to attach the flexible substrate to the skin, and the flexible substrate is deformed, such as Figure 8b As shown, after deformation, the distance between each pixel SPX site in the flexible substrate and the target A (as shown in Figure 8b In order to calibrate the actual distance between each pixel SPX site and the target A (such as d1, d2, d3), the difference is generated. Figure 8b In order to eliminate distortion and improve the position and size accuracy of imaging detection, it is necessary to obtain the curvature value of the flexible substrate.

[0167] The principle of strain gauge resistance to detect curvature: When the flexible substrate is deformed, the strain gauge resistance in the flexible substrate will sense the deformation. The resistance of a conductor with a uniform cross section is Where R is the resistance value, ρ is the resistivity, L is the conductor length, and S is the conductor cross-sectional area. When the strain resistor is subjected to a force in the row or column direction, a small deformation Δε occurs. The relationship between the resistance change ΔR of the strain resistor and the strain resistance value R is: Where Ks is the strain sensitivity coefficient of the strain resistor, and Δε is the slight deformation. By increasing the length of the strain resistor to a certain extent within the pixel, the strain resistor can be made to sense more deformation in the row or column direction, that is, the strain resistor is integrated and summed in the row or column direction. Therefore, the strain resistor can sense strain in the row or column direction. The detection method of the resistor can be based on Ohm's law. A fixed voltage U is applied to both sides of the strain resistor. According to the change value ΔI of the current flowing through it, the resistance change value ΔR of the strain resistor can be detected, and then the deformation value Δε of the strain resistor can be obtained.

[0168] In an embodiment of the present invention, the ultrasonic imaging device includes both a first type strain resistor X and a second type strain resistor Y. The first type strain resistor X is responsible for sensing the deformation of the pixel SPX in the row direction F1, and the second type strain resistor Y is responsible for sensing the deformation of the pixel SPX in the column direction F2. Since the spacing between the pixels SPX is small, only 50 μm to 300 μm, the deformation of the adjacent first type strain resistor X and second type strain resistor Y can be approximately regarded as the deformation of the dual pixel area in the row direction F1 and the deformation in the column direction F2, that is, approximately the deformation Δε (Δε) of the position P(x, y) of the pixel SPX. x , Δε y ), where Δε x Represents the deformation of the pixel SPX row direction, Δε y Represents the deformation of the pixel in the SPX column direction.

[0169] The bending direction of the detection scene of a general ultrasonic imaging device is a monotonic bending direction (i.e., deformation only occurs in the row direction or column direction). Therefore, the curvature detected points in the same direction. In addition, the flexible substrate in the ultrasonic imaging device is not stretched, but is simply flattened naturally. Therefore, the deformation generated is a bending deformation Δε. According to Hooke's law: bending deformation stress M = A × Δε, where M is the bending deformation stress, A is the bending elastic coefficient, and Δε is the bending deformation. In this way, the deformation Δε (Δε) of the position P(x, y) of the pixel SPX can be calculated. x , Δε y ) to obtain the bending stress M(M x , M y ), where M x Represents the bending deformation stress in the row direction, M y Represents the bending deformation stress in the column direction.

[0170] According to the curvature Φ and bending moment equation Where Φ is the curvature and EI is the rotational stiffness (constant). Therefore, the bending deformation stress M(M) at the position P(x, y) of the pixel SPX is x , M y ) can be used to obtain the curvature Φ(Φ) of the position P(x, y) of the pixel SPX. x , Φ y ), where Φ x represents the curvature in the row direction, Φ y Represents the curvature in the column direction. Figure 9a and 9b As shown, all positions and their corresponding curvatures Φ obtained by all pixels SPX (such as Figure 9bΦ1, Φ2, Φ3 in the figure), the curved shape distribution of the ultrasonic imaging device in the row and column directions can be drawn, so that the distance between the target object A and all pixels SPX can be obtained (such as Figure 9b d1, d2, d3 in , so as to calibrate the signal and eliminate imaging distortion.

[0171] In an embodiment of the present invention, when the ultrasonic imaging device is started or powered on, the ultrasonic circuit reads a second electrical signal Iread related to the curvature and stores Iread in the ultrasonic imaging device. Subsequently, in the curvature detection phase F1, the ultrasonic circuit reads a second electrical signal Iread' related to the curvature and, based on the pre-stored Iread, obtains a current difference ΔIread = Iread - Iread', and, ΔR represents the change in the strain gauge resistor, k represents the transconductance of the second transistor M2, U represents the voltage, C represents the capacitance, t represents the integration time, and ΔIread represents the current difference. Get ΔR, and then get the curvature Φ based on ΔR, (A, EI, Ks are all constant coefficients). The curvature of the pixel SPX containing the first type strain resistor X in the row direction F1 is Φ x represents the curvature of the pixel SPX in the row direction F1, ΔR x represents the resistance change value of the first type strain gauge resistor X, R x represents the resistance value of the first type strain resistor X. The curvature of the pixel SPX containing the second type strain resistor Y in the column direction F2 is Φ y represents the curvature of the pixel SPX in the column direction, ΔR y represents the resistance change value of the second type strain gauge resistor Y, R y represents the resistance value of the second type strain gauge resistor Y.

[0172] So according to the obtained curvature Φ x and Φ y , the curvature Φ in the pixel group can be obtained. Based on this, the curvature Φ corresponding to all positions can be obtained, so that the signal can be calibrated based on the curvature Φ to eliminate imaging distortion.

[0173] It will be understood by those skilled in the art that embodiments of the present invention may be provided as methods, systems, or computer program products. Thus, the present invention may take the form of an entirely hardware embodiment, an entirely software embodiment, or an embodiment combining software and hardware. Furthermore, the present invention may take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to magnetic disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0174] The present invention is described with reference to the flowcharts and / or block diagrams of the methods, devices (systems), and computer program products according to embodiments of the present invention. It should be understood that each process and / or box in the flowchart and / or block diagram, as well as the combination of the processes and / or boxes in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to produce a machine, so that the instructions executed by the processor of the computer or other programmable data processing device produce a device for implementing the functions specified in one or more processes in the flowchart and / or one or more boxes in the block diagram.

[0175] These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing device to operate in a specific manner, so that the instructions stored in the computer-readable memory produce a product including an instruction device that implements the functions specified in one or more processes in the flowchart and / or one or more boxes in the block diagram.

[0176] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operating steps are executed on the computer or other programmable device to produce a computer-implemented process, so that the instructions executed on the computer or other programmable device provide steps for implementing the functions specified in one or more processes in the flowchart and / or one or more boxes in the block diagram.

[0177] Although the preferred embodiments of the present invention have been described, those skilled in the art may make additional changes and modifications to these embodiments once they have learned the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the present invention.

[0178] Obviously, those skilled in the art may make various changes and modifications to the embodiments of the present invention without departing from the spirit and scope of the embodiments of the present invention. Thus, if such changes and modifications of the embodiments of the present invention fall within the scope of the claims and their equivalents, the present invention is intended to include such changes and modifications.

Claims

1. An ultrasonic circuit, characterized in that: include, an ultrasonic sensor configured to transmit an ultrasonic signal, receive a reflected ultrasonic signal, and convert the received ultrasonic signal into a first electrical signal; a first control circuit configured to respectively initialize the first node and the ultrasonic sensor, receive the first electrical signal, and transmit the first electrical signal to the first node; a second control circuit configured to transmit a second electrical signal related to the curvature of the flexible substrate to a read signal terminal, and, based on the first electrical signal of the first node, transmit a third electrical signal related to the first electrical signal to the read signal terminal; Wherein, the second control circuit includes: a first sub-control circuit and a second sub-control circuit; The first sub-control circuit is coupled to the first node, the first reference voltage signal terminal, and the first control signal terminal respectively; the first sub-control circuit is configured to provide a fourth electrical signal related to the curvature to the first node in response to a signal at the first control signal terminal; The second sub-control circuit is coupled to the first reference voltage signal terminal, the first node, the read signal terminal, and the second control signal terminal, respectively; the second sub-control circuit is configured to transmit a second electrical signal related to the fourth electrical signal to the read signal terminal based on the fourth electrical signal of the first node, and to transmit a third electrical signal related to the first electrical signal to the read signal terminal based on the first electrical signal of the first node; The first sub-control circuit includes: a first transistor and a strain resistor; The gate of the first transistor is coupled to the first control signal terminal, the first electrode of the first transistor is coupled to the strain resistor, and the second electrode of the first transistor is coupled to the first node; A first electrode of the strain resistor is coupled to the first reference voltage signal terminal, and a second electrode of the strain resistor is coupled to the first electrode of the first transistor; The second sub-control circuit includes: a second transistor, a third transistor and a storage capacitor; The gate of the second transistor is coupled to the first node, the first electrode of the second transistor is coupled to the first reference voltage signal terminal, and the second electrode of the second transistor is coupled to the first electrode of the third transistor; The gate of the third transistor is coupled to the second control signal terminal, and the second electrode of the third transistor is coupled to the read signal terminal; A first electrode of the storage capacitor is coupled to the first reference voltage signal terminal, and a second electrode of the storage capacitor is coupled to the first node.

2. The ultrasonic circuit according to claim 1, wherein: The first control circuit is coupled to the first node and the second node, and the second node is coupled to the ultrasonic sensor; wherein the first control circuit is configured to provide a signal from the second reference voltage signal terminal to the second node in response to a third control signal terminal, and to connect the second node to the first node in response to a fourth control signal terminal.

3. The ultrasonic circuit according to claim 2, wherein: The first control circuit includes: a fourth transistor and a fifth transistor; The gate of the fourth transistor is coupled to the third control signal terminal, the first electrode of the fourth transistor is coupled to the second node, and the second electrode of the fourth transistor is coupled to the second reference voltage signal terminal; A gate of the fifth transistor is coupled to the fourth control signal terminal, a first electrode of the fifth transistor is coupled to the second node and the ultrasonic sensor, and a second electrode of the fifth transistor is coupled to the first node.

4. The ultrasonic circuit according to claim 3, wherein: The first control circuit further includes: a sixth transistor, the ultrasonic sensor being coupled to the second node via the sixth transistor; A gate of the sixth transistor is coupled to the fifth control signal terminal, a first electrode of the sixth transistor is coupled to the ultrasonic sensor, and a second electrode of the sixth transistor is coupled to the second node.

5. An ultrasonic imaging device, characterized in that: include: A flexible substrate having a plurality of pixels thereon, each pixel comprising the ultrasonic circuit according to any one of claims 1 to 4; The plurality of pixels are divided into a plurality of pixel groups, each of the pixel groups includes a plurality of adjacent pixels; each of the pixel groups includes a first pixel and a second pixel; The strain resistor of the ultrasonic circuit in the first pixel is a first type strain resistor, and the first type strain resistor is configured to deform when the flexible substrate is bent along the row direction of the pixel, thereby adjusting the magnitude of the current flowing through the first type strain resistor; The strain resistor of the ultrasonic circuit in the second pixel is a second type strain resistor, which is configured to deform when the flexible substrate is bent along the column direction of the pixels to adjust the magnitude of the current flowing through the second type strain resistor.

6. The ultrasonic imaging device according to claim 5, wherein: Each of the pixel groups includes two pixels adjacent to each other along the column direction; The strain resistors in the pixels of the odd-numbered rows are strain resistors of the first type, and the strain resistors in the pixels of the even-numbered rows are strain resistors of the second type; Alternatively, the strain resistors in the pixels in the even-numbered rows are strain resistors of the first type, and the strain resistors in the pixels in the odd-numbered rows are strain resistors of the second type; Alternatively, the strain resistors in the odd-numbered rows of pixels are arranged alternately in the order of the first type of strain resistors and the second type of strain resistors, and the strain resistors in the even-numbered rows of pixels are arranged alternately in the order of the second type of strain resistors and the first type of strain resistors; Alternatively, the strain resistors in the odd-numbered rows of pixels are arranged alternately in the order of the second type of strain resistors and the first type of strain resistors, and the strain resistors in the even-numbered rows of pixels are arranged alternately in the order of the first type of strain resistors and the second type of strain resistors.

7. The ultrasonic imaging device according to claim 6, wherein: The pixel has a first side and a second side disposed opposite to each other along the row direction, and a third side and a fourth side disposed opposite to each other along the column direction; The first type of strained resistors in the odd-numbered columns of pixels are located on the first side, and the first type of strained resistors in the even-numbered columns of pixels are located on the second side; and / or, The second type strain resistors in each column of pixels are located on the fourth side, or the second type strain resistors in odd columns of pixels are located on the fourth side, and the second type strain resistors in even columns of pixels are located on the third side.

8. The ultrasonic imaging device according to any one of claims 5 to 7, wherein: The first type of strained resistors are arranged in a straight line along the row direction; or, the first type of strained resistors are arranged in a zigzag line or a serpentine line along the column direction; And / or, the second type strain resistors are arranged in a straight line along the column direction; or, the second type strain resistors are arranged in a zigzag line or a serpentine line along the row direction.

9. A driving method for an ultrasonic circuit according to any one of claims 1 to 4, characterized in that: include: During the curvature detection phase, the first control circuit initializes the first node; The second control circuit transmits a second electrical signal related to the curvature to the signal reading terminal; In the ultrasonic detection phase, the ultrasonic sensor transmits an ultrasonic signal, the first control circuit initializes the first node and the ultrasonic sensor respectively, the ultrasonic sensor receives the reflected ultrasonic signal, converts the received ultrasonic signal into a first electrical signal, and outputs the first electrical signal, the first control circuit receives the first electrical signal, and transmits the first electrical signal to the first node; The second control circuit transmits a third electrical signal related to the first electrical signal to the read signal terminal.

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