A Multi-Channel Proximity Sensor Demodulation Method and System Based on FPGA

Abstract

The present invention discloses a multi-channel proximity sensor demodulation method and system based on FPGA, belonging to the technical field of sensors. The present invention outputs a square wave signal by an internal frequency generation module of the FPGA and converts it into a standard sine wave excitation signal; it is assumed that n samplings are completed within one 1 / F period, and the sampling interval for each time is (1 / F) / n; the internal logic of the FPGA is used to control the analog switch to switch the sampling channels and perform timing control on the AD chip, and the excitation signal and sampling are respectively performed within three sampling periods; the sampling results are grouped and subjected to discrete Fourier transform, and the inductance value Ls and resistance value Rs after interpolation filtering are calculated, and then the state of the sensor is judged to complete the demodulation of the multi-channel proximity sensor. The present invention solves the technical problems of slow operation speed achieved by the existing demodulation methods and the inability to well solve the multi-channel real-time calculation, and can effectively achieve the rapid perception of the proximity sensors of the aircraft landing gear and the cabin door.

Description

Technical Field

[0001] The present invention belongs to the technical field of sensors, and particularly relates to a demodulation method and system for a multi-channel proximity sensor based on FPGA. Background Art

[0002] An inductive sensor is composed of two parts: internal resistance and inductance. The demodulation of the inductive sensor mainly focuses on the demodulation of its inductance value. It is impossible to obtain the accurate impedance information of the inductive sensor and thus demodulate the inductance value only by measuring the voltage amplitude characteristic at both ends of the inductive sensor without phase information. The key to demodulating the proximity sensor principle by the frequency domain method lies in obtaining both the amplitude and phase of the impedance of the inductive sensor simultaneously.

[0003] Figure 1 FIG. is the basic schematic diagram for sensor measurement. Among them, SIN is a signal source with a frequency of F Hz and a sinusoidal signal with an amplitude of SIN. R1 is a precision sampling resistor with a known resistance value, L1 is the proximity sensor to be measured, and R1 is a precision sampling resistor with a known resistance value. L1 is the proximity sensor to be measured. Both ends of R1 are respectively connected to the subsequent measurement circuit through a selection switch S1 for analysis and processing. When the switch S1 is set to the 1 end, the analog-to-digital conversion chip samples the relevant information of V_sin. When the switch S1 is set to the 2 end, the analog-to-digital conversion chip samples the relevant information of V_sensor. The measurement circuit samples a vector signal with amplitude and phase information. To ensure that the amplitude and phase information of the two types of waveforms are not interfered by other factors, the signal conditioning circuit after the switch S1 and the sampling channels of the AD chip need to be consistent. After the AD chip converts the analog signal into a digital signal, it is sent to the FPGA through a parallel bus. After being processed by the discrete Fourier transform DFT inside the FPGA, the internal resistance value and inductance value of the inductive sensor are calculated according to the corresponding formula. When the distance between the sensor and the target changes, the inductance value also changes accordingly. According to the magnitude of the inductance value, the position of the proximity sensor can be judged to achieve continuous demodulation; at the same time, according to the magnitude of the resistance value, it can be directly judged whether the sensor is in an open circuit state or a short circuit state to achieve real-time detection. Summary of the Invention

[0004] Aiming at the above deficiencies in the prior art, the present invention provides a demodulation method and system for a multi-channel proximity sensor based on FPGA, which solves the technical problems of slow operation speed achieved by the existing calculation method and inability to well solve multi-channel real-time calculation, and effectively realizes the rapid perception of the proximity sensors of the aircraft landing gear and the cabin door.

[0005] In order to achieve the above invention purpose, the technical solution adopted by the present invention is: a demodulation method for a multi-channel proximity sensor based on FPGA, including the following steps:

[0006] S1. The FPGA internal frequency generation module outputs a square wave signal and converts it into a standard sine wave excitation signal;

[0007] S2. Assume that n samplings are completed within a 1 / F period, and the sampling interval for each time is (1 / F) / n;

[0008] S3. Use the FPGA internal logic to control the analog switch to switch the sampling channel and perform timing control on the AD chip. First, collect the excitation signal within three sampling periods Then switch the sampling channel and collect the excitation signal again Among them, one proximity sensor needs to complete one sampling within three consecutive adjacent sampling periods. The three adjacent sampling periods are the T1 period for sampling the excitation signal Complete n samplings, the T2 period for analog switch control, and the T3 period for sampling the excitation signal Complete n samplings;

[0009] S4. Group and perform discrete Fourier transform on the sampling results, and calculate the inductance value Ls and resistance value Rs after interpolation filtering;

[0010] S5. According to the inductance value Ls and resistance value Rs after interpolation filtering, judge the state of the sensor and complete the demodulation of the multi-channel proximity sensor.

[0011] The beneficial effects of the present invention are as follows: On the one hand, by utilizing the characteristics of parallel operation and precise timing of the FPGA, real-time centralized demodulation of multiple proximity sensors can be quickly completed at one time, greatly reducing the operating load of the CPU and improving the reliability of the system. On the other hand, there is no need to purchase a DFT IP core, which saves a large amount of financial resources, improves the economy of the system, solves the technical problems of slow operation speed and inability to well solve multi-channel real-time calculation in the existing calculation methods, and effectively realizes the rapid perception of the proximity sensors of the aircraft landing gear and cabin door.

[0012] Further, the step S1 includes the following steps:

[0013] S101. The FPGA internal frequency generation module outputs a square wave signal with a frequency of F Hz and a duty cycle of 50%;

[0014] S102. After passing through the filter shaping circuit, the square wave signal is converted into a standard sine wave excitation signal with an amplitude of 1 V and a period of 1 / F, where F represents the frequency.

[0015] The beneficial effects of the above further solution are as follows: The present invention has a wide application range and strong scalability by parameterizing and configuring the demodulation parameters.

[0016] Still further, the step S3 includes the following steps:

[0017] S301. Use the internal logic of the FPGA to control the enable signal and address signal of the analog switch, turn on the V_sin sampling channel, and collect the excitation signal Among them, before sampling, the FPGA sets the address A0 and address A1 to 00. At the same time, the analog switch output terminals DOUT1 and DOUT2 are respectively connected to the V_sin_m port and the V_sin_m+2 port, where m represents the number of channels;

[0018] S302. After the FPGA samples the rising edge of the standard square wave, for the excitation signal start sampling, and within the T1 period, start an AD conversion according to the sampling interval, and parallel input the data collected by the AD chip each time into the FPGA. After being converted into 32-bit double-precision floating-point numbers inside the FPGA, it is recorded as a with the amplitude and phase information of the excitation signal of the circuit where the two sensors are located n and b n , where a n represents the amplitude information obtained after sampling the excitation signal n times, and b n represents the phase information obtained after sampling the excitation signal n times;

[0019] S303. After the sampling result in the T1 period, use the internal logic of the FPGA to control the enable signal and address signal of the analog switch, turn on the V_sensor sampling channel, and collect the excitation signal Among them, before sampling, the FPGA sets the address A0 and address A1 to 01. At the same time, the analog switch output terminals DOUT1 and DOUT2 are respectively connected to the V_sensor__m port and the V_sensor__m+2 port;

[0020] S304. Wait for the FPGA to sample the next rising edge of the standard square wave, then start sampling the sensor waveform, and within the T3 period, start an AD conversion according to the sampling interval, and parallel input the data collected by the AD chip each time into the FPGA. After being converted into floating-point numbers inside the FPGA, it is recorded as x n and y n with the amplitude and phase information of the sensor waveform of the circuit where the two sensors are located, where waiting for the FPGA to sample the next rising edge of the standard square wave is to wait for the T2 period, where x n represents the amplitude information obtained after sampling the sensor waveform n times, and y n represents the phase information obtained after sampling the sensor waveform n times.

[0021] S305. Change addresses A0 and A1 to 10. Meanwhile, connect the analog switch output terminals DOUT1 and DOUT2 to V_sin_m+1 and V_sin_m+3 respectively. After the sampling of the standard sine wave is completed, change addresses A0 and A1 to 11. Meanwhile, connect the analog switch output terminals DOUT1 and DOUT2 to V_sensor_m+1 and V_sensor_m+3 respectively to complete the sampling.

[0022] The beneficial effect of the above further solution is that: by switching channels with an analog switch and time-division multiplexing the AD chip, the present invention can effectively reduce the circuit load and improve the economic cost at the same time.

[0023] Furthermore, the step S4 includes the following steps:

[0024] S401. According to the sampling results, take a n and x n as a group, and b n and y n as a group, and perform a discrete Fourier transform DFT inside the FPGA, and calculate to obtain the inductance value Ls and the resistance value Rs;

[0025] S402. Perform interpolation filtering on the inductance value Ls and the resistance value Rs to obtain the interpolated and filtered inductance value Ls and resistance value Rs.

[0026] The beneficial effect of the above further solution is that: by implementing fast demodulation through discrete Fourier transform, the present invention greatly saves costs and greatly improves real-time performance.

[0027] Furthermore, the judgment of the sensor state in the step S5 is as follows:

[0028] For each channel, when the calculated inductance value Ls is greater than 5.05 mH and less than 10 mH, it is determined to be in the proximity state; when the calculated inductance value Ls of each channel is less than 4.95 mH and greater than 4 mH, it is determined to be in the far state;

[0029] For each channel, when the calculated resistance value Rs is less than 10 Ω and greater than 0.1 Ω, set the sensor short-circuit fault state;

[0030] For each channel, when the calculated resistance value Rs is greater than 50 Ω or less than 0.1 Ω, set the sensor open-circuit fault state.

[0031] The beneficial effect of the above further solution is that: compared with the prior art that only obtains the proximity / far state, the present invention can also judge the short-circuit / open-circuit state based on grouping the sampling results, discrete Fourier transform, and interpolation filtering.

[0032] The present invention provides a multi-channel proximity sensor demodulation system based on FPGA, including:

[0033] The first processing module is used to output a square wave signal by the internal frequency generation module of the FPGA and convert it into a standard sine wave excitation signal;

[0034] The second processing module is used to complete n samplings within the 1 / F period, and the sampling interval for each time is (1 / F) / n;

[0035] The third processing module is used to control the analog switch to switch the sampling channel and perform timing control on the AD chip by using the internal logic of the FPGA. First, the excitation signal is collected within three sampling periods Then switch the sampling channel and then collect the excitation signal Among them, one proximity sensor needs to complete one sampling within three consecutive adjacent sampling periods. The three adjacent sampling periods are the T1 period for the excitation signal Complete n samplings, the T2 period completes the analog switch control, and the T3 period is for the excitation signal Complete n samplings;

[0036] The fourth processing module is used to group the sampling results and perform discrete Fourier transform, and calculate the inductance value Ls and resistance value Rs after interpolation filtering;

[0037] The fifth processing module is used to judge the state of the sensor according to the inductance value Ls and resistance value Rs after interpolation filtering, and complete the demodulation of the multi-channel proximity sensor.

[0038] The beneficial effects of the present invention are as follows: On the one hand, by utilizing the characteristics of parallel operation and precise timing of the FPGA, the real-time centralized demodulation of multiple proximity sensors can be quickly completed at one time, greatly reducing the operating load of the CPU and improving the reliability of the system. On the other hand, there is no need to purchase a DFT IP core, saving a large amount of financial resources, improving the economy of the system, solving the technical problems of slow operation speed and inability to well solve multi-channel real-time calculation in the existing calculation methods, and effectively realizing the rapid perception of the aircraft landing gear proximity sensor. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] Figure 1 It is a schematic diagram of the measurement principle of the frequency domain method in the background technology.

[0040] Figure 2 It is a flowchart of the method of the present invention.

[0041] Figure 3 It is a system architecture diagram of the demodulation scheme in this embodiment.

[0042] Figure 4 It is a schematic diagram of analog switch control in this embodiment.

[0043] Figure 5 Schematic diagram of sampling in this embodiment.

[0044] Figure 6 This is a diagram of the internal data flow and calculation process of the FPGA in this embodiment.

[0045] Figure 7 It is a schematic diagram of the system structure of the present invention. DETAILED DESCRIPTION

[0046] The specific implementation modes of the present invention are described below so that those skilled in the art can understand the present invention. However, it should be clear that the present invention is not limited to the scope of the specific implementation modes. For those of ordinary skill in the art, as long as various changes are within the spirit and scope of the present invention as defined and determined by the attached claims, these changes are obvious, and all inventions and creations utilizing the concept of the present invention are protected.

[0047] Example 1

[0048] The existing technology uses the FFT function of DSP to achieve demodulation. The disadvantage of this solution is that when there are multiple proximity sensors in the peripheral, since the DSP executes tasks sequentially, running the FFT function consumes a lot of time, which will lead to solution congestion, and it is impossible to calculate the inductance and resistance values in real time, and thus it is impossible to quickly obtain the position and state of the proximity switch. In the aircraft landing gear and cabin doors that are full of sensors, in order to ensure the precise control of the landing gear and cabin doors, the flight control system requires high-speed and accurate identification of the approach / distance state and open circuit / short circuit state of the proximity switch. This solution has low real-time performance and certain defects. The technical problem to be solved by the present invention is to provide a multi-channel proximity sensor demodulation method based on FPGA, which solves the technical problems of slow calculation speed and inability to solve multi-channel real-time solution in the existing calculation method, and effectively realizes the rapid perception of the aircraft landing gear proximity sensor.

[0049] like Figure 2 As shown, the present invention provides a multi-channel proximity sensor demodulation method based on FPGA, and its implementation method is as follows:

[0050] S1, the square wave signal is output by the frequency generation module inside the FPGA and converted into a standard sine wave excitation signal. The implementation method is as follows:

[0051] S101, the frequency generation module inside the FPGA outputs a square wave signal with a frequency of FHz and a duty cycle of 50%;

[0052] S102, after filtering and shaping circuit, the square wave signal is converted into a standard sinusoidal wave excitation signal with an amplitude of 1V and a period of 1 / F, where F represents frequency.

[0053] In this embodiment,Figure 2 and Figure 3 As shown in Figure 3 , the present invention uses the internal logic of the FPGA to generate a continuous square wave signal with a configurable frequency and outputs it to the IO port. The output of the square wave signal is implemented using ODDR in the IOB resources of the FPGA. After being shaped into a standard sine wave by an external filter circuit, it is sent to the measurement circuit as an excitation source and then AD sampling is performed subsequently.

[0054] S2. Assume that n samplings are completed within a 1 / F period, and the sampling interval for each time is (1 / F) / n;

[0055] In this embodiment, if n samplings are to be completed within (1 / F) s, the sampling interval for each time is (1 / F) / n s, and timing is generated by an internal counter of the FPGA.

[0056] S3. Use the internal logic of the FPGA to control the switching of the sampling channel of the analog switch and perform timing control on the AD chip. First, collect the excitation signal within three sampling periods then switch the sampling channel, and then collect the excitation signal Among them, one proximity sensor needs to complete one sampling within three consecutive adjacent sampling periods. The three adjacent sampling periods are the T1 period for completing n samplings of the excitation signal the T2 period for completing the control of the analog switch, and the T3 period for the excitation signal For completing n samplings, the implementation method is as follows:

[0057] S301. Use the internal logic of the FPGA to control the enable signal and address signal of the analog switch, enable the V_sin sampling channel, and collect the excitation signal Among them, before sampling, the FPGA sets the address A0 and address A1 to 00. At the same time, the output terminals DOUT1 and DOUT2 of the analog switch are respectively connected to the V_sin_m port and the V_sin_m + 2 port, where m represents the number of channels;

[0058] S302. After the FPGA samples the rising edge of the standard square wave, start sampling the excitation signal and within the T1 period, start an AD conversion according to the sampling interval, and parallel input the data collected by the AD chip each time into the FPGA. After being converted into a 32-bit double-precision floating-point number inside the FPGA, it is denoted as a and b n with the amplitude and phase information of the excitation signal n of the circuit with two sensors, where a n represents the amplitude information obtained after sampling the excitation signal n times, and b n represents the phase information obtained after sampling the excitation signal n times;

[0059] S303. After the sampling results in the T1 period, use the internal logic of the FPGA to control the enable signal and address signal of the analog switch, turn on the V_sensor sampling channel, and collect the excitation signal Among them, before sampling, set the address A0 and address A1 to 01 through the FPGA. At the same time, the output terminals DOUT1 and DOUT2 of the analog switch are respectively connected to the V_sensor__m port and the V_sensor__m+2 port;

[0060] S304. Wait until the FPGA samples the rising edge of the next standard square wave, then start sampling the sensor waveform. And within the T3 period, start an AD conversion according to the sampling interval, and parallel input the data collected by the AD chip each time into the FPGA. After converting it into a floating point number in the FPGA, record it as x with the amplitude and phase information of the sensor waveform of the circuit where the two sensors are located n and y n , where the waiting for the FPGA to sample the rising edge of the next standard square wave is to wait for the T2 period, and x n represents the amplitude information obtained after sampling the sensor waveform n times, and y n represents the phase information obtained after sampling the sensor waveform n times.

[0061] S305. Change the address A0 and address A1 to 10. At the same time, the output terminals DOUT1 and DOUT2 of the analog switch are respectively connected to V_sin_m+1 and V_sin_m+3. After the sampling of the standard sine wave is completed, change the address A0 and A1 to 11. At the same time, the output terminals DOUT1 and DOUT2 of the analog switch are respectively connected to V_sensor_m+1 and V_sensor_m+3 to complete the sampling.

[0062] In this embodiment, use the internal logic of the FPGA to generate a continuous and configurable frequency square wave signal and output it to the IO port. After being shaped into a standard sine wave through an external circuit, it is sent to the measurement circuit as an excitation source. Use the internal logic of the FPGA to control the analog switch and realize the timing control of the AD chip. Respectively perform n = 2 and times of sampling for the excitation signal. Completing a complete information acquisition for 1 sensor requires 3 consecutive adjacent periods. The steps include performing n times of sampling on the N in the T1 period, completing the analog switch control in the T2 period, and performing n times of sampling on the in the T3 period. Perform n times of sampling.

[0063] In this embodiment, as Figure 4As shown in the figure, the enable signal and address signal of the analog switch are controlled by the internal logic of the FPGA to enable the V_sin sampling channel. Before starting sampling, the FPGA sets address A0 and address A1 to 00. At this time, the output terminals DOUT1 and DOUT2 of the analog switch are respectively connected to V_sin_1 and V_sin_3; V_sin_5 and V_sin_7; V_sin_m and V_sin_m+2. The following steps simulate the switch control and switching taking sensor_1 and sensor_3 as examples.

[0064] In this embodiment, as Figure 5 shown, after the FPGA samples the rising edge of the standard square wave, the sampling of the standard sine waveform starts. During the T1 period, an AD conversion is started every (1 / F) / n s. The 16-bit data collected each time by AD enters the FPGA in parallel and is converted into a floating-point number inside the FPGA. This value is denoted as a n (a0, a1, …, a n-1 ), b n (b0, b1, …, b n-1 ). These two data carry the amplitude and phase information of the standard sine wave of the circuits where the two sensors are located.

[0065] In this embodiment, as Figure 5 shown, after the T1 period ends, the enable signal and address signal of the analog switch chip are controlled to enable the V_sensor sampling channel. Before starting sampling, the FPGA sets address A0 and address A1 to 01. At this time, the output terminals DOUT1 and DOUT2 of the analog switch are respectively connected to V_sensor_1 and V_sensor_3.

[0066] In this embodiment, as Figure 5 shown, sampling does not start immediately at this moment (it takes a certain amount of time for the analog switch to switch). Wait until the next rising edge of the standard square wave is sampled (i.e., wait until time T2) and then start sampling. The sampling of the sensor waveform starts. During the T3 period, an AD conversion is started every (1 / F) / n s. The 16-bit data collected each time by AD enters the FPGA in parallel and is converted into a floating-point number inside the FPGA. This value is denoted as x n (x0, x1, …, x n-1 ), y n (y0, y1, …, y n-1 ). These two data carry the amplitude and phase information of the sensor waveform of the circuits where the two sensors are located.

[0067] In this embodiment, as Figure 5As shown, change address A0 and address A1 to 10. At this time, the analog switch output terminals DOUT1 and DOUT2 are respectively connected to V_sin_2 and V_sin_4; V_sin_6 and V_sin_8; V_sin_m + 1 and V_sin_m + 3. After the sampling of the standard sine wave is completed, change address A0 and address A1 to 11. At this time, the analog switch output terminals DOUT1 and DOUT2 are respectively connected to V_sensor_2 and V_sensor_4; V_sensor_6 and V_sin_sensor; V_sensor_m + 1 and V_sensor_m + 3. Group the obtained data to calculate the resistance values and inductance values of the second path, the fourth path, and the (m + 1)-th path.

[0068] S4. Group and perform discrete Fourier transform on the sampling results, and calculate the inductance value Ls and resistance value Rs after interpolation filtering. The implementation method is as follows:

[0069] S401. According to the sampling results, take a n and x n as a group, b n and y n as a group, and perform discrete Fourier transform DFT inside the FPGA, and calculate the inductance value Ls and resistance value Rs;

[0070] S402. Perform interpolation filtering on the inductance value Ls and resistance value Rs to obtain the inductance value Ls and resistance value Rs after interpolation filtering.

[0071] 1. In this embodiment, group the data. Take a n and x n as a group, b n and y n as a group, perform discrete Fourier transform DFT inside the FPGA, use the internal subtracter and divider to complete the calculation of Ls and Rs for the first path and the third path. Both Ls and Rs need to go through interpolation filtering as the final solution data;

[0072] Ls = 0.7 * L s_old + 0.3 * L s_new =; Rs = 0.7 * R s_old + 0.3 * R s_new ; The internal data flow and calculation process in the FPGA are shown in Figure 6 , Figure 6 . First, sample the excitation signal; switch the switch and wait for stability; then sample the sensor waveform, and finally perform the calculation.

[0073] In this embodiment, once the first-stage demodulation is completed, that is, A0 and A1 change from 00 to 11, the next demodulation starts again. Return to step 4, and m channels can be demodulated at one time (the value of m depends on the number l of analog switch chips, m = 4l).

[0074] S5. According to the inductance value Ls and resistance value Rs after interpolation filtering, judge the state of the sensor, and complete the demodulation of the multi-channel proximity sensor. The judgment of the sensor state is as follows:

[0075] For each channel, when the calculated inductance value Ls is greater than 5.05 mH and less than 10 mH, it is determined to be in the proximity state; when the calculated inductance value Ls of each channel is less than 4.95 mH and greater than 4 mH, it is determined to be in the far state.

[0076] For each channel, when the calculated resistance value Rs is less than 10 Ω and greater than 0.1 Ω, set the short-circuit fault state of the sensor;

[0077] For each channel, when the calculated resistance value Rs is greater than 50 Ω or less than 0.1 Ω, set the open-circuit fault state of the sensor.

[0078] On the one hand, the present invention utilizes the characteristics of parallel operation and precise timing of the FPGA, and can quickly complete the real-time centralized demodulation of multiple proximity sensors at one time, greatly reducing the operating load of the CPU and improving the reliability of the system. On the other hand, there is no need to purchase a DFT IP core, saving a large amount of financial resources, improving the economy of the system, solving the technical problems of slow operation speed and inability to well solve multi-channel real-time calculation in the existing calculation methods, and effectively realizing the rapid perception of the proximity sensor of the aircraft landing gear.

[0079] Embodiment 2

[0080] As Figure 7 shown, the present invention provides a multi-channel proximity sensor demodulation system based on FPGA, including:

[0081] The first processing module is used to output a square wave signal by the internal frequency generation module of the FPGA and convert it into a standard sine wave excitation signal;

[0082] The second processing module is used to complete n samplings within the 1 / F period, and the sampling interval for each time is (1 / F) / n;

[0083] The third processing module is used to control the analog switch to switch the sampling channel and perform timing control on the AD chip by using the internal logic of the FPGA. First, collect the excitation signal within three sampling periods Then switch the sampling channel and then collect the excitation signal Among them, one sampling of one proximity sensor needs to be completed within three consecutive adjacent sampling periods. The three adjacent sampling periods are the T1 period for the excitation signal Complete n samplings, complete analog switch control in the T2 period, and for the excitation signal in the T3 period Complete n samplings;

[0084] A fourth processing module, configured to group the sampling results and perform discrete Fourier transform, and calculate the inductance value Ls and resistance value Rs after interpolation filtering;

[0085] A fifth processing module, configured to determine the state of the sensor according to the inductance value Ls and resistance value Rs after interpolation filtering, and complete the demodulation of the multi-channel proximity sensor.

[0086] Such as Figure 7 The multi-channel proximity sensor demodulation system based on FPGA provided by the embodiment shown can execute the technical solutions shown in the above method embodiment of the multi-channel proximity sensor demodulation method based on FPGA. Its implementation principle and beneficial effects are similar, and will not be elaborated here.

[0087] In the embodiments of the present invention, the present application can perform function unit division according to the multi-channel proximity sensor demodulation method based on FPGA. For example, each function can be divided into each function unit, or two or more functions can be integrated into one processing unit. The above integrated unit can be implemented in the form of hardware or in the form of a software function unit. It should be noted that the division of units in the present invention is illustrative, only a logical division, and there may be other division methods in actual implementation.

[0088] In the embodiments of the present invention, in order to implement the principle and beneficial effects of the multi-channel proximity sensor demodulation method based on FPGA, the multi-channel proximity sensor demodulation system based on FPGA includes the corresponding hardware structure and / or software module for executing each function. Those skilled in the art should easily realize that, combined with the schematic units and algorithm steps described in the embodiments disclosed in the present invention, the present invention can be implemented in the form of hardware and / or the combination of hardware and computer software. Whether a certain function is executed in the way of hardware or computer software driving depends on the specific application and design constraint conditions of the technical solution. Different methods can be used for each specific application to implement the described function, but such implementation should not be considered to exceed the scope of the present application.

Claims

1. A multi-channel proximity sensor demodulation method based on FPGA, characterized in that It includes the following steps: S1. Output a square wave signal by the internal frequency generation module of the FPGA and convert it into a standard sine wave excitation signal; S2. Assume that n samplings are completed within a 1 / F period, and the sampling interval for each time is (1 / F) / n; S3. Use the internal logic of the FPGA to control the switching of the sampling channels of the analog switch and perform timing control on the AD chip. First, collect the excitation signal within three sampling periods Then switch the sampling channels and collect the excitation signal again Among them, one proximity sensor needs to complete one sampling within three consecutive adjacent sampling periods. The three adjacent sampling periods are the T1 period for collecting the excitation signal Complete n samplings, the T2 period completes the analog switch control, and the T3 period collects the excitation signal Complete n samplings; Step S3 includes the following steps: S301. Use the internal logic of the FPGA to control the enable signal and address signal of the analog switch, turn on the V_sin sampling channel, and collect the excitation signal Among them, before sampling, the FPGA sets the address A0 and address A1 to 00. At the same time, the analog switch output terminals DOUT1 and DOUT2 are respectively connected to the V_sin_m port and the V_sin_m+2 port, where m represents the number of channels; S302. After the rising edge of the standard square wave is retrieved by the FPGA, start sampling the excitation signal and, within the T1 period, initiate an AD conversion once according to the sampling interval, and parallelly input the data collected by the AD chip each time into the FPGA. After converting it into a 32-bit double-precision floating-point number inside the FPGA, it is denoted as a with the amplitude and phase information of the excitation signal of the circuit where the two sensors are located n and b n , where a n represents the amplitude information obtained after sampling the excitation signal n times, and b n represents the phase information obtained after sampling the excitation signal n times; S303. After the sampling result in the T1 period, use the internal logic of the FPGA to control the enable signal and address signal of the analog switch, turn on the V_sensor sampling channel, and collect the excitation signal Among them, before sampling, set the address A0 and address A1 to 01 through the FPGA. At the same time, connect the analog switch output terminals DOUT1 and DOUT2 to the V_sensor__m port and the V_sensor__m + 2 port respectively; S304. After waiting for the FPGA to sample the rising edge of the next standard square wave, start sampling the sensor waveform. During the T3 period, start an AD conversion according to the sampling interval, and parallel input the data collected by the AD chip each time into the FPGA. After converting it into a floating-point number in the FPGA, it is recorded as x with the amplitude and phase information of the sensor waveform of the circuit where the two sensors are located. n and y n , where waiting for the FPGA to sample the rising edge of the next standard square wave is waiting for the T2 period, and x n represents the amplitude information obtained after sampling the sensor waveform n times, and y n represents the phase information obtained after sampling the sensor waveform n times; S305. Change the addresses A0 and A1 to 10. At the same time, connect the output terminals DOUT1 and DOUT2 of the analog switch to V_sin_m+1 and V_sin_m+3 respectively. After the sampling of the standard sine wave is completed, change the addresses A0 and A1 to 11. At the same time, connect the output terminals DOUT1 and DOUT2 of the analog switch to V_sensor_m+1 and V_sensor_m+3 respectively to complete the sampling; S4. Group the sampling results and perform discrete Fourier transform, and calculate the inductance value Ls and resistance value Rs after interpolation filtering; S5. Judge the state of the sensor according to the inductance value Ls and resistance value Rs after interpolation filtering to complete the demodulation of the multi-channel proximity sensor.

2. The demodulation method of the multi-channel proximity sensor based on FPGA according to claim 1, wherein Step S1 includes the following steps: S101. Output a square wave signal with a frequency of F Hz and a duty cycle of 50% by the internal frequency generation module of the FPGA; S102. After passing through the filter shaping circuit, convert the square wave signal into a standard sine wave excitation signal with an amplitude of 1 V and a period of 1 / F, where F represents the frequency.

3. The demodulation method of the multi-channel proximity sensor based on FPGA according to claim 1, characterized in that Step S4 includes the following steps: S401. According to the sampling results, take a n and x n as a group, b n and y n as a group, and perform a discrete Fourier transform DFT inside the FPGA, and calculate the inductance value Ls and the resistance value Rs; S402. Perform interpolation filtering on the inductance value Ls and resistance value Rs to obtain the inductance value Ls and resistance value Rs after interpolation filtering.

4. The demodulation method of the multi-channel proximity sensor based on FPGA according to claim 1, characterized in that The judgment of the sensor state in step S5 is as follows: For each channel, when the calculated inductance value Ls is greater than 5.05 mH and less than 10 mH, it is determined to be in the proximity state. When the calculated inductance value Ls of each channel is less than 4.95 mH and greater than 4 mH, it is determined to be in the far state; For each channel, when the calculated resistance value Rs is less than 10 Ω and greater than 0.1 Ω, set the sensor short-circuit fault state; For each channel, when the calculated resistance value Rs is greater than 50 Ω or less than 0.1 Ω, set the sensor open-circuit fault state.

5. A multi-channel proximity sensor demodulation system based on FPGA, characterized in that, The multi-channel proximity sensor demodulation system is used to execute the multi-channel proximity sensor demodulation method according to any one of claims 1-4, and includes: The first processing module is used to output a square wave signal by the internal frequency generation module of the FPGA and convert it into a standard sine wave excitation signal; The second processing module is used to assume that n samplings are completed within a 1 / F period, and the sampling interval for each time is (1 / F) / n; The third processing module is used to control the switching of the sampling channels of the analog switch and perform timing control on the AD chip by using the internal logic of the FPGA, and collect the excitation signal first within three sampling periods then switch the sampling channels and then collect the excitation signal Among them, one proximity sensor needs to complete one sampling within three consecutive adjacent sampling periods. The three adjacent sampling periods are the T1 period for the excitation signal complete n samplings, the T2 period complete the analog switch control and the T3 period for the excitation signal to complete n samplings; The fourth processing module is used to group the sampling results and perform discrete Fourier transform, and calculate the inductance value Ls and resistance value Rs after interpolation filtering; The fifth processing module is used to judge the state of the sensor according to the inductance value Ls and resistance value Rs after interpolation filtering to complete the demodulation of the multi-channel proximity sensor.

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